2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
19 #include <asm/arch/control.h>
20 #include <asm/arch/cpu.h>
22 #if defined(CONFIG_ARCH_OMAP2420)
23 #define TAP_BASE (__force void __iomem *)io_p2v(0x48014000)
24 #elif defined(CONFIG_ARCH_OMAP2430)
25 #define TAP_BASE (__force void __iomem *)io_p2v(0x4900A000)
26 #elif defined(CONFIG_ARCH_OMAP34XX)
27 #define TAP_BASE (__force void __iomem *)io_p2v(0x4830A000)
30 #define OMAP_TAP_IDCODE 0x0204
31 #if defined(CONFIG_ARCH_OMAP34XX)
32 #define OMAP_TAP_PROD_ID 0x0210
34 #define OMAP_TAP_PROD_ID 0x0208
37 #define OMAP_TAP_DIE_ID_0 0x0218
38 #define OMAP_TAP_DIE_ID_1 0x021C
39 #define OMAP_TAP_DIE_ID_2 0x0220
40 #define OMAP_TAP_DIE_ID_3 0x0224
42 /* system_rev fields for OMAP2 processors:
43 * CPU id bits [31:16],
44 * CPU device type [15:12], (unprg,normal,POP)
45 * CPU revision [11:08]
46 * CPU class bits [07:00]
50 u16 hawkeye; /* Silicon type (Hawkeye id) */
51 u8 dev; /* Device type from production_id reg */
52 u32 type; /* combined type id copied to system_rev */
55 /* Register values to detect the OMAP version */
56 static struct omap_id omap_ids[] __initdata = {
57 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
58 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
59 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
60 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
61 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
62 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
65 static struct omap_chip_id omap_chip;
68 * omap_chip_is - test whether currently running OMAP matches a chip type
69 * @oc: omap_chip_t to test against
71 * Test whether the currently-running OMAP chip matches the supplied
72 * chip type 'oc'. Returns 1 upon a match; 0 upon failure.
74 int omap_chip_is(struct omap_chip_id oci)
76 return (oci.oc & omap_chip.oc) ? 1 : 0;
78 EXPORT_SYMBOL(omap_chip_is);
80 static u32 __init read_tap_reg(int reg)
82 unsigned int regval = 0;
85 /* Reading the IDCODE register on 3430 ES1 results in a
86 * data abort as the register is not exposed on the OCP
87 * Hence reading the Cortex Rev
89 cpuid = read_cpuid(CPUID_ID);
91 /* If the processor type is Cortex-A8 and the revision is 0x0
92 * it means its Cortex r0p0 which is 3430 ES1
94 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
96 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
97 /* Making DevType as 0xF in ES1 to differ from ES2 */
98 case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
99 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
100 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
101 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
102 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
105 regval = __raw_readl(TAP_BASE + reg);
112 * _set_system_rev - set the system_rev global based on current OMAP chip type
114 * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx()
117 static void __init _set_system_rev(u32 type, u8 rev)
122 * system_rev encoding is as follows
123 * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
124 * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
125 * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
126 * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
127 * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
128 * system_rev & 0x000000c0 -> IDCODE revision[6:7]
129 * system_rev & 0x0000003f -> sys_boot[0:5]
131 /* Embedding the ES revision info in type field */
133 /* Also add IDCODE revision info only two lower bits */
134 system_rev |= ((rev & 0x3) << 6);
136 /* Add in the device type and sys_boot fields (see above) */
137 if (cpu_is_omap24xx()) {
138 i = OMAP24XX_CONTROL_STATUS;
139 } else if (cpu_is_omap343x()) {
140 i = OMAP343X_CONTROL_STATUS;
142 printk(KERN_ERR "id: unknown CPU type\n");
145 ctrl_status = omap_ctrl_readl(i);
146 system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
147 OMAP2_SYSBOOT_4_MASK |
148 OMAP2_SYSBOOT_3_MASK |
149 OMAP2_SYSBOOT_2_MASK |
150 OMAP2_SYSBOOT_1_MASK |
151 OMAP2_SYSBOOT_0_MASK));
152 system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
157 * _set_omap_chip - set the omap_chip global based on OMAP chip type
159 * Build the omap_chip bits. This variable is used by powerdomain and
160 * clockdomain code to indicate whether structures are applicable for
161 * the current OMAP chip type by ANDing it against a 'platform' bitfield
164 static void __init _set_omap_chip(void)
166 if (cpu_is_omap343x()) {
168 omap_chip.oc = CHIP_IS_OMAP3430;
169 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
170 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
171 else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
172 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
174 } else if (cpu_is_omap243x()) {
176 /* Currently only supports 2430ES2.1 and 2430-all */
177 omap_chip.oc |= CHIP_IS_OMAP2430;
179 } else if (cpu_is_omap242x()) {
181 /* Currently only supports 2420ES2.1.1 and 2420-all */
182 omap_chip.oc |= CHIP_IS_OMAP2420;
186 /* Current CPU not supported by this code. */
187 printk(KERN_WARNING "OMAP chip type code does not yet support "
195 void __init omap2_check_revision(void)
204 idcode = read_tap_reg(OMAP_TAP_IDCODE);
205 prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
206 hawkeye = (idcode >> 12) & 0xffff;
207 rev = (idcode >> 28) & 0x0f;
208 dev_type = (prod_id >> 16) & 0x0f;
210 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
211 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
212 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
213 read_tap_reg(OMAP_TAP_DIE_ID_0));
214 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
215 read_tap_reg(OMAP_TAP_DIE_ID_1),
216 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
217 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
218 read_tap_reg(OMAP_TAP_DIE_ID_2));
219 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
220 read_tap_reg(OMAP_TAP_DIE_ID_3));
221 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
225 * Detection for 34xx ES2.0 and above can be done with just
226 * hawkeye and rev. See TRM 1.5.2 Device Identification.
227 * Note that rev cannot be used directly as ES1.0 uses value 0.
229 if (hawkeye == 0xb7ae) {
230 system_rev = 0x34300000 | ((1 + rev) << 12);
231 pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
236 /* Check hawkeye ids */
237 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
238 if (hawkeye == omap_ids[i].hawkeye)
242 if (i == ARRAY_SIZE(omap_ids)) {
243 printk(KERN_ERR "Unknown OMAP CPU id\n");
247 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
248 if (dev_type == omap_ids[j].dev)
252 if (j == ARRAY_SIZE(omap_ids)) {
253 printk(KERN_ERR "Unknown OMAP device type. "
254 "Handling it as OMAP%04x\n",
255 omap_ids[i].type >> 16);
259 _set_system_rev(omap_ids[j].type, rev);
263 pr_info("OMAP%04x", system_rev >> 16);
264 if ((system_rev >> 8) & 0x0f)
265 pr_info("ES%x", (system_rev >> 12) & 0xf);
270 #ifdef CONFIG_ARCH_OMAP3
272 * OMAP3 has L2 cache which has to be enabled by bootloader.
274 static int __init omap3_check_l2cache(void)
278 /* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
279 asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
281 if ((val & 0x2) == 0)
282 printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
283 "your bootloader. L2 off results in performance loss\n");
285 pr_info("OMAP3 L2 cache enabled\n");
290 arch_initcall(omap3_check_l2cache);
291 #endif /* CONFIG_ARCH_OMAP3 */