arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/board-sdp-hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c/twl4030.h>
  19 #include <mach/hardware.h>
  20 #include <mach/mmc.h>
  21 #include <mach/board.h>
  22
  23 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  24
  25 #define VMMC1_DEV_GRP           0x27
  26 #define P1_DEV_GRP              0x20
  27 #define VMMC1_DEDICATED         0x2A
  28 #define VSEL_3V                 0x02
  29 #define VSEL_18V                0x00
  30 #define TWL_GPIO_PUPDCTR1       0x13
  31 #define TWL_GPIO_IMR1A          0x1C
  32 #define TWL_GPIO_ISR1A          0x19
  33 #define LDO_CLR                 0x00
  34 #define VSEL_S2_CLR             0x40
  35 #define GPIO_0_BIT_POS          (1 << 0)
  36 #define MMC1_CD_IRQ             0
  37 #define MMC2_CD_IRQ             1
  38
  39 #define OMAP2_CONTROL_DEVCONF0  0x48002274
  40 #define OMAP2_CONTROL_DEVCONF1  0x490022E8
  41
  42 #define OMAP2_CONTROL_DEVCONF0_LBCLK    (1 << 24)
  43 #define OMAP2_CONTROL_DEVCONF1_ACTOV    (1 << 31)
  44
  45 #define OMAP2_CONTROL_PBIAS_VMODE       (1 << 0)
  46 #define OMAP2_CONTROL_PBIAS_PWRDNZ      (1 << 1)
  47 #define OMAP2_CONTROL_PBIAS_SCTRL       (1 << 2)
  48
  49 static int hsmmc_card_detect(int irq)
  50 {
  51         return twl4030_get_gpio_datain(irq - TWL4030_GPIO_IRQ_BASE);
  52 }
  53
  54 /*
  55  * MMC Slot Initialization.
  56  */
  57 static int hsmmc_late_init(struct device *dev)
  58 {
  59         int ret = 0;
  60
  61         /*
  62          * Configure TWL4030 GPIO parameters for MMC hotplug irq
  63          */
  64         ret = twl4030_request_gpio(MMC1_CD_IRQ);
  65         if (ret)
  66                 goto err;
  67
  68         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x02,
  69                                                 TWL_GPIO_PUPDCTR1);
  70         if (ret)
  71                 goto err;
  72
  73         ret = twl4030_set_gpio_debounce(MMC1_CD_IRQ, TWL4030_GPIO_IS_ENABLE);
  74         if (ret)
  75                 goto err;
  76
  77         return ret;
  78
  79 err:
  80         dev_err(dev, "Failed to configure TWL4030 GPIO IRQ\n");
  81         return ret;
  82 }
  83
  84 static void hsmmc_cleanup(struct device *dev)
  85 {
  86         int ret = 0;
  87
  88         ret = twl4030_free_gpio(MMC1_CD_IRQ);
  89         if (ret)
  90                 dev_err(dev, "Failed to configure TWL4030 GPIO IRQ\n");
  91 }
  92
  93 #ifdef CONFIG_PM
  94
  95 /*
  96  * To mask and unmask MMC Card Detect Interrupt
  97  * mask : 1
  98  * unmask : 0
  99  */
 100 static int mask_cd_interrupt(int mask)
 101 {
 102         u8 reg = 0, ret = 0;
 103
 104         ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &reg, TWL_GPIO_IMR1A);
 105         if (ret)
 106                 goto err;
 107
 108         reg = (mask == 1) ? (reg | GPIO_0_BIT_POS) : (reg & ~GPIO_0_BIT_POS);
 109
 110         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, reg, TWL_GPIO_IMR1A);
 111         if (ret)
 112                 goto err;
 113
 114         ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &reg, TWL_GPIO_ISR1A);
 115         if (ret)
 116                 goto err;
 117
 118         reg = (mask == 1) ? (reg | GPIO_0_BIT_POS) : (reg & ~GPIO_0_BIT_POS);
 119
 120         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, reg, TWL_GPIO_ISR1A);
 121         if (ret)
 122                 goto err;
 123
 124 err:
 125         return ret;
 126 }
 127
 128 static int hsmmc_suspend(struct device *dev, int slot)
 129 {
 130         int ret = 0;
 131
 132         disable_irq(TWL4030_GPIO_IRQ_NO(MMC1_CD_IRQ));
 133         ret = mask_cd_interrupt(1);
 134
 135         return ret;
 136 }
 137
 138 static int hsmmc_resume(struct device *dev, int slot)
 139 {
 140         int ret = 0;
 141
 142         enable_irq(TWL4030_GPIO_IRQ_NO(MMC1_CD_IRQ));
 143         ret = mask_cd_interrupt(0);
 144
 145         return ret;
 146 }
 147
 148 #endif
 149
 150 static int hsmmc_set_power(struct device *dev, int slot, int power_on,
 151                                 int vdd)
 152 {
 153         u32 vdd_sel = 0, devconf = 0, reg = 0;
 154         int ret = 0;
 155
 156         /* REVISIT: Using address directly till the control.h defines
 157          * are settled.
 158          */
 159 #if defined(CONFIG_ARCH_OMAP2430)
 160         #define OMAP2_CONTROL_PBIAS 0x490024A0
 161 #else
 162         #define OMAP2_CONTROL_PBIAS 0x48002520
 163 #endif
 164
 165         if (power_on) {
 166                 if (cpu_is_omap24xx())
 167                         devconf = omap_readl(OMAP2_CONTROL_DEVCONF1);
 168                 else
 169                         devconf = omap_readl(OMAP2_CONTROL_DEVCONF0);
 170
 171                 switch (1 << vdd) {
 172                 case MMC_VDD_33_34:
 173                 case MMC_VDD_32_33:
 174                         vdd_sel = VSEL_3V;
 175                         if (cpu_is_omap24xx())
 176                                 devconf |= OMAP2_CONTROL_DEVCONF1_ACTOV;
 177                         break;
 178                 case MMC_VDD_165_195:
 179                         vdd_sel = VSEL_18V;
 180                         if (cpu_is_omap24xx())
 181                                 devconf &= ~OMAP2_CONTROL_DEVCONF1_ACTOV;
 182                 }
 183
 184                 if (cpu_is_omap24xx())
 185                         omap_writel(devconf, OMAP2_CONTROL_DEVCONF1);
 186                 else
 187                         omap_writel(devconf | OMAP2_CONTROL_DEVCONF0_LBCLK,
 188                                     OMAP2_CONTROL_DEVCONF0);
 189
 190                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 191                 reg |= OMAP2_CONTROL_PBIAS_SCTRL;
 192                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 193
 194                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 195                 reg &= ~OMAP2_CONTROL_PBIAS_PWRDNZ;
 196                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 197
 198                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 199                                                 P1_DEV_GRP, VMMC1_DEV_GRP);
 200                 if (ret)
 201                         goto err;
 202
 203                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 204                                                 vdd_sel, VMMC1_DEDICATED);
 205                 if (ret)
 206                         goto err;
 207
 208                 msleep(100);
 209                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 210                 reg |= (OMAP2_CONTROL_PBIAS_SCTRL |
 211                         OMAP2_CONTROL_PBIAS_PWRDNZ);
 212                 if (vdd_sel == VSEL_18V)
 213                         reg &= ~OMAP2_CONTROL_PBIAS_VMODE;
 214                 else
 215                         reg |= OMAP2_CONTROL_PBIAS_VMODE;
 216                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 217
 218                 return ret;
 219
 220         } else {
 221                 /* Power OFF */
 222
 223                 /* For MMC1, Toggle PBIAS before every power up sequence */
 224                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 225                 reg &= ~OMAP2_CONTROL_PBIAS_PWRDNZ;
 226                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 227
 228                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 229                                                 LDO_CLR, VMMC1_DEV_GRP);
 230                 if (ret)
 231                         goto err;
 232
 233                 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 234                                                 VSEL_S2_CLR, VMMC1_DEDICATED);
 235                 if (ret)
 236                         goto err;
 237
 238                 /* 100ms delay required for PBIAS configuration */
 239                 msleep(100);
 240                 reg = omap_readl(OMAP2_CONTROL_PBIAS);
 241                 reg |= (OMAP2_CONTROL_PBIAS_VMODE |
 242                         OMAP2_CONTROL_PBIAS_PWRDNZ |
 243                         OMAP2_CONTROL_PBIAS_SCTRL);
 244                 omap_writel(reg, OMAP2_CONTROL_PBIAS);
 245         }
 246
 247         return 0;
 248
 249 err:
 250         return 1;
 251 }
 252
 253 static struct omap_mmc_platform_data mmc1_data = {
 254         .nr_slots                       = 1,
 255         .init                           = hsmmc_late_init,
 256         .cleanup                        = hsmmc_cleanup,
 257 #ifdef CONFIG_PM
 258         .suspend                        = hsmmc_suspend,
 259         .resume                         = hsmmc_resume,
 260 #endif
 261         .dma_mask                       = 0xffffffff,
 262         .slots[0] = {
 263                 .wire4                  = 1,
 264                 .set_power              = hsmmc_set_power,
 265                 .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34 |
 266                                                 MMC_VDD_165_195,
 267                 .name                   = "first slot",
 268
 269                 .card_detect_irq        = TWL4030_GPIO_IRQ_NO(MMC1_CD_IRQ),
 270                 .card_detect            = hsmmc_card_detect,
 271         },
 272 };
 273
 274 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC];
 275
 276 void __init hsmmc_init(void)
 277 {
 278         hsmmc_data[0] = &mmc1_data;
 279         omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
 280 }
 281
 282 #else
 283
 284 void __init hsmmc_init(void)
 285 {
 286
 287 }
 288
 289 #endif