arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/board-sdp-hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/gpio.h>
  19 #include <linux/i2c/twl4030.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/control.h>
  23 #include <mach/mmc.h>
  24 #include <mach/board.h>
  25
  26 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  27
  28 #define TWL_GPIO_IMR1A          0x1C
  29 #define TWL_GPIO_ISR1A          0x19
  30 #define LDO_CLR                 0x00
  31 #define VSEL_S2_CLR             0x40
  32 #define GPIO_0_BIT_POS          (1 << 0)
  33
  34 #define VMMC1_DEV_GRP           0x27
  35 #define VMMC1_CLR               0x00
  36 #define VMMC1_315V              0x03
  37 #define VMMC1_300V              0x02
  38 #define VMMC1_285V              0x01
  39 #define VMMC1_185V              0x00
  40 #define VMMC1_DEDICATED         0x2A
  41
  42 #define VMMC2_DEV_GRP           0x2B
  43 #define VMMC2_CLR               0x40
  44 #define VMMC2_315V              0x0c
  45 #define VMMC2_300V              0x0b
  46 #define VMMC2_285V              0x0a
  47 #define VMMC2_260V              0x08
  48 #define VMMC2_185V              0x06
  49 #define VMMC2_DEDICATED         0x2E
  50
  51 #define VMMC_DEV_GRP_P1         0x20
  52
  53 static u16 control_pbias_offset;
  54
  55 static struct hsmmc_controller {
  56         u16             control_devconf_offset;
  57         u32             devconf_loopback_clock;
  58         int             card_detect_gpio;
  59         u8              twl_vmmc_dev_grp;
  60         u8              twl_mmc_dedicated;
  61 } hsmmc[] = {
  62         {
  63                 .control_devconf_offset         = OMAP2_CONTROL_DEVCONF0,
  64                 .devconf_loopback_clock         = OMAP2_MMCSDIO1ADPCLKISEL,
  65                 .card_detect_gpio               = OMAP_MAX_GPIO_LINES,
  66                 .twl_vmmc_dev_grp               = VMMC1_DEV_GRP,
  67                 .twl_mmc_dedicated              = VMMC1_DEDICATED,
  68         },
  69         {
  70                 /* control_devconf_offset set dynamically */
  71                 .devconf_loopback_clock         = OMAP2_MMCSDIO2ADPCLKISEL,
  72                 .twl_vmmc_dev_grp               = VMMC2_DEV_GRP,
  73                 .twl_mmc_dedicated              = VMMC2_DEDICATED,
  74         },
  75  };
  76
  77 static int hsmmc1_card_detect(int irq)
  78 {
  79         return gpio_get_value_cansleep(hsmmc[0].card_detect_gpio);
  80 }
  81
  82 /*
  83  * MMC Slot Initialization.
  84  */
  85 static int hsmmc1_late_init(struct device *dev)
  86 {
  87         int ret = 0;
  88
  89         /*
  90          * Configure TWL4030 GPIO parameters for MMC hotplug irq
  91          */
  92         ret = gpio_request(hsmmc[0].card_detect_gpio, "mmc0_cd");
  93         if (ret)
  94                 goto err;
  95
  96         ret = twl4030_set_gpio_debounce(0, true);
  97         if (ret)
  98                 goto err;
  99
 100         return ret;
 101
 102 err:
 103         dev_err(dev, "Failed to configure TWL4030 GPIO IRQ\n");
 104         return ret;
 105 }
 106
 107 static void hsmmc1_cleanup(struct device *dev)
 108 {
 109         gpio_free(hsmmc[0].card_detect_gpio);
 110 }
 111
 112 #ifdef CONFIG_PM
 113
 114 /*
 115  * Mask and unmask MMC Card Detect Interrupt
 116  * mask : 1
 117  * unmask : 0
 118  */
 119 static int mask_cd_interrupt(int mask)
 120 {
 121         u8 reg = 0, ret = 0;
 122
 123         ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &reg, TWL_GPIO_IMR1A);
 124         if (ret)
 125                 goto err;
 126
 127         reg = (mask == 1) ? (reg | GPIO_0_BIT_POS) : (reg & ~GPIO_0_BIT_POS);
 128
 129         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, reg, TWL_GPIO_IMR1A);
 130         if (ret)
 131                 goto err;
 132
 133         ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &reg, TWL_GPIO_ISR1A);
 134         if (ret)
 135                 goto err;
 136
 137         reg = (mask == 1) ? (reg | GPIO_0_BIT_POS) : (reg & ~GPIO_0_BIT_POS);
 138
 139         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, reg, TWL_GPIO_ISR1A);
 140         if (ret)
 141                 goto err;
 142
 143 err:
 144         return ret;
 145 }
 146
 147 static int hsmmc1_suspend(struct device *dev, int slot)
 148 {
 149         int ret = 0;
 150
 151         disable_irq(TWL4030_GPIO_IRQ_NO(0));
 152         ret = mask_cd_interrupt(1);
 153
 154         return ret;
 155 }
 156
 157 static int hsmmc1_resume(struct device *dev, int slot)
 158 {
 159         int ret = 0;
 160
 161         enable_irq(TWL4030_GPIO_IRQ_NO(0));
 162         ret = mask_cd_interrupt(0);
 163
 164         return ret;
 165 }
 166
 167 #endif
 168
 169 /*
 170  * Sets the MMC voltage in twl4030
 171  */
 172 static int hsmmc_twl_set_voltage(struct hsmmc_controller *c, int vdd)
 173 {
 174         int ret;
 175         u8 vmmc, dev_grp_val;
 176
 177         switch (1 << vdd) {
 178         case MMC_VDD_35_36:
 179         case MMC_VDD_34_35:
 180         case MMC_VDD_33_34:
 181         case MMC_VDD_32_33:
 182         case MMC_VDD_31_32:
 183         case MMC_VDD_30_31:
 184                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 185                         vmmc = VMMC1_315V;
 186                 else
 187                         vmmc = VMMC2_315V;
 188                 break;
 189         case MMC_VDD_29_30:
 190                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 191                         vmmc = VMMC1_315V;
 192                 else
 193                         vmmc = VMMC2_300V;
 194                 break;
 195         case MMC_VDD_27_28:
 196         case MMC_VDD_26_27:
 197                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 198                         vmmc = VMMC1_285V;
 199                 else
 200                         vmmc = VMMC2_285V;
 201                 break;
 202         case MMC_VDD_25_26:
 203         case MMC_VDD_24_25:
 204         case MMC_VDD_23_24:
 205         case MMC_VDD_22_23:
 206         case MMC_VDD_21_22:
 207         case MMC_VDD_20_21:
 208                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 209                         vmmc = VMMC1_285V;
 210                 else
 211                         vmmc = VMMC2_260V;
 212                 break;
 213         case MMC_VDD_165_195:
 214                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 215                         vmmc = VMMC1_185V;
 216                 else
 217                         vmmc = VMMC2_185V;
 218                 break;
 219         default:
 220                 vmmc = 0;
 221                 break;
 222         }
 223
 224         if (vmmc)
 225                 dev_grp_val = VMMC_DEV_GRP_P1;  /* Power up */
 226         else
 227                 dev_grp_val = LDO_CLR;          /* Power down */
 228
 229         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 230                                         dev_grp_val, c->twl_vmmc_dev_grp);
 231         if (ret)
 232                 return ret;
 233
 234         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 235                                                 vmmc, c->twl_mmc_dedicated);
 236
 237         return ret;
 238 }
 239
 240 static int hsmmc1_set_power(struct device *dev, int slot, int power_on,
 241                                 int vdd)
 242 {
 243         u32 reg;
 244         int ret = 0;
 245         struct hsmmc_controller *c = &hsmmc[0];
 246
 247         if (power_on) {
 248                 if (cpu_is_omap2430()) {
 249                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
 250                         if ((1 << vdd) >= MMC_VDD_30_31)
 251                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
 252                         else
 253                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
 254                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
 255                 }
 256
 257                 /* REVISIT: Loop back clock not needed for 2430? */
 258                 if (!cpu_is_omap2430()) {
 259                         reg = omap_ctrl_readl(c->control_devconf_offset);
 260                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
 261                         omap_ctrl_writel(reg, c->control_devconf_offset);
 262                 }
 263
 264                 reg = omap_ctrl_readl(control_pbias_offset);
 265                 reg |= OMAP2_PBIASSPEEDCTRL0;
 266                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
 267                 omap_ctrl_writel(reg, control_pbias_offset);
 268
 269                 ret = hsmmc_twl_set_voltage(c, vdd);
 270
 271                 /* 100ms delay required for PBIAS configuration */
 272                 msleep(100);
 273                 reg = omap_ctrl_readl(control_pbias_offset);
 274                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 275                 if ((1 << vdd) <= MMC_VDD_165_195)
 276                         reg &= ~OMAP2_PBIASLITEVMODE0;
 277                 else
 278                         reg |= OMAP2_PBIASLITEVMODE0;
 279                 omap_ctrl_writel(reg, control_pbias_offset);
 280         } else {
 281                 reg = omap_ctrl_readl(control_pbias_offset);
 282                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
 283                 omap_ctrl_writel(reg, control_pbias_offset);
 284
 285                 ret = hsmmc_twl_set_voltage(c, 0);
 286
 287                 /* 100ms delay required for PBIAS configuration */
 288                 msleep(100);
 289                 reg = omap_ctrl_readl(control_pbias_offset);
 290                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 291                         OMAP2_PBIASLITEVMODE0);
 292                 omap_ctrl_writel(reg, control_pbias_offset);
 293         }
 294
 295         return ret;
 296 }
 297
 298 static int hsmmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
 299 {
 300         int ret;
 301
 302         struct hsmmc_controller *c = &hsmmc[1];
 303
 304         if (power_on) {
 305                 u32 reg;
 306
 307                 reg = omap_ctrl_readl(c->control_devconf_offset);
 308                 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 309                 omap_ctrl_writel(reg, c->control_devconf_offset);
 310                 ret = hsmmc_twl_set_voltage(c, vdd);
 311         } else {
 312                 ret = hsmmc_twl_set_voltage(c, 0);
 313         }
 314
 315         return ret;
 316 }
 317
 318 static struct omap_mmc_platform_data mmc1_data = {
 319         .nr_slots                       = 1,
 320         .init                           = hsmmc1_late_init,
 321         .cleanup                        = hsmmc1_cleanup,
 322 #ifdef CONFIG_PM
 323         .suspend                        = hsmmc1_suspend,
 324         .resume                         = hsmmc1_resume,
 325 #endif
 326         .dma_mask                       = 0xffffffff,
 327         .slots[0] = {
 328                 .wire4                  = 1,
 329                 .set_power              = hsmmc1_set_power,
 330                 .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34 |
 331                                                 MMC_VDD_165_195,
 332                 .name                   = "first slot",
 333
 334                 .card_detect_irq        = TWL4030_GPIO_IRQ_NO(0),
 335                 .card_detect            = hsmmc1_card_detect,
 336         },
 337 };
 338
 339 static struct omap_mmc_platform_data mmc2_data = {
 340         .nr_slots                       = 1,
 341         .slots[0] = {
 342                 .set_power              = hsmmc2_set_power,
 343                 .ocr_mask               = MMC_VDD_27_28 | MMC_VDD_28_29 |
 344                                           MMC_VDD_29_30 | MMC_VDD_30_31 |
 345                                           MMC_VDD_31_32 | MMC_VDD_32_33,
 346                 .name                   = "second slot",
 347         },
 348 };
 349
 350 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC];
 351
 352 void __init hsmmc_init(int controller_mask)
 353 {
 354         if (cpu_is_omap2430()) {
 355                 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 356                 hsmmc[1].control_devconf_offset = OMAP243X_CONTROL_DEVCONF1;
 357         } else {
 358                 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 359                 hsmmc[1].control_devconf_offset = OMAP343X_CONTROL_DEVCONF1;
 360         }
 361
 362         if (controller_mask & HSMMC1)
 363                 hsmmc_data[0] = &mmc1_data;
 364         if (controller_mask & HSMMC2)
 365                 hsmmc_data[1] = &mmc2_data;
 366         if (controller_mask & HSMMC3)
 367                 pr_err("HSMMC: Unknown configuration for controller 3\n");
 368         omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
 369 }
 370
 371 #else
 372
 373 void __init hsmmc_init(void)
 374 {
 375
 376 }
 377
 378 #endif