2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
16 #include <linux/ioport.h>
17 #include <linux/spinlock.h>
20 #include <asm/mach-types.h>
21 #include <asm/arch/gpmc.h>
25 #if defined(CONFIG_ARCH_OMAP2420)
26 #define GPMC_BASE 0x6800a000
27 #elif defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
28 #define GPMC_BASE 0x6e000000
31 #define GPMC_REVISION 0x00
32 #define GPMC_SYSCONFIG 0x10
33 #define GPMC_SYSSTATUS 0x14
34 #define GPMC_IRQSTATUS 0x18
35 #define GPMC_IRQENABLE 0x1c
36 #define GPMC_TIMEOUT_CONTROL 0x40
37 #define GPMC_ERR_ADDRESS 0x44
38 #define GPMC_ERR_TYPE 0x48
39 #define GPMC_CONFIG 0x50
40 #define GPMC_STATUS 0x54
41 #define GPMC_PREFETCH_CONFIG1 0x1e0
42 #define GPMC_PREFETCH_CONFIG2 0x1e4
43 #define GPMC_PREFETCH_CONTROL 0x1e8
44 #define GPMC_PREFETCH_STATUS 0x1f0
45 #define GPMC_ECC_CONFIG 0x1f4
46 #define GPMC_ECC_CONTROL 0x1f8
47 #define GPMC_ECC_SIZE_CONFIG 0x1fc
50 #define GPMC_CS_SIZE 0x30
52 #define GPMC_MEM_START 0x00000000
53 #define GPMC_MEM_END 0x3FFFFFFF
54 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
56 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
57 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
59 static struct resource gpmc_mem_root;
60 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
61 static DEFINE_SPINLOCK(gpmc_mem_lock);
62 static unsigned gpmc_cs_map;
64 static void __iomem *gpmc_base =
65 (void __iomem *) IO_ADDRESS(GPMC_BASE);
66 static void __iomem *gpmc_cs_base =
67 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
69 static struct clk *gpmc_l3_clk;
71 static void gpmc_write_reg(int idx, u32 val)
73 __raw_writel(val, gpmc_base + idx);
76 static u32 gpmc_read_reg(int idx)
78 return __raw_readl(gpmc_base + idx);
81 void gpmc_cs_write_reg(int cs, int idx, u32 val)
83 void __iomem *reg_addr;
85 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
86 __raw_writel(val, reg_addr);
89 u32 gpmc_cs_read_reg(int cs, int idx)
91 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
94 /* TODO: Add support for gpmc_fck to clock framework and use it */
95 unsigned long gpmc_get_fclk_period(void)
98 return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
101 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
103 unsigned long tick_ps;
105 /* Calculate in picosecs to yield more exact results */
106 tick_ps = gpmc_get_fclk_period();
108 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
111 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
113 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
115 return ticks * gpmc_get_fclk_period() / 1000;
119 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
120 int time, const char *name)
122 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
127 int ticks, mask, nr_bits;
132 ticks = gpmc_ns_to_ticks(time);
133 nr_bits = end_bit - st_bit + 1;
134 if (ticks >= 1 << nr_bits) {
136 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
137 cs, name, time, ticks, 1 << nr_bits);
142 mask = (1 << nr_bits) - 1;
143 l = gpmc_cs_read_reg(cs, reg);
146 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
147 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
148 (l >> st_bit) & mask, time);
150 l &= ~(mask << st_bit);
151 l |= ticks << st_bit;
152 gpmc_cs_write_reg(cs, reg, l);
158 #define GPMC_SET_ONE(reg, st, end, field) \
159 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
160 t->field, #field) < 0) \
163 #define GPMC_SET_ONE(reg, st, end, field) \
164 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
168 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
173 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
174 div = l / gpmc_get_fclk_period();
183 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
188 div = gpmc_cs_calc_divider(cs, t->sync_clk);
192 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
193 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
194 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
196 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
197 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
198 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
200 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
201 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
202 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
203 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
205 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
206 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
207 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
209 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
211 /* caller is expected to have initialized CONFIG1 to cover
212 * at least sync vs async
214 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
215 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
217 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
218 cs, (div * gpmc_get_fclk_period()) / 1000, div);
222 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
228 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
233 mask = (1 << GPMC_SECTION_SHIFT) - size;
234 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
236 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
238 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
239 l |= 1 << 6; /* CSVALID */
240 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
243 static void gpmc_cs_disable_mem(int cs)
247 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
248 l &= ~(1 << 6); /* CSVALID */
249 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
252 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
257 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
258 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
259 mask = (l >> 8) & 0x0f;
260 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
263 static int gpmc_cs_mem_enabled(int cs)
267 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
271 int gpmc_cs_set_reserved(int cs, int reserved)
273 if (cs > GPMC_CS_NUM)
276 gpmc_cs_map &= ~(1 << cs);
277 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
282 int gpmc_cs_reserved(int cs)
284 if (cs > GPMC_CS_NUM)
287 return gpmc_cs_map & (1 << cs);
290 static unsigned long gpmc_mem_align(unsigned long size)
294 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
295 order = GPMC_CHUNK_SHIFT - 1;
304 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
306 struct resource *res = &gpmc_cs_mem[cs];
309 size = gpmc_mem_align(size);
310 spin_lock(&gpmc_mem_lock);
312 res->end = base + size - 1;
313 r = request_resource(&gpmc_mem_root, res);
314 spin_unlock(&gpmc_mem_lock);
319 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
321 struct resource *res = &gpmc_cs_mem[cs];
324 if (cs > GPMC_CS_NUM)
327 size = gpmc_mem_align(size);
328 if (size > (1 << GPMC_SECTION_SHIFT))
331 spin_lock(&gpmc_mem_lock);
332 if (gpmc_cs_reserved(cs)) {
336 if (gpmc_cs_mem_enabled(cs))
337 r = adjust_resource(res, res->start & ~(size - 1), size);
339 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
344 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
346 gpmc_cs_set_reserved(cs, 1);
348 spin_unlock(&gpmc_mem_lock);
352 void gpmc_cs_free(int cs)
354 spin_lock(&gpmc_mem_lock);
355 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
356 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
358 spin_unlock(&gpmc_mem_lock);
361 gpmc_cs_disable_mem(cs);
362 release_resource(&gpmc_cs_mem[cs]);
363 gpmc_cs_set_reserved(cs, 0);
364 spin_unlock(&gpmc_mem_lock);
367 void __init gpmc_mem_init(void)
370 unsigned long boot_rom_space = 0;
372 /* never allocate the first page, to facilitate bug detection;
373 * even if we didn't boot from ROM.
375 boot_rom_space = BOOT_ROM_SPACE;
376 /* In apollon the CS0 is mapped as 0x0000 0000 */
377 if (machine_is_omap_apollon())
379 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
380 gpmc_mem_root.end = GPMC_MEM_END;
382 /* Reserve all regions that has been set up by bootloader */
383 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
386 if (!gpmc_cs_mem_enabled(cs))
388 gpmc_cs_get_memconf(cs, &base, &size);
389 if (gpmc_cs_insert_mem(cs, base, size) < 0)
394 void __init gpmc_init(void)
398 if (cpu_is_omap24xx())
399 gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
400 else if (cpu_is_omap34xx())
401 gpmc_l3_clk = clk_get(NULL, "gpmc_fck");
403 BUG_ON(IS_ERR(gpmc_l3_clk));
405 l = gpmc_read_reg(GPMC_REVISION);
406 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
407 /* Set smart idle mode and automatic L3 clock gating */
408 l = gpmc_read_reg(GPMC_SYSCONFIG);
410 l |= (0x02 << 3) | (1 << 0);
411 gpmc_write_reg(GPMC_SYSCONFIG, l);