2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
16 #include <linux/ioport.h>
17 #include <linux/spinlock.h>
18 #include <linux/module.h>
21 #include <asm/mach-types.h>
22 #include <asm/arch/gpmc.h>
26 #if defined(CONFIG_ARCH_OMAP2420)
27 #define GPMC_BASE 0x6800a000
28 #elif defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
29 #define GPMC_BASE 0x6e000000
32 #define GPMC_REVISION 0x00
33 #define GPMC_SYSCONFIG 0x10
34 #define GPMC_SYSSTATUS 0x14
35 #define GPMC_IRQSTATUS 0x18
36 #define GPMC_IRQENABLE 0x1c
37 #define GPMC_TIMEOUT_CONTROL 0x40
38 #define GPMC_ERR_ADDRESS 0x44
39 #define GPMC_ERR_TYPE 0x48
40 #define GPMC_CONFIG 0x50
41 #define GPMC_STATUS 0x54
42 #define GPMC_PREFETCH_CONFIG1 0x1e0
43 #define GPMC_PREFETCH_CONFIG2 0x1e4
44 #define GPMC_PREFETCH_CONTROL 0x1e8
45 #define GPMC_PREFETCH_STATUS 0x1f0
46 #define GPMC_ECC_CONFIG 0x1f4
47 #define GPMC_ECC_CONTROL 0x1f8
48 #define GPMC_ECC_SIZE_CONFIG 0x1fc
51 #define GPMC_CS_SIZE 0x30
53 #define GPMC_MEM_START 0x00000000
54 #define GPMC_MEM_END 0x3FFFFFFF
55 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
57 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
58 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
60 static struct resource gpmc_mem_root;
61 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
62 static DEFINE_SPINLOCK(gpmc_mem_lock);
63 static unsigned gpmc_cs_map;
65 static void __iomem *gpmc_base =
66 (void __iomem *) IO_ADDRESS(GPMC_BASE);
67 static void __iomem *gpmc_cs_base =
68 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
70 static struct clk *gpmc_l3_clk;
72 static void gpmc_write_reg(int idx, u32 val)
74 __raw_writel(val, gpmc_base + idx);
77 static u32 gpmc_read_reg(int idx)
79 return __raw_readl(gpmc_base + idx);
82 void gpmc_cs_write_reg(int cs, int idx, u32 val)
84 void __iomem *reg_addr;
86 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
87 __raw_writel(val, reg_addr);
90 u32 gpmc_cs_read_reg(int cs, int idx)
92 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
95 /* TODO: Add support for gpmc_fck to clock framework and use it */
96 unsigned long gpmc_get_fclk_period(void)
98 unsigned long rate = clk_get_rate(gpmc_l3_clk);
101 printk(KERN_WARNING "gpmc_l3_clk no enabled\n");
106 rate = 1000000000 / rate; /* In picoseconds */
111 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
113 unsigned long tick_ps;
115 /* Calculate in picosecs to yield more exact results */
116 tick_ps = gpmc_get_fclk_period();
118 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
121 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
123 return ticks * gpmc_get_fclk_period() / 1000;
126 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
128 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
130 return ticks * gpmc_get_fclk_period() / 1000;
134 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
135 int time, const char *name)
137 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
142 int ticks, mask, nr_bits;
147 ticks = gpmc_ns_to_ticks(time);
148 nr_bits = end_bit - st_bit + 1;
149 if (ticks >= 1 << nr_bits) {
151 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
152 cs, name, time, ticks, 1 << nr_bits);
157 mask = (1 << nr_bits) - 1;
158 l = gpmc_cs_read_reg(cs, reg);
161 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
162 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
163 (l >> st_bit) & mask, time);
165 l &= ~(mask << st_bit);
166 l |= ticks << st_bit;
167 gpmc_cs_write_reg(cs, reg, l);
173 #define GPMC_SET_ONE(reg, st, end, field) \
174 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
175 t->field, #field) < 0) \
178 #define GPMC_SET_ONE(reg, st, end, field) \
179 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
183 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
188 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
189 div = l / gpmc_get_fclk_period();
198 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
203 div = gpmc_cs_calc_divider(cs, t->sync_clk);
207 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
208 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
209 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
211 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
212 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
213 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
215 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
216 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
217 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
218 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
220 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
222 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
224 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
226 /* caller is expected to have initialized CONFIG1 to cover
227 * at least sync vs async
229 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
230 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
232 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
233 cs, (div * gpmc_get_fclk_period()) / 1000, div);
237 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
243 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
248 mask = (1 << GPMC_SECTION_SHIFT) - size;
249 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
251 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
253 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
254 l |= 1 << 6; /* CSVALID */
255 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
258 static void gpmc_cs_disable_mem(int cs)
262 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
263 l &= ~(1 << 6); /* CSVALID */
264 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
267 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
272 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
273 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
274 mask = (l >> 8) & 0x0f;
275 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
278 static int gpmc_cs_mem_enabled(int cs)
282 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
286 int gpmc_cs_set_reserved(int cs, int reserved)
288 if (cs > GPMC_CS_NUM)
291 gpmc_cs_map &= ~(1 << cs);
292 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
297 int gpmc_cs_reserved(int cs)
299 if (cs > GPMC_CS_NUM)
302 return gpmc_cs_map & (1 << cs);
305 static unsigned long gpmc_mem_align(unsigned long size)
309 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
310 order = GPMC_CHUNK_SHIFT - 1;
319 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
321 struct resource *res = &gpmc_cs_mem[cs];
324 size = gpmc_mem_align(size);
325 spin_lock(&gpmc_mem_lock);
327 res->end = base + size - 1;
328 r = request_resource(&gpmc_mem_root, res);
329 spin_unlock(&gpmc_mem_lock);
334 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
336 struct resource *res = &gpmc_cs_mem[cs];
339 if (cs > GPMC_CS_NUM)
342 size = gpmc_mem_align(size);
343 if (size > (1 << GPMC_SECTION_SHIFT))
346 spin_lock(&gpmc_mem_lock);
347 if (gpmc_cs_reserved(cs)) {
351 if (gpmc_cs_mem_enabled(cs))
352 r = adjust_resource(res, res->start & ~(size - 1), size);
354 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
359 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
361 gpmc_cs_set_reserved(cs, 1);
363 spin_unlock(&gpmc_mem_lock);
366 EXPORT_SYMBOL(gpmc_cs_request);
368 void gpmc_cs_free(int cs)
370 spin_lock(&gpmc_mem_lock);
371 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
372 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
374 spin_unlock(&gpmc_mem_lock);
377 gpmc_cs_disable_mem(cs);
378 release_resource(&gpmc_cs_mem[cs]);
379 gpmc_cs_set_reserved(cs, 0);
380 spin_unlock(&gpmc_mem_lock);
382 EXPORT_SYMBOL(gpmc_cs_free);
384 void __init gpmc_mem_init(void)
387 unsigned long boot_rom_space = 0;
389 /* never allocate the first page, to facilitate bug detection;
390 * even if we didn't boot from ROM.
392 boot_rom_space = BOOT_ROM_SPACE;
393 /* In apollon the CS0 is mapped as 0x0000 0000 */
394 if (machine_is_omap_apollon())
396 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
397 gpmc_mem_root.end = GPMC_MEM_END;
399 /* Reserve all regions that has been set up by bootloader */
400 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
403 if (!gpmc_cs_mem_enabled(cs))
405 gpmc_cs_get_memconf(cs, &base, &size);
406 if (gpmc_cs_insert_mem(cs, base, size) < 0)
411 void __init gpmc_init(void)
415 if (cpu_is_omap24xx())
416 gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
417 else if (cpu_is_omap34xx())
418 gpmc_l3_clk = clk_get(NULL, "gpmc_fck");
420 BUG_ON(IS_ERR(gpmc_l3_clk));
422 l = gpmc_read_reg(GPMC_REVISION);
423 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
424 /* Set smart idle mode and automatic L3 clock gating */
425 l = gpmc_read_reg(GPMC_SYSCONFIG);
427 l |= (0x02 << 3) | (1 << 0);
428 gpmc_write_reg(GPMC_SYSCONFIG, l);