2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
16 #include <linux/ioport.h>
17 #include <linux/spinlock.h>
20 #include <asm/mach-types.h>
21 #include <asm/arch/gpmc.h>
25 #if defined(CONFIG_ARCH_OMAP2420)
26 #define GPMC_BASE 0x6800a000
27 #elif defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
28 #define GPMC_BASE 0x6e000000
31 #define GPMC_REVISION 0x00
32 #define GPMC_SYSCONFIG 0x10
33 #define GPMC_SYSSTATUS 0x14
34 #define GPMC_IRQSTATUS 0x18
35 #define GPMC_IRQENABLE 0x1c
36 #define GPMC_TIMEOUT_CONTROL 0x40
37 #define GPMC_ERR_ADDRESS 0x44
38 #define GPMC_ERR_TYPE 0x48
39 #define GPMC_CONFIG 0x50
40 #define GPMC_STATUS 0x54
41 #define GPMC_PREFETCH_CONFIG1 0x1e0
42 #define GPMC_PREFETCH_CONFIG2 0x1e4
43 #define GPMC_PREFETCH_CONTROL 0x1e8
44 #define GPMC_PREFETCH_STATUS 0x1f0
45 #define GPMC_ECC_CONFIG 0x1f4
46 #define GPMC_ECC_CONTROL 0x1f8
47 #define GPMC_ECC_SIZE_CONFIG 0x1fc
50 #define GPMC_CS_SIZE 0x30
52 #define GPMC_MEM_START 0x00000000
53 #define GPMC_MEM_END 0x3FFFFFFF
54 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
56 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
57 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
59 static struct resource gpmc_mem_root;
60 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
61 static DEFINE_SPINLOCK(gpmc_mem_lock);
62 static unsigned gpmc_cs_map;
64 static void __iomem *gpmc_base =
65 (void __iomem *) IO_ADDRESS(GPMC_BASE);
66 static void __iomem *gpmc_cs_base =
67 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
69 static struct clk *gpmc_l3_clk;
71 static void gpmc_write_reg(int idx, u32 val)
73 __raw_writel(val, gpmc_base + idx);
76 static u32 gpmc_read_reg(int idx)
78 return __raw_readl(gpmc_base + idx);
81 void gpmc_cs_write_reg(int cs, int idx, u32 val)
83 void __iomem *reg_addr;
85 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
86 __raw_writel(val, reg_addr);
89 u32 gpmc_cs_read_reg(int cs, int idx)
91 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
94 /* TODO: Add support for gpmc_fck to clock framework and use it */
95 unsigned long gpmc_get_fclk_period(void)
97 unsigned long rate = clk_get_rate(gpmc_l3_clk);
100 printk(KERN_WARNING "gpmc_l3_clk no enabled\n");
105 rate = 1000000000 / rate; /* In picoseconds */
110 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
112 unsigned long tick_ps;
114 /* Calculate in picosecs to yield more exact results */
115 tick_ps = gpmc_get_fclk_period();
117 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
120 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
122 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
124 return ticks * gpmc_get_fclk_period() / 1000;
128 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
129 int time, const char *name)
131 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
136 int ticks, mask, nr_bits;
141 ticks = gpmc_ns_to_ticks(time);
142 nr_bits = end_bit - st_bit + 1;
143 if (ticks >= 1 << nr_bits) {
145 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
146 cs, name, time, ticks, 1 << nr_bits);
151 mask = (1 << nr_bits) - 1;
152 l = gpmc_cs_read_reg(cs, reg);
155 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
156 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
157 (l >> st_bit) & mask, time);
159 l &= ~(mask << st_bit);
160 l |= ticks << st_bit;
161 gpmc_cs_write_reg(cs, reg, l);
167 #define GPMC_SET_ONE(reg, st, end, field) \
168 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
169 t->field, #field) < 0) \
172 #define GPMC_SET_ONE(reg, st, end, field) \
173 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
177 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
182 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
183 div = l / gpmc_get_fclk_period();
192 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
197 div = gpmc_cs_calc_divider(cs, t->sync_clk);
201 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
202 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
203 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
205 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
206 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
207 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
209 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
210 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
211 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
212 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
214 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
215 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
216 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
218 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
220 /* caller is expected to have initialized CONFIG1 to cover
221 * at least sync vs async
223 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
224 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
226 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
227 cs, (div * gpmc_get_fclk_period()) / 1000, div);
231 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
237 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
242 mask = (1 << GPMC_SECTION_SHIFT) - size;
243 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
245 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
247 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
248 l |= 1 << 6; /* CSVALID */
249 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
252 static void gpmc_cs_disable_mem(int cs)
256 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
257 l &= ~(1 << 6); /* CSVALID */
258 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
261 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
266 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
267 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
268 mask = (l >> 8) & 0x0f;
269 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
272 static int gpmc_cs_mem_enabled(int cs)
276 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
280 int gpmc_cs_set_reserved(int cs, int reserved)
282 if (cs > GPMC_CS_NUM)
285 gpmc_cs_map &= ~(1 << cs);
286 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
291 int gpmc_cs_reserved(int cs)
293 if (cs > GPMC_CS_NUM)
296 return gpmc_cs_map & (1 << cs);
299 static unsigned long gpmc_mem_align(unsigned long size)
303 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
304 order = GPMC_CHUNK_SHIFT - 1;
313 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
315 struct resource *res = &gpmc_cs_mem[cs];
318 size = gpmc_mem_align(size);
319 spin_lock(&gpmc_mem_lock);
321 res->end = base + size - 1;
322 r = request_resource(&gpmc_mem_root, res);
323 spin_unlock(&gpmc_mem_lock);
328 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
330 struct resource *res = &gpmc_cs_mem[cs];
333 if (cs > GPMC_CS_NUM)
336 size = gpmc_mem_align(size);
337 if (size > (1 << GPMC_SECTION_SHIFT))
340 spin_lock(&gpmc_mem_lock);
341 if (gpmc_cs_reserved(cs)) {
345 if (gpmc_cs_mem_enabled(cs))
346 r = adjust_resource(res, res->start & ~(size - 1), size);
348 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
353 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
355 gpmc_cs_set_reserved(cs, 1);
357 spin_unlock(&gpmc_mem_lock);
361 void gpmc_cs_free(int cs)
363 spin_lock(&gpmc_mem_lock);
364 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
365 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
367 spin_unlock(&gpmc_mem_lock);
370 gpmc_cs_disable_mem(cs);
371 release_resource(&gpmc_cs_mem[cs]);
372 gpmc_cs_set_reserved(cs, 0);
373 spin_unlock(&gpmc_mem_lock);
376 void __init gpmc_mem_init(void)
379 unsigned long boot_rom_space = 0;
381 /* never allocate the first page, to facilitate bug detection;
382 * even if we didn't boot from ROM.
384 boot_rom_space = BOOT_ROM_SPACE;
385 /* In apollon the CS0 is mapped as 0x0000 0000 */
386 if (machine_is_omap_apollon())
388 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
389 gpmc_mem_root.end = GPMC_MEM_END;
391 /* Reserve all regions that has been set up by bootloader */
392 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
395 if (!gpmc_cs_mem_enabled(cs))
397 gpmc_cs_get_memconf(cs, &base, &size);
398 if (gpmc_cs_insert_mem(cs, base, size) < 0)
403 void __init gpmc_init(void)
407 if (cpu_is_omap24xx())
408 gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
409 else if (cpu_is_omap34xx())
410 gpmc_l3_clk = clk_get(NULL, "gpmc_fck");
412 BUG_ON(IS_ERR(gpmc_l3_clk));
414 l = gpmc_read_reg(GPMC_REVISION);
415 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
416 /* Set smart idle mode and automatic L3 clock gating */
417 l = gpmc_read_reg(GPMC_SYSCONFIG);
419 l |= (0x02 << 3) | (1 << 0);
420 gpmc_write_reg(GPMC_SYSCONFIG, l);