arch/arm/mach-omap2/cm_regbits_34xx.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
   2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
   3
   4 /*
   5  * OMAP3430 Clock Management register bits
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "cm.h"
  18
  19 /* Bits shared between registers */
  20
  21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
  22 #define OMAP3430ES2_EN_MMC3_MASK                        (1 << 30)
  23 #define OMAP3430ES2_EN_MMC3_SHIFT                       30
  24 #define OMAP3430_EN_MSPRO                               (1 << 23)
  25 #define OMAP3430_EN_MSPRO_SHIFT                         23
  26 #define OMAP3430_EN_HDQ                                 (1 << 22)
  27 #define OMAP3430_EN_HDQ_SHIFT                           22
  28 #define OMAP3430ES1_EN_FSHOSTUSB                        (1 << 5)
  29 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT                  5
  30 #define OMAP3430ES1_EN_D2D                              (1 << 3)
  31 #define OMAP3430ES1_EN_D2D_SHIFT                        3
  32 #define OMAP3430_EN_SSI                                 (1 << 0)
  33 #define OMAP3430_EN_SSI_SHIFT                           0
  34
  35 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
  36 #define OMAP3430ES2_EN_USBTLL_SHIFT                     2
  37 #define OMAP3430ES2_EN_USBTLL_MASK                      (1 << 2)
  38
  39 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
  40 #define OMAP3430_EN_WDT2                                (1 << 5)
  41 #define OMAP3430_EN_WDT2_SHIFT                          5
  42
  43 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
  44 #define OMAP3430_EN_CAM                                 (1 << 0)
  45 #define OMAP3430_EN_CAM_SHIFT                           0
  46
  47 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
  48 #define OMAP3430_EN_WDT3                                (1 << 12)
  49 #define OMAP3430_EN_WDT3_SHIFT                          12
  50
  51 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
  52 #define OMAP3430_OVERRIDE_ENABLE                        (1 << 19)
  53
  54
  55 /* Bits specific to each register */
  56
  57 /* CM_FCLKEN_IVA2 */
  58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2                 (1 << 0)
  59
  60 /* CM_CLKEN_PLL_IVA2 */
  61 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT               8
  62 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK                (0x3 << 8)
  63 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT                4
  64 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK                 (0xf << 4)
  65 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT          3
  66 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK           (1 << 3)
  67 #define OMAP3430_EN_IVA2_DPLL_SHIFT                     0
  68 #define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
  69
  70 /* CM_IDLEST_IVA2 */
  71 #define OMAP3430_ST_IVA2                                (1 << 0)
  72
  73 /* CM_IDLEST_PLL_IVA2 */
  74 #define OMAP3430_ST_IVA2_CLK                            (1 << 0)
  75
  76 /* CM_AUTOIDLE_PLL_IVA2 */
  77 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
  78 #define OMAP3430_AUTO_IVA2_DPLL_MASK                    (0x7 << 0)
  79
  80 /* CM_CLKSEL1_PLL_IVA2 */
  81 #define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
  82 #define OMAP3430_IVA2_CLK_SRC_MASK                      (0x3 << 19)
  83 #define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
  84 #define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
  85 #define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
  86 #define OMAP3430_IVA2_DPLL_DIV_MASK                     (0x7f << 0)
  87
  88 /* CM_CLKSEL2_PLL_IVA2 */
  89 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT             0
  90 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK              (0x1f << 0)
  91
  92 /* CM_CLKSTCTRL_IVA2 */
  93 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT                   0
  94 #define OMAP3430_CLKTRCTRL_IVA2_MASK                    (0x3 << 0)
  95
  96 /* CM_CLKSTST_IVA2 */
  97 #define OMAP3430_CLKACTIVITY_IVA2                       (1 << 0)
  98
  99 /* CM_REVISION specific bits */
 100
 101 /* CM_SYSCONFIG specific bits */
 102
 103 /* CM_CLKEN_PLL_MPU */
 104 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT                8
 105 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK                 (0x3 << 8)
 106 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT                 4
 107 #define OMAP3430_MPU_DPLL_FREQSEL_MASK                  (0xf << 4)
 108 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT           3
 109 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK            (1 << 3)
 110 #define OMAP3430_EN_MPU_DPLL_SHIFT                      0
 111 #define OMAP3430_EN_MPU_DPLL_MASK                       (0x7 << 0)
 112
 113 /* CM_IDLEST_MPU */
 114 #define OMAP3430_ST_MPU                                 (1 << 0)
 115
 116 /* CM_IDLEST_PLL_MPU */
 117 #define OMAP3430_ST_MPU_CLK                             (1 << 0)
 118
 119 /* CM_AUTOIDLE_PLL_MPU */
 120 #define OMAP3430_AUTO_MPU_DPLL_SHIFT                    0
 121 #define OMAP3430_AUTO_MPU_DPLL_MASK                     (0x7 << 0)
 122
 123 /* CM_CLKSEL1_PLL_MPU */
 124 #define OMAP3430_MPU_CLK_SRC_SHIFT                      19
 125 #define OMAP3430_MPU_CLK_SRC_MASK                       (0x3 << 19)
 126 #define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
 127 #define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
 128 #define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
 129 #define OMAP3430_MPU_DPLL_DIV_MASK                      (0x7f << 0)
 130
 131 /* CM_CLKSEL2_PLL_MPU */
 132 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT              0
 133 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK               (0x1f << 0)
 134
 135 /* CM_CLKSTCTRL_MPU */
 136 #define OMAP3430_CLKTRCTRL_MPU_SHIFT                    0
 137 #define OMAP3430_CLKTRCTRL_MPU_MASK                     (0x3 << 0)
 138
 139 /* CM_CLKSTST_MPU */
 140 #define OMAP3430_CLKACTIVITY_MPU                        (1 << 0)
 141
 142 /* CM_FCLKEN1_CORE specific bits */
 143
 144 /* CM_ICLKEN1_CORE specific bits */
 145 #define OMAP3430_EN_ICR                                 (1 << 29)
 146 #define OMAP3430_EN_ICR_SHIFT                           29
 147 #define OMAP3430_EN_AES2                                (1 << 28)
 148 #define OMAP3430_EN_AES2_SHIFT                          28
 149 #define OMAP3430_EN_SHA12                               (1 << 27)
 150 #define OMAP3430_EN_SHA12_SHIFT                         27
 151 #define OMAP3430_EN_DES2                                (1 << 26)
 152 #define OMAP3430_EN_DES2_SHIFT                          26
 153 #define OMAP3430ES1_EN_FAC                              (1 << 8)
 154 #define OMAP3430ES1_EN_FAC_SHIFT                        8
 155 #define OMAP3430_EN_MAILBOXES                           (1 << 7)
 156 #define OMAP3430_EN_MAILBOXES_SHIFT                     7
 157 #define OMAP3430_EN_OMAPCTRL                            (1 << 6)
 158 #define OMAP3430_EN_OMAPCTRL_SHIFT                      6
 159 #define OMAP3430_EN_SDRC                                (1 << 1)
 160 #define OMAP3430_EN_SDRC_SHIFT                          1
 161
 162 /* CM_ICLKEN2_CORE */
 163 #define OMAP3430_EN_PKA                                 (1 << 4)
 164 #define OMAP3430_EN_PKA_SHIFT                           4
 165 #define OMAP3430_EN_AES1                                (1 << 3)
 166 #define OMAP3430_EN_AES1_SHIFT                          3
 167 #define OMAP3430_EN_RNG                                 (1 << 2)
 168 #define OMAP3430_EN_RNG_SHIFT                           2
 169 #define OMAP3430_EN_SHA11                               (1 << 1)
 170 #define OMAP3430_EN_SHA11_SHIFT                         1
 171 #define OMAP3430_EN_DES1                                (1 << 0)
 172 #define OMAP3430_EN_DES1_SHIFT                          0
 173
 174 /* CM_FCLKEN3_CORE specific bits */
 175 #define OMAP3430ES2_EN_TS_SHIFT                         1
 176 #define OMAP3430ES2_EN_TS_MASK                          (1 << 1)
 177 #define OMAP3430ES2_EN_CPEFUSE_SHIFT                    0
 178 #define OMAP3430ES2_EN_CPEFUSE_MASK                     (1 << 0)
 179
 180 /* CM_IDLEST1_CORE specific bits */
 181 #define OMAP3430_ST_ICR                                 (1 << 29)
 182 #define OMAP3430_ST_AES2                                (1 << 28)
 183 #define OMAP3430_ST_SHA12                               (1 << 27)
 184 #define OMAP3430_ST_DES2                                (1 << 26)
 185 #define OMAP3430_ST_MSPRO                               (1 << 23)
 186 #define OMAP3430_ST_HDQ                                 (1 << 22)
 187 #define OMAP3430ES1_ST_FAC                              (1 << 8)
 188 #define OMAP3430ES1_ST_MAILBOXES                        (1 << 7)
 189 #define OMAP3430_ST_OMAPCTRL                            (1 << 6)
 190 #define OMAP3430_ST_SDMA                                (1 << 2)
 191 #define OMAP3430_ST_SDRC                                (1 << 1)
 192 #define OMAP3430_ST_SSI                                 (1 << 0)
 193
 194 /* CM_IDLEST2_CORE */
 195 #define OMAP3430_ST_PKA                                 (1 << 4)
 196 #define OMAP3430_ST_AES1                                (1 << 3)
 197 #define OMAP3430_ST_RNG                                 (1 << 2)
 198 #define OMAP3430_ST_SHA11                               (1 << 1)
 199 #define OMAP3430_ST_DES1                                (1 << 0)
 200
 201 /* CM_AUTOIDLE1_CORE */
 202 #define OMAP3430_AUTO_AES2                              (1 << 28)
 203 #define OMAP3430_AUTO_AES2_SHIFT                        28
 204 #define OMAP3430_AUTO_SHA12                             (1 << 27)
 205 #define OMAP3430_AUTO_SHA12_SHIFT                       27
 206 #define OMAP3430_AUTO_DES2                              (1 << 26)
 207 #define OMAP3430_AUTO_DES2_SHIFT                        26
 208 #define OMAP3430_AUTO_MMC2                              (1 << 25)
 209 #define OMAP3430_AUTO_MMC2_SHIFT                        25
 210 #define OMAP3430_AUTO_MMC1                              (1 << 24)
 211 #define OMAP3430_AUTO_MMC1_SHIFT                        24
 212 #define OMAP3430_AUTO_MSPRO                             (1 << 23)
 213 #define OMAP3430_AUTO_MSPRO_SHIFT                       23
 214 #define OMAP3430_AUTO_HDQ                               (1 << 22)
 215 #define OMAP3430_AUTO_HDQ_SHIFT                         22
 216 #define OMAP3430_AUTO_MCSPI4                            (1 << 21)
 217 #define OMAP3430_AUTO_MCSPI4_SHIFT                      21
 218 #define OMAP3430_AUTO_MCSPI3                            (1 << 20)
 219 #define OMAP3430_AUTO_MCSPI3_SHIFT                      20
 220 #define OMAP3430_AUTO_MCSPI2                            (1 << 19)
 221 #define OMAP3430_AUTO_MCSPI2_SHIFT                      19
 222 #define OMAP3430_AUTO_MCSPI1                            (1 << 18)
 223 #define OMAP3430_AUTO_MCSPI1_SHIFT                      18
 224 #define OMAP3430_AUTO_I2C3                              (1 << 17)
 225 #define OMAP3430_AUTO_I2C3_SHIFT                        17
 226 #define OMAP3430_AUTO_I2C2                              (1 << 16)
 227 #define OMAP3430_AUTO_I2C2_SHIFT                        16
 228 #define OMAP3430_AUTO_I2C1                              (1 << 15)
 229 #define OMAP3430_AUTO_I2C1_SHIFT                        15
 230 #define OMAP3430_AUTO_UART2                             (1 << 14)
 231 #define OMAP3430_AUTO_UART2_SHIFT                       14
 232 #define OMAP3430_AUTO_UART1                             (1 << 13)
 233 #define OMAP3430_AUTO_UART1_SHIFT                       13
 234 #define OMAP3430_AUTO_GPT11                             (1 << 12)
 235 #define OMAP3430_AUTO_GPT11_SHIFT                       12
 236 #define OMAP3430_AUTO_GPT10                             (1 << 11)
 237 #define OMAP3430_AUTO_GPT10_SHIFT                       11
 238 #define OMAP3430_AUTO_MCBSP5                            (1 << 10)
 239 #define OMAP3430_AUTO_MCBSP5_SHIFT                      10
 240 #define OMAP3430_AUTO_MCBSP1                            (1 << 9)
 241 #define OMAP3430_AUTO_MCBSP1_SHIFT                      9
 242 #define OMAP3430ES1_AUTO_FAC                            (1 << 8)
 243 #define OMAP3430ES1_AUTO_FAC_SHIFT                      8
 244 #define OMAP3430_AUTO_MAILBOXES                         (1 << 7)
 245 #define OMAP3430_AUTO_MAILBOXES_SHIFT                   7
 246 #define OMAP3430_AUTO_OMAPCTRL                          (1 << 6)
 247 #define OMAP3430_AUTO_OMAPCTRL_SHIFT                    6
 248 #define OMAP3430ES1_AUTO_FSHOSTUSB                      (1 << 5)
 249 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT                5
 250 #define OMAP3430_AUTO_HSOTGUSB                          (1 << 4)
 251 #define OMAP3430_AUTO_HSOTGUSB_SHIFT                    4
 252 #define OMAP3430ES1_AUTO_D2D                            (1 << 3)
 253 #define OMAP3430ES1_AUTO_D2D_SHIFT                      3
 254 #define OMAP3430_AUTO_SSI                               (1 << 0)
 255 #define OMAP3430_AUTO_SSI_SHIFT                         0
 256
 257 /* CM_AUTOIDLE2_CORE */
 258 #define OMAP3430_AUTO_PKA                               (1 << 4)
 259 #define OMAP3430_AUTO_PKA_SHIFT                         4
 260 #define OMAP3430_AUTO_AES1                              (1 << 3)
 261 #define OMAP3430_AUTO_AES1_SHIFT                        3
 262 #define OMAP3430_AUTO_RNG                               (1 << 2)
 263 #define OMAP3430_AUTO_RNG_SHIFT                         2
 264 #define OMAP3430_AUTO_SHA11                             (1 << 1)
 265 #define OMAP3430_AUTO_SHA11_SHIFT                       1
 266 #define OMAP3430_AUTO_DES1                              (1 << 0)
 267 #define OMAP3430_AUTO_DES1_SHIFT                        0
 268
 269 /* CM_CLKSEL_CORE */
 270 #define OMAP3430_CLKSEL_SSI_SHIFT                       8
 271 #define OMAP3430_CLKSEL_SSI_MASK                        (0xf << 8)
 272 #define OMAP3430_CLKSEL_GPT11_MASK                      (1 << 7)
 273 #define OMAP3430_CLKSEL_GPT11_SHIFT                     7
 274 #define OMAP3430_CLKSEL_GPT10_MASK                      (1 << 6)
 275 #define OMAP3430_CLKSEL_GPT10_SHIFT                     6
 276 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT              4
 277 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK               (0x3 << 4)
 278 #define OMAP3430_CLKSEL_L4_SHIFT                        2
 279 #define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
 280 #define OMAP3430_CLKSEL_L3_SHIFT                        0
 281 #define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
 282
 283 /* CM_CLKSTCTRL_CORE */
 284 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT                 4
 285 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK                  (0x3 << 4)
 286 #define OMAP3430_CLKTRCTRL_L4_SHIFT                     2
 287 #define OMAP3430_CLKTRCTRL_L4_MASK                      (0x3 << 2)
 288 #define OMAP3430_CLKTRCTRL_L3_SHIFT                     0
 289 #define OMAP3430_CLKTRCTRL_L3_MASK                      (0x3 << 0)
 290
 291 /* CM_CLKSTST_CORE */
 292 #define OMAP3430ES1_CLKACTIVITY_D2D                     (1 << 2)
 293 #define OMAP3430_CLKACTIVITY_L4                         (1 << 1)
 294 #define OMAP3430_CLKACTIVITY_L3                         (1 << 0)
 295
 296 /* CM_FCLKEN_GFX */
 297 #define OMAP3430ES1_EN_3D                               (1 << 2)
 298 #define OMAP3430ES1_EN_3D_SHIFT                         2
 299 #define OMAP3430ES1_EN_2D                               (1 << 1)
 300 #define OMAP3430ES1_EN_2D_SHIFT                         1
 301
 302 /* CM_ICLKEN_GFX specific bits */
 303
 304 /* CM_IDLEST_GFX specific bits */
 305
 306 /* CM_CLKSEL_GFX specific bits */
 307
 308 /* CM_SLEEPDEP_GFX specific bits */
 309
 310 /* CM_CLKSTCTRL_GFX */
 311 #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT                 0
 312 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK                  (0x3 << 0)
 313
 314 /* CM_CLKSTST_GFX */
 315 #define OMAP3430ES1_CLKACTIVITY_GFX                     (1 << 0)
 316
 317 /* CM_FCLKEN_SGX */
 318 #define OMAP3430ES2_EN_SGX_SHIFT                        1
 319 #define OMAP3430ES2_EN_SGX_MASK                         (1 << 1)
 320
 321 /* CM_CLKSEL_SGX */
 322 #define OMAP3430ES2_CLKSEL_SGX_SHIFT                    0
 323 #define OMAP3430ES2_CLKSEL_SGX_MASK                     (0x7 << 0)
 324
 325 /* CM_FCLKEN_WKUP specific bits */
 326 #define OMAP3430ES2_EN_USIMOCP_SHIFT                    9
 327
 328 /* CM_ICLKEN_WKUP specific bits */
 329 #define OMAP3430_EN_WDT1                                (1 << 4)
 330 #define OMAP3430_EN_WDT1_SHIFT                          4
 331 #define OMAP3430_EN_32KSYNC                             (1 << 2)
 332 #define OMAP3430_EN_32KSYNC_SHIFT                       2
 333
 334 /* CM_IDLEST_WKUP specific bits */
 335 #define OMAP3430_ST_WDT2                                (1 << 5)
 336 #define OMAP3430_ST_WDT1                                (1 << 4)
 337 #define OMAP3430_ST_32KSYNC                             (1 << 2)
 338
 339 /* CM_AUTOIDLE_WKUP */
 340 #define OMAP3430_AUTO_WDT2                              (1 << 5)
 341 #define OMAP3430_AUTO_WDT2_SHIFT                        5
 342 #define OMAP3430_AUTO_WDT1                              (1 << 4)
 343 #define OMAP3430_AUTO_WDT1_SHIFT                        4
 344 #define OMAP3430_AUTO_GPIO1                             (1 << 3)
 345 #define OMAP3430_AUTO_GPIO1_SHIFT                       3
 346 #define OMAP3430_AUTO_32KSYNC                           (1 << 2)
 347 #define OMAP3430_AUTO_32KSYNC_SHIFT                     2
 348 #define OMAP3430_AUTO_GPT12                             (1 << 1)
 349 #define OMAP3430_AUTO_GPT12_SHIFT                       1
 350 #define OMAP3430_AUTO_GPT1                              (1 << 0)
 351 #define OMAP3430_AUTO_GPT1_SHIFT                        0
 352
 353 /* CM_CLKSEL_WKUP */
 354 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK                 (0xf << 3)
 355 #define OMAP3430_CLKSEL_RM_SHIFT                        1
 356 #define OMAP3430_CLKSEL_RM_MASK                         (0x3 << 1)
 357 #define OMAP3430_CLKSEL_GPT1_SHIFT                      0
 358 #define OMAP3430_CLKSEL_GPT1_MASK                       (1 << 0)
 359
 360 /* CM_CLKEN_PLL */
 361 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT                 31
 362 #define OMAP3430_PWRDN_CAM_SHIFT                        30
 363 #define OMAP3430_PWRDN_DSS1_SHIFT                       29
 364 #define OMAP3430_PWRDN_TV_SHIFT                         28
 365 #define OMAP3430_PWRDN_96M_SHIFT                        27
 366 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT             24
 367 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK              (0x3 << 24)
 368 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT              20
 369 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK               (0xf << 20)
 370 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT        19
 371 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK         (1 << 19)
 372 #define OMAP3430_EN_PERIPH_DPLL_SHIFT                   16
 373 #define OMAP3430_EN_PERIPH_DPLL_MASK                    (0x7 << 16)
 374 #define OMAP3430_PWRDN_EMU_CORE_SHIFT                   12
 375 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT               8
 376 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK                (0x3 << 8)
 377 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT                4
 378 #define OMAP3430_CORE_DPLL_FREQSEL_MASK                 (0xf << 4)
 379 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT          3
 380 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK           (1 << 3)
 381 #define OMAP3430_EN_CORE_DPLL_SHIFT                     0
 382 #define OMAP3430_EN_CORE_DPLL_MASK                      (0x7 << 0)
 383
 384 /* CM_CLKEN2_PLL */
 385 #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT                10
 386 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK          (0x3 << 8)
 387 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK           (0xf << 4)
 388 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT    3
 389 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK                        (0x7 << 0)
 390
 391 /* CM_IDLEST_CKGEN */
 392 #define OMAP3430_ST_54M_CLK                             (1 << 5)
 393 #define OMAP3430_ST_12M_CLK                             (1 << 4)
 394 #define OMAP3430_ST_48M_CLK                             (1 << 3)
 395 #define OMAP3430_ST_96M_CLK                             (1 << 2)
 396 #define OMAP3430_ST_PERIPH_CLK                          (1 << 1)
 397 #define OMAP3430_ST_CORE_CLK                            (1 << 0)
 398
 399 /* CM_AUTOIDLE_PLL */
 400 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT                 3
 401 #define OMAP3430_AUTO_PERIPH_DPLL_MASK                  (0x7 << 3)
 402 #define OMAP3430_AUTO_CORE_DPLL_SHIFT                   0
 403 #define OMAP3430_AUTO_CORE_DPLL_MASK                    (0x7 << 0)
 404
 405 /* CM_CLKSEL1_PLL */
 406 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
 407 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
 408 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK              (0x1f << 27)
 409 #define OMAP3430_CORE_DPLL_MULT_SHIFT                   16
 410 #define OMAP3430_CORE_DPLL_MULT_MASK                    (0x7ff << 16)
 411 #define OMAP3430_CORE_DPLL_DIV_SHIFT                    8
 412 #define OMAP3430_CORE_DPLL_DIV_MASK                     (0x7f << 8)
 413 #define OMAP3430_SOURCE_54M                             (1 << 5)
 414 #define OMAP3430_SOURCE_48M                             (1 << 3)
 415
 416 /* CM_CLKSEL2_PLL */
 417 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT                 8
 418 #define OMAP3430_PERIPH_DPLL_MULT_MASK                  (0x7ff << 8)
 419 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT                  0
 420 #define OMAP3430_PERIPH_DPLL_DIV_MASK                   (0x7f << 0)
 421
 422 /* CM_CLKSEL3_PLL */
 423 #define OMAP3430_DIV_96M_SHIFT                          0
 424 #define OMAP3430_DIV_96M_MASK                           (0x1f << 0)
 425
 426 /* CM_CLKSEL4_PLL */
 427 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK              (0x7ff << 8)
 428 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK               (0x7f << 0)
 429
 430 /* CM_CLKSEL5_PLL */
 431 #define OMAP3430ES2_DIV_120M_MASK                       (0x1f << 0)
 432
 433 /* CM_CLKOUT_CTRL */
 434 #define OMAP3430_CLKOUT2_EN_SHIFT                       7
 435 #define OMAP3430_CLKOUT2_EN                             (1 << 7)
 436 #define OMAP3430_CLKOUT2_DIV_SHIFT                      3
 437 #define OMAP3430_CLKOUT2_DIV_MASK                       (0x7 << 3)
 438 #define OMAP3430_CLKOUT2SOURCE_SHIFT                    0
 439 #define OMAP3430_CLKOUT2SOURCE_MASK                     (0x3 << 0)
 440
 441 /* CM_FCLKEN_DSS */
 442 #define OMAP3430_EN_TV                                  (1 << 2)
 443 #define OMAP3430_EN_TV_SHIFT                                   2
 444 #define OMAP3430_EN_DSS2                                (1 << 1)
 445 #define OMAP3430_EN_DSS2_SHIFT                          1
 446 #define OMAP3430_EN_DSS1                                (1 << 0)
 447 #define OMAP3430_EN_DSS1_SHIFT                          0
 448
 449 /* CM_ICLKEN_DSS */
 450 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS                   (1 << 0)
 451 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT             0
 452
 453 /* CM_IDLEST_DSS */
 454 #define OMAP3430_ST_DSS                                 (1 << 0)
 455
 456 /* CM_AUTOIDLE_DSS */
 457 #define OMAP3430_AUTO_DSS                               (1 << 0)
 458 #define OMAP3430_AUTO_DSS_SHIFT                         0
 459
 460 /* CM_CLKSEL_DSS */
 461 #define OMAP3430_CLKSEL_TV_SHIFT                        8
 462 #define OMAP3430_CLKSEL_TV_MASK                         (0x1f << 8)
 463 #define OMAP3430_CLKSEL_DSS1_SHIFT                      0
 464 #define OMAP3430_CLKSEL_DSS1_MASK                       (0x1f << 0)
 465
 466 /* CM_SLEEPDEP_DSS specific bits */
 467
 468 /* CM_CLKSTCTRL_DSS */
 469 #define OMAP3430_CLKTRCTRL_DSS_SHIFT                    0
 470 #define OMAP3430_CLKTRCTRL_DSS_MASK                     (0x3 << 0)
 471
 472 /* CM_CLKSTST_DSS */
 473 #define OMAP3430_CLKACTIVITY_DSS                        (1 << 0)
 474
 475 /* CM_FCLKEN_CAM specific bits */
 476
 477 /* CM_ICLKEN_CAM specific bits */
 478
 479 /* CM_IDLEST_CAM */
 480 #define OMAP3430_ST_CAM                                 (1 << 0)
 481
 482 /* CM_AUTOIDLE_CAM */
 483 #define OMAP3430_AUTO_CAM                               (1 << 0)
 484 #define OMAP3430_AUTO_CAM_SHIFT                         0
 485
 486 /* CM_CLKSEL_CAM */
 487 #define OMAP3430_CLKSEL_CAM_SHIFT                       0
 488 #define OMAP3430_CLKSEL_CAM_MASK                        (0x1f << 0)
 489
 490 /* CM_SLEEPDEP_CAM specific bits */
 491
 492 /* CM_CLKSTCTRL_CAM */
 493 #define OMAP3430_CLKTRCTRL_CAM_SHIFT                    0
 494 #define OMAP3430_CLKTRCTRL_CAM_MASK                     (0x3 << 0)
 495
 496 /* CM_CLKSTST_CAM */
 497 #define OMAP3430_CLKACTIVITY_CAM                        (1 << 0)
 498
 499 /* CM_FCLKEN_PER specific bits */
 500
 501 /* CM_ICLKEN_PER specific bits */
 502
 503 /* CM_IDLEST_PER */
 504 #define OMAP3430_ST_WDT3                                (1 << 12)
 505 #define OMAP3430_ST_MCBSP4                              (1 << 2)
 506 #define OMAP3430_ST_MCBSP3                              (1 << 1)
 507 #define OMAP3430_ST_MCBSP2                              (1 << 0)
 508
 509 /* CM_AUTOIDLE_PER */
 510 #define OMAP3430_AUTO_GPIO6                             (1 << 17)
 511 #define OMAP3430_AUTO_GPIO6_SHIFT                       17
 512 #define OMAP3430_AUTO_GPIO5                             (1 << 16)
 513 #define OMAP3430_AUTO_GPIO5_SHIFT                       16
 514 #define OMAP3430_AUTO_GPIO4                             (1 << 15)
 515 #define OMAP3430_AUTO_GPIO4_SHIFT                       15
 516 #define OMAP3430_AUTO_GPIO3                             (1 << 14)
 517 #define OMAP3430_AUTO_GPIO3_SHIFT                       14
 518 #define OMAP3430_AUTO_GPIO2                             (1 << 13)
 519 #define OMAP3430_AUTO_GPIO2_SHIFT                       13
 520 #define OMAP3430_AUTO_WDT3                              (1 << 12)
 521 #define OMAP3430_AUTO_WDT3_SHIFT                        12
 522 #define OMAP3430_AUTO_UART3                             (1 << 11)
 523 #define OMAP3430_AUTO_UART3_SHIFT                       11
 524 #define OMAP3430_AUTO_GPT9                              (1 << 10)
 525 #define OMAP3430_AUTO_GPT9_SHIFT                        10
 526 #define OMAP3430_AUTO_GPT8                              (1 << 9)
 527 #define OMAP3430_AUTO_GPT8_SHIFT                        9
 528 #define OMAP3430_AUTO_GPT7                              (1 << 8)
 529 #define OMAP3430_AUTO_GPT7_SHIFT                        8
 530 #define OMAP3430_AUTO_GPT6                              (1 << 7)
 531 #define OMAP3430_AUTO_GPT6_SHIFT                        7
 532 #define OMAP3430_AUTO_GPT5                              (1 << 6)
 533 #define OMAP3430_AUTO_GPT5_SHIFT                        6
 534 #define OMAP3430_AUTO_GPT4                              (1 << 5)
 535 #define OMAP3430_AUTO_GPT4_SHIFT                        5
 536 #define OMAP3430_AUTO_GPT3                              (1 << 4)
 537 #define OMAP3430_AUTO_GPT3_SHIFT                        4
 538 #define OMAP3430_AUTO_GPT2                              (1 << 3)
 539 #define OMAP3430_AUTO_GPT2_SHIFT                        3
 540 #define OMAP3430_AUTO_MCBSP4                            (1 << 2)
 541 #define OMAP3430_AUTO_MCBSP4_SHIFT                      2
 542 #define OMAP3430_AUTO_MCBSP3                            (1 << 1)
 543 #define OMAP3430_AUTO_MCBSP3_SHIFT                      1
 544 #define OMAP3430_AUTO_MCBSP2                            (1 << 0)
 545 #define OMAP3430_AUTO_MCBSP2_SHIFT                      0
 546
 547 /* CM_CLKSEL_PER */
 548 #define OMAP3430_CLKSEL_GPT9_MASK                       (1 << 7)
 549 #define OMAP3430_CLKSEL_GPT9_SHIFT                      7
 550 #define OMAP3430_CLKSEL_GPT8_MASK                       (1 << 6)
 551 #define OMAP3430_CLKSEL_GPT8_SHIFT                      6
 552 #define OMAP3430_CLKSEL_GPT7_MASK                       (1 << 5)
 553 #define OMAP3430_CLKSEL_GPT7_SHIFT                      5
 554 #define OMAP3430_CLKSEL_GPT6_MASK                       (1 << 4)
 555 #define OMAP3430_CLKSEL_GPT6_SHIFT                      4
 556 #define OMAP3430_CLKSEL_GPT5_MASK                       (1 << 3)
 557 #define OMAP3430_CLKSEL_GPT5_SHIFT                      3
 558 #define OMAP3430_CLKSEL_GPT4_MASK                       (1 << 2)
 559 #define OMAP3430_CLKSEL_GPT4_SHIFT                      2
 560 #define OMAP3430_CLKSEL_GPT3_MASK                       (1 << 1)
 561 #define OMAP3430_CLKSEL_GPT3_SHIFT                      1
 562 #define OMAP3430_CLKSEL_GPT2_MASK                       (1 << 0)
 563 #define OMAP3430_CLKSEL_GPT2_SHIFT                      0
 564
 565 /* CM_SLEEPDEP_PER specific bits */
 566 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2                (1 << 2)
 567
 568 /* CM_CLKSTCTRL_PER */
 569 #define OMAP3430_CLKTRCTRL_PER_SHIFT                    0
 570 #define OMAP3430_CLKTRCTRL_PER_MASK                     (0x3 << 0)
 571
 572 /* CM_CLKSTST_PER */
 573 #define OMAP3430_CLKACTIVITY_PER                        (1 << 0)
 574
 575 /* CM_CLKSEL1_EMU */
 576 #define OMAP3430_DIV_DPLL4_SHIFT                        24
 577 #define OMAP3430_DIV_DPLL4_MASK                         (0x1f << 24)
 578 #define OMAP3430_DIV_DPLL3_SHIFT                        16
 579 #define OMAP3430_DIV_DPLL3_MASK                         (0x1f << 16)
 580 #define OMAP3430_CLKSEL_TRACECLK_SHIFT                  11
 581 #define OMAP3430_CLKSEL_TRACECLK_MASK                   (0x7 << 11)
 582 #define OMAP3430_CLKSEL_PCLK_SHIFT                      8
 583 #define OMAP3430_CLKSEL_PCLK_MASK                       (0x7 << 8)
 584 #define OMAP3430_CLKSEL_PCLKX2_SHIFT                    6
 585 #define OMAP3430_CLKSEL_PCLKX2_MASK                     (0x3 << 6)
 586 #define OMAP3430_CLKSEL_ATCLK_SHIFT                     4
 587 #define OMAP3430_CLKSEL_ATCLK_MASK                      (0x3 << 4)
 588 #define OMAP3430_TRACE_MUX_CTRL_SHIFT                   2
 589 #define OMAP3430_TRACE_MUX_CTRL_MASK                    (0x3 << 2)
 590 #define OMAP3430_MUX_CTRL_SHIFT                         0
 591 #define OMAP3430_MUX_CTRL_MASK                          (0x3 << 0)
 592
 593 /* CM_CLKSTCTRL_EMU */
 594 #define OMAP3430_CLKTRCTRL_EMU_SHIFT                    0
 595 #define OMAP3430_CLKTRCTRL_EMU_MASK                     (0x3 << 0)
 596
 597 /* CM_CLKSTST_EMU */
 598 #define OMAP3430_CLKACTIVITY_EMU                        (1 << 0)
 599
 600 /* CM_CLKSEL2_EMU specific bits */
 601 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT               8
 602 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK                (0x7ff << 8)
 603 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT                0
 604 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK                 (0x7f << 0)
 605
 606 /* CM_CLKSEL3_EMU specific bits */
 607 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT             8
 608 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK              (0x7ff << 8)
 609 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT              0
 610 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK               (0x7f << 0)
 611
 612 /* CM_POLCTRL */
 613 #define OMAP3430_CLKOUT2_POL                            (1 << 0)
 614
 615 /* CM_IDLEST_NEON */
 616 #define OMAP3430_ST_NEON                                (1 << 0)
 617
 618 /* CM_CLKSTCTRL_NEON */
 619 #define OMAP3430_CLKTRCTRL_NEON_SHIFT                   0
 620 #define OMAP3430_CLKTRCTRL_NEON_MASK                    (0x3 << 0)
 621
 622 /* CM_FCLKEN_USBHOST */
 623 #define OMAP3430ES2_EN_USBHOST2_SHIFT                   1
 624 #define OMAP3430ES2_EN_USBHOST2_MASK                    (1 << 1)
 625 #define OMAP3430ES2_EN_USBHOST1_SHIFT                   0
 626 #define OMAP3430ES2_EN_USBHOST1_MASK                    (1 << 0)
 627
 628 /* CM_ICLKEN_USBHOST */
 629 #define OMAP3430ES2_EN_USBHOST_SHIFT                    0
 630 #define OMAP3430ES2_EN_USBHOST_MASK                     (1 << 0)
 631
 632 #endif