arch/arm/mach-omap2/cm_regbits_34xx.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
   2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
   3
   4 /*
   5  * OMAP3430 Clock Management register bits
   6  *
   7  * Copyright (C) 2007 Texas Instruments, Inc.
   8  * Copyright (C) 2007 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "cm.h"
  18
  19 /* Bits shared between registers */
  20
  21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
  22 #define OMAP3430_EN_MSPRO                               (1 << 23)
  23 #define OMAP3430_EN_MSPRO_SHIFT                         23
  24 #define OMAP3430_EN_HDQ                                 (1 << 22)
  25 #define OMAP3430_EN_HDQ_SHIFT                           22
  26 #define OMAP3430_EN_SSI                                 (1 << 0)
  27 #define OMAP3430_EN_SSI_SHIFT                           0
  28
  29 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
  30 #define OMAP3430_EN_WDT2                                (1 << 5)
  31 #define OMAP3430_EN_WDT2_SHIFT                          5
  32
  33 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
  34 #define OMAP3430_EN_CAM                                 (1 << 0)
  35 #define OMAP3430_EN_CAM_SHIFT                           0
  36
  37 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
  38 #define OMAP3430_EN_WDT3                                (1 << 12)
  39 #define OMAP3430_EN_WDT3_SHIFT                          12
  40
  41 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
  42 #define OMAP3430_OVERRIDE_ENABLE                        (1 << 19)
  43
  44
  45 /* Bits specific to each register */
  46
  47 /* CM_FCLKEN_IVA2 */
  48 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2                 (1 << 0)
  49
  50 /* CM_CLKEN_PLL_IVA2 */
  51 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT               8
  52 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK                (0x3 << 8)
  53 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT                4
  54 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK                 (0xf << 4)
  55 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT          3
  56 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK           (1 << 3)
  57 #define OMAP3430_EN_IVA2_DPLL_SHIFT                     0
  58 #define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
  59
  60 /* CM_IDLEST_IVA2 */
  61 #define OMAP3430_ST_IVA2                                (1 << 0)
  62
  63 /* CM_IDLEST_PLL_IVA2 */
  64 #define OMAP3430_ST_IVA2_CLK                            (1 << 0)
  65
  66 /* CM_AUTOIDLE_PLL_IVA2 */
  67 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
  68 #define OMAP3430_AUTO_IVA2_DPLL_MASK                    (0x7 << 0)
  69
  70 /* CM_CLKSEL1_PLL_IVA2 */
  71 #define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
  72 #define OMAP3430_IVA2_CLK_SRC_MASK                      (0x3 << 19)
  73 #define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
  74 #define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
  75 #define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
  76 #define OMAP3430_IVA2_DPLL_DIV_MASK                     (0x7f << 0)
  77
  78 /* CM_CLKSEL2_PLL_IVA2 */
  79 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT             0
  80 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK              (0x1f << 0)
  81
  82 /* CM_CLKSTCTRL_IVA2 */
  83 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT                   0
  84 #define OMAP3430_CLKTRCTRL_IVA2_MASK                    (0x3 << 0)
  85
  86 /* CM_CLKSTST_IVA2 */
  87 #define OMAP3430_CLKACTIVITY_IVA2                       (1 << 0)
  88
  89 /* CM_REVISION specific bits */
  90
  91 /* CM_SYSCONFIG specific bits */
  92
  93 /* CM_CLKEN_PLL_MPU */
  94 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT                8
  95 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK                 (0x3 << 8)
  96 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT                 4
  97 #define OMAP3430_MPU_DPLL_FREQSEL_MASK                  (0xf << 4)
  98 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT           3
  99 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK            (1 << 3)
 100 #define OMAP3430_EN_MPU_DPLL_SHIFT                      0
 101 #define OMAP3430_EN_MPU_DPLL_MASK                       (0x7 << 0)
 102
 103 /* CM_IDLEST_MPU */
 104 #define OMAP3430_ST_MPU                                 (1 << 0)
 105
 106 /* CM_IDLEST_PLL_MPU */
 107 #define OMAP3430_ST_MPU_CLK                             (1 << 0)
 108
 109 /* CM_AUTOIDLE_PLL_MPU */
 110 #define OMAP3430_AUTO_MPU_DPLL_SHIFT                    0
 111 #define OMAP3430_AUTO_MPU_DPLL_MASK                     (0x7 << 0)
 112
 113 /* CM_CLKSEL1_PLL_MPU */
 114 #define OMAP3430_MPU_CLK_SRC_SHIFT                      19
 115 #define OMAP3430_MPU_CLK_SRC_MASK                       (0x3 << 19)
 116 #define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
 117 #define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
 118 #define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
 119 #define OMAP3430_MPU_DPLL_DIV_MASK                      (0x7f << 0)
 120
 121 /* CM_CLKSEL2_PLL_MPU */
 122 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT              0
 123 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK               (0x1f << 0)
 124
 125 /* CM_CLKSTCTRL_MPU */
 126 #define OMAP3430_CLKTRCTRL_MPU_SHIFT                    0
 127 #define OMAP3430_CLKTRCTRL_MPU_MASK                     (0x3 << 0)
 128
 129 /* CM_CLKSTST_MPU */
 130 #define OMAP3430_CLKACTIVITY_MPU                        (1 << 0)
 131
 132 /* CM_FCLKEN1_CORE specific bits */
 133
 134 /* CM_ICLKEN1_CORE specific bits */
 135 #define OMAP3430_EN_ICR                                 (1 << 29)
 136 #define OMAP3430_EN_ICR_SHIFT                           29
 137 #define OMAP3430_EN_AES2                                (1 << 28)
 138 #define OMAP3430_EN_AES2_SHIFT                          28
 139 #define OMAP3430_EN_SHA12                               (1 << 27)
 140 #define OMAP3430_EN_SHA12_SHIFT                         27
 141 #define OMAP3430_EN_DES2                                (1 << 26)
 142 #define OMAP3430_EN_DES2_SHIFT                          26
 143 #define OMAP3430_EN_FAC                                 (1 << 8)
 144 #define OMAP3430_EN_FAC_SHIFT                           8
 145 #define OMAP3430_EN_MAILBOXES                           (1 << 7)
 146 #define OMAP3430_EN_MAILBOXES_SHIFT                     7
 147 #define OMAP3430_EN_OMAPCTRL                            (1 << 6)
 148 #define OMAP3430_EN_OMAPCTRL_SHIFT                      6
 149 #define OMAP3430_EN_SDRC                                (1 << 1)
 150 #define OMAP3430_EN_SDRC_SHIFT                          1
 151
 152 /* CM_ICLKEN2_CORE */
 153 #define OMAP3430_EN_PKA                                 (1 << 4)
 154 #define OMAP3430_EN_PKA_SHIFT                           4
 155 #define OMAP3430_EN_AES1                                (1 << 3)
 156 #define OMAP3430_EN_AES1_SHIFT                          3
 157 #define OMAP3430_EN_RNG                                 (1 << 2)
 158 #define OMAP3430_EN_RNG_SHIFT                           2
 159 #define OMAP3430_EN_SHA11                               (1 << 1)
 160 #define OMAP3430_EN_SHA11_SHIFT                         1
 161 #define OMAP3430_EN_DES1                                (1 << 0)
 162 #define OMAP3430_EN_DES1_SHIFT                          0
 163
 164 /* CM_IDLEST1_CORE specific bits */
 165 #define OMAP3430_ST_ICR                                 (1 << 29)
 166 #define OMAP3430_ST_AES2                                (1 << 28)
 167 #define OMAP3430_ST_SHA12                               (1 << 27)
 168 #define OMAP3430_ST_DES2                                (1 << 26)
 169 #define OMAP3430_ST_MSPRO                               (1 << 23)
 170 #define OMAP3430_ST_HDQ                                 (1 << 22)
 171 #define OMAP3430_ST_FAC                                 (1 << 8)
 172 #define OMAP3430_ST_MAILBOXES                           (1 << 7)
 173 #define OMAP3430_ST_OMAPCTRL                            (1 << 6)
 174 #define OMAP3430_ST_SDMA                                (1 << 2)
 175 #define OMAP3430_ST_SDRC                                (1 << 1)
 176 #define OMAP3430_ST_SSI                                 (1 << 0)
 177
 178 /* CM_IDLEST2_CORE */
 179 #define OMAP3430_ST_PKA                                 (1 << 4)
 180 #define OMAP3430_ST_AES1                                (1 << 3)
 181 #define OMAP3430_ST_RNG                                 (1 << 2)
 182 #define OMAP3430_ST_SHA11                               (1 << 1)
 183 #define OMAP3430_ST_DES1                                (1 << 0)
 184
 185 /* CM_AUTOIDLE1_CORE */
 186 #define OMAP3430_AUTO_AES2                              (1 << 28)
 187 #define OMAP3430_AUTO_AES2_SHIFT                        28
 188 #define OMAP3430_AUTO_SHA12                             (1 << 27)
 189 #define OMAP3430_AUTO_SHA12_SHIFT                       27
 190 #define OMAP3430_AUTO_DES2                              (1 << 26)
 191 #define OMAP3430_AUTO_DES2_SHIFT                        26
 192 #define OMAP3430_AUTO_MMC2                              (1 << 25)
 193 #define OMAP3430_AUTO_MMC2_SHIFT                        25
 194 #define OMAP3430_AUTO_MMC1                              (1 << 24)
 195 #define OMAP3430_AUTO_MMC1_SHIFT                        24
 196 #define OMAP3430_AUTO_MSPRO                             (1 << 23)
 197 #define OMAP3430_AUTO_MSPRO_SHIFT                       23
 198 #define OMAP3430_AUTO_HDQ                               (1 << 22)
 199 #define OMAP3430_AUTO_HDQ_SHIFT                         22
 200 #define OMAP3430_AUTO_MCSPI4                            (1 << 21)
 201 #define OMAP3430_AUTO_MCSPI4_SHIFT                      21
 202 #define OMAP3430_AUTO_MCSPI3                            (1 << 20)
 203 #define OMAP3430_AUTO_MCSPI3_SHIFT                      20
 204 #define OMAP3430_AUTO_MCSPI2                            (1 << 19)
 205 #define OMAP3430_AUTO_MCSPI2_SHIFT                      19
 206 #define OMAP3430_AUTO_MCSPI1                            (1 << 18)
 207 #define OMAP3430_AUTO_MCSPI1_SHIFT                      18
 208 #define OMAP3430_AUTO_I2C3                              (1 << 17)
 209 #define OMAP3430_AUTO_I2C3_SHIFT                        17
 210 #define OMAP3430_AUTO_I2C2                              (1 << 16)
 211 #define OMAP3430_AUTO_I2C2_SHIFT                        16
 212 #define OMAP3430_AUTO_I2C1                              (1 << 15)
 213 #define OMAP3430_AUTO_I2C1_SHIFT                        15
 214 #define OMAP3430_AUTO_UART2                             (1 << 14)
 215 #define OMAP3430_AUTO_UART2_SHIFT                       14
 216 #define OMAP3430_AUTO_UART1                             (1 << 13)
 217 #define OMAP3430_AUTO_UART1_SHIFT                       13
 218 #define OMAP3430_AUTO_GPT11                             (1 << 12)
 219 #define OMAP3430_AUTO_GPT11_SHIFT                       12
 220 #define OMAP3430_AUTO_GPT10                             (1 << 11)
 221 #define OMAP3430_AUTO_GPT10_SHIFT                       11
 222 #define OMAP3430_AUTO_MCBSP5                            (1 << 10)
 223 #define OMAP3430_AUTO_MCBSP5_SHIFT                      10
 224 #define OMAP3430_AUTO_MCBSP1                            (1 << 9)
 225 #define OMAP3430_AUTO_MCBSP1_SHIFT                      9
 226 #define OMAP3430_AUTO_FAC                               (1 << 8)
 227 #define OMAP3430_AUTO_FAC_SHIFT                         8
 228 #define OMAP3430_AUTO_MAILBOXES                         (1 << 7)
 229 #define OMAP3430_AUTO_MAILBOXES_SHIFT                   7
 230 #define OMAP3430_AUTO_OMAPCTRL                          (1 << 6)
 231 #define OMAP3430_AUTO_OMAPCTRL_SHIFT                    6
 232 #define OMAP3430_AUTO_FSHOSTUSB                         (1 << 5)
 233 #define OMAP3430_AUTO_FSHOSTUSB_SHIFT                   5
 234 #define OMAP3430_AUTO_HSOTGUSB                          (1 << 4)
 235 #define OMAP3430_AUTO_HSOTGUSB_SHIFT                    4
 236 #define OMAP3430_AUTO_D2D                               (1 << 3)
 237 #define OMAP3430_AUTO_D2D_SHIFT                         3
 238 #define OMAP3430_AUTO_SSI                               (1 << 0)
 239 #define OMAP3430_AUTO_SSI_SHIFT                         0
 240
 241 /* CM_AUTOIDLE2_CORE */
 242 #define OMAP3430_AUTO_PKA                               (1 << 4)
 243 #define OMAP3430_AUTO_PKA_SHIFT                         4
 244 #define OMAP3430_AUTO_AES1                              (1 << 3)
 245 #define OMAP3430_AUTO_AES1_SHIFT                        3
 246 #define OMAP3430_AUTO_RNG                               (1 << 2)
 247 #define OMAP3430_AUTO_RNG_SHIFT                         2
 248 #define OMAP3430_AUTO_SHA11                             (1 << 1)
 249 #define OMAP3430_AUTO_SHA11_SHIFT                       1
 250 #define OMAP3430_AUTO_DES1                              (1 << 0)
 251 #define OMAP3430_AUTO_DES1_SHIFT                        0
 252
 253 /* CM_CLKSEL_CORE */
 254 #define OMAP3430_CLKSEL_SSI_SHIFT                       8
 255 #define OMAP3430_CLKSEL_SSI_MASK                        (0xf << 8)
 256 #define OMAP3430_CLKSEL_GPT11_MASK                      (1 << 7)
 257 #define OMAP3430_CLKSEL_GPT11_SHIFT                     7
 258 #define OMAP3430_CLKSEL_GPT10_MASK                      (1 << 6)
 259 #define OMAP3430_CLKSEL_GPT10_SHIFT                     6
 260 #define OMAP3430_CLKSEL_FSHOSTUSB_SHIFT                 4
 261 #define OMAP3430_CLKSEL_FSHOSTUSB_MASK                  (0x3 << 4)
 262 #define OMAP3430_CLKSEL_L4_SHIFT                        2
 263 #define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
 264 #define OMAP3430_CLKSEL_L3_SHIFT                        0
 265 #define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
 266
 267 /* CM_CLKSTCTRL_CORE */
 268 #define OMAP3430_CLKTRCTRL_D2D_SHIFT                    4
 269 #define OMAP3430_CLKTRCTRL_D2D_MASK                     (0x3 << 4)
 270 #define OMAP3430_CLKTRCTRL_L4_SHIFT                     2
 271 #define OMAP3430_CLKTRCTRL_L4_MASK                      (0x3 << 2)
 272 #define OMAP3430_CLKTRCTRL_L3_SHIFT                     0
 273 #define OMAP3430_CLKTRCTRL_L3_MASK                      (0x3 << 0)
 274
 275 /* CM_CLKSTST_CORE */
 276 #define OMAP3430_CLKACTIVITY_D2D                        (1 << 2)
 277 #define OMAP3430_CLKACTIVITY_L4                         (1 << 1)
 278 #define OMAP3430_CLKACTIVITY_L3                         (1 << 0)
 279
 280 /* CM_FCLKEN_GFX */
 281 #define OMAP3430_EN_3D                                  (1 << 2)
 282 #define OMAP3430_EN_3D_SHIFT                            2
 283 #define OMAP3430_EN_2D                                  (1 << 1)
 284 #define OMAP3430_EN_2D_SHIFT                            1
 285
 286 /* CM_ICLKEN_GFX specific bits */
 287
 288 /* CM_IDLEST_GFX specific bits */
 289
 290 /* CM_CLKSEL_GFX specific bits */
 291
 292 /* CM_SLEEPDEP_GFX specific bits */
 293
 294 /* CM_CLKSTCTRL_GFX */
 295 #define OMAP3430_CLKTRCTRL_GFX_SHIFT                    0
 296 #define OMAP3430_CLKTRCTRL_GFX_MASK                     (0x3 << 0)
 297
 298 /* CM_CLKSTST_GFX */
 299 #define OMAP3430_CLKACTIVITY_GFX                        (1 << 0)
 300
 301 /* CM_FCLKEN_WKUP specific bits */
 302
 303 /* CM_ICLKEN_WKUP specific bits */
 304 #define OMAP3430_EN_WDT1                                (1 << 4)
 305 #define OMAP3430_EN_WDT1_SHIFT                          4
 306 #define OMAP3430_EN_32KSYNC                             (1 << 2)
 307 #define OMAP3430_EN_32KSYNC_SHIFT                              2
 308
 309 /* CM_IDLEST_WKUP specific bits */
 310 #define OMAP3430_ST_WDT2                                (1 << 5)
 311 #define OMAP3430_ST_WDT1                                (1 << 4)
 312 #define OMAP3430_ST_32KSYNC                             (1 << 2)
 313
 314 /* CM_AUTOIDLE_WKUP */
 315 #define OMAP3430_AUTO_WDT2                              (1 << 5)
 316 #define OMAP3430_AUTO_WDT2_SHIFT                        5
 317 #define OMAP3430_AUTO_WDT1                              (1 << 4)
 318 #define OMAP3430_AUTO_WDT1_SHIFT                        4
 319 #define OMAP3430_AUTO_GPIO1                             (1 << 3)
 320 #define OMAP3430_AUTO_GPIO1_SHIFT                       3
 321 #define OMAP3430_AUTO_32KSYNC                           (1 << 2)
 322 #define OMAP3430_AUTO_32KSYNC_SHIFT                     2
 323 #define OMAP3430_AUTO_GPT12                             (1 << 1)
 324 #define OMAP3430_AUTO_GPT12_SHIFT                       1
 325 #define OMAP3430_AUTO_GPT1                              (1 << 0)
 326 #define OMAP3430_AUTO_GPT1_SHIFT                        0
 327
 328 /* CM_CLKSEL_WKUP */
 329 #define OMAP3430_CLKSEL_RM_SHIFT                        1
 330 #define OMAP3430_CLKSEL_RM_MASK                         (0x3 << 1)
 331 #define OMAP3430_CLKSEL_GPT1_MASK                       (1 << 0)
 332 #define OMAP3430_CLKSEL_GPT1_SHIFT                      0
 333
 334 /* CM_CLKEN_PLL */
 335 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT                 31
 336 #define OMAP3430_PWRDN_CAM_SHIFT                        30
 337 #define OMAP3430_PWRDN_DSS1_SHIFT                       29
 338 #define OMAP3430_PWRDN_TV_SHIFT                         28
 339 #define OMAP3430_PWRDN_96M_SHIFT                        27
 340 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT             24
 341 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK              (0x3 << 24)
 342 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT              20
 343 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK               (0xf << 20)
 344 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT        19
 345 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK         (1 << 19)
 346 #define OMAP3430_EN_PERIPH_DPLL_SHIFT                   16
 347 #define OMAP3430_EN_PERIPH_DPLL_MASK                    (0x7 << 16)
 348 #define OMAP3430_PWRDN_EMU_CORE_SHIFT                   12
 349 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT               8
 350 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK                (0x3 << 8)
 351 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT                4
 352 #define OMAP3430_CORE_DPLL_FREQSEL_MASK                 (0xf << 4)
 353 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT          3
 354 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK           (1 << 3)
 355 #define OMAP3430_EN_CORE_DPLL_SHIFT                     0
 356 #define OMAP3430_EN_CORE_DPLL_MASK                      (0x7 << 0)
 357
 358 /* CM_IDLEST_CKGEN */
 359 #define OMAP3430_ST_54M_CLK                             (1 << 5)
 360 #define OMAP3430_ST_12M_CLK                             (1 << 4)
 361 #define OMAP3430_ST_48M_CLK                             (1 << 3)
 362 #define OMAP3430_ST_96M_CLK                             (1 << 2)
 363 #define OMAP3430_ST_PERIPH_CLK                          (1 << 1)
 364 #define OMAP3430_ST_CORE_CLK                            (1 << 0)
 365
 366 /* CM_AUTOIDLE_PLL */
 367 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT                 3
 368 #define OMAP3430_AUTO_PERIPH_DPLL_MASK                  (0x7 << 3)
 369 #define OMAP3430_AUTO_CORE_DPLL_SHIFT                   0
 370 #define OMAP3430_AUTO_CORE_DPLL_MASK                    (0x7 << 0)
 371
 372 /* CM_CLKSEL1_PLL */
 373 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
 374 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK              (0x3 << 27)
 375 #define OMAP3430_CORE_DPLL_MULT_SHIFT                   16
 376 #define OMAP3430_CORE_DPLL_MULT_MASK                    (0x7ff << 16)
 377 #define OMAP3430_CORE_DPLL_DIV_SHIFT                    8
 378 #define OMAP3430_CORE_DPLL_DIV_MASK                     (0x7f << 8)
 379 #define OMAP3430_SOURCE_54M                             (1 << 5)
 380 #define OMAP3430_SOURCE_48M                             (1 << 3)
 381
 382 /* CM_CLKSEL2_PLL */
 383 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT                 8
 384 #define OMAP3430_PERIPH_DPLL_MULT_MASK                  (0x7ff << 8)
 385 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT                  0
 386 #define OMAP3430_PERIPH_DPLL_DIV_MASK                   (0x7f << 0)
 387
 388 /* CM_CLKSEL3_PLL */
 389 #define OMAP3430_DIV_96M_SHIFT                          0
 390 #define OMAP3430_DIV_96M_MASK                           (0x1f << 0)
 391
 392 /* CM_CLKOUT_CTRL */
 393 #define OMAP3430_CLKOUT2_EN_SHIFT                       7
 394 #define OMAP3430_CLKOUT2_EN                             (1 << 7)
 395 #define OMAP3430_CLKOUT2_DIV_SHIFT                      3
 396 #define OMAP3430_CLKOUT2_DIV_MASK                       (0x7 << 3)
 397 #define OMAP3430_CLKOUT2SOURCE_SHIFT                    0
 398 #define OMAP3430_CLKOUT2SOURCE_MASK                     (0x3 << 0)
 399
 400 /* CM_FCLKEN_DSS */
 401 #define OMAP3430_EN_TV                                  (1 << 2)
 402 #define OMAP3430_EN_TV_SHIFT                                   2
 403 #define OMAP3430_EN_DSS2                                (1 << 1)
 404 #define OMAP3430_EN_DSS2_SHIFT                          1
 405 #define OMAP3430_EN_DSS1                                (1 << 0)
 406 #define OMAP3430_EN_DSS1_SHIFT                          0
 407
 408 /* CM_ICLKEN_DSS */
 409 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS                   (1 << 0)
 410 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT             0
 411
 412 /* CM_IDLEST_DSS */
 413 #define OMAP3430_ST_DSS                                 (1 << 0)
 414
 415 /* CM_AUTOIDLE_DSS */
 416 #define OMAP3430_AUTO_DSS                               (1 << 0)
 417 #define OMAP3430_AUTO_DSS_SHIFT                         0
 418
 419 /* CM_CLKSEL_DSS */
 420 #define OMAP3430_CLKSEL_TV_SHIFT                        8
 421 #define OMAP3430_CLKSEL_TV_MASK                         (0x1f << 8)
 422 #define OMAP3430_CLKSEL_DSS1_SHIFT                      0
 423 #define OMAP3430_CLKSEL_DSS1_MASK                       (0x1f << 0)
 424
 425 /* CM_SLEEPDEP_DSS specific bits */
 426
 427 /* CM_CLKSTCTRL_DSS */
 428 #define OMAP3430_CLKTRCTRL_DSS_SHIFT                    0
 429 #define OMAP3430_CLKTRCTRL_DSS_MASK                     (0x3 << 0)
 430
 431 /* CM_CLKSTST_DSS */
 432 #define OMAP3430_CLKACTIVITY_DSS                        (1 << 0)
 433
 434 /* CM_FCLKEN_CAM specific bits */
 435
 436 /* CM_ICLKEN_CAM specific bits */
 437
 438 /* CM_IDLEST_CAM */
 439 #define OMAP3430_ST_CAM                                 (1 << 0)
 440
 441 /* CM_AUTOIDLE_CAM */
 442 #define OMAP3430_AUTO_CAM                               (1 << 0)
 443 #define OMAP3430_AUTO_CAM_SHIFT                         0
 444
 445 /* CM_CLKSEL_CAM */
 446 #define OMAP3430_CLKSEL_CAM_SHIFT                       0
 447 #define OMAP3430_CLKSEL_CAM_MASK                        (0x1f << 0)
 448
 449 /* CM_SLEEPDEP_CAM specific bits */
 450
 451 /* CM_CLKSTCTRL_CAM */
 452 #define OMAP3430_CLKTRCTRL_CAM_SHIFT                    0
 453 #define OMAP3430_CLKTRCTRL_CAM_MASK                     (0x3 << 0)
 454
 455 /* CM_CLKSTST_CAM */
 456 #define OMAP3430_CLKACTIVITY_CAM                        (1 << 0)
 457
 458 /* CM_FCLKEN_PER specific bits */
 459
 460 /* CM_ICLKEN_PER specific bits */
 461
 462 /* CM_IDLEST_PER */
 463 #define OMAP3430_ST_WDT3                                (1 << 12)
 464 #define OMAP3430_ST_MCBSP4                              (1 << 2)
 465 #define OMAP3430_ST_MCBSP3                              (1 << 1)
 466 #define OMAP3430_ST_MCBSP2                              (1 << 0)
 467
 468 /* CM_AUTOIDLE_PER */
 469 #define OMAP3430_AUTO_GPIO6                             (1 << 17)
 470 #define OMAP3430_AUTO_GPIO6_SHIFT                       17
 471 #define OMAP3430_AUTO_GPIO5                             (1 << 16)
 472 #define OMAP3430_AUTO_GPIO5_SHIFT                       16
 473 #define OMAP3430_AUTO_GPIO4                             (1 << 15)
 474 #define OMAP3430_AUTO_GPIO4_SHIFT                       15
 475 #define OMAP3430_AUTO_GPIO3                             (1 << 14)
 476 #define OMAP3430_AUTO_GPIO3_SHIFT                       14
 477 #define OMAP3430_AUTO_GPIO2                             (1 << 13)
 478 #define OMAP3430_AUTO_GPIO2_SHIFT                       13
 479 #define OMAP3430_AUTO_WDT3                              (1 << 12)
 480 #define OMAP3430_AUTO_WDT3_SHIFT                        12
 481 #define OMAP3430_AUTO_UART3                             (1 << 11)
 482 #define OMAP3430_AUTO_UART3_SHIFT                       11
 483 #define OMAP3430_AUTO_GPT9                              (1 << 10)
 484 #define OMAP3430_AUTO_GPT9_SHIFT                        10
 485 #define OMAP3430_AUTO_GPT8                              (1 << 9)
 486 #define OMAP3430_AUTO_GPT8_SHIFT                        9
 487 #define OMAP3430_AUTO_GPT7                              (1 << 8)
 488 #define OMAP3430_AUTO_GPT7_SHIFT                        8
 489 #define OMAP3430_AUTO_GPT6                              (1 << 7)
 490 #define OMAP3430_AUTO_GPT6_SHIFT                        7
 491 #define OMAP3430_AUTO_GPT5                              (1 << 6)
 492 #define OMAP3430_AUTO_GPT5_SHIFT                        6
 493 #define OMAP3430_AUTO_GPT4                              (1 << 5)
 494 #define OMAP3430_AUTO_GPT4_SHIFT                        5
 495 #define OMAP3430_AUTO_GPT3                              (1 << 4)
 496 #define OMAP3430_AUTO_GPT3_SHIFT                        4
 497 #define OMAP3430_AUTO_GPT2                              (1 << 3)
 498 #define OMAP3430_AUTO_GPT2_SHIFT                        3
 499 #define OMAP3430_AUTO_MCBSP4                            (1 << 2)
 500 #define OMAP3430_AUTO_MCBSP4_SHIFT                      2
 501 #define OMAP3430_AUTO_MCBSP3                            (1 << 1)
 502 #define OMAP3430_AUTO_MCBSP3_SHIFT                      1
 503 #define OMAP3430_AUTO_MCBSP2                            (1 << 0)
 504 #define OMAP3430_AUTO_MCBSP2_SHIFT                      0
 505
 506 /* CM_CLKSEL_PER */
 507 #define OMAP3430_CLKSEL_GPT9_MASK                       (1 << 7)
 508 #define OMAP3430_CLKSEL_GPT9_SHIFT                      7
 509 #define OMAP3430_CLKSEL_GPT8_MASK                       (1 << 6)
 510 #define OMAP3430_CLKSEL_GPT8_SHIFT                      6
 511 #define OMAP3430_CLKSEL_GPT7_MASK                       (1 << 5)
 512 #define OMAP3430_CLKSEL_GPT7_SHIFT                      5
 513 #define OMAP3430_CLKSEL_GPT6_MASK                       (1 << 4)
 514 #define OMAP3430_CLKSEL_GPT6_SHIFT                      4
 515 #define OMAP3430_CLKSEL_GPT5_MASK                       (1 << 3)
 516 #define OMAP3430_CLKSEL_GPT5_SHIFT                      3
 517 #define OMAP3430_CLKSEL_GPT4_MASK                       (1 << 2)
 518 #define OMAP3430_CLKSEL_GPT4_SHIFT                      2
 519 #define OMAP3430_CLKSEL_GPT3_MASK                       (1 << 1)
 520 #define OMAP3430_CLKSEL_GPT3_SHIFT                      1
 521 #define OMAP3430_CLKSEL_GPT2_MASK                       (1 << 0)
 522 #define OMAP3430_CLKSEL_GPT2_SHIFT                      0
 523
 524 /* CM_SLEEPDEP_PER specific bits */
 525 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2                (1 << 2)
 526
 527 /* CM_CLKSTCTRL_PER */
 528 #define OMAP3430_CLKTRCTRL_PER_SHIFT                    0
 529 #define OMAP3430_CLKTRCTRL_PER_MASK                     (0x3 << 0)
 530
 531 /* CM_CLKSTST_PER */
 532 #define OMAP3430_CLKACTIVITY_PER                        (1 << 0)
 533
 534 /* CM_CLKSEL1_EMU */
 535 #define OMAP3430_DIV_DPLL4_SHIFT                        24
 536 #define OMAP3430_DIV_DPLL4_MASK                         (0x1f << 24)
 537 #define OMAP3430_DIV_DPLL3_SHIFT                        16
 538 #define OMAP3430_DIV_DPLL3_MASK                         (0x1f << 16)
 539 #define OMAP3430_CLKSEL_TRACECLK_SHIFT                  11
 540 #define OMAP3430_CLKSEL_TRACECLK_MASK                   (0x7 << 11)
 541 #define OMAP3430_CLKSEL_PCLK_SHIFT                      8
 542 #define OMAP3430_CLKSEL_PCLK_MASK                       (0x7 << 8)
 543 #define OMAP3430_CLKSEL_PCLKX2_SHIFT                    6
 544 #define OMAP3430_CLKSEL_PCLKX2_MASK                     (0x3 << 6)
 545 #define OMAP3430_CLKSEL_ATCLK_SHIFT                     4
 546 #define OMAP3430_CLKSEL_ATCLK_MASK                      (0x3 << 4)
 547 #define OMAP3430_TRACE_MUX_CTRL_SHIFT                   2
 548 #define OMAP3430_TRACE_MUX_CTRL_MASK                    (0x3 << 2)
 549 #define OMAP3430_MUX_CTRL_SHIFT                         0
 550 #define OMAP3430_MUX_CTRL_MASK                          (0x3 << 0)
 551
 552 /* CM_CLKSTCTRL_EMU */
 553 #define OMAP3430_CLKTRCTRL_EMU_SHIFT                    0
 554 #define OMAP3430_CLKTRCTRL_EMU_MASK                     (0x3 << 0)
 555
 556 /* CM_CLKSTST_EMU */
 557 #define OMAP3430_CLKACTIVITY_EMU                        (1 << 0)
 558
 559 /* CM_CLKSEL2_EMU specific bits */
 560 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT               8
 561 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK                (0x7ff << 8)
 562 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT                0
 563 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK                 (0x7f << 0)
 564
 565 /* CM_CLKSEL3_EMU specific bits */
 566 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT             8
 567 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK              (0x7ff << 8)
 568 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT              0
 569 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK               (0x7f << 0)
 570
 571 /* CM_POLCTRL */
 572 #define OMAP3430_CLKOUT2_POL                            (1 << 0)
 573
 574 /* CM_IDLEST_NEON */
 575 #define OMAP3430_ST_NEON                                (1 << 0)
 576
 577 /* CM_CLKSTCTRL_NEON */
 578 #define OMAP3430_CLKTRCTRL_NEON_SHIFT                   0
 579 #define OMAP3430_CLKTRCTRL_NEON_MASK                    (0x3 << 0)
 580
 581 #endif