arch/arm/mach-omap2/cm.h

   1 #ifndef __ARCH_ASM_MACH_OMAP2_CM_H
   2 #define __ARCH_ASM_MACH_OMAP2_CM_H
   3
   4 /*
   5  * OMAP2/3 Clock Management (CM) register definitions
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "prcm-common.h"
  18
  19 #ifndef __ASSEMBLER__
  20 #define OMAP_CM_REGADDR(module, reg)                                    \
  21         (__force void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
  22 #endif
  23
  24 #define OMAP2420_CM_REGADDR(module, reg)                                \
  25                         IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
  26 #define OMAP2430_CM_REGADDR(module, reg)                                \
  27                         IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
  28 #define OMAP34XX_CM_REGADDR(module, reg)                                \
  29                         IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
  30
  31 /*
  32  * Architecture-specific global CM registers
  33  * Use __raw_{read,write}l() with these registers.
  34  * These registers appear once per CM module.
  35  */
  36
  37 #define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
  38 #define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
  39 #define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
  40
  41 #define OMAP3430_CM_CLKOUT_CTRL                                         \
  42                                 OMAP34XX_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
  43
  44 #ifndef __ASSEMBLER__
  45
  46 /* Read-modify-write bits in a CM register */
  47 static __inline__ u32 __attribute__((unused)) cm_rmw_reg_bits(u32 mask,
  48                                                 u32 bits, void __iomem *va)
  49 {
  50         u32 v;
  51
  52         v = __raw_readl(va);
  53         v &= ~mask;
  54         v |= bits;
  55         __raw_writel(v, va);
  56
  57         return v;
  58 }
  59
  60 #endif
  61
  62 /*
  63  * Module specific CM registers from CM_BASE + domain offset
  64  * Use cm_{read,write}_mod_reg() with these registers.
  65  * These register offsets generally appear in more than one PRCM submodule.
  66  */
  67
  68 /* Common between 24xx and 34xx */
  69
  70 #define CM_FCLKEN                                       0x0000
  71 #define CM_FCLKEN1                                      CM_FCLKEN
  72 #define CM_CLKEN                                        CM_FCLKEN
  73 #define CM_ICLKEN                                       0x0010
  74 #define CM_ICLKEN1                                      CM_ICLKEN
  75 #define CM_ICLKEN2                                      0x0014
  76 #define CM_ICLKEN3                                      0x0018
  77 #define CM_IDLEST                                       0x0020
  78 #define CM_IDLEST1                                      CM_IDLEST
  79 #define CM_IDLEST2                                      0x0024
  80 #define CM_AUTOIDLE                                     0x0030
  81 #define CM_AUTOIDLE1                                    CM_AUTOIDLE
  82 #define CM_AUTOIDLE2                                    0x0034
  83 #define CM_AUTOIDLE3                                    0x0038
  84 #define CM_CLKSEL                                       0x0040
  85 #define CM_CLKSEL1                                      CM_CLKSEL
  86 #define CM_CLKSEL2                                      0x0044
  87 #define CM_CLKSTCTRL                                    0x0048
  88
  89 /* Architecture-specific registers */
  90
  91 #define OMAP24XX_CM_FCLKEN2                             0x0004
  92 #define OMAP24XX_CM_ICLKEN4                             0x001c
  93 #define OMAP24XX_CM_AUTOIDLE4                           0x003c
  94
  95 #define OMAP2430_CM_IDLEST3                             0x0028
  96
  97 #define OMAP3430_CM_CLKEN_PLL                           0x0004
  98 #define OMAP3430ES2_CM_CLKEN2                           0x0004
  99 #define OMAP3430ES2_CM_FCLKEN3                          0x0008
 100 #define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
 101 #define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
 102 #define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
 103 #define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
 104 #define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
 105 #define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
 106 #define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
 107 #define OMAP3430_CM_CLKSEL3                             CM_CLKSTCTRL
 108 #define OMAP3430_CM_CLKSTST                             0x004c
 109 #define OMAP3430ES2_CM_CLKSEL4                          0x004c
 110 #define OMAP3430ES2_CM_CLKSEL5                          0x0050
 111 #define OMAP3430_CM_CLKSEL2_EMU                         0x0050
 112 #define OMAP3430_CM_CLKSEL3_EMU                         0x0054
 113
 114
 115 /* Clock management domain register get/set */
 116
 117 #ifndef __ASSEMBLER__
 118
 119 extern u32 cm_read_mod_reg(s16 module, u16 idx);
 120 extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
 121
 122 /* Read-modify-write bits in a CM register (by domain) */
 123 static __inline__ u32 __attribute__((unused)) cm_rmw_mod_reg_bits(u32 mask,
 124                                                 u32 bits, s16 module, s16 idx)
 125 {
 126         return cm_rmw_reg_bits(mask, bits, OMAP_CM_REGADDR(module, idx));
 127 }
 128
 129 static __inline__ u32 __attribute__((unused)) cm_set_mod_reg_bits(u32 bits,
 130                                                         s16 module, s16 idx)
 131 {
 132         return cm_rmw_mod_reg_bits(bits, bits, module, idx);
 133 }
 134
 135 static __inline__ u32 __attribute__((unused)) cm_clear_mod_reg_bits(u32 bits,
 136                                                         s16 module, s16 idx)
 137 {
 138         return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 139 }
 140
 141 #endif
 142
 143 /* CM register bits shared between 24XX and 3430 */
 144
 145 /* CM_CLKSEL_GFX */
 146 #define OMAP_CLKSEL_GFX_SHIFT                           0
 147 #define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
 148
 149 /* CM_ICLKEN_GFX */
 150 #define OMAP_EN_GFX_SHIFT                               0
 151 #define OMAP_EN_GFX                                     (1 << 0)
 152
 153 /* CM_IDLEST_GFX */
 154 #define OMAP_ST_GFX                                     (1 << 0)
 155
 156
 157 #endif