4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
7 * Written by Paul Walmsley
10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
11 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
13 #include <mach/clockdomain.h>
16 * OMAP2/3-common clockdomains
19 /* This is an implicit clockdomain - it is never defined as such in TRM */
20 static struct clockdomain wkup_clkdm = {
22 .pwrdm = { .name = "wkup_pwrdm" },
23 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
27 * 2420-only clockdomains
30 #if defined(CONFIG_ARCH_OMAP2420)
32 static struct clockdomain mpu_2420_clkdm = {
34 .pwrdm = { .name = "mpu_pwrdm" },
35 .flags = CLKDM_CAN_HWSUP,
36 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
37 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
40 static struct clockdomain iva1_2420_clkdm = {
42 .pwrdm = { .name = "dsp_pwrdm" },
43 .flags = CLKDM_CAN_HWSUP_SWSUP,
44 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
45 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
48 #endif /* CONFIG_ARCH_OMAP2420 */
52 * 2430-only clockdomains
55 #if defined(CONFIG_ARCH_OMAP2430)
57 static struct clockdomain mpu_2430_clkdm = {
59 .pwrdm = { .name = "mpu_pwrdm" },
60 .flags = CLKDM_CAN_HWSUP_SWSUP,
61 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
65 static struct clockdomain mdm_clkdm = {
67 .pwrdm = { .name = "mdm_pwrdm" },
68 .flags = CLKDM_CAN_HWSUP_SWSUP,
69 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
73 #endif /* CONFIG_ARCH_OMAP2430 */
77 * 24XX-only clockdomains
80 #if defined(CONFIG_ARCH_OMAP24XX)
82 static struct clockdomain dsp_clkdm = {
84 .pwrdm = { .name = "dsp_pwrdm" },
85 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
90 static struct clockdomain gfx_24xx_clkdm = {
92 .pwrdm = { .name = "gfx_pwrdm" },
93 .flags = CLKDM_CAN_HWSUP_SWSUP,
94 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
98 static struct clockdomain core_l3_24xx_clkdm = {
99 .name = "core_l3_clkdm",
100 .pwrdm = { .name = "core_pwrdm" },
101 .flags = CLKDM_CAN_HWSUP,
102 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
106 static struct clockdomain core_l4_24xx_clkdm = {
107 .name = "core_l4_clkdm",
108 .pwrdm = { .name = "core_pwrdm" },
109 .flags = CLKDM_CAN_HWSUP,
110 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
114 static struct clockdomain dss_24xx_clkdm = {
116 .pwrdm = { .name = "core_pwrdm" },
117 .flags = CLKDM_CAN_HWSUP,
118 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
122 #endif /* CONFIG_ARCH_OMAP24XX */
129 #if defined(CONFIG_ARCH_OMAP34XX)
131 static struct clockdomain mpu_34xx_clkdm = {
133 .pwrdm = { .name = "mpu_pwrdm" },
134 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
135 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
139 static struct clockdomain neon_clkdm = {
140 .name = "neon_clkdm",
141 .pwrdm = { .name = "neon_pwrdm" },
142 .flags = CLKDM_CAN_HWSUP_SWSUP,
143 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
144 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
147 static struct clockdomain iva2_clkdm = {
148 .name = "iva2_clkdm",
149 .pwrdm = { .name = "iva2_pwrdm" },
150 .flags = CLKDM_CAN_HWSUP_SWSUP,
151 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
155 static struct clockdomain gfx_3430es1_clkdm = {
157 .pwrdm = { .name = "gfx_pwrdm" },
158 .flags = CLKDM_CAN_HWSUP_SWSUP,
159 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
163 static struct clockdomain sgx_clkdm = {
165 .pwrdm = { .name = "sgx_pwrdm" },
166 .flags = CLKDM_CAN_HWSUP_SWSUP,
167 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
172 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
173 * then that information was removed from the 34xx ES2+ TRM. It is
174 * unclear whether the core is still there, but the clockdomain logic
175 * is there, and must be programmed to an appropriate state if the
176 * CORE clockdomain is to become inactive.
178 static struct clockdomain d2d_clkdm = {
180 .pwrdm = { .name = "core_pwrdm" },
181 .flags = CLKDM_CAN_HWSUP,
182 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
186 static struct clockdomain core_l3_34xx_clkdm = {
187 .name = "core_l3_clkdm",
188 .pwrdm = { .name = "core_pwrdm" },
189 .flags = CLKDM_CAN_HWSUP,
190 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
194 static struct clockdomain core_l4_34xx_clkdm = {
195 .name = "core_l4_clkdm",
196 .pwrdm = { .name = "core_pwrdm" },
197 .flags = CLKDM_CAN_HWSUP,
198 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
199 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
202 static struct clockdomain dss_34xx_clkdm = {
204 .pwrdm = { .name = "dss_pwrdm" },
205 .flags = CLKDM_CAN_HWSUP_SWSUP,
206 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
210 static struct clockdomain cam_clkdm = {
212 .pwrdm = { .name = "cam_pwrdm" },
213 .flags = CLKDM_CAN_HWSUP_SWSUP,
214 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
218 static struct clockdomain usbhost_clkdm = {
219 .name = "usbhost_clkdm",
220 .pwrdm = { .name = "usbhost_pwrdm" },
221 .flags = CLKDM_CAN_HWSUP_SWSUP,
222 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
226 static struct clockdomain per_clkdm = {
228 .pwrdm = { .name = "per_pwrdm" },
229 .flags = CLKDM_CAN_HWSUP_SWSUP,
230 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
234 static struct clockdomain emu_clkdm = {
236 .pwrdm = { .name = "emu_pwrdm" },
237 .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
238 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
242 #endif /* CONFIG_ARCH_OMAP34XX */
245 * Clockdomain-powerdomain hwsup dependencies (34XX only)
248 static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
250 .pwrdm = { .name = "mpu_pwrdm" },
251 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
254 .pwrdm = { .name = "iva2_pwrdm" },
255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
258 .pwrdm = { .name = NULL },
266 static struct clockdomain *clockdomains_omap[] = {
270 #ifdef CONFIG_ARCH_OMAP2420
275 #ifdef CONFIG_ARCH_OMAP2430
280 #ifdef CONFIG_ARCH_OMAP24XX
288 #ifdef CONFIG_ARCH_OMAP34XX