arch/arm/mach-omap2/clockdomains.h

   1 /*
   2  * OMAP2/3 clockdomains
   3  *
   4  * Copyright (C) 2008 Texas Instruments, Inc.
   5  * Copyright (C) 2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  */
   9
  10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
  11 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
  12
  13 #include <mach/clockdomain.h>
  14
  15 /*
  16  * OMAP2/3-common clockdomains
  17  */
  18
  19 /* This is an implicit clockdomain - it is never defined as such in TRM */
  20 static struct clockdomain wkup_clkdm = {
  21         .name           = "wkup_clkdm",
  22         .pwrdm_name     = "wkup_pwrdm",
  23         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
  24 };
  25
  26 /*
  27  * 2420-only clockdomains
  28  */
  29
  30 #if defined(CONFIG_ARCH_OMAP2420)
  31
  32 static struct clockdomain mpu_2420_clkdm = {
  33         .name           = "mpu_clkdm",
  34         .pwrdm_name     = "mpu_pwrdm",
  35         .flags          = CLKDM_CAN_HWSUP,
  36         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
  37         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  38 };
  39
  40 static struct clockdomain iva1_2420_clkdm = {
  41         .name           = "iva1_clkdm",
  42         .pwrdm_name     = "dsp_pwrdm",
  43         .flags          = CLKDM_CAN_HWSUP_SWSUP,
  44         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
  45         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  46 };
  47
  48 #endif  /* CONFIG_ARCH_OMAP2420 */
  49
  50
  51 /*
  52  * 2430-only clockdomains
  53  */
  54
  55 #if defined(CONFIG_ARCH_OMAP2430)
  56
  57 static struct clockdomain mpu_2430_clkdm = {
  58         .name           = "mpu_clkdm",
  59         .pwrdm_name     = "mpu_pwrdm",
  60         .flags          = CLKDM_CAN_HWSUP_SWSUP,
  61         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
  62         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
  63 };
  64
  65 static struct clockdomain mdm_clkdm = {
  66         .name           = "mdm_clkdm",
  67         .pwrdm_name     = "mdm_pwrdm",
  68         .flags          = CLKDM_CAN_HWSUP_SWSUP,
  69         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
  70         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
  71 };
  72
  73 #endif    /* CONFIG_ARCH_OMAP2430 */
  74
  75
  76 /*
  77  * 24XX-only clockdomains
  78  */
  79
  80 #if defined(CONFIG_ARCH_OMAP24XX)
  81
  82 static struct clockdomain dsp_clkdm = {
  83         .name           = "dsp_clkdm",
  84         .pwrdm_name     = "dsp_pwrdm",
  85         .flags          = CLKDM_CAN_HWSUP_SWSUP,
  86         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
  87         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
  88 };
  89
  90 static struct clockdomain gfx_24xx_clkdm = {
  91         .name           = "gfx_clkdm",
  92         .pwrdm_name     = "gfx_pwrdm",
  93         .flags          = CLKDM_CAN_HWSUP_SWSUP,
  94         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
  95         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
  96 };
  97
  98 static struct clockdomain core_l3_24xx_clkdm = {
  99         .name           = "core_l3_clkdm",
 100         .pwrdm_name     = "core_pwrdm",
 101         .flags          = CLKDM_CAN_HWSUP,
 102         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
 104 };
 105
 106 static struct clockdomain core_l4_24xx_clkdm = {
 107         .name           = "core_l4_clkdm",
 108         .pwrdm_name     = "core_pwrdm",
 109         .flags          = CLKDM_CAN_HWSUP,
 110         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 111         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
 112 };
 113
 114 static struct clockdomain dss_24xx_clkdm = {
 115         .name           = "dss_clkdm",
 116         .pwrdm_name     = "core_pwrdm",
 117         .flags          = CLKDM_CAN_HWSUP,
 118         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 119         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
 120 };
 121
 122 #endif   /* CONFIG_ARCH_OMAP24XX */
 123
 124
 125 /*
 126  * 34xx clockdomains
 127  */
 128
 129 #if defined(CONFIG_ARCH_OMAP34XX)
 130
 131 static struct clockdomain mpu_34xx_clkdm = {
 132         .name           = "mpu_clkdm",
 133         .pwrdm_name     = "mpu_pwrdm",
 134         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
 135         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
 136         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 137 };
 138
 139 static struct clockdomain neon_clkdm = {
 140         .name           = "neon_clkdm",
 141         .pwrdm_name     = "neon_pwrdm",
 142         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 143         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
 144         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 145 };
 146
 147 static struct clockdomain iva2_clkdm = {
 148         .name           = "iva2_clkdm",
 149         .pwrdm_name     = "iva2_pwrdm",
 150         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 151         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
 152         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 153 };
 154
 155 static struct clockdomain gfx_3430es1_clkdm = {
 156         .name           = "gfx_clkdm",
 157         .pwrdm_name     = "gfx_pwrdm",
 158         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 159         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
 160         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 161 };
 162
 163 static struct clockdomain sgx_clkdm = {
 164         .name           = "sgx_clkdm",
 165         .pwrdm_name     = "sgx_pwrdm",
 166         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 167         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
 168         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 169 };
 170
 171 static struct clockdomain d2d_clkdm = {
 172         .name           = "d2d_clkdm",
 173         .pwrdm_name     = "core_pwrdm",
 174         .flags          = CLKDM_CAN_HWSUP,
 175         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
 176         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 177 };
 178
 179 static struct clockdomain core_l3_34xx_clkdm = {
 180         .name           = "core_l3_clkdm",
 181         .pwrdm_name     = "core_pwrdm",
 182         .flags          = CLKDM_CAN_HWSUP,
 183         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
 184         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 185 };
 186
 187 static struct clockdomain core_l4_34xx_clkdm = {
 188         .name           = "core_l4_clkdm",
 189         .pwrdm_name     = "core_pwrdm",
 190         .flags          = CLKDM_CAN_HWSUP,
 191         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
 192         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 193 };
 194
 195 static struct clockdomain dss_34xx_clkdm = {
 196         .name           = "dss_clkdm",
 197         .pwrdm_name     = "dss_pwrdm",
 198         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 199         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
 200         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 201 };
 202
 203 static struct clockdomain cam_clkdm = {
 204         .name           = "cam_clkdm",
 205         .pwrdm_name     = "cam_pwrdm",
 206         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 207         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
 208         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 209 };
 210
 211 static struct clockdomain usbhost_clkdm = {
 212         .name           = "usbhost_clkdm",
 213         .pwrdm_name     = "usbhost_pwrdm",
 214         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 215         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
 216         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 217 };
 218
 219 static struct clockdomain per_clkdm = {
 220         .name           = "per_clkdm",
 221         .pwrdm_name     = "per_pwrdm",
 222         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 223         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 224         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 225 };
 226
 227 static struct clockdomain emu_clkdm = {
 228         .name           = "emu_clkdm",
 229         .pwrdm_name     = "emu_pwrdm",
 230         .flags          = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
 231         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 232         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 233 };
 234
 235 #endif   /* CONFIG_ARCH_OMAP34XX */
 236
 237 /*
 238  * Clockdomain-powerdomain hwsup dependencies (34XX only)
 239  */
 240
 241 static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
 242         {
 243                 .pwrdm_name = "mpu_pwrdm",
 244                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 245         },
 246         {
 247                 .pwrdm_name = "iva2_pwrdm",
 248                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 249         },
 250         { NULL }
 251 };
 252
 253 /*
 254  *
 255  */
 256
 257 static struct clockdomain *clockdomains_omap[] = {
 258
 259         &wkup_clkdm,
 260
 261 #ifdef CONFIG_ARCH_OMAP2420
 262         &mpu_2420_clkdm,
 263         &iva1_2420_clkdm,
 264 #endif
 265
 266 #ifdef CONFIG_ARCH_OMAP2430
 267         &mpu_2430_clkdm,
 268         &mdm_clkdm,
 269 #endif
 270
 271 #ifdef CONFIG_ARCH_OMAP24XX
 272         &dsp_clkdm,
 273         &gfx_24xx_clkdm,
 274         &core_l3_24xx_clkdm,
 275         &core_l4_24xx_clkdm,
 276         &dss_24xx_clkdm,
 277 #endif
 278
 279 #ifdef CONFIG_ARCH_OMAP34XX
 280         &mpu_34xx_clkdm,
 281         &neon_clkdm,
 282         &iva2_clkdm,
 283         &gfx_3430es1_clkdm,
 284         &sgx_clkdm,
 285         &d2d_clkdm,
 286         &core_l3_34xx_clkdm,
 287         &core_l4_34xx_clkdm,
 288         &dss_34xx_clkdm,
 289         &cam_clkdm,
 290         &usbhost_clkdm,
 291         &per_clkdm,
 292         &emu_clkdm,
 293 #endif
 294
 295         NULL,
 296 };
 297
 298 #endif