arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  53 #define DPLL_LOW_POWER_STOP             0x1
  54 #define DPLL_LOW_POWER_BYPASS           0x5
  55 #define DPLL_LOCKED                     0x7
  56
  57 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  58         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  59
  60 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  61         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  62
  63 #define OMAP3430_PRM_CLKSEL                                             \
  64         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  65
  66 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  67         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  68
  69 /* PRM CLOCKS */
  70
  71 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  72 static struct clk omap_32k_fck = {
  73         .name           = "omap_32k_fck",
  74         .rate           = 32768,
  75         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .clkdm          = { .name = "prm_clkdm" },
  78         .recalc         = &propagate_rate,
  79 };
  80
  81 static struct clk secure_32k_fck = {
  82         .name           = "secure_32k_fck",
  83         .rate           = 32768,
  84         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  85                                 ALWAYS_ENABLED,
  86         .clkdm          = { .name = "prm_clkdm" },
  87         .recalc         = &propagate_rate,
  88 };
  89
  90 /* Virtual source clocks for osc_sys_ck */
  91 static struct clk virt_12m_ck = {
  92         .name           = "virt_12m_ck",
  93         .rate           = 12000000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .clkdm          = { .name = "prm_clkdm" },
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_13m_ck = {
 101         .name           = "virt_13m_ck",
 102         .rate           = 13000000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .clkdm          = { .name = "prm_clkdm" },
 106         .recalc         = &propagate_rate,
 107 };
 108
 109 static struct clk virt_16_8m_ck = {
 110         .name           = "virt_16_8m_ck",
 111         .rate           = 16800000,
 112         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 113                                 ALWAYS_ENABLED,
 114         .clkdm          = { .name = "prm_clkdm" },
 115         .recalc         = &propagate_rate,
 116 };
 117
 118 static struct clk virt_19_2m_ck = {
 119         .name           = "virt_19_2m_ck",
 120         .rate           = 19200000,
 121         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 122                                 ALWAYS_ENABLED,
 123         .clkdm          = { .name = "prm_clkdm" },
 124         .recalc         = &propagate_rate,
 125 };
 126
 127 static struct clk virt_26m_ck = {
 128         .name           = "virt_26m_ck",
 129         .rate           = 26000000,
 130         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 131                                 ALWAYS_ENABLED,
 132         .clkdm          = { .name = "prm_clkdm" },
 133         .recalc         = &propagate_rate,
 134 };
 135
 136 static struct clk virt_38_4m_ck = {
 137         .name           = "virt_38_4m_ck",
 138         .rate           = 38400000,
 139         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 140                                 ALWAYS_ENABLED,
 141         .clkdm          = { .name = "prm_clkdm" },
 142         .recalc         = &propagate_rate,
 143 };
 144
 145 static const struct clksel_rate osc_sys_12m_rates[] = {
 146         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 147         { .div = 0 }
 148 };
 149
 150 static const struct clksel_rate osc_sys_13m_rates[] = {
 151         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 152         { .div = 0 }
 153 };
 154
 155 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 156         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 161         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 162         { .div = 0 }
 163 };
 164
 165 static const struct clksel_rate osc_sys_26m_rates[] = {
 166         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 167         { .div = 0 }
 168 };
 169
 170 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 171         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel osc_sys_clksel[] = {
 176         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 177         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 178         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 179         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 180         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 181         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 182         { .parent = NULL },
 183 };
 184
 185 /* Oscillator clock */
 186 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 187 static struct clk osc_sys_ck = {
 188         .name           = "osc_sys_ck",
 189         .init           = &omap2_init_clksel_parent,
 190         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 191         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 192         .clksel         = osc_sys_clksel,
 193         /* REVISIT: deal with autoextclkmode? */
 194         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 195                                 ALWAYS_ENABLED,
 196         .clkdm          = { .name = "prm_clkdm" },
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static const struct clksel_rate div2_rates[] = {
 201         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 202         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 203         { .div = 0 }
 204 };
 205
 206 static const struct clksel sys_clksel[] = {
 207         { .parent = &osc_sys_ck, .rates = div2_rates },
 208         { .parent = NULL }
 209 };
 210
 211 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 212 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 213 static struct clk sys_ck = {
 214         .name           = "sys_ck",
 215         .parent         = &osc_sys_ck,
 216         .init           = &omap2_init_clksel_parent,
 217         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 218         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 219         .clksel         = sys_clksel,
 220         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 221         .clkdm          = { .name = "prm_clkdm" },
 222         .recalc         = &omap2_clksel_recalc,
 223 };
 224
 225 static struct clk sys_altclk = {
 226         .name           = "sys_altclk",
 227         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 228         .clkdm          = { .name = "cm_clkdm" },
 229         .recalc         = &propagate_rate,
 230 };
 231
 232 /*
 233  * Optional external clock input for some McBSPs
 234  * Apparently this is not really in prm_clkdm, but rather is fed into
 235  * both CORE and PER separately.
 236  */
 237 static struct clk mcbsp_clks = {
 238         .name           = "mcbsp_clks",
 239         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 240         .clkdm          = { .name = "prm_clkdm" },
 241         .recalc         = &propagate_rate,
 242 };
 243
 244 /* PRM EXTERNAL CLOCK OUTPUT */
 245
 246 static struct clk sys_clkout1 = {
 247         .name           = "sys_clkout1",
 248         .parent         = &osc_sys_ck,
 249         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 250         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 251         .flags          = CLOCK_IN_OMAP343X,
 252         .clkdm          = { .name = "prm_clkdm" },
 253         .recalc         = &followparent_recalc,
 254 };
 255
 256 /* DPLLS */
 257
 258 /* CM CLOCKS */
 259
 260 static const struct clksel_rate dpll_bypass_rates[] = {
 261         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 262         { .div = 0 }
 263 };
 264
 265 static const struct clksel_rate dpll_locked_rates[] = {
 266         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 267         { .div = 0 }
 268 };
 269
 270 static const struct clksel_rate div16_dpll_rates[] = {
 271         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 272         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 273         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 274         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 275         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 276         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 277         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 278         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 279         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 280         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 281         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 282         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 283         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 284         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 285         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 286         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 287         { .div = 0 }
 288 };
 289
 290 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 291         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 292
 293 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 294         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 295
 296 /* DPLL1 */
 297 /* MPU clock source */
 298 /* Type: DPLL */
 299 static struct dpll_data dpll1_dd = {
 300         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 301         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 302         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 303         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 304         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 305         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 306         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 307         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 308         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 309         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 310         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 311         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 312         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 313         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 314         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 315         .max_divider    = OMAP3_MAX_DPLL_DIV,
 316         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 317 };
 318
 319 static struct clk dpll1_ck = {
 320         .name           = "dpll1_ck",
 321         .parent         = &sys_ck,
 322         .dpll_data      = &dpll1_dd,
 323         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 324         .round_rate     = &omap2_dpll_round_rate,
 325         .set_rate       = &omap3_noncore_dpll_set_rate,
 326         .clkdm          = { .name = "dpll1_clkdm" },
 327         .recalc         = &omap3_dpll_recalc,
 328 };
 329
 330 /*
 331  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 332  * DPLL isn't bypassed.
 333  */
 334 static struct clk dpll1_x2_ck = {
 335         .name           = "dpll1_x2_ck",
 336         .parent         = &dpll1_ck,
 337         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 338                                 PARENT_CONTROLS_CLOCK,
 339         .clkdm          = { .name = "dpll1_clkdm" },
 340         .recalc         = &omap3_clkoutx2_recalc,
 341 };
 342
 343 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 344 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 345         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 346         { .parent = NULL }
 347 };
 348
 349 /*
 350  * Does not exist in the TRM - needed to separate the M2 divider from
 351  * bypass selection in mpu_ck
 352  */
 353 static struct clk dpll1_x2m2_ck = {
 354         .name           = "dpll1_x2m2_ck",
 355         .parent         = &dpll1_x2_ck,
 356         .init           = &omap2_init_clksel_parent,
 357         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 358         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 359         .clksel         = div16_dpll1_x2m2_clksel,
 360         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 361                                 PARENT_CONTROLS_CLOCK,
 362         .clkdm          = { .name = "dpll1_clkdm" },
 363         .recalc         = &omap2_clksel_recalc,
 364 };
 365
 366 /* DPLL2 */
 367 /* IVA2 clock source */
 368 /* Type: DPLL */
 369
 370 static struct dpll_data dpll2_dd = {
 371         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 372         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 373         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 374         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 375         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 376         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 377         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 378                                 (1 << DPLL_LOW_POWER_BYPASS),
 379         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 380         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 381         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 382         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 383         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 384         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 385         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 386         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 387         .max_divider    = OMAP3_MAX_DPLL_DIV,
 388         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 389 };
 390
 391 static struct clk dpll2_ck = {
 392         .name           = "dpll2_ck",
 393         .parent         = &sys_ck,
 394         .dpll_data      = &dpll2_dd,
 395         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 396         .enable         = &omap3_noncore_dpll_enable,
 397         .disable        = &omap3_noncore_dpll_disable,
 398         .round_rate     = &omap2_dpll_round_rate,
 399         .set_rate       = &omap3_noncore_dpll_set_rate,
 400         .clkdm          = { .name = "dpll2_clkdm" },
 401         .recalc         = &omap3_dpll_recalc,
 402 };
 403
 404 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 405         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 406         { .parent = NULL }
 407 };
 408
 409 /*
 410  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 411  * or CLKOUTX2. CLKOUT seems most plausible.
 412  */
 413 static struct clk dpll2_m2_ck = {
 414         .name           = "dpll2_m2_ck",
 415         .parent         = &dpll2_ck,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 418                                           OMAP3430_CM_CLKSEL2_PLL),
 419         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 420         .clksel         = div16_dpll2_m2x2_clksel,
 421         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 422                                 PARENT_CONTROLS_CLOCK,
 423         .clkdm          = { .name = "dpll2_clkdm" },
 424         .recalc         = &omap2_clksel_recalc,
 425 };
 426
 427 /*
 428  * DPLL3
 429  * Source clock for all interfaces and for some device fclks
 430  * REVISIT: Also supports fast relock bypass - not included below
 431  */
 432 static struct dpll_data dpll3_dd = {
 433         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 434         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 435         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 436         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 437         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 438         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 439         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 440         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 441         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 442         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 443         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 444         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 445         .max_divider    = OMAP3_MAX_DPLL_DIV,
 446         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 447 };
 448
 449 static struct clk dpll3_ck = {
 450         .name           = "dpll3_ck",
 451         .parent         = &sys_ck,
 452         .dpll_data      = &dpll3_dd,
 453         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 454         .round_rate     = &omap2_dpll_round_rate,
 455         .clkdm          = { .name = "dpll3_clkdm" },
 456         .recalc         = &omap3_dpll_recalc,
 457 };
 458
 459 /*
 460  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 461  * DPLL isn't bypassed
 462  */
 463 static struct clk dpll3_x2_ck = {
 464         .name           = "dpll3_x2_ck",
 465         .parent         = &dpll3_ck,
 466         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 467                                 PARENT_CONTROLS_CLOCK,
 468         .clkdm          = { .name = "dpll3_clkdm" },
 469         .recalc         = &omap3_clkoutx2_recalc,
 470 };
 471
 472 static const struct clksel_rate div31_dpll3_rates[] = {
 473         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 474         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 475         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 476         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 477         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 478         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 479         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 480         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 481         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 482         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 483         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 484         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 485         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 486         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 487         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 488         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 489         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 490         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 491         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 492         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 493         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 494         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 495         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 496         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 497         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 498         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 499         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 500         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 501         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 502         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 503         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 504         { .div = 0 },
 505 };
 506
 507 static const struct clksel div31_dpll3m2_clksel[] = {
 508         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 509         { .parent = NULL }
 510 };
 511
 512 /* DPLL3 output M2 - primary control point for CORE speed */
 513 static struct clk dpll3_m2_ck = {
 514         .name           = "dpll3_m2_ck",
 515         .parent         = &dpll3_ck,
 516         .init           = &omap2_init_clksel_parent,
 517         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 518         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 519         .clksel         = div31_dpll3m2_clksel,
 520         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 521                                 PARENT_CONTROLS_CLOCK,
 522         .clkdm          = { .name = "dpll3_clkdm" },
 523         .round_rate     = &omap2_clksel_round_rate,
 524         .set_rate       = &omap3_core_dpll_m2_set_rate,
 525         .recalc         = &omap2_clksel_recalc,
 526 };
 527
 528 static const struct clksel core_ck_clksel[] = {
 529         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 530         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 531         { .parent = NULL }
 532 };
 533
 534 static struct clk core_ck = {
 535         .name           = "core_ck",
 536         .init           = &omap2_init_clksel_parent,
 537         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 538         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 539         .clksel         = core_ck_clksel,
 540         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 541                                 PARENT_CONTROLS_CLOCK,
 542         .clkdm          = { .name = "cm_clkdm" },
 543         .recalc         = &omap2_clksel_recalc,
 544 };
 545
 546 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 547         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 548         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 549         { .parent = NULL }
 550 };
 551
 552 static struct clk dpll3_m2x2_ck = {
 553         .name           = "dpll3_m2x2_ck",
 554         .init           = &omap2_init_clksel_parent,
 555         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 556         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 557         .clksel         = dpll3_m2x2_ck_clksel,
 558         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 559                                 PARENT_CONTROLS_CLOCK,
 560         .clkdm          = { .name = "dpll3_clkdm" },
 561         .recalc         = &omap2_clksel_recalc,
 562 };
 563
 564 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 565 static const struct clksel div16_dpll3_clksel[] = {
 566         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 567         { .parent = NULL }
 568 };
 569
 570 /* This virtual clock is the source for dpll3_m3x2_ck */
 571 static struct clk dpll3_m3_ck = {
 572         .name           = "dpll3_m3_ck",
 573         .parent         = &dpll3_ck,
 574         .init           = &omap2_init_clksel_parent,
 575         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 576         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 577         .clksel         = div16_dpll3_clksel,
 578         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 579                                 PARENT_CONTROLS_CLOCK,
 580         .clkdm          = { .name = "dpll3_clkdm" },
 581         .recalc         = &omap2_clksel_recalc,
 582 };
 583
 584 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 585 static struct clk dpll3_m3x2_ck = {
 586         .name           = "dpll3_m3x2_ck",
 587         .parent         = &dpll3_m3_ck,
 588         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 589         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 590         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 591         .clkdm          = { .name = "dpll3_clkdm" },
 592         .recalc         = &omap3_clkoutx2_recalc,
 593 };
 594
 595 static const struct clksel emu_core_alwon_ck_clksel[] = {
 596         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 597         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 598         { .parent = NULL }
 599 };
 600
 601 static struct clk emu_core_alwon_ck = {
 602         .name           = "emu_core_alwon_ck",
 603         .parent         = &dpll3_m3x2_ck,
 604         .init           = &omap2_init_clksel_parent,
 605         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 606         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 607         .clksel         = emu_core_alwon_ck_clksel,
 608         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 609                                 PARENT_CONTROLS_CLOCK,
 610         .clkdm          = { .name = "dpll3_clkdm" },
 611         .recalc         = &omap2_clksel_recalc,
 612 };
 613
 614 /* DPLL4 */
 615 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 616 /* Type: DPLL */
 617 static struct dpll_data dpll4_dd = {
 618         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 619         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 620         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 621         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 622         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 623         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 624         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 625         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 626         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 627         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 628         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 629         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 630         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 631         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 632         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 633         .max_divider    = OMAP3_MAX_DPLL_DIV,
 634         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 635 };
 636
 637 static struct clk dpll4_ck = {
 638         .name           = "dpll4_ck",
 639         .parent         = &sys_ck,
 640         .dpll_data      = &dpll4_dd,
 641         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 642         .enable         = &omap3_noncore_dpll_enable,
 643         .disable        = &omap3_noncore_dpll_disable,
 644         .round_rate     = &omap2_dpll_round_rate,
 645         .set_rate       = &omap3_noncore_dpll_set_rate,
 646         .clkdm          = { .name = "dpll4_clkdm" },
 647         .recalc         = &omap3_dpll_recalc,
 648 };
 649
 650 /*
 651  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 652  * DPLL isn't bypassed --
 653  * XXX does this serve any downstream clocks?
 654  */
 655 static struct clk dpll4_x2_ck = {
 656         .name           = "dpll4_x2_ck",
 657         .parent         = &dpll4_ck,
 658         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 659                                 PARENT_CONTROLS_CLOCK,
 660         .clkdm          = { .name = "dpll4_clkdm" },
 661         .recalc         = &omap3_clkoutx2_recalc,
 662 };
 663
 664 static const struct clksel div16_dpll4_clksel[] = {
 665         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 666         { .parent = NULL }
 667 };
 668
 669 /* This virtual clock is the source for dpll4_m2x2_ck */
 670 static struct clk dpll4_m2_ck = {
 671         .name           = "dpll4_m2_ck",
 672         .parent         = &dpll4_ck,
 673         .init           = &omap2_init_clksel_parent,
 674         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 675         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 676         .clksel         = div16_dpll4_clksel,
 677         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 678                                 PARENT_CONTROLS_CLOCK,
 679         .clkdm          = { .name = "dpll4_clkdm" },
 680         .recalc         = &omap2_clksel_recalc,
 681 };
 682
 683 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 684 static struct clk dpll4_m2x2_ck = {
 685         .name           = "dpll4_m2x2_ck",
 686         .parent         = &dpll4_m2_ck,
 687         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 688         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 689         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 690         .clkdm          = { .name = "dpll4_clkdm" },
 691         .recalc         = &omap3_clkoutx2_recalc,
 692 };
 693
 694 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 695         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 696         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 697         { .parent = NULL }
 698 };
 699
 700 /*
 701  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 702  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 703  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 704  * CM_96K_(F)CLK.
 705  */
 706 static struct clk omap_96m_alwon_fck = {
 707         .name           = "omap_96m_alwon_fck",
 708         .parent         = &dpll4_m2x2_ck,
 709         .init           = &omap2_init_clksel_parent,
 710         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 711         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 712         .clksel         = omap_96m_alwon_fck_clksel,
 713         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 714                                 PARENT_CONTROLS_CLOCK,
 715         .clkdm          = { .name = "prm_clkdm" },
 716         .recalc         = &omap2_clksel_recalc,
 717 };
 718
 719 static struct clk cm_96m_fck = {
 720         .name           = "cm_96m_fck",
 721         .parent         = &omap_96m_alwon_fck,
 722         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 723                                 PARENT_CONTROLS_CLOCK,
 724         .clkdm          = { .name = "cm_clkdm" },
 725         .recalc         = &followparent_recalc,
 726 };
 727
 728 static const struct clksel_rate omap_96m_dpll_rates[] = {
 729         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 730         { .div = 0 }
 731 };
 732
 733 static const struct clksel_rate omap_96m_sys_rates[] = {
 734         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 735         { .div = 0 }
 736 };
 737
 738 static const struct clksel omap_96m_fck_clksel[] = {
 739         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 740         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 741         { .parent = NULL }
 742 };
 743
 744 static struct clk omap_96m_fck = {
 745         .name           = "omap_96m_fck",
 746         .parent         = &sys_ck,
 747         .init           = &omap2_init_clksel_parent,
 748         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 749         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 750         .clksel         = omap_96m_fck_clksel,
 751         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 752                                 PARENT_CONTROLS_CLOCK,
 753         .clkdm          = { .name = "cm_clkdm" },
 754         .recalc         = &omap2_clksel_recalc,
 755 };
 756
 757 /* This virtual clock is the source for dpll4_m3x2_ck */
 758 static struct clk dpll4_m3_ck = {
 759         .name           = "dpll4_m3_ck",
 760         .parent         = &dpll4_ck,
 761         .init           = &omap2_init_clksel_parent,
 762         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 763         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 764         .clksel         = div16_dpll4_clksel,
 765         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 766                                 PARENT_CONTROLS_CLOCK,
 767         .clkdm          = { .name = "dpll4_clkdm" },
 768         .recalc         = &omap2_clksel_recalc,
 769 };
 770
 771 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 772 static struct clk dpll4_m3x2_ck = {
 773         .name           = "dpll4_m3x2_ck",
 774         .parent         = &dpll4_m3_ck,
 775         .init           = &omap2_init_clksel_parent,
 776         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 777         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 778         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 779         .clkdm          = { .name = "dpll4_clkdm" },
 780         .recalc         = &omap3_clkoutx2_recalc,
 781 };
 782
 783 static const struct clksel virt_omap_54m_fck_clksel[] = {
 784         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 785         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 786         { .parent = NULL }
 787 };
 788
 789 static struct clk virt_omap_54m_fck = {
 790         .name           = "virt_omap_54m_fck",
 791         .parent         = &dpll4_m3x2_ck,
 792         .init           = &omap2_init_clksel_parent,
 793         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 794         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 795         .clksel         = virt_omap_54m_fck_clksel,
 796         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 797                                 PARENT_CONTROLS_CLOCK,
 798         .clkdm          = { .name = "dpll4_clkdm" },
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 803         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 804         { .div = 0 }
 805 };
 806
 807 static const struct clksel_rate omap_54m_alt_rates[] = {
 808         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 809         { .div = 0 }
 810 };
 811
 812 static const struct clksel omap_54m_clksel[] = {
 813         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 814         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 815         { .parent = NULL }
 816 };
 817
 818 static struct clk omap_54m_fck = {
 819         .name           = "omap_54m_fck",
 820         .init           = &omap2_init_clksel_parent,
 821         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 822         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 823         .clksel         = omap_54m_clksel,
 824         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 825                                 PARENT_CONTROLS_CLOCK,
 826         .clkdm          = { .name = "cm_clkdm" },
 827         .recalc         = &omap2_clksel_recalc,
 828 };
 829
 830 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 831         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 832         { .div = 0 }
 833 };
 834
 835 static const struct clksel_rate omap_48m_alt_rates[] = {
 836         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 837         { .div = 0 }
 838 };
 839
 840 static const struct clksel omap_48m_clksel[] = {
 841         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 842         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 843         { .parent = NULL }
 844 };
 845
 846 static struct clk omap_48m_fck = {
 847         .name           = "omap_48m_fck",
 848         .init           = &omap2_init_clksel_parent,
 849         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 850         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 851         .clksel         = omap_48m_clksel,
 852         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 853                                 PARENT_CONTROLS_CLOCK,
 854         .clkdm          = { .name = "cm_clkdm" },
 855         .recalc         = &omap2_clksel_recalc,
 856 };
 857
 858 static struct clk omap_12m_fck = {
 859         .name           = "omap_12m_fck",
 860         .parent         = &omap_48m_fck,
 861         .fixed_div      = 4,
 862         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 863                                 PARENT_CONTROLS_CLOCK,
 864         .clkdm          = { .name = "cm_clkdm" },
 865         .recalc         = &omap2_fixed_divisor_recalc,
 866 };
 867
 868 /* This virstual clock is the source for dpll4_m4x2_ck */
 869 static struct clk dpll4_m4_ck = {
 870         .name           = "dpll4_m4_ck",
 871         .parent         = &dpll4_ck,
 872         .init           = &omap2_init_clksel_parent,
 873         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 874         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 875         .clksel         = div16_dpll4_clksel,
 876         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 877                                 PARENT_CONTROLS_CLOCK,
 878         .clkdm          = { .name = "dpll4_clkdm" },
 879         .recalc         = &omap2_clksel_recalc,
 880 };
 881
 882 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 883 static struct clk dpll4_m4x2_ck = {
 884         .name           = "dpll4_m4x2_ck",
 885         .parent         = &dpll4_m4_ck,
 886         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 887         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 888         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 889         .clkdm          = { .name = "dpll4_clkdm" },
 890         .recalc         = &omap3_clkoutx2_recalc,
 891 };
 892
 893 /* This virtual clock is the source for dpll4_m5x2_ck */
 894 static struct clk dpll4_m5_ck = {
 895         .name           = "dpll4_m5_ck",
 896         .parent         = &dpll4_ck,
 897         .init           = &omap2_init_clksel_parent,
 898         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 899         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 900         .clksel         = div16_dpll4_clksel,
 901         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 902                                 PARENT_CONTROLS_CLOCK,
 903         .clkdm          = { .name = "dpll4_clkdm" },
 904         .recalc         = &omap2_clksel_recalc,
 905 };
 906
 907 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 908 static struct clk dpll4_m5x2_ck = {
 909         .name           = "dpll4_m5x2_ck",
 910         .parent         = &dpll4_m5_ck,
 911         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 912         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 913         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 914         .clkdm          = { .name = "dpll4_clkdm" },
 915         .recalc         = &omap3_clkoutx2_recalc,
 916 };
 917
 918 /* This virtual clock is the source for dpll4_m6x2_ck */
 919 static struct clk dpll4_m6_ck = {
 920         .name           = "dpll4_m6_ck",
 921         .parent         = &dpll4_ck,
 922         .init           = &omap2_init_clksel_parent,
 923         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 924         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 925         .clksel         = div16_dpll4_clksel,
 926         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 927                                 PARENT_CONTROLS_CLOCK,
 928         .clkdm          = { .name = "dpll4_clkdm" },
 929         .recalc         = &omap2_clksel_recalc,
 930 };
 931
 932 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 933 static struct clk dpll4_m6x2_ck = {
 934         .name           = "dpll4_m6x2_ck",
 935         .parent         = &dpll4_m6_ck,
 936         .init           = &omap2_init_clksel_parent,
 937         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 938         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 939         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 940         .clkdm          = { .name = "dpll4_clkdm" },
 941         .recalc         = &omap3_clkoutx2_recalc,
 942 };
 943
 944 static struct clk emu_per_alwon_ck = {
 945         .name           = "emu_per_alwon_ck",
 946         .parent         = &dpll4_m6x2_ck,
 947         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 948                                 PARENT_CONTROLS_CLOCK,
 949         .clkdm          = { .name = "dpll4_clkdm" },
 950         .recalc         = &followparent_recalc,
 951 };
 952
 953 /* DPLL5 */
 954 /* Supplies 120MHz clock, USIM source clock */
 955 /* Type: DPLL */
 956 /* 3430ES2 only */
 957 static struct dpll_data dpll5_dd = {
 958         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 959         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 960         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 961         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 962         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 963         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 964         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 965         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 966         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 967         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 968         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 969         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 970         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 971         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 972         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 973         .max_divider    = OMAP3_MAX_DPLL_DIV,
 974         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 975 };
 976
 977 static struct clk dpll5_ck = {
 978         .name           = "dpll5_ck",
 979         .parent         = &sys_ck,
 980         .dpll_data      = &dpll5_dd,
 981         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 982         .enable         = &omap3_noncore_dpll_enable,
 983         .disable        = &omap3_noncore_dpll_disable,
 984         .round_rate     = &omap2_dpll_round_rate,
 985         .set_rate       = &omap3_noncore_dpll_set_rate,
 986         .clkdm          = { .name = "dpll5_clkdm" },
 987         .recalc         = &omap3_dpll_recalc,
 988 };
 989
 990 static const struct clksel div16_dpll5_clksel[] = {
 991         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 992         { .parent = NULL }
 993 };
 994
 995 static struct clk dpll5_m2_ck = {
 996         .name           = "dpll5_m2_ck",
 997         .parent         = &dpll5_ck,
 998         .init           = &omap2_init_clksel_parent,
 999         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1000         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
1001         .clksel         = div16_dpll5_clksel,
1002         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1003                                 PARENT_CONTROLS_CLOCK,
1004         .clkdm          = { .name = "dpll5_clkdm" },
1005         .recalc         = &omap2_clksel_recalc,
1006 };
1007
1008 static const struct clksel omap_120m_fck_clksel[] = {
1009         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
1010         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
1011         { .parent = NULL }
1012 };
1013
1014 static struct clk omap_120m_fck = {
1015         .name           = "omap_120m_fck",
1016         .parent         = &dpll5_m2_ck,
1017         .init           = &omap2_init_clksel_parent,
1018         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1019         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1020         .clksel         = omap_120m_fck_clksel,
1021         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1022                                 PARENT_CONTROLS_CLOCK,
1023         .clkdm          = { .name = "dpll5_clkdm" },
1024         .recalc         = &omap2_clksel_recalc,
1025 };
1026
1027 /* CM EXTERNAL CLOCK OUTPUTS */
1028
1029 static const struct clksel_rate clkout2_src_core_rates[] = {
1030         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1031         { .div = 0 }
1032 };
1033
1034 static const struct clksel_rate clkout2_src_sys_rates[] = {
1035         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1036         { .div = 0 }
1037 };
1038
1039 static const struct clksel_rate clkout2_src_96m_rates[] = {
1040         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1041         { .div = 0 }
1042 };
1043
1044 static const struct clksel_rate clkout2_src_54m_rates[] = {
1045         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1046         { .div = 0 }
1047 };
1048
1049 static const struct clksel clkout2_src_clksel[] = {
1050         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1051         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1052         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1053         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1054         { .parent = NULL }
1055 };
1056
1057 static struct clk clkout2_src_ck = {
1058         .name           = "clkout2_src_ck",
1059         .init           = &omap2_init_clksel_parent,
1060         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1061         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1062         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1063         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1064         .clksel         = clkout2_src_clksel,
1065         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1066         .clkdm          = { .name = "cm_clkdm" },
1067         .recalc         = &omap2_clksel_recalc,
1068 };
1069
1070 static const struct clksel_rate sys_clkout2_rates[] = {
1071         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1072         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1073         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1074         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1075         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1076         { .div = 0 },
1077 };
1078
1079 static const struct clksel sys_clkout2_clksel[] = {
1080         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1081         { .parent = NULL },
1082 };
1083
1084 static struct clk sys_clkout2 = {
1085         .name           = "sys_clkout2",
1086         .init           = &omap2_init_clksel_parent,
1087         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1088         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1089         .clksel         = sys_clkout2_clksel,
1090         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1091         .clkdm          = { .name = "cm_clkdm" },
1092         .recalc         = &omap2_clksel_recalc,
1093 };
1094
1095 /* CM OUTPUT CLOCKS */
1096
1097 static struct clk corex2_fck = {
1098         .name           = "corex2_fck",
1099         .parent         = &dpll3_m2x2_ck,
1100         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1101                                 PARENT_CONTROLS_CLOCK,
1102         .clkdm          = { .name = "cm_clkdm" },
1103         .recalc         = &followparent_recalc,
1104 };
1105
1106 /* DPLL power domain clock controls */
1107
1108 static const struct clksel_rate div4_rates[] = {
1109         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1110         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1111         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1112         { .div = 0 }
1113 };
1114
1115 static const struct clksel div4_core_clksel[] = {
1116         { .parent = &core_ck, .rates = div4_rates },
1117         { .parent = NULL }
1118 };
1119
1120 static struct clk dpll1_fck = {
1121         .name           = "dpll1_fck",
1122         .parent         = &core_ck,
1123         .init           = &omap2_init_clksel_parent,
1124         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1125         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1126         .clksel         = div4_core_clksel,
1127         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1128                                 PARENT_CONTROLS_CLOCK,
1129         .clkdm          = { .name = "cm_clkdm" },
1130         .recalc         = &omap2_clksel_recalc,
1131 };
1132
1133 /*
1134  * MPU clksel:
1135  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1136  * derives from the high-frequency bypass clock originating from DPLL3,
1137  * called 'dpll1_fck'
1138  */
1139 static const struct clksel mpu_clksel[] = {
1140         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1141         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1142         { .parent = NULL }
1143 };
1144
1145 static struct clk mpu_ck = {
1146         .name           = "mpu_ck",
1147         .parent         = &dpll1_x2m2_ck,
1148         .init           = &omap2_init_clksel_parent,
1149         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1150         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1151         .clksel         = mpu_clksel,
1152         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1153                                 PARENT_CONTROLS_CLOCK,
1154         .clkdm          = { .name = "mpu_clkdm" },
1155         .recalc         = &omap2_clksel_recalc,
1156 };
1157
1158 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1159 static const struct clksel_rate arm_fck_rates[] = {
1160         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1161         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1162         { .div = 0 },
1163 };
1164
1165 static const struct clksel arm_fck_clksel[] = {
1166         { .parent = &mpu_ck, .rates = arm_fck_rates },
1167         { .parent = NULL }
1168 };
1169
1170 static struct clk arm_fck = {
1171         .name           = "arm_fck",
1172         .parent         = &mpu_ck,
1173         .init           = &omap2_init_clksel_parent,
1174         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1175         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1176         .clksel         = arm_fck_clksel,
1177         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1178                                 PARENT_CONTROLS_CLOCK,
1179         .clkdm          = { .name = "mpu_clkdm" },
1180         .recalc         = &omap2_clksel_recalc,
1181 };
1182
1183 /* XXX What about neon_clkdm ? */
1184
1185 /*
1186  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1187  * although it is referenced - so this is a guess
1188  */
1189 static struct clk emu_mpu_alwon_ck = {
1190         .name           = "emu_mpu_alwon_ck",
1191         .parent         = &mpu_ck,
1192         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1193                                 PARENT_CONTROLS_CLOCK,
1194         .clkdm          = { .name = "mpu_clkdm" },
1195         .recalc         = &followparent_recalc,
1196 };
1197
1198 static struct clk dpll2_fck = {
1199         .name           = "dpll2_fck",
1200         .parent         = &core_ck,
1201         .init           = &omap2_init_clksel_parent,
1202         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1203         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1204         .clksel         = div4_core_clksel,
1205         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1206                                 PARENT_CONTROLS_CLOCK,
1207         .clkdm          = { .name = "cm_clkdm" },
1208         .recalc         = &omap2_clksel_recalc,
1209 };
1210
1211 /*
1212  * IVA2 clksel:
1213  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1214  * derives from the high-frequency bypass clock originating from DPLL3,
1215  * called 'dpll2_fck'
1216  */
1217
1218 static const struct clksel iva2_clksel[] = {
1219         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1220         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1221         { .parent = NULL }
1222 };
1223
1224 static struct clk iva2_ck = {
1225         .name           = "iva2_ck",
1226         .parent         = &dpll2_m2_ck,
1227         .init           = &omap2_init_clksel_parent,
1228         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1229         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1230         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1231                                           OMAP3430_CM_IDLEST_PLL),
1232         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1233         .clksel         = iva2_clksel,
1234         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1235         .clkdm          = { .name = "iva2_clkdm" },
1236         .recalc         = &omap2_clksel_recalc,
1237 };
1238
1239 /* Common interface clocks */
1240
1241 static const struct clksel div2_core_clksel[] = {
1242         { .parent = &core_ck, .rates = div2_rates },
1243         { .parent = NULL }
1244 };
1245
1246 static struct clk l3_ick = {
1247         .name           = "l3_ick",
1248         .parent         = &core_ck,
1249         .init           = &omap2_init_clksel_parent,
1250         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1251         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1252         .clksel         = div2_core_clksel,
1253         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1254                                 PARENT_CONTROLS_CLOCK,
1255         .clkdm          = { .name = "core_l3_clkdm" },
1256         .recalc         = &omap2_clksel_recalc,
1257 };
1258
1259 static const struct clksel div2_l3_clksel[] = {
1260         { .parent = &l3_ick, .rates = div2_rates },
1261         { .parent = NULL }
1262 };
1263
1264 static struct clk l4_ick = {
1265         .name           = "l4_ick",
1266         .parent         = &l3_ick,
1267         .init           = &omap2_init_clksel_parent,
1268         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1269         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1270         .clksel         = div2_l3_clksel,
1271         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1272                                 PARENT_CONTROLS_CLOCK,
1273         .clkdm          = { .name = "core_l4_clkdm" },
1274         .recalc         = &omap2_clksel_recalc,
1275
1276 };
1277
1278 static const struct clksel div2_l4_clksel[] = {
1279         { .parent = &l4_ick, .rates = div2_rates },
1280         { .parent = NULL }
1281 };
1282
1283 static struct clk rm_ick = {
1284         .name           = "rm_ick",
1285         .parent         = &l4_ick,
1286         .init           = &omap2_init_clksel_parent,
1287         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1288         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1289         .clksel         = div2_l4_clksel,
1290         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1291         .clkdm          = { .name = "cm_clkdm" },
1292         .recalc         = &omap2_clksel_recalc,
1293 };
1294
1295 /* GFX power domain */
1296
1297 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1298
1299 static const struct clksel gfx_l3_clksel[] = {
1300         { .parent = &l3_ick, .rates = gfx_l3_rates },
1301         { .parent = NULL }
1302 };
1303
1304 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1305 static struct clk gfx_l3_ck = {
1306         .name           = "gfx_l3_ck",
1307         .parent         = &l3_ick,
1308         .init           = &omap2_init_clksel_parent,
1309         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1310         .enable_bit     = OMAP_EN_GFX_SHIFT,
1311         .flags          = CLOCK_IN_OMAP3430ES1,
1312         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1313         .recalc         = &followparent_recalc,
1314 };
1315
1316 static struct clk gfx_l3_fck = {
1317         .name           = "gfx_l3_fck",
1318         .parent         = &gfx_l3_ck,
1319         .init           = &omap2_init_clksel_parent,
1320         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1321         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1322         .clksel         = gfx_l3_clksel,
1323         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1324                                 PARENT_CONTROLS_CLOCK,
1325         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1326         .recalc         = &omap2_clksel_recalc,
1327 };
1328
1329 static struct clk gfx_l3_ick = {
1330         .name           = "gfx_l3_ick",
1331         .parent         = &gfx_l3_ck,
1332         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1333         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk gfx_cg1_ck = {
1338         .name           = "gfx_cg1_ck",
1339         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1340         .init           = &omap2_init_clk_clkdm,
1341         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1342         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1343         .flags          = CLOCK_IN_OMAP3430ES1,
1344         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1345         .recalc         = &followparent_recalc,
1346 };
1347
1348 static struct clk gfx_cg2_ck = {
1349         .name           = "gfx_cg2_ck",
1350         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1351         .init           = &omap2_init_clk_clkdm,
1352         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1353         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1354         .flags          = CLOCK_IN_OMAP3430ES1,
1355         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1356         .recalc         = &followparent_recalc,
1357 };
1358
1359 /* SGX power domain - 3430ES2 only */
1360
1361 static const struct clksel_rate sgx_core_rates[] = {
1362         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1363         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1364         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1365         { .div = 0 },
1366 };
1367
1368 static const struct clksel_rate sgx_96m_rates[] = {
1369         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1370         { .div = 0 },
1371 };
1372
1373 static const struct clksel sgx_clksel[] = {
1374         { .parent = &core_ck,    .rates = sgx_core_rates },
1375         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1376         { .parent = NULL },
1377 };
1378
1379 static struct clk sgx_fck = {
1380         .name           = "sgx_fck",
1381         .init           = &omap2_init_clksel_parent,
1382         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1383         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1384         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1385         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1386         .clksel         = sgx_clksel,
1387         .flags          = CLOCK_IN_OMAP3430ES2,
1388         .clkdm          = { .name = "sgx_clkdm" },
1389         .recalc         = &omap2_clksel_recalc,
1390 };
1391
1392 static struct clk sgx_ick = {
1393         .name           = "sgx_ick",
1394         .parent         = &l3_ick,
1395         .init           = &omap2_init_clk_clkdm,
1396         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1397         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1398         .flags          = CLOCK_IN_OMAP3430ES2,
1399         .clkdm          = { .name = "sgx_clkdm" },
1400         .recalc         = &followparent_recalc,
1401 };
1402
1403 /* CORE power domain */
1404
1405 static struct clk d2d_26m_fck = {
1406         .name           = "d2d_26m_fck",
1407         .parent         = &sys_ck,
1408         .init           = &omap2_init_clk_clkdm,
1409         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1410         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1411         .flags          = CLOCK_IN_OMAP3430ES1,
1412         .clkdm          = { .name = "d2d_clkdm" },
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 static const struct clksel omap343x_gpt_clksel[] = {
1417         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1418         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1419         { .parent = NULL}
1420 };
1421
1422 static struct clk gpt10_fck = {
1423         .name           = "gpt10_fck",
1424         .parent         = &sys_ck,
1425         .init           = &omap2_init_clksel_parent,
1426         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1427         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1428         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1429         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1430         .clksel         = omap343x_gpt_clksel,
1431         .flags          = CLOCK_IN_OMAP343X,
1432         .clkdm          = { .name = "core_l4_clkdm" },
1433         .recalc         = &omap2_clksel_recalc,
1434 };
1435
1436 static struct clk gpt11_fck = {
1437         .name           = "gpt11_fck",
1438         .parent         = &sys_ck,
1439         .init           = &omap2_init_clksel_parent,
1440         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1442         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1443         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1444         .clksel         = omap343x_gpt_clksel,
1445         .flags          = CLOCK_IN_OMAP343X,
1446         .clkdm          = { .name = "core_l4_clkdm" },
1447         .recalc         = &omap2_clksel_recalc,
1448 };
1449
1450 static struct clk cpefuse_fck = {
1451         .name           = "cpefuse_fck",
1452         .parent         = &sys_ck,
1453         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1454         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1455         .flags          = CLOCK_IN_OMAP3430ES2,
1456         .clkdm          = { .name = "cm_clkdm" },
1457         .recalc         = &followparent_recalc,
1458 };
1459
1460 static struct clk ts_fck = {
1461         .name           = "ts_fck",
1462         .parent         = &omap_32k_fck,
1463         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1464         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1465         .flags          = CLOCK_IN_OMAP3430ES2,
1466         .clkdm          = { .name = "core_l4_clkdm" },
1467         .recalc         = &followparent_recalc,
1468 };
1469
1470 static struct clk usbtll_fck = {
1471         .name           = "usbtll_fck",
1472         .parent         = &omap_120m_fck,
1473         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1474         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1475         .flags          = CLOCK_IN_OMAP3430ES2,
1476         .clkdm          = { .name = "core_l4_clkdm" },
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 /* CORE 96M FCLK-derived clocks */
1481
1482 static struct clk core_96m_fck = {
1483         .name           = "core_96m_fck",
1484         .parent         = &omap_96m_fck,
1485         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1486                                 PARENT_CONTROLS_CLOCK,
1487         .clkdm          = { .name = "core_l4_clkdm" },
1488         .recalc         = &followparent_recalc,
1489 };
1490
1491 static struct clk mmchs3_fck = {
1492         .name           = "mmchs_fck",
1493         .id             = 3,
1494         .parent         = &core_96m_fck,
1495         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1496         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1497         .flags          = CLOCK_IN_OMAP3430ES2,
1498         .clkdm          = { .name = "core_l4_clkdm" },
1499         .recalc         = &followparent_recalc,
1500 };
1501
1502 static struct clk mmchs2_fck = {
1503         .name           = "mmchs_fck",
1504         .id             = 2,
1505         .parent         = &core_96m_fck,
1506         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1507         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1508         .flags          = CLOCK_IN_OMAP343X,
1509         .clkdm          = { .name = "core_l4_clkdm" },
1510         .recalc         = &followparent_recalc,
1511 };
1512
1513 static struct clk mspro_fck = {
1514         .name           = "mspro_fck",
1515         .parent         = &core_96m_fck,
1516         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1517         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1518         .flags          = CLOCK_IN_OMAP343X,
1519         .clkdm          = { .name = "core_l4_clkdm" },
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 static struct clk mmchs1_fck = {
1524         .name           = "mmchs_fck",
1525         .id             = 1,
1526         .parent         = &core_96m_fck,
1527         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1528         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1529         .flags          = CLOCK_IN_OMAP343X,
1530         .clkdm          = { .name = "core_l4_clkdm" },
1531         .recalc         = &followparent_recalc,
1532 };
1533
1534 static struct clk i2c3_fck = {
1535         .name           = "i2c_fck",
1536         .id             = 3,
1537         .parent         = &core_96m_fck,
1538         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1539         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1540         .flags          = CLOCK_IN_OMAP343X,
1541         .clkdm          = { .name = "core_l4_clkdm" },
1542         .recalc         = &followparent_recalc,
1543 };
1544
1545 static struct clk i2c2_fck = {
1546         .name           = "i2c_fck",
1547         .id             = 2,
1548         .parent         = &core_96m_fck,
1549         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1551         .flags          = CLOCK_IN_OMAP343X,
1552         .clkdm          = { .name = "core_l4_clkdm" },
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 static struct clk i2c1_fck = {
1557         .name           = "i2c_fck",
1558         .id             = 1,
1559         .parent         = &core_96m_fck,
1560         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1562         .flags          = CLOCK_IN_OMAP343X,
1563         .clkdm          = { .name = "core_l4_clkdm" },
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 /*
1568  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1569  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1570  */
1571 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1572         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1573         { .div = 0 }
1574 };
1575
1576 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1577         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1578         { .div = 0 }
1579 };
1580
1581 static const struct clksel mcbsp_15_clksel[] = {
1582         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1583         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1584         { .parent = NULL }
1585 };
1586
1587 static struct clk mcbsp5_fck = {
1588         .name           = "mcbsp_fck",
1589         .id             = 5,
1590         .init           = &omap2_init_clksel_parent,
1591         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1593         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1594         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1595         .clksel         = mcbsp_15_clksel,
1596         .flags          = CLOCK_IN_OMAP343X,
1597         .clkdm          = { .name = "core_l4_clkdm" },
1598         .recalc         = &omap2_clksel_recalc,
1599 };
1600
1601 static struct clk mcbsp1_fck = {
1602         .name           = "mcbsp_fck",
1603         .id             = 1,
1604         .init           = &omap2_init_clksel_parent,
1605         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1606         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1607         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1608         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1609         .clksel         = mcbsp_15_clksel,
1610         .flags          = CLOCK_IN_OMAP343X,
1611         .clkdm          = { .name = "core_l4_clkdm" },
1612         .recalc         = &omap2_clksel_recalc,
1613 };
1614
1615 /* CORE_48M_FCK-derived clocks */
1616
1617 static struct clk core_48m_fck = {
1618         .name           = "core_48m_fck",
1619         .parent         = &omap_48m_fck,
1620         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1621                                 PARENT_CONTROLS_CLOCK,
1622         .clkdm          = { .name = "core_l4_clkdm" },
1623         .recalc         = &followparent_recalc,
1624 };
1625
1626 static struct clk mcspi4_fck = {
1627         .name           = "mcspi_fck",
1628         .id             = 4,
1629         .parent         = &core_48m_fck,
1630         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1631         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1632         .flags          = CLOCK_IN_OMAP343X,
1633         .clkdm          = { .name = "core_l4_clkdm" },
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 static struct clk mcspi3_fck = {
1638         .name           = "mcspi_fck",
1639         .id             = 3,
1640         .parent         = &core_48m_fck,
1641         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1642         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1643         .flags          = CLOCK_IN_OMAP343X,
1644         .clkdm          = { .name = "core_l4_clkdm" },
1645         .recalc         = &followparent_recalc,
1646 };
1647
1648 static struct clk mcspi2_fck = {
1649         .name           = "mcspi_fck",
1650         .id             = 2,
1651         .parent         = &core_48m_fck,
1652         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1654         .flags          = CLOCK_IN_OMAP343X,
1655         .clkdm          = { .name = "core_l4_clkdm" },
1656         .recalc         = &followparent_recalc,
1657 };
1658
1659 static struct clk mcspi1_fck = {
1660         .name           = "mcspi_fck",
1661         .id             = 1,
1662         .parent         = &core_48m_fck,
1663         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1664         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1665         .flags          = CLOCK_IN_OMAP343X,
1666         .clkdm          = { .name = "core_l4_clkdm" },
1667         .recalc         = &followparent_recalc,
1668 };
1669
1670 static struct clk uart2_fck = {
1671         .name           = "uart2_fck",
1672         .parent         = &core_48m_fck,
1673         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1674         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1675         .flags          = CLOCK_IN_OMAP343X,
1676         .clkdm          = { .name = "core_l4_clkdm" },
1677         .recalc         = &followparent_recalc,
1678 };
1679
1680 static struct clk uart1_fck = {
1681         .name           = "uart1_fck",
1682         .parent         = &core_48m_fck,
1683         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1684         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1685         .flags          = CLOCK_IN_OMAP343X,
1686         .clkdm          = { .name = "core_l4_clkdm" },
1687         .recalc         = &followparent_recalc,
1688 };
1689
1690 static struct clk fshostusb_fck = {
1691         .name           = "fshostusb_fck",
1692         .parent         = &core_48m_fck,
1693         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1694         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1695         .flags          = CLOCK_IN_OMAP3430ES1,
1696         .clkdm          = { .name = "core_l4_clkdm" },
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 /* CORE_12M_FCK based clocks */
1701
1702 static struct clk core_12m_fck = {
1703         .name           = "core_12m_fck",
1704         .parent         = &omap_12m_fck,
1705         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1706                                 PARENT_CONTROLS_CLOCK,
1707         .clkdm          = { .name = "core_l4_clkdm" },
1708         .recalc         = &followparent_recalc,
1709 };
1710
1711 static struct clk hdq_fck = {
1712         .name           = "hdq_fck",
1713         .parent         = &core_12m_fck,
1714         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1715         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1716         .flags          = CLOCK_IN_OMAP343X,
1717         .clkdm          = { .name = "core_l4_clkdm" },
1718         .recalc         = &followparent_recalc,
1719 };
1720
1721 /* DPLL3-derived clock */
1722
1723 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1724         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1725         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1726         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1727         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1728         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1729         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1730         { .div = 0 }
1731 };
1732
1733 static const struct clksel ssi_ssr_clksel[] = {
1734         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1735         { .parent = NULL }
1736 };
1737
1738 static struct clk ssi_ssr_fck = {
1739         .name           = "ssi_ssr_fck",
1740         .init           = &omap2_init_clksel_parent,
1741         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1742         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1743         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1744         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1745         .clksel         = ssi_ssr_clksel,
1746         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1747         .clkdm          = { .name = "core_l4_clkdm" },
1748         .recalc         = &omap2_clksel_recalc,
1749 };
1750
1751 static struct clk ssi_sst_fck = {
1752         .name           = "ssi_sst_fck",
1753         .parent         = &ssi_ssr_fck,
1754         .fixed_div      = 2,
1755         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1756         .clkdm          = { .name = "core_l4_clkdm" },
1757         .recalc         = &omap2_fixed_divisor_recalc,
1758 };
1759
1760
1761
1762 /* CORE_L3_ICK based clocks */
1763
1764 /*
1765  * XXX must add clk_enable/clk_disable for these if standard code won't
1766  * handle it
1767  */
1768 static struct clk core_l3_ick = {
1769         .name           = "core_l3_ick",
1770         .parent         = &l3_ick,
1771         .init           = &omap2_init_clk_clkdm,
1772         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1773                                 PARENT_CONTROLS_CLOCK,
1774         .clkdm          = { .name = "core_l3_clkdm" },
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 static struct clk hsotgusb_ick = {
1779         .name           = "hsotgusb_ick",
1780         .parent         = &core_l3_ick,
1781         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1782         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1783         .flags          = CLOCK_IN_OMAP343X,
1784         .clkdm          = { .name = "core_l3_clkdm" },
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk sdrc_ick = {
1789         .name           = "sdrc_ick",
1790         .parent         = &core_l3_ick,
1791         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1792         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1793         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1794         .clkdm          = { .name = "core_l3_clkdm" },
1795         .recalc         = &followparent_recalc,
1796 };
1797
1798 static struct clk gpmc_fck = {
1799         .name           = "gpmc_fck",
1800         .parent         = &core_l3_ick,
1801         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1802                                 ENABLE_ON_INIT,
1803         .clkdm          = { .name = "core_l3_clkdm" },
1804         .recalc         = &followparent_recalc,
1805 };
1806
1807 /* SECURITY_L3_ICK based clocks */
1808
1809 static struct clk security_l3_ick = {
1810         .name           = "security_l3_ick",
1811         .parent         = &l3_ick,
1812         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1813                                 PARENT_CONTROLS_CLOCK,
1814         .clkdm          = { .name = "core_l3_clkdm" },
1815         .recalc         = &followparent_recalc,
1816 };
1817
1818 static struct clk pka_ick = {
1819         .name           = "pka_ick",
1820         .parent         = &security_l3_ick,
1821         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1822         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1823         .flags          = CLOCK_IN_OMAP343X,
1824         .clkdm          = { .name = "core_l3_clkdm" },
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 /* CORE_L4_ICK based clocks */
1829
1830 static struct clk core_l4_ick = {
1831         .name           = "core_l4_ick",
1832         .parent         = &l4_ick,
1833         .init           = &omap2_init_clk_clkdm,
1834         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1835                                 PARENT_CONTROLS_CLOCK,
1836         .clkdm          = { .name = "core_l4_clkdm" },
1837         .recalc         = &followparent_recalc,
1838 };
1839
1840 static struct clk usbtll_ick = {
1841         .name           = "usbtll_ick",
1842         .parent         = &core_l4_ick,
1843         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1844         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1845         .flags          = CLOCK_IN_OMAP3430ES2,
1846         .clkdm          = { .name = "core_l4_clkdm" },
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk mmchs3_ick = {
1851         .name           = "mmchs_ick",
1852         .id             = 3,
1853         .parent         = &core_l4_ick,
1854         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1855         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1856         .flags          = CLOCK_IN_OMAP3430ES2,
1857         .clkdm          = { .name = "core_l4_clkdm" },
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 /* Intersystem Communication Registers - chassis mode only */
1862 static struct clk icr_ick = {
1863         .name           = "icr_ick",
1864         .parent         = &core_l4_ick,
1865         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1867         .flags          = CLOCK_IN_OMAP343X,
1868         .clkdm          = { .name = "core_l4_clkdm" },
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk aes2_ick = {
1873         .name           = "aes2_ick",
1874         .parent         = &core_l4_ick,
1875         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1876         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1877         .flags          = CLOCK_IN_OMAP343X,
1878         .clkdm          = { .name = "core_l4_clkdm" },
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk sha12_ick = {
1883         .name           = "sha12_ick",
1884         .parent         = &core_l4_ick,
1885         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1887         .flags          = CLOCK_IN_OMAP343X,
1888         .clkdm          = { .name = "core_l4_clkdm" },
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk des2_ick = {
1893         .name           = "des2_ick",
1894         .parent         = &core_l4_ick,
1895         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1897         .flags          = CLOCK_IN_OMAP343X,
1898         .clkdm          = { .name = "core_l4_clkdm" },
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk mmchs2_ick = {
1903         .name           = "mmchs_ick",
1904         .id             = 2,
1905         .parent         = &core_l4_ick,
1906         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1908         .flags          = CLOCK_IN_OMAP343X,
1909         .clkdm          = { .name = "core_l4_clkdm" },
1910         .recalc         = &followparent_recalc,
1911 };
1912
1913 static struct clk mmchs1_ick = {
1914         .name           = "mmchs_ick",
1915         .id             = 1,
1916         .parent         = &core_l4_ick,
1917         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1918         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1919         .flags          = CLOCK_IN_OMAP343X,
1920         .clkdm          = { .name = "core_l4_clkdm" },
1921         .recalc         = &followparent_recalc,
1922 };
1923
1924 static struct clk mspro_ick = {
1925         .name           = "mspro_ick",
1926         .parent         = &core_l4_ick,
1927         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1928         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1929         .flags          = CLOCK_IN_OMAP343X,
1930         .clkdm          = { .name = "core_l4_clkdm" },
1931         .recalc         = &followparent_recalc,
1932 };
1933
1934 static struct clk hdq_ick = {
1935         .name           = "hdq_ick",
1936         .parent         = &core_l4_ick,
1937         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1938         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1939         .flags          = CLOCK_IN_OMAP343X,
1940         .clkdm          = { .name = "core_l4_clkdm" },
1941         .recalc         = &followparent_recalc,
1942 };
1943
1944 static struct clk mcspi4_ick = {
1945         .name           = "mcspi_ick",
1946         .id             = 4,
1947         .parent         = &core_l4_ick,
1948         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1950         .flags          = CLOCK_IN_OMAP343X,
1951         .clkdm          = { .name = "core_l4_clkdm" },
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk mcspi3_ick = {
1956         .name           = "mcspi_ick",
1957         .id             = 3,
1958         .parent         = &core_l4_ick,
1959         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1960         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1961         .flags          = CLOCK_IN_OMAP343X,
1962         .clkdm          = { .name = "core_l4_clkdm" },
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk mcspi2_ick = {
1967         .name           = "mcspi_ick",
1968         .id             = 2,
1969         .parent         = &core_l4_ick,
1970         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1971         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1972         .flags          = CLOCK_IN_OMAP343X,
1973         .clkdm          = { .name = "core_l4_clkdm" },
1974         .recalc         = &followparent_recalc,
1975 };
1976
1977 static struct clk mcspi1_ick = {
1978         .name           = "mcspi_ick",
1979         .id             = 1,
1980         .parent         = &core_l4_ick,
1981         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1982         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1983         .flags          = CLOCK_IN_OMAP343X,
1984         .clkdm          = { .name = "core_l4_clkdm" },
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk i2c3_ick = {
1989         .name           = "i2c_ick",
1990         .id             = 3,
1991         .parent         = &core_l4_ick,
1992         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1994         .flags          = CLOCK_IN_OMAP343X,
1995         .clkdm          = { .name = "core_l4_clkdm" },
1996         .recalc         = &followparent_recalc,
1997 };
1998
1999 static struct clk i2c2_ick = {
2000         .name           = "i2c_ick",
2001         .id             = 2,
2002         .parent         = &core_l4_ick,
2003         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2004         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2005         .flags          = CLOCK_IN_OMAP343X,
2006         .clkdm          = { .name = "core_l4_clkdm" },
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 static struct clk i2c1_ick = {
2011         .name           = "i2c_ick",
2012         .id             = 1,
2013         .parent         = &core_l4_ick,
2014         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2015         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2016         .flags          = CLOCK_IN_OMAP343X,
2017         .clkdm          = { .name = "core_l4_clkdm" },
2018         .recalc         = &followparent_recalc,
2019 };
2020
2021 static struct clk uart2_ick = {
2022         .name           = "uart2_ick",
2023         .parent         = &core_l4_ick,
2024         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2025         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2026         .flags          = CLOCK_IN_OMAP343X,
2027         .clkdm          = { .name = "core_l4_clkdm" },
2028         .recalc         = &followparent_recalc,
2029 };
2030
2031 static struct clk uart1_ick = {
2032         .name           = "uart1_ick",
2033         .parent         = &core_l4_ick,
2034         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2035         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2036         .flags          = CLOCK_IN_OMAP343X,
2037         .clkdm          = { .name = "core_l4_clkdm" },
2038         .recalc         = &followparent_recalc,
2039 };
2040
2041 static struct clk gpt11_ick = {
2042         .name           = "gpt11_ick",
2043         .parent         = &core_l4_ick,
2044         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2045         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2046         .flags          = CLOCK_IN_OMAP343X,
2047         .clkdm          = { .name = "core_l4_clkdm" },
2048         .recalc         = &followparent_recalc,
2049 };
2050
2051 static struct clk gpt10_ick = {
2052         .name           = "gpt10_ick",
2053         .parent         = &core_l4_ick,
2054         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2055         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2056         .flags          = CLOCK_IN_OMAP343X,
2057         .clkdm          = { .name = "core_l4_clkdm" },
2058         .recalc         = &followparent_recalc,
2059 };
2060
2061 static struct clk mcbsp5_ick = {
2062         .name           = "mcbsp_ick",
2063         .id             = 5,
2064         .parent         = &core_l4_ick,
2065         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2066         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2067         .flags          = CLOCK_IN_OMAP343X,
2068         .clkdm          = { .name = "core_l4_clkdm" },
2069         .recalc         = &followparent_recalc,
2070 };
2071
2072 static struct clk mcbsp1_ick = {
2073         .name           = "mcbsp_ick",
2074         .id             = 1,
2075         .parent         = &core_l4_ick,
2076         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2077         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2078         .flags          = CLOCK_IN_OMAP343X,
2079         .clkdm          = { .name = "core_l4_clkdm" },
2080         .recalc         = &followparent_recalc,
2081 };
2082
2083 static struct clk fac_ick = {
2084         .name           = "fac_ick",
2085         .parent         = &core_l4_ick,
2086         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2087         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2088         .flags          = CLOCK_IN_OMAP3430ES1,
2089         .clkdm          = { .name = "core_l4_clkdm" },
2090         .recalc         = &followparent_recalc,
2091 };
2092
2093 static struct clk mailboxes_ick = {
2094         .name           = "mailboxes_ick",
2095         .parent         = &core_l4_ick,
2096         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2097         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2098         .flags          = CLOCK_IN_OMAP343X,
2099         .clkdm          = { .name = "core_l4_clkdm" },
2100         .recalc         = &followparent_recalc,
2101 };
2102
2103 static struct clk omapctrl_ick = {
2104         .name           = "omapctrl_ick",
2105         .parent         = &core_l4_ick,
2106         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2107         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2108         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2109         .clkdm          = { .name = "core_l4_clkdm" },
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 /* SSI_L4_ICK based clocks */
2114
2115 static struct clk ssi_l4_ick = {
2116         .name           = "ssi_l4_ick",
2117         .parent         = &l4_ick,
2118         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2119                                 PARENT_CONTROLS_CLOCK,
2120         .clkdm          = { .name = "core_l4_clkdm" },
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 static struct clk ssi_ick = {
2125         .name           = "ssi_ick",
2126         .parent         = &ssi_l4_ick,
2127         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2128         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2129         .flags          = CLOCK_IN_OMAP343X,
2130         .clkdm          = { .name = "core_l4_clkdm" },
2131         .recalc         = &followparent_recalc,
2132 };
2133
2134 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2135  * but l4_ick makes more sense to me */
2136
2137 static const struct clksel usb_l4_clksel[] = {
2138         { .parent = &l4_ick, .rates = div2_rates },
2139         { .parent = NULL },
2140 };
2141
2142 static struct clk usb_l4_ick = {
2143         .name           = "usb_l4_ick",
2144         .parent         = &l4_ick,
2145         .init           = &omap2_init_clksel_parent,
2146         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2147         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2148         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2149         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2150         .clksel         = usb_l4_clksel,
2151         .flags          = CLOCK_IN_OMAP3430ES1,
2152         .clkdm          = { .name = "core_l4_clkdm" },
2153         .recalc         = &omap2_clksel_recalc,
2154 };
2155
2156 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2157
2158 /* SECURITY_L4_ICK2 based clocks */
2159
2160 static struct clk security_l4_ick2 = {
2161         .name           = "security_l4_ick2",
2162         .parent         = &l4_ick,
2163         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2164                                 PARENT_CONTROLS_CLOCK,
2165         .clkdm          = { .name = "core_l4_clkdm" },
2166         .recalc         = &followparent_recalc,
2167 };
2168
2169 static struct clk aes1_ick = {
2170         .name           = "aes1_ick",
2171         .parent         = &security_l4_ick2,
2172         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2173         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2174         .flags          = CLOCK_IN_OMAP343X,
2175         .clkdm          = { .name = "core_l4_clkdm" },
2176         .recalc         = &followparent_recalc,
2177 };
2178
2179 static struct clk rng_ick = {
2180         .name           = "rng_ick",
2181         .parent         = &security_l4_ick2,
2182         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2183         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2184         .flags          = CLOCK_IN_OMAP343X,
2185         .clkdm          = { .name = "core_l4_clkdm" },
2186         .recalc         = &followparent_recalc,
2187 };
2188
2189 static struct clk sha11_ick = {
2190         .name           = "sha11_ick",
2191         .parent         = &security_l4_ick2,
2192         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2193         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2194         .flags          = CLOCK_IN_OMAP343X,
2195         .clkdm          = { .name = "core_l4_clkdm" },
2196         .recalc         = &followparent_recalc,
2197 };
2198
2199 static struct clk des1_ick = {
2200         .name           = "des1_ick",
2201         .parent         = &security_l4_ick2,
2202         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2203         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2204         .flags          = CLOCK_IN_OMAP343X,
2205         .clkdm          = { .name = "core_l4_clkdm" },
2206         .recalc         = &followparent_recalc,
2207 };
2208
2209 /* DSS */
2210 static const struct clksel dss1_alwon_fck_clksel[] = {
2211         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2212         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2213         { .parent = NULL }
2214 };
2215
2216 static struct clk dss1_alwon_fck = {
2217         .name           = "dss1_alwon_fck",
2218         .parent         = &dpll4_m4x2_ck,
2219         .init           = &omap2_init_clksel_parent,
2220         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2221         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2222         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2223         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2224         .clksel         = dss1_alwon_fck_clksel,
2225         .flags          = CLOCK_IN_OMAP343X,
2226         .clkdm          = { .name = "dss_clkdm" },
2227         .recalc         = &omap2_clksel_recalc,
2228 };
2229
2230 static struct clk dss_tv_fck = {
2231         .name           = "dss_tv_fck",
2232         .parent         = &omap_54m_fck,
2233         .init           = &omap2_init_clk_clkdm,
2234         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2235         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2236         .flags          = CLOCK_IN_OMAP343X,
2237         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2238         .recalc         = &followparent_recalc,
2239 };
2240
2241 static struct clk dss_96m_fck = {
2242         .name           = "dss_96m_fck",
2243         .parent         = &omap_96m_fck,
2244         .init           = &omap2_init_clk_clkdm,
2245         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2246         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2247         .flags          = CLOCK_IN_OMAP343X,
2248         .clkdm          = { .name = "dss_clkdm" },
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk dss2_alwon_fck = {
2253         .name           = "dss2_alwon_fck",
2254         .parent         = &sys_ck,
2255         .init           = &omap2_init_clk_clkdm,
2256         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2257         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2258         .flags          = CLOCK_IN_OMAP343X,
2259         .clkdm          = { .name = "dss_clkdm" },
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk dss_ick = {
2264         /* Handles both L3 and L4 clocks */
2265         .name           = "dss_ick",
2266         .parent         = &l4_ick,
2267         .init           = &omap2_init_clk_clkdm,
2268         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2269         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2270         .flags          = CLOCK_IN_OMAP343X,
2271         .clkdm          = { .name = "dss_clkdm" },
2272         .recalc         = &followparent_recalc,
2273 };
2274
2275 /* CAM */
2276
2277 static const struct clksel cam_mclk_clksel[] = {
2278         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2279         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2280         { .parent = NULL }
2281 };
2282
2283 static struct clk cam_mclk = {
2284         .name           = "cam_mclk",
2285         .parent         = &dpll4_m5x2_ck,
2286         .init           = &omap2_init_clksel_parent,
2287         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2288         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2289         .clksel         = cam_mclk_clksel,
2290         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2291         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2292         .flags          = CLOCK_IN_OMAP343X,
2293         .clkdm          = { .name = "cam_clkdm" },
2294         .recalc         = &omap2_clksel_recalc,
2295 };
2296
2297 static struct clk cam_ick = {
2298         /* Handles both L3 and L4 clocks */
2299         .name           = "cam_ick",
2300         .parent         = &l4_ick,
2301         .init           = &omap2_init_clk_clkdm,
2302         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2303         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2304         .flags          = CLOCK_IN_OMAP343X,
2305         .clkdm          = { .name = "cam_clkdm" },
2306         .recalc         = &followparent_recalc,
2307 };
2308
2309 static struct clk csi2_96m_fck = {
2310         .name           = "csi2_96m_fck",
2311         .parent         = &core_96m_fck,
2312         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2313         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2314         .flags          = CLOCK_IN_OMAP343X,
2315         .clkdm          = { .name = "cam_clkdm" },
2316         .recalc         = &followparent_recalc,
2317 };
2318
2319 /* USBHOST - 3430ES2 only */
2320
2321 static struct clk usbhost_120m_fck = {
2322         .name           = "usbhost_120m_fck",
2323         .parent         = &omap_120m_fck,
2324         .init           = &omap2_init_clk_clkdm,
2325         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2326         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2327         .flags          = CLOCK_IN_OMAP3430ES2,
2328         .clkdm          = { .name = "usbhost_clkdm" },
2329         .recalc         = &followparent_recalc,
2330 };
2331
2332 static struct clk usbhost_48m_fck = {
2333         .name           = "usbhost_48m_fck",
2334         .parent         = &omap_48m_fck,
2335         .init           = &omap2_init_clk_clkdm,
2336         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2337         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2338         .flags          = CLOCK_IN_OMAP3430ES2,
2339         .clkdm          = { .name = "usbhost_clkdm" },
2340         .recalc         = &followparent_recalc,
2341 };
2342
2343 static struct clk usbhost_ick = {
2344         /* Handles both L3 and L4 clocks */
2345         .name           = "usbhost_ick",
2346         .parent         = &l4_ick,
2347         .init           = &omap2_init_clk_clkdm,
2348         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2349         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2350         .flags          = CLOCK_IN_OMAP3430ES2,
2351         .clkdm          = { .name = "usbhost_clkdm" },
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 /* WKUP */
2356
2357 static const struct clksel_rate usim_96m_rates[] = {
2358         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2359         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2360         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2361         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2362         { .div = 0 },
2363 };
2364
2365 static const struct clksel_rate usim_120m_rates[] = {
2366         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2367         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2368         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2369         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2370         { .div = 0 },
2371 };
2372
2373 static const struct clksel usim_clksel[] = {
2374         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2375         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2376         { .parent = &sys_ck,            .rates = div2_rates },
2377         { .parent = NULL },
2378 };
2379
2380 /* 3430ES2 only */
2381 static struct clk usim_fck = {
2382         .name           = "usim_fck",
2383         .init           = &omap2_init_clksel_parent,
2384         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2385         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2386         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2387         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2388         .clksel         = usim_clksel,
2389         .flags          = CLOCK_IN_OMAP3430ES2,
2390         .clkdm          = { .name = "prm_clkdm" },
2391         .recalc         = &omap2_clksel_recalc,
2392 };
2393
2394 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2395 static struct clk gpt1_fck = {
2396         .name           = "gpt1_fck",
2397         .init           = &omap2_init_clksel_parent,
2398         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2399         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2400         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2401         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2402         .clksel         = omap343x_gpt_clksel,
2403         .flags          = CLOCK_IN_OMAP343X,
2404         .clkdm          = { .name = "prm_clkdm" },
2405         .recalc         = &omap2_clksel_recalc,
2406 };
2407
2408 static struct clk wkup_32k_fck = {
2409         .name           = "wkup_32k_fck",
2410         .init           = &omap2_init_clk_clkdm,
2411         .parent         = &omap_32k_fck,
2412         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2413         .clkdm          = { .name = "prm_clkdm" },
2414         .recalc         = &followparent_recalc,
2415 };
2416
2417 static struct clk gpio1_fck = {
2418         .name           = "gpio1_fck",
2419         .parent         = &wkup_32k_fck,
2420         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2421         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2422         .flags          = CLOCK_IN_OMAP343X,
2423         .clkdm          = { .name = "prm_clkdm" },
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk wdt2_fck = {
2428         .name           = "wdt2_fck",
2429         .parent         = &wkup_32k_fck,
2430         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2431         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2432         .flags          = CLOCK_IN_OMAP343X,
2433         .clkdm          = { .name = "prm_clkdm" },
2434         .recalc         = &followparent_recalc,
2435 };
2436
2437 static struct clk wkup_l4_ick = {
2438         .name           = "wkup_l4_ick",
2439         .parent         = &sys_ck,
2440         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2441         .clkdm          = { .name = "prm_clkdm" },
2442         .recalc         = &followparent_recalc,
2443 };
2444
2445 /* 3430ES2 only */
2446 /* Never specifically named in the TRM, so we have to infer a likely name */
2447 static struct clk usim_ick = {
2448         .name           = "usim_ick",
2449         .parent         = &wkup_l4_ick,
2450         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2451         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2452         .flags          = CLOCK_IN_OMAP3430ES2,
2453         .clkdm          = { .name = "prm_clkdm" },
2454         .recalc         = &followparent_recalc,
2455 };
2456
2457 static struct clk wdt2_ick = {
2458         .name           = "wdt2_ick",
2459         .parent         = &wkup_l4_ick,
2460         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2461         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2462         .flags          = CLOCK_IN_OMAP343X,
2463         .clkdm          = { .name = "prm_clkdm" },
2464         .recalc         = &followparent_recalc,
2465 };
2466
2467 static struct clk wdt1_ick = {
2468         .name           = "wdt1_ick",
2469         .parent         = &wkup_l4_ick,
2470         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2471         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2472         .flags          = CLOCK_IN_OMAP343X,
2473         .clkdm          = { .name = "prm_clkdm" },
2474         .recalc         = &followparent_recalc,
2475 };
2476
2477 static struct clk gpio1_ick = {
2478         .name           = "gpio1_ick",
2479         .parent         = &wkup_l4_ick,
2480         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2481         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2482         .flags          = CLOCK_IN_OMAP343X,
2483         .clkdm          = { .name = "prm_clkdm" },
2484         .recalc         = &followparent_recalc,
2485 };
2486
2487 static struct clk omap_32ksync_ick = {
2488         .name           = "omap_32ksync_ick",
2489         .parent         = &wkup_l4_ick,
2490         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2491         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2492         .flags          = CLOCK_IN_OMAP343X,
2493         .clkdm          = { .name = "prm_clkdm" },
2494         .recalc         = &followparent_recalc,
2495 };
2496
2497 static struct clk gpt12_ick = {
2498         .name           = "gpt12_ick",
2499         .parent         = &wkup_l4_ick,
2500         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2501         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2502         .flags          = CLOCK_IN_OMAP343X,
2503         .clkdm          = { .name = "prm_clkdm" },
2504         .recalc         = &followparent_recalc,
2505 };
2506
2507 static struct clk gpt1_ick = {
2508         .name           = "gpt1_ick",
2509         .parent         = &wkup_l4_ick,
2510         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2511         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2512         .flags          = CLOCK_IN_OMAP343X,
2513         .clkdm          = { .name = "prm_clkdm" },
2514         .recalc         = &followparent_recalc,
2515 };
2516
2517
2518
2519 /* PER clock domain */
2520
2521 static struct clk per_96m_fck = {
2522         .name           = "per_96m_fck",
2523         .parent         = &omap_96m_alwon_fck,
2524         .init           = &omap2_init_clk_clkdm,
2525         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2526                                 PARENT_CONTROLS_CLOCK,
2527         .clkdm          = { .name = "per_clkdm" },
2528         .recalc         = &followparent_recalc,
2529 };
2530
2531 static struct clk per_48m_fck = {
2532         .name           = "per_48m_fck",
2533         .parent         = &omap_48m_fck,
2534         .init           = &omap2_init_clk_clkdm,
2535         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2536                                 PARENT_CONTROLS_CLOCK,
2537         .clkdm          = { .name = "per_clkdm" },
2538         .recalc         = &followparent_recalc,
2539 };
2540
2541 static struct clk uart3_fck = {
2542         .name           = "uart3_fck",
2543         .parent         = &per_48m_fck,
2544         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2545         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2546         .flags          = CLOCK_IN_OMAP343X,
2547         .clkdm          = { .name = "per_clkdm" },
2548         .recalc         = &followparent_recalc,
2549 };
2550
2551 static struct clk gpt2_fck = {
2552         .name           = "gpt2_fck",
2553         .init           = &omap2_init_clksel_parent,
2554         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2555         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2556         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2557         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2558         .clksel         = omap343x_gpt_clksel,
2559         .flags          = CLOCK_IN_OMAP343X,
2560         .clkdm          = { .name = "per_clkdm" },
2561         .recalc         = &omap2_clksel_recalc,
2562 };
2563
2564 static struct clk gpt3_fck = {
2565         .name           = "gpt3_fck",
2566         .init           = &omap2_init_clksel_parent,
2567         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2568         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2569         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2570         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2571         .clksel         = omap343x_gpt_clksel,
2572         .flags          = CLOCK_IN_OMAP343X,
2573         .clkdm          = { .name = "per_clkdm" },
2574         .recalc         = &omap2_clksel_recalc,
2575 };
2576
2577 static struct clk gpt4_fck = {
2578         .name           = "gpt4_fck",
2579         .init           = &omap2_init_clksel_parent,
2580         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2581         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2582         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2583         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2584         .clksel         = omap343x_gpt_clksel,
2585         .flags          = CLOCK_IN_OMAP343X,
2586         .clkdm          = { .name = "per_clkdm" },
2587         .recalc         = &omap2_clksel_recalc,
2588 };
2589
2590 static struct clk gpt5_fck = {
2591         .name           = "gpt5_fck",
2592         .init           = &omap2_init_clksel_parent,
2593         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2594         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2595         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2596         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2597         .clksel         = omap343x_gpt_clksel,
2598         .flags          = CLOCK_IN_OMAP343X,
2599         .clkdm          = { .name = "per_clkdm" },
2600         .recalc         = &omap2_clksel_recalc,
2601 };
2602
2603 static struct clk gpt6_fck = {
2604         .name           = "gpt6_fck",
2605         .init           = &omap2_init_clksel_parent,
2606         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2607         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2608         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2609         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2610         .clksel         = omap343x_gpt_clksel,
2611         .flags          = CLOCK_IN_OMAP343X,
2612         .clkdm          = { .name = "per_clkdm" },
2613         .recalc         = &omap2_clksel_recalc,
2614 };
2615
2616 static struct clk gpt7_fck = {
2617         .name           = "gpt7_fck",
2618         .init           = &omap2_init_clksel_parent,
2619         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2620         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2621         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2622         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2623         .clksel         = omap343x_gpt_clksel,
2624         .flags          = CLOCK_IN_OMAP343X,
2625         .clkdm          = { .name = "per_clkdm" },
2626         .recalc         = &omap2_clksel_recalc,
2627 };
2628
2629 static struct clk gpt8_fck = {
2630         .name           = "gpt8_fck",
2631         .init           = &omap2_init_clksel_parent,
2632         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2633         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2634         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2635         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2636         .clksel         = omap343x_gpt_clksel,
2637         .flags          = CLOCK_IN_OMAP343X,
2638         .clkdm          = { .name = "per_clkdm" },
2639         .recalc         = &omap2_clksel_recalc,
2640 };
2641
2642 static struct clk gpt9_fck = {
2643         .name           = "gpt9_fck",
2644         .init           = &omap2_init_clksel_parent,
2645         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2646         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2647         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2648         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2649         .clksel         = omap343x_gpt_clksel,
2650         .flags          = CLOCK_IN_OMAP343X,
2651         .clkdm          = { .name = "per_clkdm" },
2652         .recalc         = &omap2_clksel_recalc,
2653 };
2654
2655 static struct clk per_32k_alwon_fck = {
2656         .name           = "per_32k_alwon_fck",
2657         .parent         = &omap_32k_fck,
2658         .clkdm          = { .name = "per_clkdm" },
2659         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2660         .recalc         = &followparent_recalc,
2661 };
2662
2663 static struct clk gpio6_fck = {
2664         .name           = "gpio6_fck",
2665         .parent         = &per_32k_alwon_fck,
2666         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2667         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2668         .flags          = CLOCK_IN_OMAP343X,
2669         .clkdm          = { .name = "per_clkdm" },
2670         .recalc         = &followparent_recalc,
2671 };
2672
2673 static struct clk gpio5_fck = {
2674         .name           = "gpio5_fck",
2675         .parent         = &per_32k_alwon_fck,
2676         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2677         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2678         .flags          = CLOCK_IN_OMAP343X,
2679         .clkdm          = { .name = "per_clkdm" },
2680         .recalc         = &followparent_recalc,
2681 };
2682
2683 static struct clk gpio4_fck = {
2684         .name           = "gpio4_fck",
2685         .parent         = &per_32k_alwon_fck,
2686         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2687         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2688         .flags          = CLOCK_IN_OMAP343X,
2689         .clkdm          = { .name = "per_clkdm" },
2690         .recalc         = &followparent_recalc,
2691 };
2692
2693 static struct clk gpio3_fck = {
2694         .name           = "gpio3_fck",
2695         .parent         = &per_32k_alwon_fck,
2696         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2697         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2698         .flags          = CLOCK_IN_OMAP343X,
2699         .clkdm          = { .name = "per_clkdm" },
2700         .recalc         = &followparent_recalc,
2701 };
2702
2703 static struct clk gpio2_fck = {
2704         .name           = "gpio2_fck",
2705         .parent         = &per_32k_alwon_fck,
2706         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2707         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2708         .flags          = CLOCK_IN_OMAP343X,
2709         .clkdm          = { .name = "per_clkdm" },
2710         .recalc         = &followparent_recalc,
2711 };
2712
2713 static struct clk wdt3_fck = {
2714         .name           = "wdt3_fck",
2715         .parent         = &per_32k_alwon_fck,
2716         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2717         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2718         .flags          = CLOCK_IN_OMAP343X,
2719         .clkdm          = { .name = "per_clkdm" },
2720         .recalc         = &followparent_recalc,
2721 };
2722
2723 static struct clk per_l4_ick = {
2724         .name           = "per_l4_ick",
2725         .parent         = &l4_ick,
2726         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2727                                 PARENT_CONTROLS_CLOCK,
2728         .clkdm          = { .name = "per_clkdm" },
2729         .recalc         = &followparent_recalc,
2730 };
2731
2732 static struct clk gpio6_ick = {
2733         .name           = "gpio6_ick",
2734         .parent         = &per_l4_ick,
2735         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2736         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2737         .flags          = CLOCK_IN_OMAP343X,
2738         .clkdm          = { .name = "per_clkdm" },
2739         .recalc         = &followparent_recalc,
2740 };
2741
2742 static struct clk gpio5_ick = {
2743         .name           = "gpio5_ick",
2744         .parent         = &per_l4_ick,
2745         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2746         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2747         .flags          = CLOCK_IN_OMAP343X,
2748         .clkdm          = { .name = "per_clkdm" },
2749         .recalc         = &followparent_recalc,
2750 };
2751
2752 static struct clk gpio4_ick = {
2753         .name           = "gpio4_ick",
2754         .parent         = &per_l4_ick,
2755         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2756         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2757         .flags          = CLOCK_IN_OMAP343X,
2758         .clkdm          = { .name = "per_clkdm" },
2759         .recalc         = &followparent_recalc,
2760 };
2761
2762 static struct clk gpio3_ick = {
2763         .name           = "gpio3_ick",
2764         .parent         = &per_l4_ick,
2765         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2766         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2767         .flags          = CLOCK_IN_OMAP343X,
2768         .clkdm          = { .name = "per_clkdm" },
2769         .recalc         = &followparent_recalc,
2770 };
2771
2772 static struct clk gpio2_ick = {
2773         .name           = "gpio2_ick",
2774         .parent         = &per_l4_ick,
2775         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2776         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2777         .flags          = CLOCK_IN_OMAP343X,
2778         .clkdm          = { .name = "per_clkdm" },
2779         .recalc         = &followparent_recalc,
2780 };
2781
2782 static struct clk wdt3_ick = {
2783         .name           = "wdt3_ick",
2784         .parent         = &per_l4_ick,
2785         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2786         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2787         .flags          = CLOCK_IN_OMAP343X,
2788         .clkdm          = { .name = "per_clkdm" },
2789         .recalc         = &followparent_recalc,
2790 };
2791
2792 static struct clk uart3_ick = {
2793         .name           = "uart3_ick",
2794         .parent         = &per_l4_ick,
2795         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2796         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2797         .flags          = CLOCK_IN_OMAP343X,
2798         .clkdm          = { .name = "per_clkdm" },
2799         .recalc         = &followparent_recalc,
2800 };
2801
2802 static struct clk gpt9_ick = {
2803         .name           = "gpt9_ick",
2804         .parent         = &per_l4_ick,
2805         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2806         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2807         .flags          = CLOCK_IN_OMAP343X,
2808         .clkdm          = { .name = "per_clkdm" },
2809         .recalc         = &followparent_recalc,
2810 };
2811
2812 static struct clk gpt8_ick = {
2813         .name           = "gpt8_ick",
2814         .parent         = &per_l4_ick,
2815         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2816         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2817         .flags          = CLOCK_IN_OMAP343X,
2818         .clkdm          = { .name = "per_clkdm" },
2819         .recalc         = &followparent_recalc,
2820 };
2821
2822 static struct clk gpt7_ick = {
2823         .name           = "gpt7_ick",
2824         .parent         = &per_l4_ick,
2825         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2826         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2827         .flags          = CLOCK_IN_OMAP343X,
2828         .clkdm          = { .name = "per_clkdm" },
2829         .recalc         = &followparent_recalc,
2830 };
2831
2832 static struct clk gpt6_ick = {
2833         .name           = "gpt6_ick",
2834         .parent         = &per_l4_ick,
2835         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2836         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2837         .flags          = CLOCK_IN_OMAP343X,
2838         .clkdm          = { .name = "per_clkdm" },
2839         .recalc         = &followparent_recalc,
2840 };
2841
2842 static struct clk gpt5_ick = {
2843         .name           = "gpt5_ick",
2844         .parent         = &per_l4_ick,
2845         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2846         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2847         .flags          = CLOCK_IN_OMAP343X,
2848         .clkdm          = { .name = "per_clkdm" },
2849         .recalc         = &followparent_recalc,
2850 };
2851
2852 static struct clk gpt4_ick = {
2853         .name           = "gpt4_ick",
2854         .parent         = &per_l4_ick,
2855         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2856         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2857         .flags          = CLOCK_IN_OMAP343X,
2858         .clkdm          = { .name = "per_clkdm" },
2859         .recalc         = &followparent_recalc,
2860 };
2861
2862 static struct clk gpt3_ick = {
2863         .name           = "gpt3_ick",
2864         .parent         = &per_l4_ick,
2865         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2866         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2867         .flags          = CLOCK_IN_OMAP343X,
2868         .clkdm          = { .name = "per_clkdm" },
2869         .recalc         = &followparent_recalc,
2870 };
2871
2872 static struct clk gpt2_ick = {
2873         .name           = "gpt2_ick",
2874         .parent         = &per_l4_ick,
2875         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2876         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2877         .flags          = CLOCK_IN_OMAP343X,
2878         .clkdm          = { .name = "per_clkdm" },
2879         .recalc         = &followparent_recalc,
2880 };
2881
2882 static struct clk mcbsp2_ick = {
2883         .name           = "mcbsp_ick",
2884         .id             = 2,
2885         .parent         = &per_l4_ick,
2886         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2887         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2888         .flags          = CLOCK_IN_OMAP343X,
2889         .clkdm          = { .name = "per_clkdm" },
2890         .recalc         = &followparent_recalc,
2891 };
2892
2893 static struct clk mcbsp3_ick = {
2894         .name           = "mcbsp_ick",
2895         .id             = 3,
2896         .parent         = &per_l4_ick,
2897         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2898         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2899         .flags          = CLOCK_IN_OMAP343X,
2900         .clkdm          = { .name = "per_clkdm" },
2901         .recalc         = &followparent_recalc,
2902 };
2903
2904 static struct clk mcbsp4_ick = {
2905         .name           = "mcbsp_ick",
2906         .id             = 4,
2907         .parent         = &per_l4_ick,
2908         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2909         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2910         .flags          = CLOCK_IN_OMAP343X,
2911         .clkdm          = { .name = "per_clkdm" },
2912         .recalc         = &followparent_recalc,
2913 };
2914
2915 static const struct clksel mcbsp_234_clksel[] = {
2916         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2917         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2918         { .parent = NULL }
2919 };
2920
2921 static struct clk mcbsp2_fck = {
2922         .name           = "mcbsp_fck",
2923         .id             = 2,
2924         .init           = &omap2_init_clksel_parent,
2925         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2926         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2927         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2928         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2929         .clksel         = mcbsp_234_clksel,
2930         .flags          = CLOCK_IN_OMAP343X,
2931         .clkdm          = { .name = "per_clkdm" },
2932         .recalc         = &omap2_clksel_recalc,
2933 };
2934
2935 static struct clk mcbsp3_fck = {
2936         .name           = "mcbsp_fck",
2937         .id             = 3,
2938         .init           = &omap2_init_clksel_parent,
2939         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2940         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2941         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2942         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2943         .clksel         = mcbsp_234_clksel,
2944         .flags          = CLOCK_IN_OMAP343X,
2945         .clkdm          = { .name = "per_clkdm" },
2946         .recalc         = &omap2_clksel_recalc,
2947 };
2948
2949 static struct clk mcbsp4_fck = {
2950         .name           = "mcbsp_fck",
2951         .id             = 4,
2952         .init           = &omap2_init_clksel_parent,
2953         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2954         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2955         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2956         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2957         .clksel         = mcbsp_234_clksel,
2958         .flags          = CLOCK_IN_OMAP343X,
2959         .clkdm          = { .name = "per_clkdm" },
2960         .recalc         = &omap2_clksel_recalc,
2961 };
2962
2963 /* EMU clocks */
2964
2965 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2966
2967 static const struct clksel_rate emu_src_sys_rates[] = {
2968         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2969         { .div = 0 },
2970 };
2971
2972 static const struct clksel_rate emu_src_core_rates[] = {
2973         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2974         { .div = 0 },
2975 };
2976
2977 static const struct clksel_rate emu_src_per_rates[] = {
2978         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2979         { .div = 0 },
2980 };
2981
2982 static const struct clksel_rate emu_src_mpu_rates[] = {
2983         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2984         { .div = 0 },
2985 };
2986
2987 static const struct clksel emu_src_clksel[] = {
2988         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2989         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2990         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2991         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2992         { .parent = NULL },
2993 };
2994
2995 /*
2996  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2997  * to switch the source of some of the EMU clocks.
2998  * XXX Are there CLKEN bits for these EMU clks?
2999  */
3000 static struct clk emu_src_ck = {
3001         .name           = "emu_src_ck",
3002         .init           = &omap2_init_clksel_parent,
3003         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3004         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
3005         .clksel         = emu_src_clksel,
3006         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3007         .clkdm          = { .name = "emu_clkdm" },
3008         .recalc         = &omap2_clksel_recalc,
3009 };
3010
3011 static const struct clksel_rate pclk_emu_rates[] = {
3012         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3013         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3014         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3015         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3016         { .div = 0 },
3017 };
3018
3019 static const struct clksel pclk_emu_clksel[] = {
3020         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3021         { .parent = NULL },
3022 };
3023
3024 static struct clk pclk_fck = {
3025         .name           = "pclk_fck",
3026         .init           = &omap2_init_clksel_parent,
3027         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3028         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3029         .clksel         = pclk_emu_clksel,
3030         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3031         .clkdm          = { .name = "emu_clkdm" },
3032         .recalc         = &omap2_clksel_recalc,
3033 };
3034
3035 static const struct clksel_rate pclkx2_emu_rates[] = {
3036         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3037         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3038         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3039         { .div = 0 },
3040 };
3041
3042 static const struct clksel pclkx2_emu_clksel[] = {
3043         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3044         { .parent = NULL },
3045 };
3046
3047 static struct clk pclkx2_fck = {
3048         .name           = "pclkx2_fck",
3049         .init           = &omap2_init_clksel_parent,
3050         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3051         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3052         .clksel         = pclkx2_emu_clksel,
3053         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3054         .clkdm          = { .name = "emu_clkdm" },
3055         .recalc         = &omap2_clksel_recalc,
3056 };
3057
3058 static const struct clksel atclk_emu_clksel[] = {
3059         { .parent = &emu_src_ck, .rates = div2_rates },
3060         { .parent = NULL },
3061 };
3062
3063 static struct clk atclk_fck = {
3064         .name           = "atclk_fck",
3065         .init           = &omap2_init_clksel_parent,
3066         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3067         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3068         .clksel         = atclk_emu_clksel,
3069         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3070         .clkdm          = { .name = "emu_clkdm" },
3071         .recalc         = &omap2_clksel_recalc,
3072 };
3073
3074 static struct clk traceclk_src_fck = {
3075         .name           = "traceclk_src_fck",
3076         .init           = &omap2_init_clksel_parent,
3077         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3078         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3079         .clksel         = emu_src_clksel,
3080         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3081         .clkdm          = { .name = "emu_clkdm" },
3082         .recalc         = &omap2_clksel_recalc,
3083 };
3084
3085 static const struct clksel_rate traceclk_rates[] = {
3086         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3087         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3088         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3089         { .div = 0 },
3090 };
3091
3092 static const struct clksel traceclk_clksel[] = {
3093         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3094         { .parent = NULL },
3095 };
3096
3097 static struct clk traceclk_fck = {
3098         .name           = "traceclk_fck",
3099         .init           = &omap2_init_clksel_parent,
3100         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3101         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3102         .clksel         = traceclk_clksel,
3103         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3104         .clkdm          = { .name = "emu_clkdm" },
3105         .recalc         = &omap2_clksel_recalc,
3106 };
3107
3108 /* SR clocks */
3109
3110 /* SmartReflex fclk (VDD1) */
3111 static struct clk sr1_fck = {
3112         .name           = "sr1_fck",
3113         .parent         = &sys_ck,
3114         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3115         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3116         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3117         .clkdm          = { .name = "prm_clkdm" },
3118         .recalc         = &followparent_recalc,
3119 };
3120
3121 /* SmartReflex fclk (VDD2) */
3122 static struct clk sr2_fck = {
3123         .name           = "sr2_fck",
3124         .parent         = &sys_ck,
3125         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3126         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3127         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3128         .clkdm          = { .name = "prm_clkdm" },
3129         .recalc         = &followparent_recalc,
3130 };
3131
3132 static struct clk sr_l4_ick = {
3133         .name           = "sr_l4_ick",
3134         .parent         = &l4_ick,
3135         .flags          = CLOCK_IN_OMAP343X,
3136         .clkdm          = { .name = "core_l4_clkdm" },
3137         .recalc         = &followparent_recalc,
3138 };
3139
3140 /* SECURE_32K_FCK clocks */
3141
3142 /* XXX This clock no longer exists in 3430 TRM rev F */
3143 static struct clk gpt12_fck = {
3144         .name           = "gpt12_fck",
3145         .parent         = &secure_32k_fck,
3146         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3147         .clkdm          = { .name = "prm_clkdm" },
3148         .recalc         = &followparent_recalc,
3149 };
3150
3151 static struct clk wdt1_fck = {
3152         .name           = "wdt1_fck",
3153         .parent         = &secure_32k_fck,
3154         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3155         .clkdm          = { .name = "prm_clkdm" },
3156         .recalc         = &followparent_recalc,
3157 };
3158
3159 static struct clk *onchip_34xx_clks[] __initdata = {
3160         &omap_32k_fck,
3161         &virt_12m_ck,
3162         &virt_13m_ck,
3163         &virt_16_8m_ck,
3164         &virt_19_2m_ck,
3165         &virt_26m_ck,
3166         &virt_38_4m_ck,
3167         &osc_sys_ck,
3168         &sys_ck,
3169         &sys_altclk,
3170         &mcbsp_clks,
3171         &sys_clkout1,
3172         &dpll1_ck,
3173         &dpll1_x2_ck,
3174         &dpll1_x2m2_ck,
3175         &dpll2_ck,
3176         &dpll2_m2_ck,
3177         &dpll3_ck,
3178         &core_ck,
3179         &dpll3_x2_ck,
3180         &dpll3_m2_ck,
3181         &dpll3_m2x2_ck,
3182         &dpll3_m3_ck,
3183         &dpll3_m3x2_ck,
3184         &emu_core_alwon_ck,
3185         &dpll4_ck,
3186         &dpll4_x2_ck,
3187         &omap_96m_alwon_fck,
3188         &omap_96m_fck,
3189         &cm_96m_fck,
3190         &virt_omap_54m_fck,
3191         &omap_54m_fck,
3192         &omap_48m_fck,
3193         &omap_12m_fck,
3194         &dpll4_m2_ck,
3195         &dpll4_m2x2_ck,
3196         &dpll4_m3_ck,
3197         &dpll4_m3x2_ck,
3198         &dpll4_m4_ck,
3199         &dpll4_m4x2_ck,
3200         &dpll4_m5_ck,
3201         &dpll4_m5x2_ck,
3202         &dpll4_m6_ck,
3203         &dpll4_m6x2_ck,
3204         &emu_per_alwon_ck,
3205         &dpll5_ck,
3206         &dpll5_m2_ck,
3207         &omap_120m_fck,
3208         &clkout2_src_ck,
3209         &sys_clkout2,
3210         &corex2_fck,
3211         &dpll1_fck,
3212         &mpu_ck,
3213         &arm_fck,
3214         &emu_mpu_alwon_ck,
3215         &dpll2_fck,
3216         &iva2_ck,
3217         &l3_ick,
3218         &l4_ick,
3219         &rm_ick,
3220         &gfx_l3_ck,
3221         &gfx_l3_fck,
3222         &gfx_l3_ick,
3223         &gfx_cg1_ck,
3224         &gfx_cg2_ck,
3225         &sgx_fck,
3226         &sgx_ick,
3227         &d2d_26m_fck,
3228         &gpt10_fck,
3229         &gpt11_fck,
3230         &cpefuse_fck,
3231         &ts_fck,
3232         &usbtll_fck,
3233         &core_96m_fck,
3234         &mmchs3_fck,
3235         &mmchs2_fck,
3236         &mspro_fck,
3237         &mmchs1_fck,
3238         &i2c3_fck,
3239         &i2c2_fck,
3240         &i2c1_fck,
3241         &mcbsp5_fck,
3242         &mcbsp1_fck,
3243         &core_48m_fck,
3244         &mcspi4_fck,
3245         &mcspi3_fck,
3246         &mcspi2_fck,
3247         &mcspi1_fck,
3248         &uart2_fck,
3249         &uart1_fck,
3250         &fshostusb_fck,
3251         &core_12m_fck,
3252         &hdq_fck,
3253         &ssi_ssr_fck,
3254         &ssi_sst_fck,
3255         &core_l3_ick,
3256         &hsotgusb_ick,
3257         &sdrc_ick,
3258         &gpmc_fck,
3259         &security_l3_ick,
3260         &pka_ick,
3261         &core_l4_ick,
3262         &usbtll_ick,
3263         &mmchs3_ick,
3264         &icr_ick,
3265         &aes2_ick,
3266         &sha12_ick,
3267         &des2_ick,
3268         &mmchs2_ick,
3269         &mmchs1_ick,
3270         &mspro_ick,
3271         &hdq_ick,
3272         &mcspi4_ick,
3273         &mcspi3_ick,
3274         &mcspi2_ick,
3275         &mcspi1_ick,
3276         &i2c3_ick,
3277         &i2c2_ick,
3278         &i2c1_ick,
3279         &uart2_ick,
3280         &uart1_ick,
3281         &gpt11_ick,
3282         &gpt10_ick,
3283         &mcbsp5_ick,
3284         &mcbsp1_ick,
3285         &fac_ick,
3286         &mailboxes_ick,
3287         &omapctrl_ick,
3288         &ssi_l4_ick,
3289         &ssi_ick,
3290         &usb_l4_ick,
3291         &security_l4_ick2,
3292         &aes1_ick,
3293         &rng_ick,
3294         &sha11_ick,
3295         &des1_ick,
3296         &dss1_alwon_fck,
3297         &dss_tv_fck,
3298         &dss_96m_fck,
3299         &dss2_alwon_fck,
3300         &dss_ick,
3301         &cam_mclk,
3302         &cam_ick,
3303         &csi2_96m_fck,
3304         &usbhost_120m_fck,
3305         &usbhost_48m_fck,
3306         &usbhost_ick,
3307         &usim_fck,
3308         &gpt1_fck,
3309         &wkup_32k_fck,
3310         &gpio1_fck,
3311         &wdt2_fck,
3312         &wkup_l4_ick,
3313         &usim_ick,
3314         &wdt2_ick,
3315         &wdt1_ick,
3316         &gpio1_ick,
3317         &omap_32ksync_ick,
3318         &gpt12_ick,
3319         &gpt1_ick,
3320         &per_96m_fck,
3321         &per_48m_fck,
3322         &uart3_fck,
3323         &gpt2_fck,
3324         &gpt3_fck,
3325         &gpt4_fck,
3326         &gpt5_fck,
3327         &gpt6_fck,
3328         &gpt7_fck,
3329         &gpt8_fck,
3330         &gpt9_fck,
3331         &per_32k_alwon_fck,
3332         &gpio6_fck,
3333         &gpio5_fck,
3334         &gpio4_fck,
3335         &gpio3_fck,
3336         &gpio2_fck,
3337         &wdt3_fck,
3338         &per_l4_ick,
3339         &gpio6_ick,
3340         &gpio5_ick,
3341         &gpio4_ick,
3342         &gpio3_ick,
3343         &gpio2_ick,
3344         &wdt3_ick,
3345         &uart3_ick,
3346         &gpt9_ick,
3347         &gpt8_ick,
3348         &gpt7_ick,
3349         &gpt6_ick,
3350         &gpt5_ick,
3351         &gpt4_ick,
3352         &gpt3_ick,
3353         &gpt2_ick,
3354         &mcbsp2_ick,
3355         &mcbsp3_ick,
3356         &mcbsp4_ick,
3357         &mcbsp2_fck,
3358         &mcbsp3_fck,
3359         &mcbsp4_fck,
3360         &emu_src_ck,
3361         &pclk_fck,
3362         &pclkx2_fck,
3363         &atclk_fck,
3364         &traceclk_src_fck,
3365         &traceclk_fck,
3366         &sr1_fck,
3367         &sr2_fck,
3368         &sr_l4_ick,
3369         &secure_32k_fck,
3370         &gpt12_fck,
3371         &wdt1_fck,
3372 };
3373
3374 #endif