arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  */
   9
  10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  11 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  12
  13 #include <asm/arch/control.h>
  14
  15 #include "clock.h"
  16 #include "cm.h"
  17 #include "cm_regbits_34xx.h"
  18 #include "prm.h"
  19 #include "prm_regbits_34xx.h"
  20
  21 static void omap3_dpll_recalc(struct clk *clk);
  22 static void omap3_clkoutx2_recalc(struct clk *clk);
  23
  24 /*
  25  * DPLL1 supplies clock to the MPU.
  26  * DPLL2 supplies clock to the IVA2.
  27  * DPLL3 supplies CORE domain clocks.
  28  * DPLL4 supplies peripheral clocks.
  29  */
  30
  31 /* PRM CLOCKS */
  32
  33 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  34 static struct clk omap_32k_fck = {
  35         .name           = "omap_32k_fck",
  36         .rate           = 32768,
  37         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  38                                 ALWAYS_ENABLED,
  39         .recalc         = &propagate_rate,
  40 };
  41
  42 static struct clk secure_32k_fck = {
  43         .name           = "secure_32k_fck",
  44         .rate           = 32768,
  45         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  46                                 ALWAYS_ENABLED,
  47         .recalc         = &propagate_rate,
  48 };
  49
  50 /* Virtual source clocks for osc_sys_ck */
  51 static struct clk virt_12m_ck = {
  52         .name           = "virt_12m_ck",
  53         .rate           = 12000000,
  54         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  55                                 ALWAYS_ENABLED,
  56         .recalc         = &propagate_rate,
  57 };
  58
  59 static struct clk virt_13m_ck = {
  60         .name           = "virt_13m_ck",
  61         .rate           = 13000000,
  62         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  63                                 ALWAYS_ENABLED,
  64         .recalc         = &propagate_rate,
  65 };
  66
  67 /* 3430ES2 only */
  68 static struct clk virt_16_8m_ck = {
  69         .name           = "virt_16_8m_ck",
  70         .rate           = 16800000,
  71         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  72                                 ALWAYS_ENABLED,
  73         .recalc         = &propagate_rate,
  74 };
  75
  76 static struct clk virt_19_2m_ck = {
  77         .name           = "virt_19_2m_ck",
  78         .rate           = 19200000,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .recalc         = &propagate_rate,
  82 };
  83
  84 static struct clk virt_26m_ck = {
  85         .name           = "virt_26m_ck",
  86         .rate           = 26000000,
  87         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  88                                 ALWAYS_ENABLED,
  89         .recalc         = &propagate_rate,
  90 };
  91
  92 static struct clk virt_38_4m_ck = {
  93         .name           = "virt_38_4m_ck",
  94         .rate           = 38400000,
  95         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  96                                 ALWAYS_ENABLED,
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static const struct clksel_rate osc_sys_12m_rates[] = {
 101         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 102         { .div = 0 }
 103 };
 104
 105 static const struct clksel_rate osc_sys_13m_rates[] = {
 106         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 107         { .div = 0 }
 108 };
 109
 110 /* 3430ES2 only */
 111 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 112         { .div = 1, .val = 5, .flags = RATE_IN_343X | DEFAULT_RATE },
 113         { .div = 0 }
 114 };
 115
 116 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 117         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 118         { .div = 0 }
 119 };
 120
 121 static const struct clksel_rate osc_sys_26m_rates[] = {
 122         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 123         { .div = 0 }
 124 };
 125
 126 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 127         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 128         { .div = 0 }
 129 };
 130
 131 static const struct clksel osc_sys_clksel[] = {
 132         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 133         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 134         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 135         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 136         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 137         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 138         { .parent = NULL },
 139 };
 140
 141 /* Oscillator clock */
 142 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 143 static struct clk osc_sys_ck = {
 144         .name           = "osc_sys_ck",
 145         .init           = &omap2_init_clksel_parent,
 146         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 147         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 148         .clksel         = osc_sys_clksel,
 149         /* REVISIT: deal with autoextclkmode? */
 150         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 151                                 ALWAYS_ENABLED,
 152         .recalc         = &omap2_clksel_recalc,
 153 };
 154
 155 static const struct clksel_rate div2_rates[] = {
 156         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 157         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 158         { .div = 0 }
 159 };
 160
 161 static const struct clksel sys_clksel[] = {
 162         { .parent = &osc_sys_ck, .rates = div2_rates },
 163         { .parent = NULL }
 164 };
 165
 166 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 167 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 168 static struct clk sys_ck = {
 169         .name           = "sys_ck",
 170         .parent         = &osc_sys_ck,
 171         .init           = &omap2_init_clksel_parent,
 172         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 173         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 174         .clksel         = sys_clksel,
 175         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 176         .recalc         = &omap2_clksel_recalc,
 177 };
 178
 179 static struct clk sys_altclk = {
 180         .name           = "sys_altclk",
 181         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 182         .recalc         = &propagate_rate,
 183 };
 184
 185 /* Optional external clock input for some McBSPs */
 186 static struct clk mcbsp_clks = {
 187         .name           = "mcbsp_clks",
 188         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 189         .recalc         = &propagate_rate,
 190 };
 191
 192 /* PRM EXTERNAL CLOCK OUTPUT */
 193
 194 static struct clk sys_clkout1 = {
 195         .name           = "sys_clkout1",
 196         .parent         = &osc_sys_ck,
 197         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 198         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 199         .flags          = CLOCK_IN_OMAP343X,
 200         .recalc         = &followparent_recalc,
 201 };
 202
 203 /* DPLLS */
 204
 205 /* CM CLOCKS */
 206
 207 /* DPLL1 */
 208 /* MPU clock source */
 209 /* Type: DPLL */
 210 static const struct dpll_data dpll1_dd = {
 211         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 212         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 213         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 214         .div2_reg       = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 215         .div2_mask      = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 216         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 217         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 218         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 219         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 220         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 221 };
 222
 223 static struct clk dpll1_ck = {
 224         .name           = "dpll1_ck",
 225         .parent         = &sys_ck,
 226         .dpll_data      = &dpll1_dd,
 227         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 228         .recalc         = &omap3_dpll_recalc,
 229 };
 230
 231 /*
 232  * REVISIT: This clock is never specifically defined in the 3430 TRM,
 233  * although it is referenced - so this is a guess
 234  */
 235 static struct clk emu_mpu_alwon_ck = {
 236         .name           = "emu_mpu_alwon_ck",
 237         .parent         = &dpll1_ck,
 238         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 239                                 PARENT_CONTROLS_CLOCK,
 240         .recalc         = &followparent_recalc,
 241 };
 242
 243 /* DPLL2 */
 244 /* IVA2 clock source */
 245 /* Type: DPLL */
 246
 247 static const struct dpll_data dpll2_dd = {
 248         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 249         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 250         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 251         .div2_reg       = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
 252         .div2_mask      = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 253         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 254         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 255         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 256         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 257         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 258 };
 259
 260 static struct clk dpll2_ck = {
 261         .name           = "dpll2_ck",
 262         .parent         = &sys_ck,
 263         .dpll_data      = &dpll2_dd,
 264         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 265         .recalc         = &omap3_dpll_recalc,
 266 };
 267
 268 /* DPLL3 */
 269 /* Source clock for all interfaces and for some device fclks */
 270 /* Type: DPLL */
 271 static const struct dpll_data dpll3_dd = {
 272         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 273         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 274         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 275         .div2_reg       = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 276         .div2_mask      = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 277         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 278         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 279         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 280         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 281         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 282 };
 283
 284 static struct clk dpll3_ck = {
 285         .name           = "dpll3_ck",
 286         .parent         = &sys_ck,
 287         .dpll_data      = &dpll3_dd,
 288         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 289         .recalc         = &omap3_dpll_recalc,
 290 };
 291
 292 static const struct clksel_rate div16_dpll_rates[] = {
 293         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 294         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 295         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 296         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 297         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 298         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 299         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 300         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 301         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 302         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 303         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 304         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 305         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 306         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 307         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 308         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 309         { .div = 0 }
 310 };
 311
 312 static const struct clksel div2_dpll3m2_clksel[] = {
 313         { .parent = &dpll3_ck, .rates = div2_rates },
 314         { .parent = NULL }
 315 };
 316
 317 /*
 318  * REVISIT: Not sure what to do about clksel & these M2 divider clocks.
 319  * Shouldn't they be changed in SRAM?
 320  * This should probably remain a 'read-only' clksel clock.
 321  */
 322 static struct clk dpll3_m2_ck = {
 323         .name           = "dpll3_m2_ck",
 324         .parent         = &dpll3_ck,
 325         .init           = &omap2_init_clksel_parent,
 326         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 327         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 328         .clksel         = div2_dpll3m2_clksel,
 329         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 330                                 PARENT_CONTROLS_CLOCK,
 331         .recalc         = &omap2_clksel_recalc,
 332 };
 333
 334 static struct clk core_ck = {
 335         .name           = "core_ck",
 336         .parent         = &dpll3_m2_ck,
 337         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 338                                 PARENT_CONTROLS_CLOCK,
 339         .recalc         = &followparent_recalc,
 340 };
 341
 342 /*
 343  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 344  * DPLL isn't bypassed
 345  */
 346 static struct clk dpll3_x2_ck = {
 347         .name           = "dpll3_x2_ck",
 348         .parent         = &core_ck,
 349         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 350                                 PARENT_CONTROLS_CLOCK,
 351         .recalc         = &omap3_clkoutx2_recalc,
 352 };
 353
 354 static struct clk dpll3_m2x2_ck = {
 355         .name           = "dpll3_m2x2_ck",
 356         .parent         = &dpll3_x2_ck,
 357         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 358                                 PARENT_CONTROLS_CLOCK,
 359         .recalc         = &followparent_recalc,
 360 };
 361
 362 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 363 static struct clk dpll3_m3x2_ck = {
 364         .name           = "dpll3_m3x2_ck",
 365         .parent         = &dpll3_x2_ck,
 366         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 367         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 368         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 369         .recalc         = &followparent_recalc,
 370 };
 371
 372 static const struct clksel div16_dpll3_clksel[] = {
 373         { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates },
 374         { .parent = NULL }
 375 };
 376
 377 static struct clk emu_core_alwon_ck = {
 378         .name           = "emu_core_alwon_ck",
 379         .parent         = &dpll3_x2_ck,
 380         .init           = &omap2_init_clksel_parent,
 381         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 382         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 383         .clksel         = div16_dpll3_clksel,
 384         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 385         .recalc         = &followparent_recalc,
 386 };
 387
 388 /* DPLL4 */
 389 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 390 /* Type: DPLL */
 391 static const struct dpll_data dpll4_dd = {
 392         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 393         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 394         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 395         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 396         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 397         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 398         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 399         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 400 };
 401
 402 static struct clk dpll4_ck = {
 403         .name           = "dpll4_ck",
 404         .parent         = &sys_ck,
 405         .dpll_data      = &dpll4_dd,
 406         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 407         .recalc         = &omap3_dpll_recalc,
 408 };
 409
 410 /*
 411  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 412  * DPLL isn't bypassed
 413  */
 414 static struct clk dpll4_x2_ck = {
 415         .name           = "dpll4_x2_ck",
 416         .parent         = &dpll4_ck,
 417         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 418                                 PARENT_CONTROLS_CLOCK,
 419         .recalc         = &omap3_clkoutx2_recalc,
 420 };
 421
 422 static const struct clksel div16_dpll4_clksel[] = {
 423         { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates },
 424         { .parent = NULL }
 425 };
 426
 427 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 428 static struct clk dpll4_m2x2_ck = {
 429         .name           = "dpll4_m2x2_ck",
 430         .parent         = &dpll4_x2_ck,
 431         .init           = &omap2_init_clksel_parent,
 432         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 433         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 434         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 435         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 436         .clksel         = div16_dpll4_clksel,
 437         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 438         .recalc         = &omap2_clksel_recalc,
 439 };
 440
 441 static struct clk omap_96m_alwon_fck = {
 442         .name           = "omap_96m_alwon_fck",
 443         .parent         = &dpll4_m2x2_ck,
 444         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 445                                  PARENT_CONTROLS_CLOCK,
 446         .recalc         = &followparent_recalc,
 447 };
 448
 449 static struct clk omap_96m_fck = {
 450         .name           = "omap_96m_fck",
 451         .parent         = &omap_96m_alwon_fck,
 452         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 453                                 PARENT_CONTROLS_CLOCK,
 454         .recalc         = &followparent_recalc,
 455 };
 456
 457 static struct clk cm_96m_fck = {
 458         .name           = "cm_96m_fck",
 459         .parent         = &dpll4_m2x2_ck,
 460         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 461                                 PARENT_CONTROLS_CLOCK,
 462         .recalc         = &followparent_recalc,
 463 };
 464
 465 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 466 static struct clk dpll4_m3x2_ck = {
 467         .name           = "dpll4_m3x2_ck",
 468         .parent         = &dpll4_x2_ck,
 469         .init           = &omap2_init_clksel_parent,
 470         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 471         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 472         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 473         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 474         .clksel         = div16_dpll4_clksel,
 475         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 476         .recalc         = &omap2_clksel_recalc,
 477 };
 478
 479 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 480         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 481         { .div = 0 }
 482 };
 483
 484 static const struct clksel_rate omap_54m_alt_rates[] = {
 485         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 486         { .div = 0 }
 487 };
 488
 489 static const struct clksel omap_54m_clksel[] = {
 490         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 491         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 492         { .parent = NULL }
 493 };
 494
 495 static struct clk omap_54m_fck = {
 496         .name           = "omap_54m_fck",
 497         .init           = &omap2_init_clksel_parent,
 498         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 499         .clksel_mask    = OMAP3430_SOURCE_54M,
 500         .clksel         = omap_54m_clksel,
 501         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 502                                 PARENT_CONTROLS_CLOCK,
 503         .recalc         = &omap2_clksel_recalc,
 504 };
 505
 506 static const struct clksel_rate omap_48m_96md2_rates[] = {
 507         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 508         { .div = 0 }
 509 };
 510
 511 static const struct clksel_rate omap_48m_alt_rates[] = {
 512         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 513         { .div = 0 }
 514 };
 515
 516 static const struct clksel omap_48m_clksel[] = {
 517         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 518         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 519         { .parent = NULL }
 520 };
 521
 522 static struct clk omap_48m_fck = {
 523         .name           = "omap_48m_fck",
 524         .init           = &omap2_init_clksel_parent,
 525         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 526         .clksel_mask    = OMAP3430_SOURCE_48M,
 527         .clksel         = omap_48m_clksel,
 528         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 529                                 PARENT_CONTROLS_CLOCK,
 530         .recalc         = &omap2_clksel_recalc,
 531 };
 532
 533 static struct clk omap_12m_fck = {
 534         .name           = "omap_12m_fck",
 535         .parent         = &omap_48m_fck,
 536         .fixed_div      = 4,
 537         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 538                                 PARENT_CONTROLS_CLOCK,
 539         .recalc         = &omap2_fixed_divisor_recalc,
 540 };
 541
 542 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 543 static struct clk dpll4_m4x2_ck = {
 544         .name           = "dpll4_m4x2_ck",
 545         .parent         = &dpll4_x2_ck,
 546         .init           = &omap2_init_clksel_parent,
 547         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 548         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 549         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 550         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 551         .clksel         = div16_dpll4_clksel,
 552         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 553         .recalc         = &omap2_clksel_recalc,
 554 };
 555
 556 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 557 static struct clk dpll4_m5x2_ck = {
 558         .name           = "dpll4_m5x2_ck",
 559         .parent         = &dpll4_x2_ck,
 560         .init           = &omap2_init_clksel_parent,
 561         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 562         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 563         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 564         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 565         .clksel         = div16_dpll4_clksel,
 566         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 567         .recalc         = &omap2_clksel_recalc,
 568 };
 569
 570 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 571 static struct clk dpll4_m6x2_ck = {
 572         .name           = "dpll4_m6x2_ck",
 573         .parent         = &dpll4_x2_ck,
 574         .init           = &omap2_init_clksel_parent,
 575         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 576         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 577         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 578         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 579         .clksel         = div16_dpll4_clksel,
 580         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 581         .recalc         = &omap2_clksel_recalc,
 582 };
 583
 584 static struct clk emu_per_alwon_ck = {
 585         .name           = "emu_per_alwon_ck",
 586         .parent         = &dpll4_m6x2_ck,
 587         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 588                                 PARENT_CONTROLS_CLOCK,
 589         .recalc         = &followparent_recalc,
 590 };
 591
 592
 593 /* CM EXTERNAL CLOCK OUTPUTS */
 594
 595 static const struct clksel_rate clkout2_src_core_rates[] = {
 596         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 597         { .div = 0 }
 598 };
 599
 600 static const struct clksel_rate clkout2_src_sys_rates[] = {
 601         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 602         { .div = 0 }
 603 };
 604
 605 static const struct clksel_rate clkout2_src_96m_rates[] = {
 606         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 607         { .div = 0 }
 608 };
 609
 610 static const struct clksel_rate clkout2_src_54m_rates[] = {
 611         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 612         { .div = 0 }
 613 };
 614
 615 static const struct clksel clkout2_src_clksel[] = {
 616         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 617         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 618         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 619         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 620         { .parent = NULL }
 621 };
 622
 623 static struct clk clkout2_src_ck = {
 624         .name           = "clkout2_src_ck",
 625         .init           = &omap2_init_clksel_parent,
 626         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 627         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 628         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 629         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 630         .clksel         = clkout2_src_clksel,
 631         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 632         .recalc         = &omap2_clksel_recalc,
 633 };
 634
 635 static const struct clksel_rate sys_clkout2_rates[] = {
 636         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 637         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 638         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 639         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 640         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 641         { .div = 0 },
 642 };
 643
 644 static const struct clksel sys_clkout2_clksel[] = {
 645         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 646         { .parent = NULL },
 647 };
 648
 649 static struct clk sys_clkout2 = {
 650         .name           = "sys_clkout2",
 651         .init           = &omap2_init_clksel_parent,
 652         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 653         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 654         .clksel         = sys_clkout2_clksel,
 655         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 656         .recalc         = &omap2_clksel_recalc,
 657 };
 658
 659 /* CM OUTPUT CLOCKS */
 660
 661 static struct clk corex2_fck = {
 662         .name           = "corex2_fck",
 663         .parent         = &dpll3_m2x2_ck,
 664         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 665                                 PARENT_CONTROLS_CLOCK,
 666         .recalc         = &followparent_recalc,
 667 };
 668
 669 /* DPLL power domain clock controls */
 670
 671 static const struct clksel div2_core_clksel[] = {
 672         { .parent = &core_ck, .rates = div2_rates },
 673         { .parent = NULL }
 674 };
 675
 676 /* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK,
 677    but presuming that is an error, or at least an overgeneralization */
 678 /* REVISIT: Are these in DPLL power domain or CM power domain?  docs
 679    may be inconsistent here? */
 680 static struct clk dpll1_fck = {
 681         .name           = "dpll1_fck",
 682         .parent         = &core_ck,
 683         .init           = &omap2_init_clksel_parent,
 684         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 685         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 686         .clksel         = div2_core_clksel,
 687         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 688                                 PARENT_CONTROLS_CLOCK,
 689         .recalc         = &omap2_clksel_recalc,
 690 };
 691
 692 static struct clk dpll2_fck = {
 693         .name           = "dpll2_fck",
 694         .parent         = &core_ck,
 695         .init           = &omap2_init_clksel_parent,
 696         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 697         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
 698         .clksel         = div2_core_clksel,
 699         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 700                                 PARENT_CONTROLS_CLOCK,
 701         .recalc         = &omap2_clksel_recalc,
 702 };
 703
 704 /* Common interface clocks */
 705
 706 static struct clk l3_ick = {
 707         .name           = "l3_ick",
 708         .parent         = &core_ck,
 709         .init           = &omap2_init_clksel_parent,
 710         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 711         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
 712         .clksel         = div2_core_clksel,
 713         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 714                                 PARENT_CONTROLS_CLOCK,
 715         .recalc         = &omap2_clksel_recalc,
 716 };
 717
 718 static const struct clksel div2_l3_clksel[] = {
 719         { .parent = &l3_ick, .rates = div2_rates },
 720         { .parent = NULL }
 721 };
 722
 723 static struct clk l4_ick = {
 724         .name           = "l4_ick",
 725         .parent         = &l3_ick,
 726         .init           = &omap2_init_clksel_parent,
 727         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 728         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
 729         .clksel         = div2_l3_clksel,
 730         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 731                                 PARENT_CONTROLS_CLOCK,
 732         .recalc         = &omap2_clksel_recalc,
 733
 734 };
 735
 736 static const struct clksel div2_l4_clksel[] = {
 737         { .parent = &l4_ick, .rates = div2_rates },
 738         { .parent = NULL }
 739 };
 740
 741 static struct clk rm_ick = {
 742         .name           = "rm_ick",
 743         .parent         = &l4_ick,
 744         .init           = &omap2_init_clksel_parent,
 745         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 746         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
 747         .clksel         = div2_l4_clksel,
 748         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 749         .recalc         = &omap2_clksel_recalc,
 750 };
 751
 752 /* GFX power domain */
 753
 754 /* REVISIT: These clocks have disappeared in the 3430 ES2 TRM ?? */
 755
 756 static const struct clksel gfx_l3_clksel[] = {
 757         { .parent = &l3_ick, .rates = gfx_l3_rates },
 758         { .parent = NULL }
 759 };
 760
 761 static struct clk gfx_l3_fck = {
 762         .name           = "gfx_l3_fck",
 763         .parent         = &l3_ick,
 764         .init           = &omap2_init_clksel_parent,
 765         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 766         .enable_bit     = OMAP_EN_GFX_SHIFT,
 767         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 768         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 769         .clksel         = gfx_l3_clksel,
 770         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 771         .recalc         = &omap2_clksel_recalc,
 772 };
 773
 774 static struct clk gfx_l3_ick = {
 775         .name           = "gfx_l3_ick",
 776         .parent         = &l3_ick,
 777         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 778         .enable_bit     = OMAP_EN_GFX_SHIFT,
 779         .flags          = CLOCK_IN_OMAP343X,
 780         .recalc         = &followparent_recalc,
 781 };
 782
 783 static struct clk gfx_cg1_ck = {
 784         .name           = "gfx_cg1_ck",
 785         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
 786         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 787         .enable_bit     = OMAP3430_EN_2D_SHIFT,
 788         .flags          = CLOCK_IN_OMAP343X,
 789         .recalc         = &followparent_recalc,
 790 };
 791
 792 static struct clk gfx_cg2_ck = {
 793         .name           = "gfx_cg2_ck",
 794         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
 795         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 796         .enable_bit     = OMAP3430_EN_3D_SHIFT,
 797         .flags          = CLOCK_IN_OMAP343X,
 798         .recalc         = &followparent_recalc,
 799 };
 800
 801 /* CORE power domain */
 802
 803 static struct clk d2d_26m_fck = {
 804         .name           = "d2d_26m_fck",
 805         .parent         = &sys_ck,
 806         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 807         .enable_bit     = OMAP3430_EN_D2D_SHIFT,
 808         .flags          = CLOCK_IN_OMAP343X,
 809         .recalc         = &followparent_recalc,
 810 };
 811
 812 static const struct clksel omap343x_gpt_clksel[] = {
 813         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
 814         { .parent = &sys_ck,       .rates = gpt_sys_rates },
 815         { .parent = NULL}
 816 };
 817
 818 static struct clk gpt10_fck = {
 819         .name           = "gpt10_fck",
 820         .parent         = &sys_ck,
 821         .init           = &omap2_init_clksel_parent,
 822         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 823         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
 824         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 825         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
 826         .clksel         = omap343x_gpt_clksel,
 827         .flags          = CLOCK_IN_OMAP343X,
 828         .recalc         = &omap2_clksel_recalc,
 829 };
 830
 831 static struct clk gpt11_fck = {
 832         .name           = "gpt11_fck",
 833         .parent         = &sys_ck,
 834         .init           = &omap2_init_clksel_parent,
 835         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 836         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
 837         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 838         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
 839         .clksel         = omap343x_gpt_clksel,
 840         .flags          = CLOCK_IN_OMAP343X,
 841         .recalc         = &omap2_clksel_recalc,
 842 };
 843
 844 /* CORE 96M FCLK-derived clocks */
 845
 846 static struct clk core_96m_fck = {
 847         .name           = "core_96m_fck",
 848         .parent         = &omap_96m_fck,
 849         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 850                                 PARENT_CONTROLS_CLOCK,
 851         .recalc         = &followparent_recalc,
 852 };
 853
 854 static struct clk mmchs2_fck = {
 855         .name           = "mmchs_fck",
 856         .id             = 2,
 857         .parent         = &core_96m_fck,
 858         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 859         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
 860         .flags          = CLOCK_IN_OMAP343X,
 861         .recalc         = &followparent_recalc,
 862 };
 863
 864 static struct clk mspro_fck = {
 865         .name           = "mspro_fck",
 866         .parent         = &core_96m_fck,
 867         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 868         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
 869         .flags          = CLOCK_IN_OMAP343X,
 870         .recalc         = &followparent_recalc,
 871 };
 872
 873 static struct clk mmchs1_fck = {
 874         .name           = "mmchs_fck",
 875         .id             = 1,
 876         .parent         = &core_96m_fck,
 877         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 878         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
 879         .flags          = CLOCK_IN_OMAP343X,
 880         .recalc         = &followparent_recalc,
 881 };
 882
 883 static struct clk i2c3_fck = {
 884         .name           = "i2c_fck",
 885         .id             = 3,
 886         .parent         = &core_96m_fck,
 887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 888         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
 889         .flags          = CLOCK_IN_OMAP343X,
 890         .recalc         = &followparent_recalc,
 891 };
 892
 893 static struct clk i2c2_fck = {
 894         .name           = "i2c_fck",
 895         .id             = 2,
 896         .parent         = &core_96m_fck,
 897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 898         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
 899         .flags          = CLOCK_IN_OMAP343X,
 900         .recalc         = &followparent_recalc,
 901 };
 902
 903 static struct clk i2c1_fck = {
 904         .name           = "i2c_fck",
 905         .id             = 1,
 906         .parent         = &core_96m_fck,
 907         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 908         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
 909         .flags          = CLOCK_IN_OMAP343X,
 910         .recalc         = &followparent_recalc,
 911 };
 912
 913 /*
 914  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
 915  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
 916  */
 917 static const struct clksel_rate common_mcbsp_96m_rates[] = {
 918         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 919         { .div = 0 }
 920 };
 921
 922 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
 923         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 924         { .div = 0 }
 925 };
 926
 927 static const struct clksel mcbsp_15_clksel[] = {
 928         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
 929         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
 930         { .parent = NULL }
 931 };
 932
 933 static struct clk mcbsp5_fck = {
 934         .name           = "mcbsp5_fck",
 935         .init           = &omap2_init_clksel_parent,
 936         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 937         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
 938         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 939         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
 940         .clksel         = mcbsp_15_clksel,
 941         .flags          = CLOCK_IN_OMAP343X,
 942         .recalc         = &omap2_clksel_recalc,
 943 };
 944
 945 static struct clk mcbsp1_fck = {
 946         .name           = "mcbsp1_fck",
 947         .init           = &omap2_init_clksel_parent,
 948         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 949         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
 950         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 951         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
 952         .clksel         = mcbsp_15_clksel,
 953         .flags          = CLOCK_IN_OMAP343X,
 954         .recalc         = &omap2_clksel_recalc,
 955 };
 956
 957 /* CORE_48M_FCK-derived clocks */
 958
 959 static struct clk core_48m_fck = {
 960         .name           = "core_48m_fck",
 961         .parent         = &omap_48m_fck,
 962         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 963                                 PARENT_CONTROLS_CLOCK,
 964         .recalc         = &followparent_recalc,
 965 };
 966
 967 static struct clk mcspi4_fck = {
 968         .name           = "mcspi4_fck",
 969         .parent         = &core_48m_fck,
 970         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 971         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
 972         .flags          = CLOCK_IN_OMAP343X,
 973         .recalc         = &followparent_recalc,
 974 };
 975
 976 static struct clk mcspi3_fck = {
 977         .name           = "mcspi3_fck",
 978         .parent         = &core_48m_fck,
 979         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 980         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
 981         .flags          = CLOCK_IN_OMAP343X,
 982         .recalc         = &followparent_recalc,
 983 };
 984
 985 static struct clk mcspi2_fck = {
 986         .name           = "mcspi2_fck",
 987         .parent         = &core_48m_fck,
 988         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 989         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
 990         .flags          = CLOCK_IN_OMAP343X,
 991         .recalc         = &followparent_recalc,
 992 };
 993
 994 static struct clk mcspi1_fck = {
 995         .name           = "mcspi1_fck",
 996         .parent         = &core_48m_fck,
 997         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 998         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
 999         .flags          = CLOCK_IN_OMAP343X,
1000         .recalc         = &followparent_recalc,
1001 };
1002
1003 static struct clk uart2_fck = {
1004         .name           = "uart2_fck",
1005         .parent         = &core_48m_fck,
1006         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1007         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1008         .flags          = CLOCK_IN_OMAP343X,
1009         .recalc         = &followparent_recalc,
1010 };
1011
1012 static struct clk uart1_fck = {
1013         .name           = "uart1_fck",
1014         .parent         = &core_48m_fck,
1015         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1016         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1017         .flags          = CLOCK_IN_OMAP343X,
1018         .recalc         = &followparent_recalc,
1019 };
1020
1021 static struct clk fshostusb_fck = {
1022         .name           = "fshostusb_fck",
1023         .parent         = &core_48m_fck,
1024         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1025         .enable_bit     = OMAP3430_EN_FSHOSTUSB_SHIFT,
1026         .flags          = CLOCK_IN_OMAP343X,
1027         .recalc         = &followparent_recalc,
1028 };
1029
1030 /* CORE_12M_FCK based clocks */
1031
1032 static struct clk core_12m_fck = {
1033         .name           = "core_12m_fck",
1034         .parent         = &omap_12m_fck,
1035         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1036                                 PARENT_CONTROLS_CLOCK,
1037         .recalc         = &followparent_recalc,
1038 };
1039
1040 static struct clk hdq_fck = {
1041         .name           = "hdq_fck",
1042         .parent         = &core_12m_fck,
1043         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1044         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1045         .flags          = CLOCK_IN_OMAP343X,
1046         .recalc         = &followparent_recalc,
1047 };
1048
1049 /* DPLL3-derived clock */
1050
1051 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1052         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1053         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1054         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1055         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1056         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1057         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1058         { .div = 0 }
1059 };
1060
1061 static const struct clksel ssi_ssr_clksel[] = {
1062         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1063         { .parent = NULL }
1064 };
1065
1066 static struct clk ssi_ssr_fck = {
1067         .name           = "ssi_ssr_fck",
1068         .init           = &omap2_init_clksel_parent,
1069         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1070         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1071         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1072         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1073         .clksel         = ssi_ssr_clksel,
1074         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1075         .recalc         = &omap2_clksel_recalc,
1076 };
1077
1078 static struct clk ssi_sst_fck = {
1079         .name           = "ssi_sst_fck",
1080         .parent         = &ssi_ssr_fck,
1081         .fixed_div      = 2,
1082         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1083         .recalc         = &omap2_fixed_divisor_recalc,
1084 };
1085
1086
1087
1088 /* CORE_L3_ICK based clocks */
1089
1090 static struct clk core_l3_ick = {
1091         .name           = "core_l3_ick",
1092         .parent         = &l3_ick,
1093         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1094                                 PARENT_CONTROLS_CLOCK,
1095         .recalc         = &followparent_recalc,
1096 };
1097
1098 static struct clk hsotgusb_ick = {
1099         .name           = "hsotgusb_ick",
1100         .parent         = &core_l3_ick,
1101         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1102         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1103         .flags          = CLOCK_IN_OMAP343X,
1104         .recalc         = &followparent_recalc,
1105 };
1106
1107 static struct clk sdrc_ick = {
1108         .name           = "sdrc_ick",
1109         .parent         = &core_l3_ick,
1110         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1111         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1112         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1113         .recalc         = &followparent_recalc,
1114 };
1115
1116 static struct clk gpmc_fck = {
1117         .name           = "gpmc_fck",
1118         .parent         = &core_l3_ick,
1119         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1120         .recalc         = &followparent_recalc,
1121 };
1122
1123 /* SECURITY_L3_ICK based clocks */
1124
1125 static struct clk security_l3_ick = {
1126         .name           = "security_l3_ick",
1127         .parent         = &l3_ick,
1128         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1129                                 PARENT_CONTROLS_CLOCK,
1130         .recalc         = &followparent_recalc,
1131 };
1132
1133 static struct clk pka_ick = {
1134         .name           = "pka_ick",
1135         .parent         = &security_l3_ick,
1136         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1137         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1138         .flags          = CLOCK_IN_OMAP343X,
1139         .recalc         = &followparent_recalc,
1140 };
1141
1142 /* CORE_L4_ICK based clocks */
1143
1144 static struct clk core_l4_ick = {
1145         .name           = "core_l4_ick",
1146         .parent         = &l4_ick,
1147         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1148                                 PARENT_CONTROLS_CLOCK,
1149         .recalc         = &followparent_recalc,
1150 };
1151
1152 /* Intersystem Communication Registers - chassis mode only */
1153 static struct clk icr_ick = {
1154         .name           = "icr_ick",
1155         .parent         = &core_l4_ick,
1156         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1157         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1158         .flags          = CLOCK_IN_OMAP343X,
1159         .recalc         = &followparent_recalc,
1160 };
1161
1162 static struct clk aes2_ick = {
1163         .name           = "aes2_ick",
1164         .parent         = &core_l4_ick,
1165         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1166         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1167         .flags          = CLOCK_IN_OMAP343X,
1168         .recalc         = &followparent_recalc,
1169 };
1170
1171 static struct clk sha12_ick = {
1172         .name           = "sha12_ick",
1173         .parent         = &core_l4_ick,
1174         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1175         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1176         .flags          = CLOCK_IN_OMAP343X,
1177         .recalc         = &followparent_recalc,
1178 };
1179
1180 static struct clk des2_ick = {
1181         .name           = "des2_ick",
1182         .parent         = &core_l4_ick,
1183         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1184         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1185         .flags          = CLOCK_IN_OMAP343X,
1186         .recalc         = &followparent_recalc,
1187 };
1188
1189 static struct clk mmchs2_ick = {
1190         .name           = "mmchs_ick",
1191         .id             = 2,
1192         .parent         = &core_l4_ick,
1193         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1194         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1195         .flags          = CLOCK_IN_OMAP343X,
1196         .recalc         = &followparent_recalc,
1197 };
1198
1199 static struct clk mmchs1_ick = {
1200         .name           = "mmchs_ick",
1201         .id             = 1,
1202         .parent         = &core_l4_ick,
1203         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1204         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1205         .flags          = CLOCK_IN_OMAP343X,
1206         .recalc         = &followparent_recalc,
1207 };
1208
1209 static struct clk mspro_ick = {
1210         .name           = "mspro_ick",
1211         .parent         = &core_l4_ick,
1212         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1213         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1214         .flags          = CLOCK_IN_OMAP343X,
1215         .recalc         = &followparent_recalc,
1216 };
1217
1218 static struct clk hdq_ick = {
1219         .name           = "hdq_ick",
1220         .parent         = &core_l4_ick,
1221         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1222         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1223         .flags          = CLOCK_IN_OMAP343X,
1224         .recalc         = &followparent_recalc,
1225 };
1226
1227 static struct clk mcspi4_ick = {
1228         .name           = "mcspi4_ick",
1229         .parent         = &core_l4_ick,
1230         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1231         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1232         .flags          = CLOCK_IN_OMAP343X,
1233         .recalc         = &followparent_recalc,
1234 };
1235
1236 static struct clk mcspi3_ick = {
1237         .name           = "mcspi3_ick",
1238         .parent         = &core_l4_ick,
1239         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1240         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1241         .flags          = CLOCK_IN_OMAP343X,
1242         .recalc         = &followparent_recalc,
1243 };
1244
1245 static struct clk mcspi2_ick = {
1246         .name           = "mcspi2_ick",
1247         .parent         = &core_l4_ick,
1248         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1249         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1250         .flags          = CLOCK_IN_OMAP343X,
1251         .recalc         = &followparent_recalc,
1252 };
1253
1254 static struct clk mcspi1_ick = {
1255         .name           = "mcspi1_ick",
1256         .parent         = &core_l4_ick,
1257         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1258         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1259         .flags          = CLOCK_IN_OMAP343X,
1260         .recalc         = &followparent_recalc,
1261 };
1262
1263 static struct clk i2c3_ick = {
1264         .name           = "i2c_ick",
1265         .id             = 3,
1266         .parent         = &core_l4_ick,
1267         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1268         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1269         .flags          = CLOCK_IN_OMAP343X,
1270         .recalc         = &followparent_recalc,
1271 };
1272
1273 static struct clk i2c2_ick = {
1274         .name           = "i2c_ick",
1275         .id             = 2,
1276         .parent         = &core_l4_ick,
1277         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1278         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1279         .flags          = CLOCK_IN_OMAP343X,
1280         .recalc         = &followparent_recalc,
1281 };
1282
1283 static struct clk i2c1_ick = {
1284         .name           = "i2c_ick",
1285         .id             = 1,
1286         .parent         = &core_l4_ick,
1287         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1288         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1289         .flags          = CLOCK_IN_OMAP343X,
1290         .recalc         = &followparent_recalc,
1291 };
1292
1293 static struct clk uart2_ick = {
1294         .name           = "uart2_ick",
1295         .parent         = &core_l4_ick,
1296         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1297         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1298         .flags          = CLOCK_IN_OMAP343X,
1299         .recalc         = &followparent_recalc,
1300 };
1301
1302 static struct clk uart1_ick = {
1303         .name           = "uart1_ick",
1304         .parent         = &core_l4_ick,
1305         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1306         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1307         .flags          = CLOCK_IN_OMAP343X,
1308         .recalc         = &followparent_recalc,
1309 };
1310
1311 static struct clk gpt11_ick = {
1312         .name           = "gpt11_ick",
1313         .parent         = &core_l4_ick,
1314         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1315         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1316         .flags          = CLOCK_IN_OMAP343X,
1317         .recalc         = &followparent_recalc,
1318 };
1319
1320 static struct clk gpt10_ick = {
1321         .name           = "gpt10_ick",
1322         .parent         = &core_l4_ick,
1323         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1324         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1325         .flags          = CLOCK_IN_OMAP343X,
1326         .recalc         = &followparent_recalc,
1327 };
1328
1329 static struct clk mcbsp5_ick = {
1330         .name           = "mcbsp5_ick",
1331         .parent         = &core_l4_ick,
1332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1333         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1334         .flags          = CLOCK_IN_OMAP343X,
1335         .recalc         = &followparent_recalc,
1336 };
1337
1338 static struct clk mcbsp1_ick = {
1339         .name           = "mcbsp1_ick",
1340         .parent         = &core_l4_ick,
1341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1342         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1343         .flags          = CLOCK_IN_OMAP343X,
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 static struct clk fac_ick = {
1348         .name           = "fac_ick",
1349         .parent         = &core_l4_ick,
1350         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1351         .enable_bit     = OMAP3430_EN_FAC_SHIFT,
1352         .flags          = CLOCK_IN_OMAP343X,
1353         .recalc         = &followparent_recalc,
1354 };
1355
1356 static struct clk mailboxes_ick = {
1357         .name           = "mailboxes_ick",
1358         .parent         = &core_l4_ick,
1359         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1360         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1361         .flags          = CLOCK_IN_OMAP343X,
1362         .recalc         = &followparent_recalc,
1363 };
1364
1365 static struct clk omapctrl_ick = {
1366         .name           = "omapctrl_ick",
1367         .parent         = &core_l4_ick,
1368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1369         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1370         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1371         .recalc         = &followparent_recalc,
1372 };
1373
1374 /* SSI_L4_ICK based clocks */
1375
1376 static struct clk ssi_l4_ick = {
1377         .name           = "ssi_l4_ick",
1378         .parent         = &l4_ick,
1379         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1380         .recalc         = &followparent_recalc,
1381 };
1382
1383 static struct clk ssi_ick = {
1384         .name           = "ssi_ick",
1385         .parent         = &ssi_l4_ick,
1386         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1387         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1388         .flags          = CLOCK_IN_OMAP343X,
1389         .recalc         = &followparent_recalc,
1390 };
1391
1392 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1393  * but l4_ick makes more sense to me */
1394
1395 static const struct clksel usb_l4_clksel[] = {
1396         { .parent = &l4_ick, .rates = div2_rates },
1397         { .parent = NULL },
1398 };
1399
1400 static struct clk usb_l4_ick = {
1401         .name           = "usb_l4_ick",
1402         .parent         = &l4_ick,
1403         .init           = &omap2_init_clksel_parent,
1404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1405         .enable_bit     = OMAP3430_EN_FSHOSTUSB_SHIFT,
1406         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1407         .clksel_mask    = OMAP3430_CLKSEL_FSHOSTUSB_MASK,
1408         .clksel         = usb_l4_clksel,
1409         .flags          = CLOCK_IN_OMAP343X,
1410         .recalc         = &omap2_clksel_recalc,
1411 };
1412
1413 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1414
1415 /* SECURITY_L4_ICK2 based clocks */
1416
1417 static struct clk security_l4_ick2 = {
1418         .name           = "security_l4_ick2",
1419         .parent         = &l4_ick,
1420         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1421                                 PARENT_CONTROLS_CLOCK,
1422         .recalc         = &followparent_recalc,
1423 };
1424
1425 static struct clk aes1_ick = {
1426         .name           = "aes1_ick",
1427         .parent         = &security_l4_ick2,
1428         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1429         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1430         .flags          = CLOCK_IN_OMAP343X,
1431         .recalc         = &followparent_recalc,
1432 };
1433
1434 static struct clk rng_ick = {
1435         .name           = "rng_ick",
1436         .parent         = &security_l4_ick2,
1437         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1438         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1439         .flags          = CLOCK_IN_OMAP343X,
1440         .recalc         = &followparent_recalc,
1441 };
1442
1443 static struct clk sha11_ick = {
1444         .name           = "sha11_ick",
1445         .parent         = &security_l4_ick2,
1446         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1447         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1448         .flags          = CLOCK_IN_OMAP343X,
1449         .recalc         = &followparent_recalc,
1450 };
1451
1452 static struct clk des1_ick = {
1453         .name           = "des1_ick",
1454         .parent         = &security_l4_ick2,
1455         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1456         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1457         .flags          = CLOCK_IN_OMAP343X,
1458         .recalc         = &followparent_recalc,
1459 };
1460
1461 /* DSS */
1462
1463 static struct clk dss1_alwon_fck = {
1464         .name           = "dss1_alwon_fck",
1465         .parent         = &dpll4_m4x2_ck,
1466         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1467         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1468         .flags          = CLOCK_IN_OMAP343X,
1469         .recalc         = &followparent_recalc,
1470 };
1471
1472 static struct clk dss_tv_fck = {
1473         .name           = "dss_tv_fck",
1474         .parent         = &omap_54m_fck,
1475         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1476         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1477         .flags          = CLOCK_IN_OMAP343X,
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 static struct clk dss_96m_fck = {
1482         .name           = "dss_96m_fck",
1483         .parent         = &omap_96m_fck,
1484         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1485         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1486         .flags          = CLOCK_IN_OMAP343X,
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 static struct clk dss2_alwon_fck = {
1491         .name           = "dss2_alwon_fck",
1492         .parent         = &sys_ck,
1493         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1494         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
1495         .flags          = CLOCK_IN_OMAP343X,
1496         .recalc         = &followparent_recalc,
1497 };
1498
1499 static struct clk dss_ick = {
1500         /* Handles both L3 and L4 clocks */
1501         .name           = "dss_ick",
1502         .parent         = &l4_ick,
1503         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1504         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1505         .flags          = CLOCK_IN_OMAP343X,
1506         .recalc         = &followparent_recalc,
1507 };
1508
1509 /* CAM */
1510
1511 static struct clk cam_mclk = {
1512         .name           = "cam_mclk",
1513         .parent         = &dpll4_m5x2_ck,
1514         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1515         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1516         .flags          = CLOCK_IN_OMAP343X,
1517         .recalc         = &followparent_recalc,
1518 };
1519
1520 static struct clk cam_l3_ick = {
1521         .name           = "cam_l3_ick",
1522         .parent         = &l3_ick,
1523         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1524         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1525         .flags          = CLOCK_IN_OMAP343X,
1526         .recalc         = &followparent_recalc,
1527 };
1528
1529 static struct clk cam_l4_ick = {
1530         .name           = "cam_l4_ick",
1531         .parent         = &l4_ick,
1532         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1533         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1534         .flags          = CLOCK_IN_OMAP343X,
1535         .recalc         = &followparent_recalc,
1536 };
1537
1538 /* WKUP */
1539
1540 static struct clk gpt1_fck = {
1541         .name           = "gpt1_fck",
1542         .init           = &omap2_init_clksel_parent,
1543         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1544         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1545         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1546         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
1547         .clksel         = omap343x_gpt_clksel,
1548         .flags          = CLOCK_IN_OMAP343X,
1549         .recalc         = &omap2_clksel_recalc,
1550 };
1551
1552 static struct clk wkup_32k_fck = {
1553         .name           = "wkup_32k_fck",
1554         .parent         = &omap_32k_fck,
1555         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1556         .recalc         = &followparent_recalc,
1557 };
1558
1559 static struct clk gpio1_fck = {
1560         .name           = "gpio1_fck",
1561         .parent         = &wkup_32k_fck,
1562         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1563         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1564         .flags          = CLOCK_IN_OMAP343X,
1565         .recalc         = &followparent_recalc,
1566 };
1567
1568 static struct clk wdt2_fck = {
1569         .name           = "wdt2_fck",
1570         .parent         = &wkup_32k_fck,
1571         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1572         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
1573         .flags          = CLOCK_IN_OMAP343X,
1574         .recalc         = &followparent_recalc,
1575 };
1576
1577 static struct clk wkup_l4_ick = {
1578         .name           = "wkup_l4_ick",
1579         .parent         = &sys_ck,
1580         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1581         .recalc         = &followparent_recalc,
1582 };
1583
1584 static struct clk wdt2_ick = {
1585         .name           = "wdt2_ick",
1586         .parent         = &wkup_l4_ick,
1587         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1588         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
1589         .flags          = CLOCK_IN_OMAP343X,
1590         .recalc         = &followparent_recalc,
1591 };
1592
1593 static struct clk wdt1_ick = {
1594         .name           = "wdt1_ick",
1595         .parent         = &wkup_l4_ick,
1596         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1597         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
1598         .flags          = CLOCK_IN_OMAP343X,
1599         .recalc         = &followparent_recalc,
1600 };
1601
1602 static struct clk gpio1_ick = {
1603         .name           = "gpio1_ick",
1604         .parent         = &wkup_l4_ick,
1605         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1606         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1607         .flags          = CLOCK_IN_OMAP343X,
1608         .recalc         = &followparent_recalc,
1609 };
1610
1611 static struct clk omap_32ksync_ick = {
1612         .name           = "omap_32ksync_ick",
1613         .parent         = &wkup_l4_ick,
1614         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1615         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
1616         .flags          = CLOCK_IN_OMAP343X,
1617         .recalc         = &followparent_recalc,
1618 };
1619
1620 static struct clk gpt12_ick = {
1621         .name           = "gpt12_ick",
1622         .parent         = &wkup_l4_ick,
1623         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1624         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
1625         .flags          = CLOCK_IN_OMAP343X,
1626         .recalc         = &followparent_recalc,
1627 };
1628
1629 static struct clk gpt1_ick = {
1630         .name           = "gpt1_ick",
1631         .parent         = &wkup_l4_ick,
1632         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1633         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1634         .flags          = CLOCK_IN_OMAP343X,
1635         .recalc         = &followparent_recalc,
1636 };
1637
1638
1639
1640 /* PER clock domain */
1641
1642 static struct clk per_96m_fck = {
1643         .name           = "per_96m_fck",
1644         .parent         = &omap_96m_alwon_fck,
1645         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1646                                 PARENT_CONTROLS_CLOCK,
1647         .recalc         = &followparent_recalc,
1648 };
1649
1650 static struct clk per_48m_fck = {
1651         .name           = "per_48m_fck",
1652         .parent         = &omap_48m_fck,
1653         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1654                                 PARENT_CONTROLS_CLOCK,
1655         .recalc         = &followparent_recalc,
1656 };
1657
1658 static struct clk uart3_fck = {
1659         .name           = "uart3_fck",
1660         .parent         = &per_48m_fck,
1661         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1662         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
1663         .flags          = CLOCK_IN_OMAP343X,
1664         .recalc         = &followparent_recalc,
1665 };
1666
1667 static struct clk gpt2_fck = {
1668         .name           = "gpt2_fck",
1669         .init           = &omap2_init_clksel_parent,
1670         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1671         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1672         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1673         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
1674         .clksel         = omap343x_gpt_clksel,
1675         .flags          = CLOCK_IN_OMAP343X,
1676         .recalc         = &omap2_clksel_recalc,
1677 };
1678
1679 static struct clk gpt3_fck = {
1680         .name           = "gpt3_fck",
1681         .init           = &omap2_init_clksel_parent,
1682         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1683         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1684         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1685         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
1686         .clksel         = omap343x_gpt_clksel,
1687         .flags          = CLOCK_IN_OMAP343X,
1688         .recalc         = &omap2_clksel_recalc,
1689 };
1690
1691 static struct clk gpt4_fck = {
1692         .name           = "gpt4_fck",
1693         .init           = &omap2_init_clksel_parent,
1694         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1695         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1696         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1697         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
1698         .clksel         = omap343x_gpt_clksel,
1699         .flags          = CLOCK_IN_OMAP343X,
1700         .recalc         = &omap2_clksel_recalc,
1701 };
1702
1703 static struct clk gpt5_fck = {
1704         .name           = "gpt5_fck",
1705         .init           = &omap2_init_clksel_parent,
1706         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1707         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1708         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1709         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
1710         .clksel         = omap343x_gpt_clksel,
1711         .flags          = CLOCK_IN_OMAP343X,
1712         .recalc         = &omap2_clksel_recalc,
1713 };
1714
1715 static struct clk gpt6_fck = {
1716         .name           = "gpt6_fck",
1717         .init           = &omap2_init_clksel_parent,
1718         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1719         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1720         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1721         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
1722         .clksel         = omap343x_gpt_clksel,
1723         .flags          = CLOCK_IN_OMAP343X,
1724         .recalc         = &omap2_clksel_recalc,
1725 };
1726
1727 static struct clk gpt7_fck = {
1728         .name           = "gpt7_fck",
1729         .init           = &omap2_init_clksel_parent,
1730         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1731         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1732         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1733         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
1734         .clksel         = omap343x_gpt_clksel,
1735         .flags          = CLOCK_IN_OMAP343X,
1736         .recalc         = &omap2_clksel_recalc,
1737 };
1738
1739 static struct clk gpt8_fck = {
1740         .name           = "gpt8_fck",
1741         .init           = &omap2_init_clksel_parent,
1742         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1743         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1744         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1745         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
1746         .clksel         = omap343x_gpt_clksel,
1747         .flags          = CLOCK_IN_OMAP343X,
1748         .recalc         = &omap2_clksel_recalc,
1749 };
1750
1751 static struct clk gpt9_fck = {
1752         .name           = "gpt9_fck",
1753         .init           = &omap2_init_clksel_parent,
1754         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1755         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1756         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1757         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
1758         .clksel         = omap343x_gpt_clksel,
1759         .flags          = CLOCK_IN_OMAP343X,
1760         .recalc         = &omap2_clksel_recalc,
1761 };
1762
1763 static struct clk per_32k_alwon_fck = {
1764         .name           = "per_32k_alwon_fck",
1765         .parent         = &omap_32k_fck,
1766         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1767         .recalc         = &followparent_recalc,
1768 };
1769
1770 static struct clk gpio6_fck = {
1771         .name           = "gpio6_fck",
1772         .parent         = &per_32k_alwon_fck,
1773         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1774         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1775         .flags          = CLOCK_IN_OMAP343X,
1776         .recalc         = &followparent_recalc,
1777 };
1778
1779 static struct clk gpio5_fck = {
1780         .name           = "gpio5_fck",
1781         .parent         = &per_32k_alwon_fck,
1782         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1783         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1784         .flags          = CLOCK_IN_OMAP343X,
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk gpio4_fck = {
1789         .name           = "gpio4_fck",
1790         .parent         = &per_32k_alwon_fck,
1791         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1792         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1793         .flags          = CLOCK_IN_OMAP343X,
1794         .recalc         = &followparent_recalc,
1795 };
1796
1797 static struct clk gpio3_fck = {
1798         .name           = "gpio3_fck",
1799         .parent         = &per_32k_alwon_fck,
1800         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1801         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1802         .flags          = CLOCK_IN_OMAP343X,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk gpio2_fck = {
1807         .name           = "gpio2_fck",
1808         .parent         = &per_32k_alwon_fck,
1809         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1810         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1811         .flags          = CLOCK_IN_OMAP343X,
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk wdt3_fck = {
1816         .name           = "wdt3_fck",
1817         .parent         = &per_32k_alwon_fck,
1818         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1819         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
1820         .flags          = CLOCK_IN_OMAP343X,
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk per_l4_ick = {
1825         .name           = "per_l4_ick",
1826         .parent         = &l4_ick,
1827         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1828                                 PARENT_CONTROLS_CLOCK,
1829         .recalc         = &followparent_recalc,
1830 };
1831
1832 static struct clk gpio6_ick = {
1833         .name           = "gpio6_ick",
1834         .parent         = &per_l4_ick,
1835         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1836         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1837         .flags          = CLOCK_IN_OMAP343X,
1838         .recalc         = &followparent_recalc,
1839 };
1840
1841 static struct clk gpio5_ick = {
1842         .name           = "gpio5_ick",
1843         .parent         = &per_l4_ick,
1844         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1845         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1846         .flags          = CLOCK_IN_OMAP343X,
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk gpio4_ick = {
1851         .name           = "gpio4_ick",
1852         .parent         = &per_l4_ick,
1853         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1854         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1855         .flags          = CLOCK_IN_OMAP343X,
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk gpio3_ick = {
1860         .name           = "gpio3_ick",
1861         .parent         = &per_l4_ick,
1862         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1863         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1864         .flags          = CLOCK_IN_OMAP343X,
1865         .recalc         = &followparent_recalc,
1866 };
1867
1868 static struct clk gpio2_ick = {
1869         .name           = "gpio2_ick",
1870         .parent         = &per_l4_ick,
1871         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1872         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1873         .flags          = CLOCK_IN_OMAP343X,
1874         .recalc         = &followparent_recalc,
1875 };
1876
1877 static struct clk wdt3_ick = {
1878         .name           = "wdt3_ick",
1879         .parent         = &per_l4_ick,
1880         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1881         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
1882         .flags          = CLOCK_IN_OMAP343X,
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk uart3_ick = {
1887         .name           = "uart3_ick",
1888         .parent         = &per_l4_ick,
1889         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1890         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
1891         .flags          = CLOCK_IN_OMAP343X,
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk gpt9_ick = {
1896         .name           = "gpt9_ick",
1897         .parent         = &per_l4_ick,
1898         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1899         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1900         .flags          = CLOCK_IN_OMAP343X,
1901         .recalc         = &followparent_recalc,
1902 };
1903
1904 static struct clk gpt8_ick = {
1905         .name           = "gpt8_ick",
1906         .parent         = &per_l4_ick,
1907         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1908         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1909         .flags          = CLOCK_IN_OMAP343X,
1910         .recalc         = &followparent_recalc,
1911 };
1912
1913 static struct clk gpt7_ick = {
1914         .name           = "gpt7_ick",
1915         .parent         = &per_l4_ick,
1916         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1917         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1918         .flags          = CLOCK_IN_OMAP343X,
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk gpt6_ick = {
1923         .name           = "gpt6_ick",
1924         .parent         = &per_l4_ick,
1925         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1926         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1927         .flags          = CLOCK_IN_OMAP343X,
1928         .recalc         = &followparent_recalc,
1929 };
1930
1931 static struct clk gpt5_ick = {
1932         .name           = "gpt5_ick",
1933         .parent         = &per_l4_ick,
1934         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1935         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1936         .flags          = CLOCK_IN_OMAP343X,
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 static struct clk gpt4_ick = {
1941         .name           = "gpt4_ick",
1942         .parent         = &per_l4_ick,
1943         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1944         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1945         .flags          = CLOCK_IN_OMAP343X,
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk gpt3_ick = {
1950         .name           = "gpt3_ick",
1951         .parent         = &per_l4_ick,
1952         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1953         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1954         .flags          = CLOCK_IN_OMAP343X,
1955         .recalc         = &followparent_recalc,
1956 };
1957
1958 static struct clk gpt2_ick = {
1959         .name           = "gpt2_ick",
1960         .parent         = &per_l4_ick,
1961         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1962         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1963         .flags          = CLOCK_IN_OMAP343X,
1964         .recalc         = &followparent_recalc,
1965 };
1966
1967 static struct clk mcbsp2_ick = {
1968         .name           = "mcbsp2_ick",
1969         .parent         = &per_l4_ick,
1970         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1971         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
1972         .flags          = CLOCK_IN_OMAP343X,
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk mcbsp3_ick = {
1977         .name           = "mcbsp3_ick",
1978         .parent         = &per_l4_ick,
1979         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1980         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
1981         .flags          = CLOCK_IN_OMAP343X,
1982         .recalc         = &followparent_recalc,
1983 };
1984
1985 static struct clk mcbsp4_ick = {
1986         .name           = "mcbsp4_ick",
1987         .parent         = &per_l4_ick,
1988         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1989         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
1990         .flags          = CLOCK_IN_OMAP343X,
1991         .recalc         = &followparent_recalc,
1992 };
1993
1994 static const struct clksel mcbsp_234_clksel[] = {
1995         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
1996         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1997         { .parent = NULL }
1998 };
1999
2000 static struct clk mcbsp2_fck = {
2001         .name           = "mcbsp2_fck",
2002         .init           = &omap2_init_clksel_parent,
2003         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2004         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2005         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2006         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2007         .clksel         = mcbsp_234_clksel,
2008         .flags          = CLOCK_IN_OMAP343X,
2009         .recalc         = &omap2_clksel_recalc,
2010 };
2011
2012 static struct clk mcbsp3_fck = {
2013         .name           = "mcbsp3_fck",
2014         .init           = &omap2_init_clksel_parent,
2015         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2016         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2017         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2018         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2019         .clksel         = mcbsp_234_clksel,
2020         .flags          = CLOCK_IN_OMAP343X,
2021         .recalc         = &omap2_clksel_recalc,
2022 };
2023
2024 static struct clk mcbsp4_fck = {
2025         .name           = "mcbsp4_fck",
2026         .init           = &omap2_init_clksel_parent,
2027         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2028         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2029         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2030         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2031         .clksel         = mcbsp_234_clksel,
2032         .flags          = CLOCK_IN_OMAP343X,
2033         .recalc         = &omap2_clksel_recalc,
2034 };
2035
2036 /* EMU clocks */
2037
2038 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2039
2040 static const struct clksel_rate emu_src_sys_rates[] = {
2041         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2042         { .div = 0 },
2043 };
2044
2045 static const struct clksel_rate emu_src_core_rates[] = {
2046         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2047         { .div = 0 },
2048 };
2049
2050 static const struct clksel_rate emu_src_per_rates[] = {
2051         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2052         { .div = 0 },
2053 };
2054
2055 static const struct clksel_rate emu_src_mpu_rates[] = {
2056         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2057         { .div = 0 },
2058 };
2059
2060 static const struct clksel emu_src_clksel[] = {
2061         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2062         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2063         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2064         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2065         { .parent = NULL },
2066 };
2067
2068 /*
2069  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2070  * to switch the source of some of the EMU clocks.
2071  * XXX Are there CLKEN bits for these EMU clks?
2072  */
2073 static struct clk emu_src_ck = {
2074         .name           = "emu_src_ck",
2075         .init           = &omap2_init_clksel_parent,
2076         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2077         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2078         .clksel         = emu_src_clksel,
2079         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2080         .recalc         = &omap2_clksel_recalc,
2081 };
2082
2083 static const struct clksel_rate pclk_emu_rates[] = {
2084         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2085         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2086         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2087         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2088         { .div = 0 },
2089 };
2090
2091 static const struct clksel pclk_emu_clksel[] = {
2092         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2093         { .parent = NULL },
2094 };
2095
2096 static struct clk pclk_fck = {
2097         .name           = "pclk_fck",
2098         .init           = &omap2_init_clksel_parent,
2099         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2100         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2101         .clksel         = pclk_emu_clksel,
2102         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2103         .recalc         = &omap2_clksel_recalc,
2104 };
2105
2106 static const struct clksel_rate pclkx2_emu_rates[] = {
2107         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2108         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2109         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2110         { .div = 0 },
2111 };
2112
2113 static const struct clksel pclkx2_emu_clksel[] = {
2114         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2115         { .parent = NULL },
2116 };
2117
2118 static struct clk pclkx2_fck = {
2119         .name           = "pclkx2_fck",
2120         .init           = &omap2_init_clksel_parent,
2121         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2122         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2123         .clksel         = pclkx2_emu_clksel,
2124         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2125         .recalc         = &omap2_clksel_recalc,
2126 };
2127
2128 static const struct clksel atclk_emu_clksel[] = {
2129         { .parent = &emu_src_ck, .rates = div2_rates },
2130         { .parent = NULL },
2131 };
2132
2133 static struct clk atclk_fck = {
2134         .name           = "atclk_fck",
2135         .init           = &omap2_init_clksel_parent,
2136         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2137         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2138         .clksel         = atclk_emu_clksel,
2139         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2140         .recalc         = &omap2_clksel_recalc,
2141 };
2142
2143 static struct clk traceclk_src_fck = {
2144         .name           = "traceclk_src_fck",
2145         .init           = &omap2_init_clksel_parent,
2146         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2147         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2148         .clksel         = emu_src_clksel,
2149         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2150         .recalc         = &omap2_clksel_recalc,
2151 };
2152
2153 static const struct clksel_rate traceclk_rates[] = {
2154         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2155         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2156         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2157         { .div = 0 },
2158 };
2159
2160 static const struct clksel traceclk_clksel[] = {
2161         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2162         { .parent = NULL },
2163 };
2164
2165 static struct clk traceclk_fck = {
2166         .name           = "traceclk_fck",
2167         .init           = &omap2_init_clksel_parent,
2168         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2169         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2170         .clksel         = traceclk_clksel,
2171         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2172         .recalc         = &omap2_clksel_recalc,
2173 };
2174
2175 /* SR clocks */
2176
2177 /* SmartReflex fclk (VDD1) */
2178 static struct clk sr1_fck = {
2179         .name           = "sr1_fck",
2180         .parent         = &sys_ck,
2181         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2182         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2183         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2184         .recalc         = &followparent_recalc,
2185 };
2186
2187 /* SmartReflex fclk (VDD2) */
2188 static struct clk sr2_fck = {
2189         .name           = "sr2_fck",
2190         .parent         = &sys_ck,
2191         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2192         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2193         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2194         .recalc         = &followparent_recalc,
2195 };
2196
2197 static struct clk sr_l4_ick = {
2198         .name           = "sr_l4_ick",
2199         .parent         = &l4_ick,
2200         .flags          = CLOCK_IN_OMAP343X,
2201         .recalc         = &followparent_recalc,
2202 };
2203
2204 /* SECURE_32K_FCK clocks */
2205
2206 static struct clk gpt12_fck = {
2207         .name           = "gpt12_fck",
2208         .parent         = &secure_32k_fck,
2209         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 static struct clk wdt1_fck = {
2214         .name           = "wdt1_fck",
2215         .parent         = &secure_32k_fck,
2216         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220
2221 static struct clk *onchip_34xx_clks[] __initdata = {
2222         &omap_32k_fck,
2223         &virt_12m_ck,
2224         &virt_13m_ck,
2225         &virt_16_8m_ck,
2226         &virt_19_2m_ck,
2227         &virt_26m_ck,
2228         &virt_38_4m_ck,
2229         &osc_sys_ck,
2230         &sys_ck,
2231         &sys_altclk,
2232         &sys_clkout1,
2233         &dpll1_ck,
2234         &emu_mpu_alwon_ck,
2235         &dpll2_ck,
2236         &dpll3_ck,
2237         &core_ck,
2238         &dpll3_x2_ck,
2239         &dpll3_m2_ck,
2240         &dpll3_m2x2_ck,
2241         &dpll3_m3x2_ck,
2242         &emu_core_alwon_ck,
2243         &dpll4_ck,
2244         &dpll4_x2_ck,
2245         &omap_96m_alwon_fck,
2246         &omap_96m_fck,
2247         &cm_96m_fck,
2248         &omap_54m_fck,
2249         &omap_48m_fck,
2250         &omap_12m_fck,
2251         &dpll4_m2x2_ck,
2252         &dpll4_m3x2_ck,
2253         &dpll4_m4x2_ck,
2254         &dpll4_m5x2_ck,
2255         &dpll4_m6x2_ck,
2256         &emu_per_alwon_ck,
2257         &clkout2_src_ck,
2258         &sys_clkout2,
2259         &corex2_fck,
2260         &dpll1_fck,
2261         &dpll2_fck,
2262         &l3_ick,
2263         &l4_ick,
2264         &rm_ick,
2265         &gfx_l3_fck,
2266         &gfx_l3_ick,
2267         &gfx_cg1_ck,
2268         &gfx_cg2_ck,
2269         &d2d_26m_fck,
2270         &gpt10_fck,
2271         &gpt11_fck,
2272         &core_96m_fck,
2273         &mmchs2_fck,
2274         &mspro_fck,
2275         &mmchs1_fck,
2276         &i2c3_fck,
2277         &i2c2_fck,
2278         &i2c1_fck,
2279         &mcbsp5_fck,
2280         &mcbsp1_fck,
2281         &core_48m_fck,
2282         &mcspi4_fck,
2283         &mcspi3_fck,
2284         &mcspi2_fck,
2285         &mcspi1_fck,
2286         &uart2_fck,
2287         &uart1_fck,
2288         &fshostusb_fck,
2289         &core_12m_fck,
2290         &hdq_fck,
2291         &ssi_ssr_fck,
2292         &ssi_sst_fck,
2293         &core_l3_ick,
2294         &hsotgusb_ick,
2295         &sdrc_ick,
2296         &gpmc_fck,
2297         &security_l3_ick,
2298         &pka_ick,
2299         &core_l4_ick,
2300         &icr_ick,
2301         &aes2_ick,
2302         &sha12_ick,
2303         &des2_ick,
2304         &mmchs2_ick,
2305         &mmchs1_ick,
2306         &mspro_ick,
2307         &hdq_ick,
2308         &mcspi4_ick,
2309         &mcspi3_ick,
2310         &mcspi2_ick,
2311         &mcspi1_ick,
2312         &i2c3_ick,
2313         &i2c2_ick,
2314         &i2c1_ick,
2315         &uart2_ick,
2316         &uart1_ick,
2317         &gpt11_ick,
2318         &gpt10_ick,
2319         &mcbsp5_ick,
2320         &mcbsp1_ick,
2321         &fac_ick,
2322         &mailboxes_ick,
2323         &omapctrl_ick,
2324         &ssi_l4_ick,
2325         &ssi_ick,
2326         &usb_l4_ick,
2327         &security_l4_ick2,
2328         &aes1_ick,
2329         &rng_ick,
2330         &sha11_ick,
2331         &des1_ick,
2332         &dss1_alwon_fck,
2333         &dss_tv_fck,
2334         &dss_96m_fck,
2335         &dss2_alwon_fck,
2336         &dss_ick,
2337         &cam_mclk,
2338         &cam_l3_ick,
2339         &cam_l4_ick,
2340         &gpt1_fck,
2341         &wkup_32k_fck,
2342         &gpio1_fck,
2343         &wdt2_fck,
2344         &wkup_l4_ick,
2345         &wdt2_ick,
2346         &wdt1_ick,
2347         &gpio1_ick,
2348         &omap_32ksync_ick,
2349         &gpt12_ick,
2350         &gpt1_ick,
2351         &per_96m_fck,
2352         &per_48m_fck,
2353         &uart3_fck,
2354         &gpt2_fck,
2355         &gpt3_fck,
2356         &gpt4_fck,
2357         &gpt5_fck,
2358         &gpt6_fck,
2359         &gpt7_fck,
2360         &gpt8_fck,
2361         &gpt9_fck,
2362         &per_32k_alwon_fck,
2363         &gpio6_fck,
2364         &gpio5_fck,
2365         &gpio4_fck,
2366         &gpio3_fck,
2367         &gpio2_fck,
2368         &wdt3_fck,
2369         &per_l4_ick,
2370         &gpio6_ick,
2371         &gpio5_ick,
2372         &gpio4_ick,
2373         &gpio3_ick,
2374         &gpio2_ick,
2375         &wdt3_ick,
2376         &uart3_ick,
2377         &gpt9_ick,
2378         &gpt8_ick,
2379         &gpt7_ick,
2380         &gpt6_ick,
2381         &gpt5_ick,
2382         &gpt4_ick,
2383         &gpt3_ick,
2384         &gpt2_ick,
2385         &mcbsp2_ick,
2386         &mcbsp3_ick,
2387         &mcbsp4_ick,
2388         &mcbsp2_fck,
2389         &mcbsp3_fck,
2390         &mcbsp4_fck,
2391         &emu_src_ck,
2392         &pclk_fck,
2393         &pclkx2_fck,
2394         &atclk_fck,
2395         &traceclk_src_fck,
2396         &traceclk_fck,
2397         &sr1_fck,
2398         &sr2_fck,
2399         &sr_l4_ick,
2400         &secure_32k_fck,
2401         &gpt12_fck,
2402         &wdt1_fck,
2403 };
2404
2405 #endif