arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <asm/arch/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  52 #define DPLL_LOW_POWER_STOP             0x1
  53 #define DPLL_LOW_POWER_BYPASS           0x5
  54 #define DPLL_LOCKED                     0x7
  55
  56 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  57         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  58
  59 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  60         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  61
  62 #define OMAP3430_PRM_CLKSEL                                             \
  63         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  64
  65 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  66         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  67
  68 /* PRM CLOCKS */
  69
  70 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  71 static struct clk omap_32k_fck = {
  72         .name           = "omap_32k_fck",
  73         .rate           = 32768,
  74         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  75                                 ALWAYS_ENABLED,
  76         .recalc         = &propagate_rate,
  77 };
  78
  79 static struct clk secure_32k_fck = {
  80         .name           = "secure_32k_fck",
  81         .rate           = 32768,
  82         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  83                                 ALWAYS_ENABLED,
  84         .recalc         = &propagate_rate,
  85 };
  86
  87 /* Virtual source clocks for osc_sys_ck */
  88 static struct clk virt_12m_ck = {
  89         .name           = "virt_12m_ck",
  90         .rate           = 12000000,
  91         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  92                                 ALWAYS_ENABLED,
  93         .recalc         = &propagate_rate,
  94 };
  95
  96 static struct clk virt_13m_ck = {
  97         .name           = "virt_13m_ck",
  98         .rate           = 13000000,
  99         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 100                                 ALWAYS_ENABLED,
 101         .recalc         = &propagate_rate,
 102 };
 103
 104 static struct clk virt_16_8m_ck = {
 105         .name           = "virt_16_8m_ck",
 106         .rate           = 16800000,
 107         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 108                                 ALWAYS_ENABLED,
 109         .recalc         = &propagate_rate,
 110 };
 111
 112 static struct clk virt_19_2m_ck = {
 113         .name           = "virt_19_2m_ck",
 114         .rate           = 19200000,
 115         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 116                                 ALWAYS_ENABLED,
 117         .recalc         = &propagate_rate,
 118 };
 119
 120 static struct clk virt_26m_ck = {
 121         .name           = "virt_26m_ck",
 122         .rate           = 26000000,
 123         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 124                                 ALWAYS_ENABLED,
 125         .recalc         = &propagate_rate,
 126 };
 127
 128 static struct clk virt_38_4m_ck = {
 129         .name           = "virt_38_4m_ck",
 130         .rate           = 38400000,
 131         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 132                                 ALWAYS_ENABLED,
 133         .recalc         = &propagate_rate,
 134 };
 135
 136 static const struct clksel_rate osc_sys_12m_rates[] = {
 137         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 138         { .div = 0 }
 139 };
 140
 141 static const struct clksel_rate osc_sys_13m_rates[] = {
 142         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 143         { .div = 0 }
 144 };
 145
 146 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 147         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 148         { .div = 0 }
 149 };
 150
 151 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 152         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 153         { .div = 0 }
 154 };
 155
 156 static const struct clksel_rate osc_sys_26m_rates[] = {
 157         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 158         { .div = 0 }
 159 };
 160
 161 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 162         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 163         { .div = 0 }
 164 };
 165
 166 static const struct clksel osc_sys_clksel[] = {
 167         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 168         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 169         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 170         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 171         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 172         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 173         { .parent = NULL },
 174 };
 175
 176 /* Oscillator clock */
 177 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 178 static struct clk osc_sys_ck = {
 179         .name           = "osc_sys_ck",
 180         .init           = &omap2_init_clksel_parent,
 181         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 182         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 183         .clksel         = osc_sys_clksel,
 184         /* REVISIT: deal with autoextclkmode? */
 185         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 186                                 ALWAYS_ENABLED,
 187         .recalc         = &omap2_clksel_recalc,
 188 };
 189
 190 static const struct clksel_rate div2_rates[] = {
 191         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 192         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 193         { .div = 0 }
 194 };
 195
 196 static const struct clksel sys_clksel[] = {
 197         { .parent = &osc_sys_ck, .rates = div2_rates },
 198         { .parent = NULL }
 199 };
 200
 201 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 202 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 203 static struct clk sys_ck = {
 204         .name           = "sys_ck",
 205         .parent         = &osc_sys_ck,
 206         .init           = &omap2_init_clksel_parent,
 207         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 208         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 209         .clksel         = sys_clksel,
 210         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 211         .recalc         = &omap2_clksel_recalc,
 212 };
 213
 214 static struct clk sys_altclk = {
 215         .name           = "sys_altclk",
 216         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 217         .recalc         = &propagate_rate,
 218 };
 219
 220 /* Optional external clock input for some McBSPs */
 221 static struct clk mcbsp_clks = {
 222         .name           = "mcbsp_clks",
 223         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 224         .recalc         = &propagate_rate,
 225 };
 226
 227 /* PRM EXTERNAL CLOCK OUTPUT */
 228
 229 static struct clk sys_clkout1 = {
 230         .name           = "sys_clkout1",
 231         .parent         = &osc_sys_ck,
 232         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 233         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 234         .flags          = CLOCK_IN_OMAP343X,
 235         .recalc         = &followparent_recalc,
 236 };
 237
 238 /* DPLLS */
 239
 240 /* CM CLOCKS */
 241
 242 static const struct clksel_rate dpll_bypass_rates[] = {
 243         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 244         { .div = 0 }
 245 };
 246
 247 static const struct clksel_rate dpll_locked_rates[] = {
 248         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 249         { .div = 0 }
 250 };
 251
 252 static const struct clksel_rate div16_dpll_rates[] = {
 253         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 254         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 255         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 256         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 257         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 258         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 259         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 260         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 261         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 262         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 263         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 264         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 265         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 266         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 267         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 268         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 269         { .div = 0 }
 270 };
 271
 272 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 273         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 274
 275 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 276         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 277
 278 /* DPLL1 */
 279 /* MPU clock source */
 280 /* Type: DPLL */
 281 static struct dpll_data dpll1_dd = {
 282         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 283         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 284         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 285         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 286         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 287         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 288         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 289         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 290         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 291         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 292         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 293         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 294         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 295         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 296         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 297         .max_divider    = OMAP3_MAX_DPLL_DIV,
 298         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 299 };
 300
 301 static struct clk dpll1_ck = {
 302         .name           = "dpll1_ck",
 303         .parent         = &sys_ck,
 304         .dpll_data      = &dpll1_dd,
 305         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 306         .round_rate     = &omap2_dpll_round_rate,
 307         .set_rate       = &omap3_noncore_dpll_set_rate,
 308         .recalc         = &omap3_dpll_recalc,
 309 };
 310
 311 /*
 312  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 313  * DPLL isn't bypassed.
 314  */
 315 static struct clk dpll1_x2_ck = {
 316         .name           = "dpll1_x2_ck",
 317         .parent         = &dpll1_ck,
 318         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 319                                 PARENT_CONTROLS_CLOCK,
 320         .recalc         = &omap3_clkoutx2_recalc,
 321 };
 322
 323 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 324 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 325         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 326         { .parent = NULL }
 327 };
 328
 329 /*
 330  * Does not exist in the TRM - needed to separate the M2 divider from
 331  * bypass selection in mpu_ck
 332  */
 333 static struct clk dpll1_x2m2_ck = {
 334         .name           = "dpll1_x2m2_ck",
 335         .parent         = &dpll1_x2_ck,
 336         .init           = &omap2_init_clksel_parent,
 337         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 338         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 339         .clksel         = div16_dpll1_x2m2_clksel,
 340         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 341                                 PARENT_CONTROLS_CLOCK,
 342         .recalc         = &omap2_clksel_recalc,
 343 };
 344
 345 /* DPLL2 */
 346 /* IVA2 clock source */
 347 /* Type: DPLL */
 348
 349 static struct dpll_data dpll2_dd = {
 350         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 351         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 352         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 353         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 354         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 355         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 356         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 357                                 (1 << DPLL_LOW_POWER_BYPASS),
 358         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 359         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 360         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 361         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 362         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 363         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 364         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 365         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 366         .max_divider    = OMAP3_MAX_DPLL_DIV,
 367         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 368 };
 369
 370 static struct clk dpll2_ck = {
 371         .name           = "dpll2_ck",
 372         .parent         = &sys_ck,
 373         .dpll_data      = &dpll2_dd,
 374         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 375         .enable         = &omap3_noncore_dpll_enable,
 376         .disable        = &omap3_noncore_dpll_disable,
 377         .round_rate     = &omap2_dpll_round_rate,
 378         .set_rate       = &omap3_noncore_dpll_set_rate,
 379         .recalc         = &omap3_dpll_recalc,
 380 };
 381
 382 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 383         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 384         { .parent = NULL }
 385 };
 386
 387 /*
 388  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 389  * or CLKOUTX2. CLKOUT seems most plausible.
 390  */
 391 static struct clk dpll2_m2_ck = {
 392         .name           = "dpll2_m2_ck",
 393         .parent         = &dpll2_ck,
 394         .init           = &omap2_init_clksel_parent,
 395         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 396                                           OMAP3430_CM_CLKSEL2_PLL),
 397         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 398         .clksel         = div16_dpll2_m2x2_clksel,
 399         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 400                                 PARENT_CONTROLS_CLOCK,
 401         .recalc         = &omap2_clksel_recalc,
 402 };
 403
 404 /*
 405  * DPLL3
 406  * Source clock for all interfaces and for some device fclks
 407  * REVISIT: Also supports fast relock bypass - not included below
 408  */
 409 static struct dpll_data dpll3_dd = {
 410         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 411         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 412         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 413         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 414         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 415         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 416         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 417         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 418         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 419         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 420         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 421         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 422         .max_divider    = OMAP3_MAX_DPLL_DIV,
 423         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 424 };
 425
 426 static struct clk dpll3_ck = {
 427         .name           = "dpll3_ck",
 428         .parent         = &sys_ck,
 429         .dpll_data      = &dpll3_dd,
 430         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 431         .round_rate     = &omap2_dpll_round_rate,
 432         .recalc         = &omap3_dpll_recalc,
 433 };
 434
 435 /*
 436  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 437  * DPLL isn't bypassed
 438  */
 439 static struct clk dpll3_x2_ck = {
 440         .name           = "dpll3_x2_ck",
 441         .parent         = &dpll3_ck,
 442         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 443                                 PARENT_CONTROLS_CLOCK,
 444         .recalc         = &omap3_clkoutx2_recalc,
 445 };
 446
 447 static const struct clksel_rate div31_dpll3_rates[] = {
 448         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 449         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 450         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 451         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 452         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 453         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 454         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 455         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 456         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 457         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 458         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 459         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 460         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 461         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 462         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 463         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 464         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 465         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 466         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 467         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 468         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 469         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 470         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 471         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 472         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 473         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 474         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 475         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 476         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 477         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 478         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 479         { .div = 0 },
 480 };
 481
 482 static const struct clksel div31_dpll3m2_clksel[] = {
 483         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 484         { .parent = NULL }
 485 };
 486
 487 /*
 488  * DPLL3 output M2
 489  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 490  * that code is ready, this should remain a 'read-only' clksel clock.
 491  */
 492 static struct clk dpll3_m2_ck = {
 493         .name           = "dpll3_m2_ck",
 494         .parent         = &dpll3_ck,
 495         .init           = &omap2_init_clksel_parent,
 496         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 497         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 498         .clksel         = div31_dpll3m2_clksel,
 499         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 500                                 PARENT_CONTROLS_CLOCK,
 501         .recalc         = &omap2_clksel_recalc,
 502 };
 503
 504 static const struct clksel core_ck_clksel[] = {
 505         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 506         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 507         { .parent = NULL }
 508 };
 509
 510 static struct clk core_ck = {
 511         .name           = "core_ck",
 512         .init           = &omap2_init_clksel_parent,
 513         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 514         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 515         .clksel         = core_ck_clksel,
 516         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 517                                 PARENT_CONTROLS_CLOCK,
 518         .recalc         = &omap2_clksel_recalc,
 519 };
 520
 521 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 522         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 523         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 524         { .parent = NULL }
 525 };
 526
 527 static struct clk dpll3_m2x2_ck = {
 528         .name           = "dpll3_m2x2_ck",
 529         .init           = &omap2_init_clksel_parent,
 530         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 531         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 532         .clksel         = dpll3_m2x2_ck_clksel,
 533         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 534                                 PARENT_CONTROLS_CLOCK,
 535         .recalc         = &omap2_clksel_recalc,
 536 };
 537
 538 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 539 static const struct clksel div16_dpll3_clksel[] = {
 540         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 541         { .parent = NULL }
 542 };
 543
 544 /* This virtual clock is the source for dpll3_m3x2_ck */
 545 static struct clk dpll3_m3_ck = {
 546         .name           = "dpll3_m3_ck",
 547         .parent         = &dpll3_ck,
 548         .init           = &omap2_init_clksel_parent,
 549         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 550         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 551         .clksel         = div16_dpll3_clksel,
 552         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 553                                 PARENT_CONTROLS_CLOCK,
 554         .recalc         = &omap2_clksel_recalc,
 555 };
 556
 557 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 558 static struct clk dpll3_m3x2_ck = {
 559         .name           = "dpll3_m3x2_ck",
 560         .parent         = &dpll3_m3_ck,
 561         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 562         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 563         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 564         .recalc         = &omap3_clkoutx2_recalc,
 565 };
 566
 567 static const struct clksel emu_core_alwon_ck_clksel[] = {
 568         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 569         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 570         { .parent = NULL }
 571 };
 572
 573 static struct clk emu_core_alwon_ck = {
 574         .name           = "emu_core_alwon_ck",
 575         .parent         = &dpll3_m3x2_ck,
 576         .init           = &omap2_init_clksel_parent,
 577         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 578         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 579         .clksel         = emu_core_alwon_ck_clksel,
 580         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 581                                 PARENT_CONTROLS_CLOCK,
 582         .recalc         = &omap2_clksel_recalc,
 583 };
 584
 585 /* DPLL4 */
 586 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 587 /* Type: DPLL */
 588 static struct dpll_data dpll4_dd = {
 589         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 590         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 591         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 592         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 593         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 594         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 595         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 596         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 597         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 598         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 599         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 600         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 601         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 602         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 603         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 604         .max_divider    = OMAP3_MAX_DPLL_DIV,
 605         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 606 };
 607
 608 static struct clk dpll4_ck = {
 609         .name           = "dpll4_ck",
 610         .parent         = &sys_ck,
 611         .dpll_data      = &dpll4_dd,
 612         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 613         .enable         = &omap3_noncore_dpll_enable,
 614         .disable        = &omap3_noncore_dpll_disable,
 615         .round_rate     = &omap2_dpll_round_rate,
 616         .set_rate       = &omap3_noncore_dpll_set_rate,
 617         .recalc         = &omap3_dpll_recalc,
 618 };
 619
 620 /*
 621  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 622  * DPLL isn't bypassed --
 623  * XXX does this serve any downstream clocks?
 624  */
 625 static struct clk dpll4_x2_ck = {
 626         .name           = "dpll4_x2_ck",
 627         .parent         = &dpll4_ck,
 628         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 629                                 PARENT_CONTROLS_CLOCK,
 630         .recalc         = &omap3_clkoutx2_recalc,
 631 };
 632
 633 static const struct clksel div16_dpll4_clksel[] = {
 634         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 635         { .parent = NULL }
 636 };
 637
 638 /* This virtual clock is the source for dpll4_m2x2_ck */
 639 static struct clk dpll4_m2_ck = {
 640         .name           = "dpll4_m2_ck",
 641         .parent         = &dpll4_ck,
 642         .init           = &omap2_init_clksel_parent,
 643         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 644         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 645         .clksel         = div16_dpll4_clksel,
 646         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 647                                 PARENT_CONTROLS_CLOCK,
 648         .recalc         = &omap2_clksel_recalc,
 649 };
 650
 651 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 652 static struct clk dpll4_m2x2_ck = {
 653         .name           = "dpll4_m2x2_ck",
 654         .parent         = &dpll4_m2_ck,
 655         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 656         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 657         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 658         .recalc         = &omap3_clkoutx2_recalc,
 659 };
 660
 661 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 662         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 663         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 664         { .parent = NULL }
 665 };
 666
 667 /*
 668  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 669  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 670  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 671  * CM_96K_(F)CLK.
 672  */
 673 static struct clk omap_96m_alwon_fck = {
 674         .name           = "omap_96m_alwon_fck",
 675         .parent         = &dpll4_m2x2_ck,
 676         .init           = &omap2_init_clksel_parent,
 677         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 678         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 679         .clksel         = omap_96m_alwon_fck_clksel,
 680         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 681                                 PARENT_CONTROLS_CLOCK,
 682         .recalc         = &omap2_clksel_recalc,
 683 };
 684
 685 static struct clk cm_96m_fck = {
 686         .name           = "cm_96m_fck",
 687         .parent         = &omap_96m_alwon_fck,
 688         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 689                                 PARENT_CONTROLS_CLOCK,
 690         .recalc         = &followparent_recalc,
 691 };
 692
 693 static const struct clksel_rate omap_96m_dpll_rates[] = {
 694         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 695         { .div = 0 }
 696 };
 697
 698 static const struct clksel_rate omap_96m_sys_rates[] = {
 699         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 700         { .div = 0 }
 701 };
 702
 703 static const struct clksel omap_96m_fck_clksel[] = {
 704         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 705         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 706         { .parent = NULL }
 707 };
 708
 709 static struct clk omap_96m_fck = {
 710         .name           = "omap_96m_fck",
 711         .parent         = &sys_ck,
 712         .init           = &omap2_init_clksel_parent,
 713         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 714         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 715         .clksel         = omap_96m_fck_clksel,
 716         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 717                                 PARENT_CONTROLS_CLOCK,
 718         .recalc         = &omap2_clksel_recalc,
 719 };
 720
 721 /* This virtual clock is the source for dpll4_m3x2_ck */
 722 static struct clk dpll4_m3_ck = {
 723         .name           = "dpll4_m3_ck",
 724         .parent         = &dpll4_ck,
 725         .init           = &omap2_init_clksel_parent,
 726         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 727         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 728         .clksel         = div16_dpll4_clksel,
 729         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 730                                 PARENT_CONTROLS_CLOCK,
 731         .recalc         = &omap2_clksel_recalc,
 732 };
 733
 734 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 735 static struct clk dpll4_m3x2_ck = {
 736         .name           = "dpll4_m3x2_ck",
 737         .parent         = &dpll4_m3_ck,
 738         .init           = &omap2_init_clksel_parent,
 739         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 740         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 741         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 742         .recalc         = &omap3_clkoutx2_recalc,
 743 };
 744
 745 static const struct clksel virt_omap_54m_fck_clksel[] = {
 746         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 747         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 748         { .parent = NULL }
 749 };
 750
 751 static struct clk virt_omap_54m_fck = {
 752         .name           = "virt_omap_54m_fck",
 753         .parent         = &dpll4_m3x2_ck,
 754         .init           = &omap2_init_clksel_parent,
 755         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 756         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 757         .clksel         = virt_omap_54m_fck_clksel,
 758         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 759                                 PARENT_CONTROLS_CLOCK,
 760         .recalc         = &omap2_clksel_recalc,
 761 };
 762
 763 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 764         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 765         { .div = 0 }
 766 };
 767
 768 static const struct clksel_rate omap_54m_alt_rates[] = {
 769         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 770         { .div = 0 }
 771 };
 772
 773 static const struct clksel omap_54m_clksel[] = {
 774         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 775         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 776         { .parent = NULL }
 777 };
 778
 779 static struct clk omap_54m_fck = {
 780         .name           = "omap_54m_fck",
 781         .init           = &omap2_init_clksel_parent,
 782         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 783         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 784         .clksel         = omap_54m_clksel,
 785         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 786                                 PARENT_CONTROLS_CLOCK,
 787         .recalc         = &omap2_clksel_recalc,
 788 };
 789
 790 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 791         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 792         { .div = 0 }
 793 };
 794
 795 static const struct clksel_rate omap_48m_alt_rates[] = {
 796         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 797         { .div = 0 }
 798 };
 799
 800 static const struct clksel omap_48m_clksel[] = {
 801         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 802         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 803         { .parent = NULL }
 804 };
 805
 806 static struct clk omap_48m_fck = {
 807         .name           = "omap_48m_fck",
 808         .init           = &omap2_init_clksel_parent,
 809         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 810         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 811         .clksel         = omap_48m_clksel,
 812         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 813                                 PARENT_CONTROLS_CLOCK,
 814         .recalc         = &omap2_clksel_recalc,
 815 };
 816
 817 static struct clk omap_12m_fck = {
 818         .name           = "omap_12m_fck",
 819         .parent         = &omap_48m_fck,
 820         .fixed_div      = 4,
 821         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 822                                 PARENT_CONTROLS_CLOCK,
 823         .recalc         = &omap2_fixed_divisor_recalc,
 824 };
 825
 826 /* This virstual clock is the source for dpll4_m4x2_ck */
 827 static struct clk dpll4_m4_ck = {
 828         .name           = "dpll4_m4_ck",
 829         .parent         = &dpll4_ck,
 830         .init           = &omap2_init_clksel_parent,
 831         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 832         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 833         .clksel         = div16_dpll4_clksel,
 834         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 835                                 PARENT_CONTROLS_CLOCK,
 836         .recalc         = &omap2_clksel_recalc,
 837 };
 838
 839 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 840 static struct clk dpll4_m4x2_ck = {
 841         .name           = "dpll4_m4x2_ck",
 842         .parent         = &dpll4_m4_ck,
 843         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 844         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 845         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 846         .recalc         = &omap3_clkoutx2_recalc,
 847 };
 848
 849 /* This virtual clock is the source for dpll4_m5x2_ck */
 850 static struct clk dpll4_m5_ck = {
 851         .name           = "dpll4_m5_ck",
 852         .parent         = &dpll4_ck,
 853         .init           = &omap2_init_clksel_parent,
 854         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 855         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 856         .clksel         = div16_dpll4_clksel,
 857         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 858                                 PARENT_CONTROLS_CLOCK,
 859         .recalc         = &omap2_clksel_recalc,
 860 };
 861
 862 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 863 static struct clk dpll4_m5x2_ck = {
 864         .name           = "dpll4_m5x2_ck",
 865         .parent         = &dpll4_m5_ck,
 866         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 867         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 868         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 869         .recalc         = &omap3_clkoutx2_recalc,
 870 };
 871
 872 /* This virtual clock is the source for dpll4_m6x2_ck */
 873 static struct clk dpll4_m6_ck = {
 874         .name           = "dpll4_m6_ck",
 875         .parent         = &dpll4_ck,
 876         .init           = &omap2_init_clksel_parent,
 877         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 878         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 879         .clksel         = div16_dpll4_clksel,
 880         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 881                                 PARENT_CONTROLS_CLOCK,
 882         .recalc         = &omap2_clksel_recalc,
 883 };
 884
 885 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 886 static struct clk dpll4_m6x2_ck = {
 887         .name           = "dpll4_m6x2_ck",
 888         .parent         = &dpll4_m6_ck,
 889         .init           = &omap2_init_clksel_parent,
 890         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 891         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 892         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 893         .recalc         = &omap3_clkoutx2_recalc,
 894 };
 895
 896 static struct clk emu_per_alwon_ck = {
 897         .name           = "emu_per_alwon_ck",
 898         .parent         = &dpll4_m6x2_ck,
 899         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 900                                 PARENT_CONTROLS_CLOCK,
 901         .recalc         = &followparent_recalc,
 902 };
 903
 904 /* DPLL5 */
 905 /* Supplies 120MHz clock, USIM source clock */
 906 /* Type: DPLL */
 907 /* 3430ES2 only */
 908 static struct dpll_data dpll5_dd = {
 909         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 910         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 911         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 912         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 913         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 914         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 915         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 916         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 917         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 918         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 919         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 920         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 921         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 922         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 923         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 924         .max_divider    = OMAP3_MAX_DPLL_DIV,
 925         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 926 };
 927
 928 static struct clk dpll5_ck = {
 929         .name           = "dpll5_ck",
 930         .parent         = &sys_ck,
 931         .dpll_data      = &dpll5_dd,
 932         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 933         .enable         = &omap3_noncore_dpll_enable,
 934         .disable        = &omap3_noncore_dpll_disable,
 935         .round_rate     = &omap2_dpll_round_rate,
 936         .set_rate       = &omap3_noncore_dpll_set_rate,
 937         .recalc         = &omap3_dpll_recalc,
 938 };
 939
 940 static const struct clksel div16_dpll5_clksel[] = {
 941         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 942         { .parent = NULL }
 943 };
 944
 945 static struct clk dpll5_m2_ck = {
 946         .name           = "dpll5_m2_ck",
 947         .parent         = &dpll5_ck,
 948         .init           = &omap2_init_clksel_parent,
 949         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 950         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 951         .clksel         = div16_dpll5_clksel,
 952         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 953                                 PARENT_CONTROLS_CLOCK,
 954         .recalc         = &omap2_clksel_recalc,
 955 };
 956
 957 static const struct clksel omap_120m_fck_clksel[] = {
 958         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 959         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 960         { .parent = NULL }
 961 };
 962
 963 static struct clk omap_120m_fck = {
 964         .name           = "omap_120m_fck",
 965         .parent         = &dpll5_m2_ck,
 966         .init           = &omap2_init_clksel_parent,
 967         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 968         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 969         .clksel         = omap_120m_fck_clksel,
 970         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 971                                 PARENT_CONTROLS_CLOCK,
 972         .recalc         = &omap2_clksel_recalc,
 973 };
 974
 975 /* CM EXTERNAL CLOCK OUTPUTS */
 976
 977 static const struct clksel_rate clkout2_src_core_rates[] = {
 978         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 979         { .div = 0 }
 980 };
 981
 982 static const struct clksel_rate clkout2_src_sys_rates[] = {
 983         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 984         { .div = 0 }
 985 };
 986
 987 static const struct clksel_rate clkout2_src_96m_rates[] = {
 988         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 989         { .div = 0 }
 990 };
 991
 992 static const struct clksel_rate clkout2_src_54m_rates[] = {
 993         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 994         { .div = 0 }
 995 };
 996
 997 static const struct clksel clkout2_src_clksel[] = {
 998         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 999         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1000         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1001         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1002         { .parent = NULL }
1003 };
1004
1005 static struct clk clkout2_src_ck = {
1006         .name           = "clkout2_src_ck",
1007         .init           = &omap2_init_clksel_parent,
1008         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1009         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1010         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1011         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1012         .clksel         = clkout2_src_clksel,
1013         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1014         .clkdm_name     = "core_clkdm",
1015         .recalc         = &omap2_clksel_recalc,
1016 };
1017
1018 static const struct clksel_rate sys_clkout2_rates[] = {
1019         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1020         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1021         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1022         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1023         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1024         { .div = 0 },
1025 };
1026
1027 static const struct clksel sys_clkout2_clksel[] = {
1028         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1029         { .parent = NULL },
1030 };
1031
1032 static struct clk sys_clkout2 = {
1033         .name           = "sys_clkout2",
1034         .init           = &omap2_init_clksel_parent,
1035         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1036         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1037         .clksel         = sys_clkout2_clksel,
1038         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1039         .recalc         = &omap2_clksel_recalc,
1040 };
1041
1042 /* CM OUTPUT CLOCKS */
1043
1044 static struct clk corex2_fck = {
1045         .name           = "corex2_fck",
1046         .parent         = &dpll3_m2x2_ck,
1047         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1048                                 PARENT_CONTROLS_CLOCK,
1049         .recalc         = &followparent_recalc,
1050 };
1051
1052 /* DPLL power domain clock controls */
1053
1054 static const struct clksel_rate div4_rates[] = {
1055         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1056         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1057         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1058         { .div = 0 }
1059 };
1060
1061 static const struct clksel div4_core_clksel[] = {
1062         { .parent = &core_ck, .rates = div4_rates },
1063         { .parent = NULL }
1064 };
1065
1066 /*
1067  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1068  * may be inconsistent here?
1069  */
1070 static struct clk dpll1_fck = {
1071         .name           = "dpll1_fck",
1072         .parent         = &core_ck,
1073         .init           = &omap2_init_clksel_parent,
1074         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1075         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1076         .clksel         = div4_core_clksel,
1077         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1078                                 PARENT_CONTROLS_CLOCK,
1079         .recalc         = &omap2_clksel_recalc,
1080 };
1081
1082 /*
1083  * MPU clksel:
1084  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1085  * derives from the high-frequency bypass clock originating from DPLL3,
1086  * called 'dpll1_fck'
1087  */
1088 static const struct clksel mpu_clksel[] = {
1089         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1090         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1091         { .parent = NULL }
1092 };
1093
1094 static struct clk mpu_ck = {
1095         .name           = "mpu_ck",
1096         .parent         = &dpll1_x2m2_ck,
1097         .init           = &omap2_init_clksel_parent,
1098         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1099         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1100         .clksel         = mpu_clksel,
1101         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1102                                 PARENT_CONTROLS_CLOCK,
1103         .clkdm_name     = "mpu_clkdm",
1104         .recalc         = &omap2_clksel_recalc,
1105 };
1106
1107 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1108 static const struct clksel_rate arm_fck_rates[] = {
1109         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1110         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1111         { .div = 0 },
1112 };
1113
1114 static const struct clksel arm_fck_clksel[] = {
1115         { .parent = &mpu_ck, .rates = arm_fck_rates },
1116         { .parent = NULL }
1117 };
1118
1119 static struct clk arm_fck = {
1120         .name           = "arm_fck",
1121         .parent         = &mpu_ck,
1122         .init           = &omap2_init_clksel_parent,
1123         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1124         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1125         .clksel         = arm_fck_clksel,
1126         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1127                                 PARENT_CONTROLS_CLOCK,
1128         .recalc         = &omap2_clksel_recalc,
1129 };
1130
1131 /* XXX What about neon_clkdm ? */
1132
1133 /*
1134  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1135  * although it is referenced - so this is a guess
1136  */
1137 static struct clk emu_mpu_alwon_ck = {
1138         .name           = "emu_mpu_alwon_ck",
1139         .parent         = &mpu_ck,
1140         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1141                                 PARENT_CONTROLS_CLOCK,
1142         .recalc         = &followparent_recalc,
1143 };
1144
1145 static struct clk dpll2_fck = {
1146         .name           = "dpll2_fck",
1147         .parent         = &core_ck,
1148         .init           = &omap2_init_clksel_parent,
1149         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1150         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1151         .clksel         = div4_core_clksel,
1152         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1153                                 PARENT_CONTROLS_CLOCK,
1154         .recalc         = &omap2_clksel_recalc,
1155 };
1156
1157 /*
1158  * IVA2 clksel:
1159  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1160  * derives from the high-frequency bypass clock originating from DPLL3,
1161  * called 'dpll2_fck'
1162  */
1163
1164 static const struct clksel iva2_clksel[] = {
1165         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1166         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1167         { .parent = NULL }
1168 };
1169
1170 static struct clk iva2_ck = {
1171         .name           = "iva2_ck",
1172         .parent         = &dpll2_m2_ck,
1173         .init           = &omap2_init_clksel_parent,
1174         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1175         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1176         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1177                                           OMAP3430_CM_IDLEST_PLL),
1178         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1179         .clksel         = iva2_clksel,
1180         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1181         .clkdm_name     = "iva2_clkdm",
1182         .recalc         = &omap2_clksel_recalc,
1183 };
1184
1185 /* Common interface clocks */
1186
1187 static const struct clksel div2_core_clksel[] = {
1188         { .parent = &core_ck, .rates = div2_rates },
1189         { .parent = NULL }
1190 };
1191
1192 static struct clk l3_ick = {
1193         .name           = "l3_ick",
1194         .parent         = &core_ck,
1195         .init           = &omap2_init_clksel_parent,
1196         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1197         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1198         .clksel         = div2_core_clksel,
1199         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1200                                 PARENT_CONTROLS_CLOCK,
1201         .clkdm_name     = "core_l3_clkdm",
1202         .recalc         = &omap2_clksel_recalc,
1203 };
1204
1205 static const struct clksel div2_l3_clksel[] = {
1206         { .parent = &l3_ick, .rates = div2_rates },
1207         { .parent = NULL }
1208 };
1209
1210 static struct clk l4_ick = {
1211         .name           = "l4_ick",
1212         .parent         = &l3_ick,
1213         .init           = &omap2_init_clksel_parent,
1214         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1215         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1216         .clksel         = div2_l3_clksel,
1217         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1218                                 PARENT_CONTROLS_CLOCK,
1219         .clkdm_name     = "core_l4_clkdm",
1220         .recalc         = &omap2_clksel_recalc,
1221
1222 };
1223
1224 static const struct clksel div2_l4_clksel[] = {
1225         { .parent = &l4_ick, .rates = div2_rates },
1226         { .parent = NULL }
1227 };
1228
1229 static struct clk rm_ick = {
1230         .name           = "rm_ick",
1231         .parent         = &l4_ick,
1232         .init           = &omap2_init_clksel_parent,
1233         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1234         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1235         .clksel         = div2_l4_clksel,
1236         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1237         .recalc         = &omap2_clksel_recalc,
1238 };
1239
1240 /* GFX power domain */
1241
1242 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1243
1244 static const struct clksel gfx_l3_clksel[] = {
1245         { .parent = &l3_ick, .rates = gfx_l3_rates },
1246         { .parent = NULL }
1247 };
1248
1249 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1250 static struct clk gfx_l3_ck = {
1251         .name           = "gfx_l3_ck",
1252         .parent         = &l3_ick,
1253         .init           = &omap2_init_clksel_parent,
1254         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1255         .enable_bit     = OMAP_EN_GFX_SHIFT,
1256         .flags          = CLOCK_IN_OMAP3430ES1,
1257         .recalc         = &followparent_recalc,
1258 };
1259
1260 static struct clk gfx_l3_fck = {
1261         .name           = "gfx_l3_fck",
1262         .parent         = &gfx_l3_ck,
1263         .init           = &omap2_init_clksel_parent,
1264         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1265         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1266         .clksel         = gfx_l3_clksel,
1267         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1268                                 PARENT_CONTROLS_CLOCK,
1269         .clkdm_name     = "gfx_3430es1_clkdm",
1270         .recalc         = &omap2_clksel_recalc,
1271 };
1272
1273 static struct clk gfx_l3_ick = {
1274         .name           = "gfx_l3_ick",
1275         .parent         = &gfx_l3_ck,
1276         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1277         .clkdm_name     = "gfx_3430es1_clkdm",
1278         .recalc         = &followparent_recalc,
1279 };
1280
1281 static struct clk gfx_cg1_ck = {
1282         .name           = "gfx_cg1_ck",
1283         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1284         .init           = &omap2_init_clk_clkdm,
1285         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1286         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1287         .flags          = CLOCK_IN_OMAP3430ES1,
1288         .clkdm_name     = "gfx_3430es1_clkdm",
1289         .recalc         = &followparent_recalc,
1290 };
1291
1292 static struct clk gfx_cg2_ck = {
1293         .name           = "gfx_cg2_ck",
1294         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1295         .init           = &omap2_init_clk_clkdm,
1296         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1297         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1298         .flags          = CLOCK_IN_OMAP3430ES1,
1299         .clkdm_name     = "gfx_3430es1_clkdm",
1300         .recalc         = &followparent_recalc,
1301 };
1302
1303 /* SGX power domain - 3430ES2 only */
1304
1305 static const struct clksel_rate sgx_core_rates[] = {
1306         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1307         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1308         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1309         { .div = 0 },
1310 };
1311
1312 static const struct clksel_rate sgx_96m_rates[] = {
1313         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1314         { .div = 0 },
1315 };
1316
1317 static const struct clksel sgx_clksel[] = {
1318         { .parent = &core_ck,    .rates = sgx_core_rates },
1319         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1320         { .parent = NULL },
1321 };
1322
1323 static struct clk sgx_fck = {
1324         .name           = "sgx_fck",
1325         .init           = &omap2_init_clksel_parent,
1326         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1327         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1328         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1329         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1330         .clksel         = sgx_clksel,
1331         .flags          = CLOCK_IN_OMAP3430ES2,
1332         .clkdm_name     = "sgx_clkdm",
1333         .recalc         = &omap2_clksel_recalc,
1334 };
1335
1336 static struct clk sgx_ick = {
1337         .name           = "sgx_ick",
1338         .parent         = &l3_ick,
1339         .init           = &omap2_init_clk_clkdm,
1340         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1341         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1342         .flags          = CLOCK_IN_OMAP3430ES2,
1343         .clkdm_name     = "sgx_clkdm",
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 /* CORE power domain */
1348
1349 static struct clk d2d_26m_fck = {
1350         .name           = "d2d_26m_fck",
1351         .parent         = &sys_ck,
1352         .init           = &omap2_init_clk_clkdm,
1353         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1354         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1355         .flags          = CLOCK_IN_OMAP3430ES1,
1356         .clkdm_name     = "d2d_clkdm",
1357         .recalc         = &followparent_recalc,
1358 };
1359
1360 static const struct clksel omap343x_gpt_clksel[] = {
1361         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1362         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1363         { .parent = NULL}
1364 };
1365
1366 static struct clk gpt10_fck = {
1367         .name           = "gpt10_fck",
1368         .parent         = &sys_ck,
1369         .init           = &omap2_init_clksel_parent,
1370         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1372         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1373         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1374         .clksel         = omap343x_gpt_clksel,
1375         .flags          = CLOCK_IN_OMAP343X,
1376         .clkdm_name     = "core_l4_clkdm",
1377         .recalc         = &omap2_clksel_recalc,
1378 };
1379
1380 static struct clk gpt11_fck = {
1381         .name           = "gpt11_fck",
1382         .parent         = &sys_ck,
1383         .init           = &omap2_init_clksel_parent,
1384         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1385         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1386         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1387         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1388         .clksel         = omap343x_gpt_clksel,
1389         .flags          = CLOCK_IN_OMAP343X,
1390         .clkdm_name     = "core_l4_clkdm",
1391         .recalc         = &omap2_clksel_recalc,
1392 };
1393
1394 static struct clk cpefuse_fck = {
1395         .name           = "cpefuse_fck",
1396         .parent         = &sys_ck,
1397         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1398         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1399         .flags          = CLOCK_IN_OMAP3430ES2,
1400         .recalc         = &followparent_recalc,
1401 };
1402
1403 static struct clk ts_fck = {
1404         .name           = "ts_fck",
1405         .parent         = &omap_32k_fck,
1406         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1407         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1408         .flags          = CLOCK_IN_OMAP3430ES2,
1409         .recalc         = &followparent_recalc,
1410 };
1411
1412 static struct clk usbtll_fck = {
1413         .name           = "usbtll_fck",
1414         .parent         = &omap_120m_fck,
1415         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1416         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1417         .flags          = CLOCK_IN_OMAP3430ES2,
1418         .recalc         = &followparent_recalc,
1419 };
1420
1421 /* CORE 96M FCLK-derived clocks */
1422
1423 static struct clk core_96m_fck = {
1424         .name           = "core_96m_fck",
1425         .parent         = &omap_96m_fck,
1426         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1427                                 PARENT_CONTROLS_CLOCK,
1428         .clkdm_name     = "core_l4_clkdm",
1429         .recalc         = &followparent_recalc,
1430 };
1431
1432 static struct clk mmchs3_fck = {
1433         .name           = "mmchs_fck",
1434         .id             = 3,
1435         .parent         = &core_96m_fck,
1436         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1438         .flags          = CLOCK_IN_OMAP3430ES2,
1439         .clkdm_name     = "core_l4_clkdm",
1440         .recalc         = &followparent_recalc,
1441 };
1442
1443 static struct clk mmchs2_fck = {
1444         .name           = "mmchs_fck",
1445         .id             = 2,
1446         .parent         = &core_96m_fck,
1447         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1449         .flags          = CLOCK_IN_OMAP343X,
1450         .clkdm_name     = "core_l4_clkdm",
1451         .recalc         = &followparent_recalc,
1452 };
1453
1454 static struct clk mspro_fck = {
1455         .name           = "mspro_fck",
1456         .parent         = &core_96m_fck,
1457         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1458         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1459         .flags          = CLOCK_IN_OMAP343X,
1460         .clkdm_name     = "core_l4_clkdm",
1461         .recalc         = &followparent_recalc,
1462 };
1463
1464 static struct clk mmchs1_fck = {
1465         .name           = "mmchs_fck",
1466         .id             = 1,
1467         .parent         = &core_96m_fck,
1468         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1469         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1470         .flags          = CLOCK_IN_OMAP343X,
1471         .clkdm_name     = "core_l4_clkdm",
1472         .recalc         = &followparent_recalc,
1473 };
1474
1475 static struct clk i2c3_fck = {
1476         .name           = "i2c_fck",
1477         .id             = 3,
1478         .parent         = &core_96m_fck,
1479         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1480         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1481         .flags          = CLOCK_IN_OMAP343X,
1482         .clkdm_name     = "core_l4_clkdm",
1483         .recalc         = &followparent_recalc,
1484 };
1485
1486 static struct clk i2c2_fck = {
1487         .name           = "i2c_fck",
1488         .id             = 2,
1489         .parent         = &core_96m_fck,
1490         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1491         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1492         .flags          = CLOCK_IN_OMAP343X,
1493         .clkdm_name     = "core_l4_clkdm",
1494         .recalc         = &followparent_recalc,
1495 };
1496
1497 static struct clk i2c1_fck = {
1498         .name           = "i2c_fck",
1499         .id             = 1,
1500         .parent         = &core_96m_fck,
1501         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1502         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1503         .flags          = CLOCK_IN_OMAP343X,
1504         .clkdm_name     = "core_l4_clkdm",
1505         .recalc         = &followparent_recalc,
1506 };
1507
1508 /*
1509  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1510  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1511  */
1512 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1513         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1514         { .div = 0 }
1515 };
1516
1517 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1518         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1519         { .div = 0 }
1520 };
1521
1522 static const struct clksel mcbsp_15_clksel[] = {
1523         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1524         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1525         { .parent = NULL }
1526 };
1527
1528 static struct clk mcbsp5_fck = {
1529         .name           = "mcbsp_fck",
1530         .id             = 5,
1531         .init           = &omap2_init_clksel_parent,
1532         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1533         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1534         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1535         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1536         .clksel         = mcbsp_15_clksel,
1537         .flags          = CLOCK_IN_OMAP343X,
1538         .clkdm_name     = "core_l4_clkdm",
1539         .recalc         = &omap2_clksel_recalc,
1540 };
1541
1542 static struct clk mcbsp1_fck = {
1543         .name           = "mcbsp_fck",
1544         .id             = 1,
1545         .init           = &omap2_init_clksel_parent,
1546         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1547         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1548         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1549         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1550         .clksel         = mcbsp_15_clksel,
1551         .flags          = CLOCK_IN_OMAP343X,
1552         .clkdm_name     = "core_l4_clkdm",
1553         .recalc         = &omap2_clksel_recalc,
1554 };
1555
1556 /* CORE_48M_FCK-derived clocks */
1557
1558 static struct clk core_48m_fck = {
1559         .name           = "core_48m_fck",
1560         .parent         = &omap_48m_fck,
1561         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1562                                 PARENT_CONTROLS_CLOCK,
1563         .clkdm_name     = "core_l4_clkdm",
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk mcspi4_fck = {
1568         .name           = "mcspi_fck",
1569         .id             = 4,
1570         .parent         = &core_48m_fck,
1571         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1573         .flags          = CLOCK_IN_OMAP343X,
1574         .recalc         = &followparent_recalc,
1575 };
1576
1577 static struct clk mcspi3_fck = {
1578         .name           = "mcspi_fck",
1579         .id             = 3,
1580         .parent         = &core_48m_fck,
1581         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1582         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1583         .flags          = CLOCK_IN_OMAP343X,
1584         .recalc         = &followparent_recalc,
1585 };
1586
1587 static struct clk mcspi2_fck = {
1588         .name           = "mcspi_fck",
1589         .id             = 2,
1590         .parent         = &core_48m_fck,
1591         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1593         .flags          = CLOCK_IN_OMAP343X,
1594         .recalc         = &followparent_recalc,
1595 };
1596
1597 static struct clk mcspi1_fck = {
1598         .name           = "mcspi_fck",
1599         .id             = 1,
1600         .parent         = &core_48m_fck,
1601         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1603         .flags          = CLOCK_IN_OMAP343X,
1604         .recalc         = &followparent_recalc,
1605 };
1606
1607 static struct clk uart2_fck = {
1608         .name           = "uart2_fck",
1609         .parent         = &core_48m_fck,
1610         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1611         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1612         .flags          = CLOCK_IN_OMAP343X,
1613         .recalc         = &followparent_recalc,
1614 };
1615
1616 static struct clk uart1_fck = {
1617         .name           = "uart1_fck",
1618         .parent         = &core_48m_fck,
1619         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1620         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1621         .flags          = CLOCK_IN_OMAP343X,
1622         .recalc         = &followparent_recalc,
1623 };
1624
1625 static struct clk fshostusb_fck = {
1626         .name           = "fshostusb_fck",
1627         .parent         = &core_48m_fck,
1628         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1629         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1630         .flags          = CLOCK_IN_OMAP3430ES1,
1631         .recalc         = &followparent_recalc,
1632 };
1633
1634 /* CORE_12M_FCK based clocks */
1635
1636 static struct clk core_12m_fck = {
1637         .name           = "core_12m_fck",
1638         .parent         = &omap_12m_fck,
1639         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1640                                 PARENT_CONTROLS_CLOCK,
1641         .clkdm_name     = "core_l4_clkdm",
1642         .recalc         = &followparent_recalc,
1643 };
1644
1645 static struct clk hdq_fck = {
1646         .name           = "hdq_fck",
1647         .parent         = &core_12m_fck,
1648         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1649         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1650         .flags          = CLOCK_IN_OMAP343X,
1651         .recalc         = &followparent_recalc,
1652 };
1653
1654 /* DPLL3-derived clock */
1655
1656 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1657         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1658         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1659         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1660         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1661         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1662         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1663         { .div = 0 }
1664 };
1665
1666 static const struct clksel ssi_ssr_clksel[] = {
1667         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1668         { .parent = NULL }
1669 };
1670
1671 static struct clk ssi_ssr_fck = {
1672         .name           = "ssi_ssr_fck",
1673         .init           = &omap2_init_clksel_parent,
1674         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1675         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1676         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1677         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1678         .clksel         = ssi_ssr_clksel,
1679         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1680         .clkdm_name     = "core_l4_clkdm",
1681         .recalc         = &omap2_clksel_recalc,
1682 };
1683
1684 static struct clk ssi_sst_fck = {
1685         .name           = "ssi_sst_fck",
1686         .parent         = &ssi_ssr_fck,
1687         .fixed_div      = 2,
1688         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1689         .recalc         = &omap2_fixed_divisor_recalc,
1690 };
1691
1692
1693
1694 /* CORE_L3_ICK based clocks */
1695
1696 /*
1697  * XXX must add clk_enable/clk_disable for these if standard code won't
1698  * handle it
1699  */
1700 static struct clk core_l3_ick = {
1701         .name           = "core_l3_ick",
1702         .parent         = &l3_ick,
1703         .init           = &omap2_init_clk_clkdm,
1704         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1705                                 PARENT_CONTROLS_CLOCK,
1706         .clkdm_name     = "core_l3_clkdm",
1707         .recalc         = &followparent_recalc,
1708 };
1709
1710 static struct clk hsotgusb_ick = {
1711         .name           = "hsotgusb_ick",
1712         .parent         = &core_l3_ick,
1713         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1714         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1715         .flags          = CLOCK_IN_OMAP343X,
1716         .clkdm_name     = "core_l3_clkdm",
1717         .recalc         = &followparent_recalc,
1718 };
1719
1720 static struct clk sdrc_ick = {
1721         .name           = "sdrc_ick",
1722         .parent         = &core_l3_ick,
1723         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1724         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1725         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1726         .clkdm_name     = "core_l3_clkdm",
1727         .recalc         = &followparent_recalc,
1728 };
1729
1730 static struct clk gpmc_fck = {
1731         .name           = "gpmc_fck",
1732         .parent         = &core_l3_ick,
1733         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1734                                 ENABLE_ON_INIT,
1735         .clkdm_name     = "core_l3_clkdm",
1736         .recalc         = &followparent_recalc,
1737 };
1738
1739 /* SECURITY_L3_ICK based clocks */
1740
1741 static struct clk security_l3_ick = {
1742         .name           = "security_l3_ick",
1743         .parent         = &l3_ick,
1744         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1745                                 PARENT_CONTROLS_CLOCK,
1746         .recalc         = &followparent_recalc,
1747 };
1748
1749 static struct clk pka_ick = {
1750         .name           = "pka_ick",
1751         .parent         = &security_l3_ick,
1752         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1753         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1754         .flags          = CLOCK_IN_OMAP343X,
1755         .recalc         = &followparent_recalc,
1756 };
1757
1758 /* CORE_L4_ICK based clocks */
1759
1760 static struct clk core_l4_ick = {
1761         .name           = "core_l4_ick",
1762         .parent         = &l4_ick,
1763         .init           = &omap2_init_clk_clkdm,
1764         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1765                                 PARENT_CONTROLS_CLOCK,
1766         .clkdm_name     = "core_l4_clkdm",
1767         .recalc         = &followparent_recalc,
1768 };
1769
1770 static struct clk usbtll_ick = {
1771         .name           = "usbtll_ick",
1772         .parent         = &core_l4_ick,
1773         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1774         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1775         .flags          = CLOCK_IN_OMAP3430ES2,
1776         .clkdm_name     = "core_l4_clkdm",
1777         .recalc         = &followparent_recalc,
1778 };
1779
1780 static struct clk mmchs3_ick = {
1781         .name           = "mmchs_ick",
1782         .id             = 3,
1783         .parent         = &core_l4_ick,
1784         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1785         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1786         .flags          = CLOCK_IN_OMAP3430ES2,
1787         .clkdm_name     = "core_l4_clkdm",
1788         .recalc         = &followparent_recalc,
1789 };
1790
1791 /* Intersystem Communication Registers - chassis mode only */
1792 static struct clk icr_ick = {
1793         .name           = "icr_ick",
1794         .parent         = &core_l4_ick,
1795         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1796         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1797         .flags          = CLOCK_IN_OMAP343X,
1798         .clkdm_name     = "core_l4_clkdm",
1799         .recalc         = &followparent_recalc,
1800 };
1801
1802 static struct clk aes2_ick = {
1803         .name           = "aes2_ick",
1804         .parent         = &core_l4_ick,
1805         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1806         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1807         .flags          = CLOCK_IN_OMAP343X,
1808         .clkdm_name     = "core_l4_clkdm",
1809         .recalc         = &followparent_recalc,
1810 };
1811
1812 static struct clk sha12_ick = {
1813         .name           = "sha12_ick",
1814         .parent         = &core_l4_ick,
1815         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1816         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1817         .flags          = CLOCK_IN_OMAP343X,
1818         .clkdm_name     = "core_l4_clkdm",
1819         .recalc         = &followparent_recalc,
1820 };
1821
1822 static struct clk des2_ick = {
1823         .name           = "des2_ick",
1824         .parent         = &core_l4_ick,
1825         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1826         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1827         .flags          = CLOCK_IN_OMAP343X,
1828         .clkdm_name     = "core_l4_clkdm",
1829         .recalc         = &followparent_recalc,
1830 };
1831
1832 static struct clk mmchs2_ick = {
1833         .name           = "mmchs_ick",
1834         .id             = 2,
1835         .parent         = &core_l4_ick,
1836         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1838         .flags          = CLOCK_IN_OMAP343X,
1839         .clkdm_name     = "core_l4_clkdm",
1840         .recalc         = &followparent_recalc,
1841 };
1842
1843 static struct clk mmchs1_ick = {
1844         .name           = "mmchs_ick",
1845         .id             = 1,
1846         .parent         = &core_l4_ick,
1847         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1849         .flags          = CLOCK_IN_OMAP343X,
1850         .clkdm_name     = "core_l4_clkdm",
1851         .recalc         = &followparent_recalc,
1852 };
1853
1854 static struct clk mspro_ick = {
1855         .name           = "mspro_ick",
1856         .parent         = &core_l4_ick,
1857         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1858         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1859         .flags          = CLOCK_IN_OMAP343X,
1860         .clkdm_name     = "core_l4_clkdm",
1861         .recalc         = &followparent_recalc,
1862 };
1863
1864 static struct clk hdq_ick = {
1865         .name           = "hdq_ick",
1866         .parent         = &core_l4_ick,
1867         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1868         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1869         .flags          = CLOCK_IN_OMAP343X,
1870         .clkdm_name     = "core_l4_clkdm",
1871         .recalc         = &followparent_recalc,
1872 };
1873
1874 static struct clk mcspi4_ick = {
1875         .name           = "mcspi_ick",
1876         .id             = 4,
1877         .parent         = &core_l4_ick,
1878         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1879         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1880         .flags          = CLOCK_IN_OMAP343X,
1881         .clkdm_name     = "core_l4_clkdm",
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk mcspi3_ick = {
1886         .name           = "mcspi_ick",
1887         .id             = 3,
1888         .parent         = &core_l4_ick,
1889         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1891         .flags          = CLOCK_IN_OMAP343X,
1892         .clkdm_name     = "core_l4_clkdm",
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mcspi2_ick = {
1897         .name           = "mcspi_ick",
1898         .id             = 2,
1899         .parent         = &core_l4_ick,
1900         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1902         .flags          = CLOCK_IN_OMAP343X,
1903         .clkdm_name     = "core_l4_clkdm",
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mcspi1_ick = {
1908         .name           = "mcspi_ick",
1909         .id             = 1,
1910         .parent         = &core_l4_ick,
1911         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1913         .flags          = CLOCK_IN_OMAP343X,
1914         .clkdm_name     = "core_l4_clkdm",
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk i2c3_ick = {
1919         .name           = "i2c_ick",
1920         .id             = 3,
1921         .parent         = &core_l4_ick,
1922         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1924         .flags          = CLOCK_IN_OMAP343X,
1925         .clkdm_name     = "core_l4_clkdm",
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk i2c2_ick = {
1930         .name           = "i2c_ick",
1931         .id             = 2,
1932         .parent         = &core_l4_ick,
1933         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1934         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1935         .flags          = CLOCK_IN_OMAP343X,
1936         .clkdm_name     = "core_l4_clkdm",
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 static struct clk i2c1_ick = {
1941         .name           = "i2c_ick",
1942         .id             = 1,
1943         .parent         = &core_l4_ick,
1944         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1945         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1946         .flags          = CLOCK_IN_OMAP343X,
1947         .clkdm_name     = "core_l4_clkdm",
1948         .recalc         = &followparent_recalc,
1949 };
1950
1951 static struct clk uart2_ick = {
1952         .name           = "uart2_ick",
1953         .parent         = &core_l4_ick,
1954         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1955         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1956         .flags          = CLOCK_IN_OMAP343X,
1957         .clkdm_name     = "core_l4_clkdm",
1958         .recalc         = &followparent_recalc,
1959 };
1960
1961 static struct clk uart1_ick = {
1962         .name           = "uart1_ick",
1963         .parent         = &core_l4_ick,
1964         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1966         .flags          = CLOCK_IN_OMAP343X,
1967         .clkdm_name     = "core_l4_clkdm",
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk gpt11_ick = {
1972         .name           = "gpt11_ick",
1973         .parent         = &core_l4_ick,
1974         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1975         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1976         .flags          = CLOCK_IN_OMAP343X,
1977         .clkdm_name     = "core_l4_clkdm",
1978         .recalc         = &followparent_recalc,
1979 };
1980
1981 static struct clk gpt10_ick = {
1982         .name           = "gpt10_ick",
1983         .parent         = &core_l4_ick,
1984         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1985         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1986         .flags          = CLOCK_IN_OMAP343X,
1987         .clkdm_name     = "core_l4_clkdm",
1988         .recalc         = &followparent_recalc,
1989 };
1990
1991 static struct clk mcbsp5_ick = {
1992         .name           = "mcbsp_ick",
1993         .id             = 5,
1994         .parent         = &core_l4_ick,
1995         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1996         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1997         .flags          = CLOCK_IN_OMAP343X,
1998         .clkdm_name     = "core_l4_clkdm",
1999         .recalc         = &followparent_recalc,
2000 };
2001
2002 static struct clk mcbsp1_ick = {
2003         .name           = "mcbsp_ick",
2004         .id             = 1,
2005         .parent         = &core_l4_ick,
2006         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2008         .flags          = CLOCK_IN_OMAP343X,
2009         .clkdm_name     = "core_l4_clkdm",
2010         .recalc         = &followparent_recalc,
2011 };
2012
2013 static struct clk fac_ick = {
2014         .name           = "fac_ick",
2015         .parent         = &core_l4_ick,
2016         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2017         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2018         .flags          = CLOCK_IN_OMAP3430ES1,
2019         .clkdm_name     = "core_l4_clkdm",
2020         .recalc         = &followparent_recalc,
2021 };
2022
2023 static struct clk mailboxes_ick = {
2024         .name           = "mailboxes_ick",
2025         .parent         = &core_l4_ick,
2026         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2028         .flags          = CLOCK_IN_OMAP343X,
2029         .clkdm_name     = "core_l4_clkdm",
2030         .recalc         = &followparent_recalc,
2031 };
2032
2033 static struct clk omapctrl_ick = {
2034         .name           = "omapctrl_ick",
2035         .parent         = &core_l4_ick,
2036         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2037         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2038         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2039         .recalc         = &followparent_recalc,
2040 };
2041
2042 /* SSI_L4_ICK based clocks */
2043
2044 static struct clk ssi_l4_ick = {
2045         .name           = "ssi_l4_ick",
2046         .parent         = &l4_ick,
2047         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2048                                 PARENT_CONTROLS_CLOCK,
2049         .clkdm_name     = "core_l4_clkdm",
2050         .recalc         = &followparent_recalc,
2051 };
2052
2053 static struct clk ssi_ick = {
2054         .name           = "ssi_ick",
2055         .parent         = &ssi_l4_ick,
2056         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2057         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2058         .flags          = CLOCK_IN_OMAP343X,
2059         .clkdm_name     = "core_l4_clkdm",
2060         .recalc         = &followparent_recalc,
2061 };
2062
2063 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2064  * but l4_ick makes more sense to me */
2065
2066 static const struct clksel usb_l4_clksel[] = {
2067         { .parent = &l4_ick, .rates = div2_rates },
2068         { .parent = NULL },
2069 };
2070
2071 static struct clk usb_l4_ick = {
2072         .name           = "usb_l4_ick",
2073         .parent         = &l4_ick,
2074         .init           = &omap2_init_clksel_parent,
2075         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2076         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2077         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2078         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2079         .clksel         = usb_l4_clksel,
2080         .flags          = CLOCK_IN_OMAP3430ES1,
2081         .recalc         = &omap2_clksel_recalc,
2082 };
2083
2084 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2085
2086 /* SECURITY_L4_ICK2 based clocks */
2087
2088 static struct clk security_l4_ick2 = {
2089         .name           = "security_l4_ick2",
2090         .parent         = &l4_ick,
2091         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2092                                 PARENT_CONTROLS_CLOCK,
2093         .recalc         = &followparent_recalc,
2094 };
2095
2096 static struct clk aes1_ick = {
2097         .name           = "aes1_ick",
2098         .parent         = &security_l4_ick2,
2099         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2100         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2101         .flags          = CLOCK_IN_OMAP343X,
2102         .recalc         = &followparent_recalc,
2103 };
2104
2105 static struct clk rng_ick = {
2106         .name           = "rng_ick",
2107         .parent         = &security_l4_ick2,
2108         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2109         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2110         .flags          = CLOCK_IN_OMAP343X,
2111         .recalc         = &followparent_recalc,
2112 };
2113
2114 static struct clk sha11_ick = {
2115         .name           = "sha11_ick",
2116         .parent         = &security_l4_ick2,
2117         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2118         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2119         .flags          = CLOCK_IN_OMAP343X,
2120         .recalc         = &followparent_recalc,
2121 };
2122
2123 static struct clk des1_ick = {
2124         .name           = "des1_ick",
2125         .parent         = &security_l4_ick2,
2126         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2127         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2128         .flags          = CLOCK_IN_OMAP343X,
2129         .recalc         = &followparent_recalc,
2130 };
2131
2132 /* DSS */
2133 static const struct clksel dss1_alwon_fck_clksel[] = {
2134         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2135         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2136         { .parent = NULL }
2137 };
2138
2139 static struct clk dss1_alwon_fck = {
2140         .name           = "dss1_alwon_fck",
2141         .parent         = &dpll4_m4x2_ck,
2142         .init           = &omap2_init_clksel_parent,
2143         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2144         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2145         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2146         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2147         .clksel         = dss1_alwon_fck_clksel,
2148         .flags          = CLOCK_IN_OMAP343X,
2149         .clkdm_name     = "dss_clkdm",
2150         .recalc         = &omap2_clksel_recalc,
2151 };
2152
2153 static struct clk dss_tv_fck = {
2154         .name           = "dss_tv_fck",
2155         .parent         = &omap_54m_fck,
2156         .init           = &omap2_init_clk_clkdm,
2157         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2158         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2159         .flags          = CLOCK_IN_OMAP343X,
2160         .clkdm_name     = "dss_clkdm",
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 static struct clk dss_96m_fck = {
2165         .name           = "dss_96m_fck",
2166         .parent         = &omap_96m_fck,
2167         .init           = &omap2_init_clk_clkdm,
2168         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2169         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2170         .flags          = CLOCK_IN_OMAP343X,
2171         .clkdm_name     = "dss_clkdm",
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk dss2_alwon_fck = {
2176         .name           = "dss2_alwon_fck",
2177         .parent         = &sys_ck,
2178         .init           = &omap2_init_clk_clkdm,
2179         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2180         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2181         .flags          = CLOCK_IN_OMAP343X,
2182         .clkdm_name     = "dss_clkdm",
2183         .recalc         = &followparent_recalc,
2184 };
2185
2186 static struct clk dss_ick = {
2187         /* Handles both L3 and L4 clocks */
2188         .name           = "dss_ick",
2189         .parent         = &l4_ick,
2190         .init           = &omap2_init_clk_clkdm,
2191         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2192         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2193         .flags          = CLOCK_IN_OMAP343X,
2194         .clkdm_name     = "dss_clkdm",
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 /* CAM */
2199
2200 static const struct clksel cam_mclk_clksel[] = {
2201         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2202         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2203         { .parent = NULL }
2204 };
2205
2206 static struct clk cam_mclk = {
2207         .name           = "cam_mclk",
2208         .parent         = &dpll4_m5x2_ck,
2209         .init           = &omap2_init_clksel_parent,
2210         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2211         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2212         .clksel         = cam_mclk_clksel,
2213         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2214         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2215         .flags          = CLOCK_IN_OMAP343X,
2216         .clkdm_name     = "cam_clkdm",
2217         .recalc         = &omap2_clksel_recalc,
2218 };
2219
2220 static struct clk cam_ick = {
2221         /* Handles both L3 and L4 clocks */
2222         .name           = "cam_ick",
2223         .parent         = &l4_ick,
2224         .init           = &omap2_init_clk_clkdm,
2225         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2226         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2227         .flags          = CLOCK_IN_OMAP343X,
2228         .clkdm_name     = "cam_clkdm",
2229         .recalc         = &followparent_recalc,
2230 };
2231
2232 /* USBHOST - 3430ES2 only */
2233
2234 static struct clk usbhost_120m_fck = {
2235         .name           = "usbhost_120m_fck",
2236         .parent         = &omap_120m_fck,
2237         .init           = &omap2_init_clk_clkdm,
2238         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2239         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2240         .flags          = CLOCK_IN_OMAP3430ES2,
2241         .clkdm_name     = "usbhost_clkdm",
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk usbhost_48m_fck = {
2246         .name           = "usbhost_48m_fck",
2247         .parent         = &omap_48m_fck,
2248         .init           = &omap2_init_clk_clkdm,
2249         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2250         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2251         .flags          = CLOCK_IN_OMAP3430ES2,
2252         .clkdm_name     = "usbhost_clkdm",
2253         .recalc         = &followparent_recalc,
2254 };
2255
2256 static struct clk usbhost_ick = {
2257         /* Handles both L3 and L4 clocks */
2258         .name           = "usbhost_ick",
2259         .parent         = &l4_ick,
2260         .init           = &omap2_init_clk_clkdm,
2261         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2262         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2263         .flags          = CLOCK_IN_OMAP3430ES2,
2264         .clkdm_name     = "usbhost_clkdm",
2265         .recalc         = &followparent_recalc,
2266 };
2267
2268 /* WKUP */
2269
2270 static const struct clksel_rate usim_96m_rates[] = {
2271         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2272         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2273         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2274         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2275         { .div = 0 },
2276 };
2277
2278 static const struct clksel_rate usim_120m_rates[] = {
2279         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2280         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2281         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2282         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2283         { .div = 0 },
2284 };
2285
2286 static const struct clksel usim_clksel[] = {
2287         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2288         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2289         { .parent = &sys_ck,            .rates = div2_rates },
2290         { .parent = NULL },
2291 };
2292
2293 /* 3430ES2 only */
2294 static struct clk usim_fck = {
2295         .name           = "usim_fck",
2296         .init           = &omap2_init_clksel_parent,
2297         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2298         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2299         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2300         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2301         .clksel         = usim_clksel,
2302         .flags          = CLOCK_IN_OMAP3430ES2,
2303         .recalc         = &omap2_clksel_recalc,
2304 };
2305
2306 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2307 static struct clk gpt1_fck = {
2308         .name           = "gpt1_fck",
2309         .init           = &omap2_init_clksel_parent,
2310         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2311         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2312         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2313         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2314         .clksel         = omap343x_gpt_clksel,
2315         .flags          = CLOCK_IN_OMAP343X,
2316         .clkdm_name     = "wkup_clkdm",
2317         .recalc         = &omap2_clksel_recalc,
2318 };
2319
2320 static struct clk wkup_32k_fck = {
2321         .name           = "wkup_32k_fck",
2322         .init           = &omap2_init_clk_clkdm,
2323         .parent         = &omap_32k_fck,
2324         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2325         .clkdm_name     = "wkup_clkdm",
2326         .recalc         = &followparent_recalc,
2327 };
2328
2329 static struct clk gpio1_fck = {
2330         .name           = "gpio1_fck",
2331         .parent         = &wkup_32k_fck,
2332         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2333         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2334         .flags          = CLOCK_IN_OMAP343X,
2335         .clkdm_name     = "wkup_clkdm",
2336         .recalc         = &followparent_recalc,
2337 };
2338
2339 static struct clk wdt2_fck = {
2340         .name           = "wdt2_fck",
2341         .parent         = &wkup_32k_fck,
2342         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2343         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2344         .flags          = CLOCK_IN_OMAP343X,
2345         .clkdm_name     = "wkup_clkdm",
2346         .recalc         = &followparent_recalc,
2347 };
2348
2349 static struct clk wkup_l4_ick = {
2350         .name           = "wkup_l4_ick",
2351         .parent         = &sys_ck,
2352         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2353         .clkdm_name     = "wkup_clkdm",
2354         .recalc         = &followparent_recalc,
2355 };
2356
2357 /* 3430ES2 only */
2358 /* Never specifically named in the TRM, so we have to infer a likely name */
2359 static struct clk usim_ick = {
2360         .name           = "usim_ick",
2361         .parent         = &wkup_l4_ick,
2362         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2363         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2364         .flags          = CLOCK_IN_OMAP3430ES2,
2365         .clkdm_name     = "wkup_clkdm",
2366         .recalc         = &followparent_recalc,
2367 };
2368
2369 static struct clk wdt2_ick = {
2370         .name           = "wdt2_ick",
2371         .parent         = &wkup_l4_ick,
2372         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2373         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2374         .flags          = CLOCK_IN_OMAP343X,
2375         .clkdm_name     = "wkup_clkdm",
2376         .recalc         = &followparent_recalc,
2377 };
2378
2379 static struct clk wdt1_ick = {
2380         .name           = "wdt1_ick",
2381         .parent         = &wkup_l4_ick,
2382         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2383         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2384         .flags          = CLOCK_IN_OMAP343X,
2385         .clkdm_name     = "wkup_clkdm",
2386         .recalc         = &followparent_recalc,
2387 };
2388
2389 static struct clk gpio1_ick = {
2390         .name           = "gpio1_ick",
2391         .parent         = &wkup_l4_ick,
2392         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2393         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2394         .flags          = CLOCK_IN_OMAP343X,
2395         .clkdm_name     = "wkup_clkdm",
2396         .recalc         = &followparent_recalc,
2397 };
2398
2399 static struct clk omap_32ksync_ick = {
2400         .name           = "omap_32ksync_ick",
2401         .parent         = &wkup_l4_ick,
2402         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2403         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2404         .flags          = CLOCK_IN_OMAP343X,
2405         .clkdm_name     = "wkup_clkdm",
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 /* XXX This clock no longer exists in 3430 TRM rev F */
2410 static struct clk gpt12_ick = {
2411         .name           = "gpt12_ick",
2412         .parent         = &wkup_l4_ick,
2413         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2414         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2415         .flags          = CLOCK_IN_OMAP343X,
2416         .clkdm_name     = "wkup_clkdm",
2417         .recalc         = &followparent_recalc,
2418 };
2419
2420 static struct clk gpt1_ick = {
2421         .name           = "gpt1_ick",
2422         .parent         = &wkup_l4_ick,
2423         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2424         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2425         .flags          = CLOCK_IN_OMAP343X,
2426         .clkdm_name     = "wkup_clkdm",
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430
2431
2432 /* PER clock domain */
2433
2434 static struct clk per_96m_fck = {
2435         .name           = "per_96m_fck",
2436         .parent         = &omap_96m_alwon_fck,
2437         .init           = &omap2_init_clk_clkdm,
2438         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2439                                 PARENT_CONTROLS_CLOCK,
2440         .clkdm_name     = "per_clkdm",
2441         .recalc         = &followparent_recalc,
2442 };
2443
2444 static struct clk per_48m_fck = {
2445         .name           = "per_48m_fck",
2446         .parent         = &omap_48m_fck,
2447         .init           = &omap2_init_clk_clkdm,
2448         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2449                                 PARENT_CONTROLS_CLOCK,
2450         .clkdm_name     = "per_clkdm",
2451         .recalc         = &followparent_recalc,
2452 };
2453
2454 static struct clk uart3_fck = {
2455         .name           = "uart3_fck",
2456         .parent         = &per_48m_fck,
2457         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2458         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2459         .flags          = CLOCK_IN_OMAP343X,
2460         .clkdm_name     = "per_clkdm",
2461         .recalc         = &followparent_recalc,
2462 };
2463
2464 static struct clk gpt2_fck = {
2465         .name           = "gpt2_fck",
2466         .init           = &omap2_init_clksel_parent,
2467         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2469         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2470         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2471         .clksel         = omap343x_gpt_clksel,
2472         .flags          = CLOCK_IN_OMAP343X,
2473         .clkdm_name     = "per_clkdm",
2474         .recalc         = &omap2_clksel_recalc,
2475 };
2476
2477 static struct clk gpt3_fck = {
2478         .name           = "gpt3_fck",
2479         .init           = &omap2_init_clksel_parent,
2480         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2481         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2482         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2483         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2484         .clksel         = omap343x_gpt_clksel,
2485         .flags          = CLOCK_IN_OMAP343X,
2486         .clkdm_name     = "per_clkdm",
2487         .recalc         = &omap2_clksel_recalc,
2488 };
2489
2490 static struct clk gpt4_fck = {
2491         .name           = "gpt4_fck",
2492         .init           = &omap2_init_clksel_parent,
2493         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2494         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2495         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2496         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2497         .clksel         = omap343x_gpt_clksel,
2498         .flags          = CLOCK_IN_OMAP343X,
2499         .clkdm_name     = "per_clkdm",
2500         .recalc         = &omap2_clksel_recalc,
2501 };
2502
2503 static struct clk gpt5_fck = {
2504         .name           = "gpt5_fck",
2505         .init           = &omap2_init_clksel_parent,
2506         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2507         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2508         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2509         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2510         .clksel         = omap343x_gpt_clksel,
2511         .flags          = CLOCK_IN_OMAP343X,
2512         .clkdm_name     = "per_clkdm",
2513         .recalc         = &omap2_clksel_recalc,
2514 };
2515
2516 static struct clk gpt6_fck = {
2517         .name           = "gpt6_fck",
2518         .init           = &omap2_init_clksel_parent,
2519         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2520         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2521         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2522         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2523         .clksel         = omap343x_gpt_clksel,
2524         .flags          = CLOCK_IN_OMAP343X,
2525         .clkdm_name     = "per_clkdm",
2526         .recalc         = &omap2_clksel_recalc,
2527 };
2528
2529 static struct clk gpt7_fck = {
2530         .name           = "gpt7_fck",
2531         .init           = &omap2_init_clksel_parent,
2532         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2533         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2534         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2535         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2536         .clksel         = omap343x_gpt_clksel,
2537         .flags          = CLOCK_IN_OMAP343X,
2538         .clkdm_name     = "per_clkdm",
2539         .recalc         = &omap2_clksel_recalc,
2540 };
2541
2542 static struct clk gpt8_fck = {
2543         .name           = "gpt8_fck",
2544         .init           = &omap2_init_clksel_parent,
2545         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2546         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2547         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2548         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2549         .clksel         = omap343x_gpt_clksel,
2550         .flags          = CLOCK_IN_OMAP343X,
2551         .clkdm_name     = "per_clkdm",
2552         .recalc         = &omap2_clksel_recalc,
2553 };
2554
2555 static struct clk gpt9_fck = {
2556         .name           = "gpt9_fck",
2557         .init           = &omap2_init_clksel_parent,
2558         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2559         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2560         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2561         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2562         .clksel         = omap343x_gpt_clksel,
2563         .flags          = CLOCK_IN_OMAP343X,
2564         .clkdm_name     = "per_clkdm",
2565         .recalc         = &omap2_clksel_recalc,
2566 };
2567
2568 static struct clk per_32k_alwon_fck = {
2569         .name           = "per_32k_alwon_fck",
2570         .parent         = &omap_32k_fck,
2571         .clkdm_name     = "per_clkdm",
2572         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2573         .recalc         = &followparent_recalc,
2574 };
2575
2576 static struct clk gpio6_fck = {
2577         .name           = "gpio6_fck",
2578         .parent         = &per_32k_alwon_fck,
2579         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2580         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2581         .flags          = CLOCK_IN_OMAP343X,
2582         .clkdm_name     = "per_clkdm",
2583         .recalc         = &followparent_recalc,
2584 };
2585
2586 static struct clk gpio5_fck = {
2587         .name           = "gpio5_fck",
2588         .parent         = &per_32k_alwon_fck,
2589         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2590         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2591         .flags          = CLOCK_IN_OMAP343X,
2592         .clkdm_name     = "per_clkdm",
2593         .recalc         = &followparent_recalc,
2594 };
2595
2596 static struct clk gpio4_fck = {
2597         .name           = "gpio4_fck",
2598         .parent         = &per_32k_alwon_fck,
2599         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2600         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2601         .flags          = CLOCK_IN_OMAP343X,
2602         .clkdm_name     = "per_clkdm",
2603         .recalc         = &followparent_recalc,
2604 };
2605
2606 static struct clk gpio3_fck = {
2607         .name           = "gpio3_fck",
2608         .parent         = &per_32k_alwon_fck,
2609         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2610         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2611         .flags          = CLOCK_IN_OMAP343X,
2612         .clkdm_name     = "per_clkdm",
2613         .recalc         = &followparent_recalc,
2614 };
2615
2616 static struct clk gpio2_fck = {
2617         .name           = "gpio2_fck",
2618         .parent         = &per_32k_alwon_fck,
2619         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2620         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2621         .flags          = CLOCK_IN_OMAP343X,
2622         .clkdm_name     = "per_clkdm",
2623         .recalc         = &followparent_recalc,
2624 };
2625
2626 static struct clk wdt3_fck = {
2627         .name           = "wdt3_fck",
2628         .parent         = &per_32k_alwon_fck,
2629         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2630         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2631         .flags          = CLOCK_IN_OMAP343X,
2632         .clkdm_name     = "per_clkdm",
2633         .recalc         = &followparent_recalc,
2634 };
2635
2636 static struct clk per_l4_ick = {
2637         .name           = "per_l4_ick",
2638         .parent         = &l4_ick,
2639         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2640                                 PARENT_CONTROLS_CLOCK,
2641         .clkdm_name     = "per_clkdm",
2642         .recalc         = &followparent_recalc,
2643 };
2644
2645 static struct clk gpio6_ick = {
2646         .name           = "gpio6_ick",
2647         .parent         = &per_l4_ick,
2648         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2649         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2650         .flags          = CLOCK_IN_OMAP343X,
2651         .clkdm_name     = "per_clkdm",
2652         .recalc         = &followparent_recalc,
2653 };
2654
2655 static struct clk gpio5_ick = {
2656         .name           = "gpio5_ick",
2657         .parent         = &per_l4_ick,
2658         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2659         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2660         .flags          = CLOCK_IN_OMAP343X,
2661         .clkdm_name     = "per_clkdm",
2662         .recalc         = &followparent_recalc,
2663 };
2664
2665 static struct clk gpio4_ick = {
2666         .name           = "gpio4_ick",
2667         .parent         = &per_l4_ick,
2668         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2669         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2670         .flags          = CLOCK_IN_OMAP343X,
2671         .clkdm_name     = "per_clkdm",
2672         .recalc         = &followparent_recalc,
2673 };
2674
2675 static struct clk gpio3_ick = {
2676         .name           = "gpio3_ick",
2677         .parent         = &per_l4_ick,
2678         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2679         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2680         .flags          = CLOCK_IN_OMAP343X,
2681         .clkdm_name     = "per_clkdm",
2682         .recalc         = &followparent_recalc,
2683 };
2684
2685 static struct clk gpio2_ick = {
2686         .name           = "gpio2_ick",
2687         .parent         = &per_l4_ick,
2688         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2689         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2690         .flags          = CLOCK_IN_OMAP343X,
2691         .clkdm_name     = "per_clkdm",
2692         .recalc         = &followparent_recalc,
2693 };
2694
2695 static struct clk wdt3_ick = {
2696         .name           = "wdt3_ick",
2697         .parent         = &per_l4_ick,
2698         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2699         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2700         .flags          = CLOCK_IN_OMAP343X,
2701         .clkdm_name     = "per_clkdm",
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk uart3_ick = {
2706         .name           = "uart3_ick",
2707         .parent         = &per_l4_ick,
2708         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2710         .flags          = CLOCK_IN_OMAP343X,
2711         .clkdm_name     = "per_clkdm",
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk gpt9_ick = {
2716         .name           = "gpt9_ick",
2717         .parent         = &per_l4_ick,
2718         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2720         .flags          = CLOCK_IN_OMAP343X,
2721         .clkdm_name     = "per_clkdm",
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk gpt8_ick = {
2726         .name           = "gpt8_ick",
2727         .parent         = &per_l4_ick,
2728         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2730         .flags          = CLOCK_IN_OMAP343X,
2731         .clkdm_name     = "per_clkdm",
2732         .recalc         = &followparent_recalc,
2733 };
2734
2735 static struct clk gpt7_ick = {
2736         .name           = "gpt7_ick",
2737         .parent         = &per_l4_ick,
2738         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2740         .flags          = CLOCK_IN_OMAP343X,
2741         .clkdm_name     = "per_clkdm",
2742         .recalc         = &followparent_recalc,
2743 };
2744
2745 static struct clk gpt6_ick = {
2746         .name           = "gpt6_ick",
2747         .parent         = &per_l4_ick,
2748         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2750         .flags          = CLOCK_IN_OMAP343X,
2751         .clkdm_name     = "per_clkdm",
2752         .recalc         = &followparent_recalc,
2753 };
2754
2755 static struct clk gpt5_ick = {
2756         .name           = "gpt5_ick",
2757         .parent         = &per_l4_ick,
2758         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2759         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2760         .flags          = CLOCK_IN_OMAP343X,
2761         .clkdm_name     = "per_clkdm",
2762         .recalc         = &followparent_recalc,
2763 };
2764
2765 static struct clk gpt4_ick = {
2766         .name           = "gpt4_ick",
2767         .parent         = &per_l4_ick,
2768         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2770         .flags          = CLOCK_IN_OMAP343X,
2771         .clkdm_name     = "per_clkdm",
2772         .recalc         = &followparent_recalc,
2773 };
2774
2775 static struct clk gpt3_ick = {
2776         .name           = "gpt3_ick",
2777         .parent         = &per_l4_ick,
2778         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2780         .flags          = CLOCK_IN_OMAP343X,
2781         .clkdm_name     = "per_clkdm",
2782         .recalc         = &followparent_recalc,
2783 };
2784
2785 static struct clk gpt2_ick = {
2786         .name           = "gpt2_ick",
2787         .parent         = &per_l4_ick,
2788         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2789         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2790         .flags          = CLOCK_IN_OMAP343X,
2791         .clkdm_name     = "per_clkdm",
2792         .recalc         = &followparent_recalc,
2793 };
2794
2795 static struct clk mcbsp2_ick = {
2796         .name           = "mcbsp_ick",
2797         .id             = 2,
2798         .parent         = &per_l4_ick,
2799         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2800         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2801         .flags          = CLOCK_IN_OMAP343X,
2802         .clkdm_name     = "per_clkdm",
2803         .recalc         = &followparent_recalc,
2804 };
2805
2806 static struct clk mcbsp3_ick = {
2807         .name           = "mcbsp_ick",
2808         .id             = 3,
2809         .parent         = &per_l4_ick,
2810         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2811         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2812         .flags          = CLOCK_IN_OMAP343X,
2813         .clkdm_name     = "per_clkdm",
2814         .recalc         = &followparent_recalc,
2815 };
2816
2817 static struct clk mcbsp4_ick = {
2818         .name           = "mcbsp_ick",
2819         .id             = 4,
2820         .parent         = &per_l4_ick,
2821         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2822         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2823         .flags          = CLOCK_IN_OMAP343X,
2824         .clkdm_name     = "per_clkdm",
2825         .recalc         = &followparent_recalc,
2826 };
2827
2828 static const struct clksel mcbsp_234_clksel[] = {
2829         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2830         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2831         { .parent = NULL }
2832 };
2833
2834 static struct clk mcbsp2_fck = {
2835         .name           = "mcbsp_fck",
2836         .id             = 2,
2837         .init           = &omap2_init_clksel_parent,
2838         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2839         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2840         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2841         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2842         .clksel         = mcbsp_234_clksel,
2843         .flags          = CLOCK_IN_OMAP343X,
2844         .clkdm_name     = "per_clkdm",
2845         .recalc         = &omap2_clksel_recalc,
2846 };
2847
2848 static struct clk mcbsp3_fck = {
2849         .name           = "mcbsp_fck",
2850         .id             = 3,
2851         .init           = &omap2_init_clksel_parent,
2852         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2853         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2854         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2855         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2856         .clksel         = mcbsp_234_clksel,
2857         .flags          = CLOCK_IN_OMAP343X,
2858         .clkdm_name     = "per_clkdm",
2859         .recalc         = &omap2_clksel_recalc,
2860 };
2861
2862 static struct clk mcbsp4_fck = {
2863         .name           = "mcbsp_fck",
2864         .id             = 4,
2865         .init           = &omap2_init_clksel_parent,
2866         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2867         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2868         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2869         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2870         .clksel         = mcbsp_234_clksel,
2871         .flags          = CLOCK_IN_OMAP343X,
2872         .clkdm_name     = "per_clkdm",
2873         .recalc         = &omap2_clksel_recalc,
2874 };
2875
2876 /* EMU clocks */
2877
2878 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2879
2880 static const struct clksel_rate emu_src_sys_rates[] = {
2881         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2882         { .div = 0 },
2883 };
2884
2885 static const struct clksel_rate emu_src_core_rates[] = {
2886         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2887         { .div = 0 },
2888 };
2889
2890 static const struct clksel_rate emu_src_per_rates[] = {
2891         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2892         { .div = 0 },
2893 };
2894
2895 static const struct clksel_rate emu_src_mpu_rates[] = {
2896         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2897         { .div = 0 },
2898 };
2899
2900 static const struct clksel emu_src_clksel[] = {
2901         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2902         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2903         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2904         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2905         { .parent = NULL },
2906 };
2907
2908 /*
2909  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2910  * to switch the source of some of the EMU clocks.
2911  * XXX Are there CLKEN bits for these EMU clks?
2912  */
2913 static struct clk emu_src_ck = {
2914         .name           = "emu_src_ck",
2915         .init           = &omap2_init_clksel_parent,
2916         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2917         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2918         .clksel         = emu_src_clksel,
2919         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2920         .clkdm_name     = "emu_clkdm",
2921         .recalc         = &omap2_clksel_recalc,
2922 };
2923
2924 static const struct clksel_rate pclk_emu_rates[] = {
2925         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2926         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2927         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2928         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2929         { .div = 0 },
2930 };
2931
2932 static const struct clksel pclk_emu_clksel[] = {
2933         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2934         { .parent = NULL },
2935 };
2936
2937 static struct clk pclk_fck = {
2938         .name           = "pclk_fck",
2939         .init           = &omap2_init_clksel_parent,
2940         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2941         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2942         .clksel         = pclk_emu_clksel,
2943         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2944         .clkdm_name     = "emu_clkdm",
2945         .recalc         = &omap2_clksel_recalc,
2946 };
2947
2948 static const struct clksel_rate pclkx2_emu_rates[] = {
2949         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2950         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2951         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2952         { .div = 0 },
2953 };
2954
2955 static const struct clksel pclkx2_emu_clksel[] = {
2956         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2957         { .parent = NULL },
2958 };
2959
2960 static struct clk pclkx2_fck = {
2961         .name           = "pclkx2_fck",
2962         .init           = &omap2_init_clksel_parent,
2963         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2964         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2965         .clksel         = pclkx2_emu_clksel,
2966         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2967         .clkdm_name     = "emu_clkdm",
2968         .recalc         = &omap2_clksel_recalc,
2969 };
2970
2971 static const struct clksel atclk_emu_clksel[] = {
2972         { .parent = &emu_src_ck, .rates = div2_rates },
2973         { .parent = NULL },
2974 };
2975
2976 static struct clk atclk_fck = {
2977         .name           = "atclk_fck",
2978         .init           = &omap2_init_clksel_parent,
2979         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2980         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2981         .clksel         = atclk_emu_clksel,
2982         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2983         .clkdm_name     = "emu_clkdm",
2984         .recalc         = &omap2_clksel_recalc,
2985 };
2986
2987 static struct clk traceclk_src_fck = {
2988         .name           = "traceclk_src_fck",
2989         .init           = &omap2_init_clksel_parent,
2990         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2991         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2992         .clksel         = emu_src_clksel,
2993         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2994         .clkdm_name     = "emu_clkdm",
2995         .recalc         = &omap2_clksel_recalc,
2996 };
2997
2998 static const struct clksel_rate traceclk_rates[] = {
2999         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3000         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3001         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3002         { .div = 0 },
3003 };
3004
3005 static const struct clksel traceclk_clksel[] = {
3006         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3007         { .parent = NULL },
3008 };
3009
3010 static struct clk traceclk_fck = {
3011         .name           = "traceclk_fck",
3012         .init           = &omap2_init_clksel_parent,
3013         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3014         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3015         .clksel         = traceclk_clksel,
3016         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3017         .clkdm_name     = "emu_clkdm",
3018         .recalc         = &omap2_clksel_recalc,
3019 };
3020
3021 /* SR clocks */
3022
3023 /* SmartReflex fclk (VDD1) */
3024 static struct clk sr1_fck = {
3025         .name           = "sr1_fck",
3026         .parent         = &sys_ck,
3027         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3028         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3029         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3030         .recalc         = &followparent_recalc,
3031 };
3032
3033 /* SmartReflex fclk (VDD2) */
3034 static struct clk sr2_fck = {
3035         .name           = "sr2_fck",
3036         .parent         = &sys_ck,
3037         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3038         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3039         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3040         .recalc         = &followparent_recalc,
3041 };
3042
3043 static struct clk sr_l4_ick = {
3044         .name           = "sr_l4_ick",
3045         .parent         = &l4_ick,
3046         .flags          = CLOCK_IN_OMAP343X,
3047         .clkdm_name     = "core_l4_clkdm",
3048         .recalc         = &followparent_recalc,
3049 };
3050
3051 /* SECURE_32K_FCK clocks */
3052
3053 /* XXX This clock no longer exists in 3430 TRM rev F */
3054 static struct clk gpt12_fck = {
3055         .name           = "gpt12_fck",
3056         .parent         = &secure_32k_fck,
3057         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3058         .recalc         = &followparent_recalc,
3059 };
3060
3061 static struct clk wdt1_fck = {
3062         .name           = "wdt1_fck",
3063         .parent         = &secure_32k_fck,
3064         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3065         .recalc         = &followparent_recalc,
3066 };
3067
3068 static struct clk *onchip_34xx_clks[] __initdata = {
3069         &omap_32k_fck,
3070         &virt_12m_ck,
3071         &virt_13m_ck,
3072         &virt_16_8m_ck,
3073         &virt_19_2m_ck,
3074         &virt_26m_ck,
3075         &virt_38_4m_ck,
3076         &osc_sys_ck,
3077         &sys_ck,
3078         &sys_altclk,
3079         &mcbsp_clks,
3080         &sys_clkout1,
3081         &dpll1_ck,
3082         &dpll1_x2_ck,
3083         &dpll1_x2m2_ck,
3084         &dpll2_ck,
3085         &dpll2_m2_ck,
3086         &dpll3_ck,
3087         &core_ck,
3088         &dpll3_x2_ck,
3089         &dpll3_m2_ck,
3090         &dpll3_m2x2_ck,
3091         &dpll3_m3_ck,
3092         &dpll3_m3x2_ck,
3093         &emu_core_alwon_ck,
3094         &dpll4_ck,
3095         &dpll4_x2_ck,
3096         &omap_96m_alwon_fck,
3097         &omap_96m_fck,
3098         &cm_96m_fck,
3099         &virt_omap_54m_fck,
3100         &omap_54m_fck,
3101         &omap_48m_fck,
3102         &omap_12m_fck,
3103         &dpll4_m2_ck,
3104         &dpll4_m2x2_ck,
3105         &dpll4_m3_ck,
3106         &dpll4_m3x2_ck,
3107         &dpll4_m4_ck,
3108         &dpll4_m4x2_ck,
3109         &dpll4_m5_ck,
3110         &dpll4_m5x2_ck,
3111         &dpll4_m6_ck,
3112         &dpll4_m6x2_ck,
3113         &emu_per_alwon_ck,
3114         &dpll5_ck,
3115         &dpll5_m2_ck,
3116         &omap_120m_fck,
3117         &clkout2_src_ck,
3118         &sys_clkout2,
3119         &corex2_fck,
3120         &dpll1_fck,
3121         &mpu_ck,
3122         &arm_fck,
3123         &emu_mpu_alwon_ck,
3124         &dpll2_fck,
3125         &iva2_ck,
3126         &l3_ick,
3127         &l4_ick,
3128         &rm_ick,
3129         &gfx_l3_ck,
3130         &gfx_l3_fck,
3131         &gfx_l3_ick,
3132         &gfx_cg1_ck,
3133         &gfx_cg2_ck,
3134         &sgx_fck,
3135         &sgx_ick,
3136         &d2d_26m_fck,
3137         &gpt10_fck,
3138         &gpt11_fck,
3139         &cpefuse_fck,
3140         &ts_fck,
3141         &usbtll_fck,
3142         &core_96m_fck,
3143         &mmchs3_fck,
3144         &mmchs2_fck,
3145         &mspro_fck,
3146         &mmchs1_fck,
3147         &i2c3_fck,
3148         &i2c2_fck,
3149         &i2c1_fck,
3150         &mcbsp5_fck,
3151         &mcbsp1_fck,
3152         &core_48m_fck,
3153         &mcspi4_fck,
3154         &mcspi3_fck,
3155         &mcspi2_fck,
3156         &mcspi1_fck,
3157         &uart2_fck,
3158         &uart1_fck,
3159         &fshostusb_fck,
3160         &core_12m_fck,
3161         &hdq_fck,
3162         &ssi_ssr_fck,
3163         &ssi_sst_fck,
3164         &core_l3_ick,
3165         &hsotgusb_ick,
3166         &sdrc_ick,
3167         &gpmc_fck,
3168         &security_l3_ick,
3169         &pka_ick,
3170         &core_l4_ick,
3171         &usbtll_ick,
3172         &mmchs3_ick,
3173         &icr_ick,
3174         &aes2_ick,
3175         &sha12_ick,
3176         &des2_ick,
3177         &mmchs2_ick,
3178         &mmchs1_ick,
3179         &mspro_ick,
3180         &hdq_ick,
3181         &mcspi4_ick,
3182         &mcspi3_ick,
3183         &mcspi2_ick,
3184         &mcspi1_ick,
3185         &i2c3_ick,
3186         &i2c2_ick,
3187         &i2c1_ick,
3188         &uart2_ick,
3189         &uart1_ick,
3190         &gpt11_ick,
3191         &gpt10_ick,
3192         &mcbsp5_ick,
3193         &mcbsp1_ick,
3194         &fac_ick,
3195         &mailboxes_ick,
3196         &omapctrl_ick,
3197         &ssi_l4_ick,
3198         &ssi_ick,
3199         &usb_l4_ick,
3200         &security_l4_ick2,
3201         &aes1_ick,
3202         &rng_ick,
3203         &sha11_ick,
3204         &des1_ick,
3205         &dss1_alwon_fck,
3206         &dss_tv_fck,
3207         &dss_96m_fck,
3208         &dss2_alwon_fck,
3209         &dss_ick,
3210         &cam_mclk,
3211         &cam_ick,
3212         &usbhost_120m_fck,
3213         &usbhost_48m_fck,
3214         &usbhost_ick,
3215         &usim_fck,
3216         &gpt1_fck,
3217         &wkup_32k_fck,
3218         &gpio1_fck,
3219         &wdt2_fck,
3220         &wkup_l4_ick,
3221         &usim_ick,
3222         &wdt2_ick,
3223         &wdt1_ick,
3224         &gpio1_ick,
3225         &omap_32ksync_ick,
3226         &gpt12_ick,
3227         &gpt1_ick,
3228         &per_96m_fck,
3229         &per_48m_fck,
3230         &uart3_fck,
3231         &gpt2_fck,
3232         &gpt3_fck,
3233         &gpt4_fck,
3234         &gpt5_fck,
3235         &gpt6_fck,
3236         &gpt7_fck,
3237         &gpt8_fck,
3238         &gpt9_fck,
3239         &per_32k_alwon_fck,
3240         &gpio6_fck,
3241         &gpio5_fck,
3242         &gpio4_fck,
3243         &gpio3_fck,
3244         &gpio2_fck,
3245         &wdt3_fck,
3246         &per_l4_ick,
3247         &gpio6_ick,
3248         &gpio5_ick,
3249         &gpio4_ick,
3250         &gpio3_ick,
3251         &gpio2_ick,
3252         &wdt3_ick,
3253         &uart3_ick,
3254         &gpt9_ick,
3255         &gpt8_ick,
3256         &gpt7_ick,
3257         &gpt6_ick,
3258         &gpt5_ick,
3259         &gpt4_ick,
3260         &gpt3_ick,
3261         &gpt2_ick,
3262         &mcbsp2_ick,
3263         &mcbsp3_ick,
3264         &mcbsp4_ick,
3265         &mcbsp2_fck,
3266         &mcbsp3_fck,
3267         &mcbsp4_fck,
3268         &emu_src_ck,
3269         &pclk_fck,
3270         &pclkx2_fck,
3271         &atclk_fck,
3272         &traceclk_src_fck,
3273         &traceclk_fck,
3274         &sr1_fck,
3275         &sr2_fck,
3276         &sr_l4_ick,
3277         &secure_32k_fck,
3278         &gpt12_fck,
3279         &wdt1_fck,
3280 };
3281
3282 #endif