arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* Forward declarations for DPLL bypass clocks */
  53 static struct clk dpll1_fck;
  54 static struct clk dpll2_fck;
  55
  56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  57 #define DPLL_LOW_POWER_STOP             0x1
  58 #define DPLL_LOW_POWER_BYPASS           0x5
  59 #define DPLL_LOCKED                     0x7
  60
  61 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  62         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  63
  64 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  65         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  66
  67 #define OMAP3430_PRM_CLKSEL                                             \
  68         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  69
  70 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  71         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  72
  73 /* PRM CLOCKS */
  74
  75 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  76 static struct clk omap_32k_fck = {
  77         .name           = "omap_32k_fck",
  78         .rate           = 32768,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .clkdm          = { .name = "prm_clkdm" },
  82         .recalc         = &propagate_rate,
  83 };
  84
  85 static struct clk secure_32k_fck = {
  86         .name           = "secure_32k_fck",
  87         .rate           = 32768,
  88         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  89                                 ALWAYS_ENABLED,
  90         .clkdm          = { .name = "prm_clkdm" },
  91         .recalc         = &propagate_rate,
  92 };
  93
  94 /* Virtual source clocks for osc_sys_ck */
  95 static struct clk virt_12m_ck = {
  96         .name           = "virt_12m_ck",
  97         .rate           = 12000000,
  98         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  99                                 ALWAYS_ENABLED,
 100         .clkdm          = { .name = "prm_clkdm" },
 101         .recalc         = &propagate_rate,
 102 };
 103
 104 static struct clk virt_13m_ck = {
 105         .name           = "virt_13m_ck",
 106         .rate           = 13000000,
 107         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 108                                 ALWAYS_ENABLED,
 109         .clkdm          = { .name = "prm_clkdm" },
 110         .recalc         = &propagate_rate,
 111 };
 112
 113 static struct clk virt_16_8m_ck = {
 114         .name           = "virt_16_8m_ck",
 115         .rate           = 16800000,
 116         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 117                                 ALWAYS_ENABLED,
 118         .clkdm          = { .name = "prm_clkdm" },
 119         .recalc         = &propagate_rate,
 120 };
 121
 122 static struct clk virt_19_2m_ck = {
 123         .name           = "virt_19_2m_ck",
 124         .rate           = 19200000,
 125         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 126                                 ALWAYS_ENABLED,
 127         .clkdm          = { .name = "prm_clkdm" },
 128         .recalc         = &propagate_rate,
 129 };
 130
 131 static struct clk virt_26m_ck = {
 132         .name           = "virt_26m_ck",
 133         .rate           = 26000000,
 134         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 135                                 ALWAYS_ENABLED,
 136         .clkdm          = { .name = "prm_clkdm" },
 137         .recalc         = &propagate_rate,
 138 };
 139
 140 static struct clk virt_38_4m_ck = {
 141         .name           = "virt_38_4m_ck",
 142         .rate           = 38400000,
 143         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 144                                 ALWAYS_ENABLED,
 145         .clkdm          = { .name = "prm_clkdm" },
 146         .recalc         = &propagate_rate,
 147 };
 148
 149 static const struct clksel_rate osc_sys_12m_rates[] = {
 150         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 151         { .div = 0 }
 152 };
 153
 154 static const struct clksel_rate osc_sys_13m_rates[] = {
 155         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 156         { .div = 0 }
 157 };
 158
 159 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 160         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 161         { .div = 0 }
 162 };
 163
 164 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 165         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 166         { .div = 0 }
 167 };
 168
 169 static const struct clksel_rate osc_sys_26m_rates[] = {
 170         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 171         { .div = 0 }
 172 };
 173
 174 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 175         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 176         { .div = 0 }
 177 };
 178
 179 static const struct clksel osc_sys_clksel[] = {
 180         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 181         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 182         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 183         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 184         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 185         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 186         { .parent = NULL },
 187 };
 188
 189 /* Oscillator clock */
 190 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 191 static struct clk osc_sys_ck = {
 192         .name           = "osc_sys_ck",
 193         .init           = &omap2_init_clksel_parent,
 194         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 195         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 196         .clksel         = osc_sys_clksel,
 197         /* REVISIT: deal with autoextclkmode? */
 198         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 199                                 ALWAYS_ENABLED,
 200         .clkdm          = { .name = "prm_clkdm" },
 201         .recalc         = &omap2_clksel_recalc,
 202 };
 203
 204 static const struct clksel_rate div2_rates[] = {
 205         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 206         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 207         { .div = 0 }
 208 };
 209
 210 static const struct clksel sys_clksel[] = {
 211         { .parent = &osc_sys_ck, .rates = div2_rates },
 212         { .parent = NULL }
 213 };
 214
 215 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 216 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 217 static struct clk sys_ck = {
 218         .name           = "sys_ck",
 219         .parent         = &osc_sys_ck,
 220         .init           = &omap2_init_clksel_parent,
 221         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 222         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 223         .clksel         = sys_clksel,
 224         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 225         .clkdm          = { .name = "prm_clkdm" },
 226         .recalc         = &omap2_clksel_recalc,
 227 };
 228
 229 static struct clk sys_altclk = {
 230         .name           = "sys_altclk",
 231         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 232         .clkdm          = { .name = "cm_clkdm" },
 233         .recalc         = &propagate_rate,
 234 };
 235
 236 /*
 237  * Optional external clock input for some McBSPs
 238  * Apparently this is not really in prm_clkdm, but rather is fed into
 239  * both CORE and PER separately.
 240  */
 241 static struct clk mcbsp_clks = {
 242         .name           = "mcbsp_clks",
 243         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 244         .clkdm          = { .name = "prm_clkdm" },
 245         .recalc         = &propagate_rate,
 246 };
 247
 248 /* PRM EXTERNAL CLOCK OUTPUT */
 249
 250 static struct clk sys_clkout1 = {
 251         .name           = "sys_clkout1",
 252         .parent         = &osc_sys_ck,
 253         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 254         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 255         .flags          = CLOCK_IN_OMAP343X,
 256         .clkdm          = { .name = "prm_clkdm" },
 257         .recalc         = &followparent_recalc,
 258 };
 259
 260 /* DPLLS */
 261
 262 /* CM CLOCKS */
 263
 264 static const struct clksel_rate dpll_bypass_rates[] = {
 265         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 266         { .div = 0 }
 267 };
 268
 269 static const struct clksel_rate dpll_locked_rates[] = {
 270         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 271         { .div = 0 }
 272 };
 273
 274 static const struct clksel_rate div16_dpll_rates[] = {
 275         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 276         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 277         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 278         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 279         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 280         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 281         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 282         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 283         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 284         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 285         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 286         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 287         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 288         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 289         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 290         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 291         { .div = 0 }
 292 };
 293
 294 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 295         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 296
 297 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 298         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 299
 300 /* DPLL1 */
 301 /* MPU clock source */
 302 /* Type: DPLL */
 303 static struct dpll_data dpll1_dd = {
 304         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 305         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 306         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 307         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 308         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 309         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 310         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 311         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 312         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 313         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 314         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 315         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 316         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 317         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 318         .bypass_clk     = &dpll1_fck,
 319         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 320         .max_divider    = OMAP3_MAX_DPLL_DIV,
 321         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 322 };
 323
 324 static struct clk dpll1_ck = {
 325         .name           = "dpll1_ck",
 326         .parent         = &sys_ck,
 327         .dpll_data      = &dpll1_dd,
 328         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 329         .round_rate     = &omap2_dpll_round_rate,
 330         .set_rate       = &omap3_noncore_dpll_set_rate,
 331         .clkdm          = { .name = "dpll1_clkdm" },
 332         .recalc         = &omap3_dpll_recalc,
 333 };
 334
 335 /*
 336  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 337  * DPLL isn't bypassed.
 338  */
 339 static struct clk dpll1_x2_ck = {
 340         .name           = "dpll1_x2_ck",
 341         .parent         = &dpll1_ck,
 342         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 343                                 PARENT_CONTROLS_CLOCK,
 344         .clkdm          = { .name = "dpll1_clkdm" },
 345         .recalc         = &omap3_clkoutx2_recalc,
 346 };
 347
 348 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 349 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 350         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 351         { .parent = NULL }
 352 };
 353
 354 /*
 355  * Does not exist in the TRM - needed to separate the M2 divider from
 356  * bypass selection in mpu_ck
 357  */
 358 static struct clk dpll1_x2m2_ck = {
 359         .name           = "dpll1_x2m2_ck",
 360         .parent         = &dpll1_x2_ck,
 361         .init           = &omap2_init_clksel_parent,
 362         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 363         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 364         .clksel         = div16_dpll1_x2m2_clksel,
 365         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 366                                 PARENT_CONTROLS_CLOCK,
 367         .clkdm          = { .name = "dpll1_clkdm" },
 368         .recalc         = &omap2_clksel_recalc,
 369 };
 370
 371 /* DPLL2 */
 372 /* IVA2 clock source */
 373 /* Type: DPLL */
 374
 375 static struct dpll_data dpll2_dd = {
 376         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 377         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 378         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 379         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 380         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 381         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 382         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 383                                 (1 << DPLL_LOW_POWER_BYPASS),
 384         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 385         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 386         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 387         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 388         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 389         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 390         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 391         .bypass_clk     = &dpll2_fck,
 392         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 393         .max_divider    = OMAP3_MAX_DPLL_DIV,
 394         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 395 };
 396
 397 static struct clk dpll2_ck = {
 398         .name           = "dpll2_ck",
 399         .parent         = &sys_ck,
 400         .dpll_data      = &dpll2_dd,
 401         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 402         .enable         = &omap3_noncore_dpll_enable,
 403         .disable        = &omap3_noncore_dpll_disable,
 404         .round_rate     = &omap2_dpll_round_rate,
 405         .set_rate       = &omap3_noncore_dpll_set_rate,
 406         .clkdm          = { .name = "dpll2_clkdm" },
 407         .recalc         = &omap3_dpll_recalc,
 408 };
 409
 410 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 411         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 412         { .parent = NULL }
 413 };
 414
 415 /*
 416  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 417  * or CLKOUTX2. CLKOUT seems most plausible.
 418  */
 419 static struct clk dpll2_m2_ck = {
 420         .name           = "dpll2_m2_ck",
 421         .parent         = &dpll2_ck,
 422         .init           = &omap2_init_clksel_parent,
 423         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 424                                           OMAP3430_CM_CLKSEL2_PLL),
 425         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 426         .clksel         = div16_dpll2_m2x2_clksel,
 427         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 428                                 PARENT_CONTROLS_CLOCK,
 429         .clkdm          = { .name = "dpll2_clkdm" },
 430         .recalc         = &omap2_clksel_recalc,
 431 };
 432
 433 /*
 434  * DPLL3
 435  * Source clock for all interfaces and for some device fclks
 436  * REVISIT: Also supports fast relock bypass - not included below
 437  */
 438 static struct dpll_data dpll3_dd = {
 439         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 440         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 441         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 442         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 443         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 444         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 445         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 446         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 447         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 448         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 449         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 450         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 451         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 452         .bypass_clk     = &sys_ck,
 453         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 454         .max_divider    = OMAP3_MAX_DPLL_DIV,
 455         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 456 };
 457
 458 static struct clk dpll3_ck = {
 459         .name           = "dpll3_ck",
 460         .parent         = &sys_ck,
 461         .dpll_data      = &dpll3_dd,
 462         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 463         .round_rate     = &omap2_dpll_round_rate,
 464         .clkdm          = { .name = "dpll3_clkdm" },
 465         .recalc         = &omap3_dpll_recalc,
 466 };
 467
 468 /*
 469  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 470  * DPLL isn't bypassed
 471  */
 472 static struct clk dpll3_x2_ck = {
 473         .name           = "dpll3_x2_ck",
 474         .parent         = &dpll3_ck,
 475         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 476                                 PARENT_CONTROLS_CLOCK,
 477         .clkdm          = { .name = "dpll3_clkdm" },
 478         .recalc         = &omap3_clkoutx2_recalc,
 479 };
 480
 481 static const struct clksel_rate div31_dpll3_rates[] = {
 482         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 483         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 484         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 485         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 486         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 487         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 488         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 489         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 490         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 491         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 492         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 493         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 494         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 495         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 496         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 497         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 498         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 499         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 500         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 501         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 502         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 503         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 504         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 505         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 506         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 507         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 508         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 509         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 510         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 511         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 512         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 513         { .div = 0 },
 514 };
 515
 516 static const struct clksel div31_dpll3m2_clksel[] = {
 517         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 518         { .parent = NULL }
 519 };
 520
 521 /* DPLL3 output M2 - primary control point for CORE speed */
 522 static struct clk dpll3_m2_ck = {
 523         .name           = "dpll3_m2_ck",
 524         .parent         = &dpll3_ck,
 525         .init           = &omap2_init_clksel_parent,
 526         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 527         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 528         .clksel         = div31_dpll3m2_clksel,
 529         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 530                                 PARENT_CONTROLS_CLOCK,
 531         .clkdm          = { .name = "dpll3_clkdm" },
 532         .round_rate     = &omap2_clksel_round_rate,
 533         .set_rate       = &omap3_core_dpll_m2_set_rate,
 534         .recalc         = &omap2_clksel_recalc,
 535 };
 536
 537 static const struct clksel core_ck_clksel[] = {
 538         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 539         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 540         { .parent = NULL }
 541 };
 542
 543 static struct clk core_ck = {
 544         .name           = "core_ck",
 545         .init           = &omap2_init_clksel_parent,
 546         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 547         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 548         .clksel         = core_ck_clksel,
 549         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 550                                 PARENT_CONTROLS_CLOCK,
 551         .clkdm          = { .name = "cm_clkdm" },
 552         .recalc         = &omap2_clksel_recalc,
 553 };
 554
 555 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 556         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 557         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 558         { .parent = NULL }
 559 };
 560
 561 static struct clk dpll3_m2x2_ck = {
 562         .name           = "dpll3_m2x2_ck",
 563         .init           = &omap2_init_clksel_parent,
 564         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 565         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 566         .clksel         = dpll3_m2x2_ck_clksel,
 567         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 568                                 PARENT_CONTROLS_CLOCK,
 569         .clkdm          = { .name = "dpll3_clkdm" },
 570         .recalc         = &omap2_clksel_recalc,
 571 };
 572
 573 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 574 static const struct clksel div16_dpll3_clksel[] = {
 575         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 576         { .parent = NULL }
 577 };
 578
 579 /* This virtual clock is the source for dpll3_m3x2_ck */
 580 static struct clk dpll3_m3_ck = {
 581         .name           = "dpll3_m3_ck",
 582         .parent         = &dpll3_ck,
 583         .init           = &omap2_init_clksel_parent,
 584         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 585         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 586         .clksel         = div16_dpll3_clksel,
 587         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 588                                 PARENT_CONTROLS_CLOCK,
 589         .clkdm          = { .name = "dpll3_clkdm" },
 590         .recalc         = &omap2_clksel_recalc,
 591 };
 592
 593 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 594 static struct clk dpll3_m3x2_ck = {
 595         .name           = "dpll3_m3x2_ck",
 596         .parent         = &dpll3_m3_ck,
 597         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 598         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 599         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 600         .clkdm          = { .name = "dpll3_clkdm" },
 601         .recalc         = &omap3_clkoutx2_recalc,
 602 };
 603
 604 static const struct clksel emu_core_alwon_ck_clksel[] = {
 605         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 606         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 607         { .parent = NULL }
 608 };
 609
 610 static struct clk emu_core_alwon_ck = {
 611         .name           = "emu_core_alwon_ck",
 612         .parent         = &dpll3_m3x2_ck,
 613         .init           = &omap2_init_clksel_parent,
 614         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 615         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 616         .clksel         = emu_core_alwon_ck_clksel,
 617         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 618                                 PARENT_CONTROLS_CLOCK,
 619         .clkdm          = { .name = "dpll3_clkdm" },
 620         .recalc         = &omap2_clksel_recalc,
 621 };
 622
 623 /* DPLL4 */
 624 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 625 /* Type: DPLL */
 626 static struct dpll_data dpll4_dd = {
 627         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 628         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 629         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 630         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 631         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 632         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 633         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 634         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 635         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 636         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 637         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 638         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 639         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 640         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 641         .bypass_clk     = &sys_ck,
 642         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 643         .max_divider    = OMAP3_MAX_DPLL_DIV,
 644         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 645 };
 646
 647 static struct clk dpll4_ck = {
 648         .name           = "dpll4_ck",
 649         .parent         = &sys_ck,
 650         .dpll_data      = &dpll4_dd,
 651         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 652         .enable         = &omap3_noncore_dpll_enable,
 653         .disable        = &omap3_noncore_dpll_disable,
 654         .round_rate     = &omap2_dpll_round_rate,
 655         .set_rate       = &omap3_noncore_dpll_set_rate,
 656         .clkdm          = { .name = "dpll4_clkdm" },
 657         .recalc         = &omap3_dpll_recalc,
 658 };
 659
 660 /*
 661  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 662  * DPLL isn't bypassed --
 663  * XXX does this serve any downstream clocks?
 664  */
 665 static struct clk dpll4_x2_ck = {
 666         .name           = "dpll4_x2_ck",
 667         .parent         = &dpll4_ck,
 668         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 669                                 PARENT_CONTROLS_CLOCK,
 670         .clkdm          = { .name = "dpll4_clkdm" },
 671         .recalc         = &omap3_clkoutx2_recalc,
 672 };
 673
 674 static const struct clksel div16_dpll4_clksel[] = {
 675         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 676         { .parent = NULL }
 677 };
 678
 679 /* This virtual clock is the source for dpll4_m2x2_ck */
 680 static struct clk dpll4_m2_ck = {
 681         .name           = "dpll4_m2_ck",
 682         .parent         = &dpll4_ck,
 683         .init           = &omap2_init_clksel_parent,
 684         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 685         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 686         .clksel         = div16_dpll4_clksel,
 687         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 688                                 PARENT_CONTROLS_CLOCK,
 689         .clkdm          = { .name = "dpll4_clkdm" },
 690         .recalc         = &omap2_clksel_recalc,
 691 };
 692
 693 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 694 static struct clk dpll4_m2x2_ck = {
 695         .name           = "dpll4_m2x2_ck",
 696         .parent         = &dpll4_m2_ck,
 697         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 698         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 699         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 700         .clkdm          = { .name = "dpll4_clkdm" },
 701         .recalc         = &omap3_clkoutx2_recalc,
 702 };
 703
 704 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 705         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 706         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 707         { .parent = NULL }
 708 };
 709
 710 /*
 711  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 712  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 713  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 714  * CM_96K_(F)CLK.
 715  */
 716 static struct clk omap_96m_alwon_fck = {
 717         .name           = "omap_96m_alwon_fck",
 718         .parent         = &dpll4_m2x2_ck,
 719         .init           = &omap2_init_clksel_parent,
 720         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 721         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 722         .clksel         = omap_96m_alwon_fck_clksel,
 723         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 724                                 PARENT_CONTROLS_CLOCK,
 725         .clkdm          = { .name = "prm_clkdm" },
 726         .recalc         = &omap2_clksel_recalc,
 727 };
 728
 729 static struct clk cm_96m_fck = {
 730         .name           = "cm_96m_fck",
 731         .parent         = &omap_96m_alwon_fck,
 732         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 733                                 PARENT_CONTROLS_CLOCK,
 734         .clkdm          = { .name = "cm_clkdm" },
 735         .recalc         = &followparent_recalc,
 736 };
 737
 738 static const struct clksel_rate omap_96m_dpll_rates[] = {
 739         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 740         { .div = 0 }
 741 };
 742
 743 static const struct clksel_rate omap_96m_sys_rates[] = {
 744         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 745         { .div = 0 }
 746 };
 747
 748 static const struct clksel omap_96m_fck_clksel[] = {
 749         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 750         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 751         { .parent = NULL }
 752 };
 753
 754 static struct clk omap_96m_fck = {
 755         .name           = "omap_96m_fck",
 756         .parent         = &sys_ck,
 757         .init           = &omap2_init_clksel_parent,
 758         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 759         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 760         .clksel         = omap_96m_fck_clksel,
 761         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 762                                 PARENT_CONTROLS_CLOCK,
 763         .clkdm          = { .name = "cm_clkdm" },
 764         .recalc         = &omap2_clksel_recalc,
 765 };
 766
 767 /* This virtual clock is the source for dpll4_m3x2_ck */
 768 static struct clk dpll4_m3_ck = {
 769         .name           = "dpll4_m3_ck",
 770         .parent         = &dpll4_ck,
 771         .init           = &omap2_init_clksel_parent,
 772         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 773         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 774         .clksel         = div16_dpll4_clksel,
 775         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 776                                 PARENT_CONTROLS_CLOCK,
 777         .clkdm          = { .name = "dpll4_clkdm" },
 778         .recalc         = &omap2_clksel_recalc,
 779 };
 780
 781 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 782 static struct clk dpll4_m3x2_ck = {
 783         .name           = "dpll4_m3x2_ck",
 784         .parent         = &dpll4_m3_ck,
 785         .init           = &omap2_init_clksel_parent,
 786         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 787         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 788         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 789         .clkdm          = { .name = "dpll4_clkdm" },
 790         .recalc         = &omap3_clkoutx2_recalc,
 791 };
 792
 793 static const struct clksel virt_omap_54m_fck_clksel[] = {
 794         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 795         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 796         { .parent = NULL }
 797 };
 798
 799 static struct clk virt_omap_54m_fck = {
 800         .name           = "virt_omap_54m_fck",
 801         .parent         = &dpll4_m3x2_ck,
 802         .init           = &omap2_init_clksel_parent,
 803         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 804         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 805         .clksel         = virt_omap_54m_fck_clksel,
 806         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 807                                 PARENT_CONTROLS_CLOCK,
 808         .clkdm          = { .name = "dpll4_clkdm" },
 809         .recalc         = &omap2_clksel_recalc,
 810 };
 811
 812 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 813         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 814         { .div = 0 }
 815 };
 816
 817 static const struct clksel_rate omap_54m_alt_rates[] = {
 818         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 819         { .div = 0 }
 820 };
 821
 822 static const struct clksel omap_54m_clksel[] = {
 823         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 824         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 825         { .parent = NULL }
 826 };
 827
 828 static struct clk omap_54m_fck = {
 829         .name           = "omap_54m_fck",
 830         .init           = &omap2_init_clksel_parent,
 831         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 832         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 833         .clksel         = omap_54m_clksel,
 834         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 835                                 PARENT_CONTROLS_CLOCK,
 836         .clkdm          = { .name = "cm_clkdm" },
 837         .recalc         = &omap2_clksel_recalc,
 838 };
 839
 840 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 841         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 842         { .div = 0 }
 843 };
 844
 845 static const struct clksel_rate omap_48m_alt_rates[] = {
 846         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 847         { .div = 0 }
 848 };
 849
 850 static const struct clksel omap_48m_clksel[] = {
 851         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 852         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 853         { .parent = NULL }
 854 };
 855
 856 static struct clk omap_48m_fck = {
 857         .name           = "omap_48m_fck",
 858         .init           = &omap2_init_clksel_parent,
 859         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 860         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 861         .clksel         = omap_48m_clksel,
 862         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 863                                 PARENT_CONTROLS_CLOCK,
 864         .clkdm          = { .name = "cm_clkdm" },
 865         .recalc         = &omap2_clksel_recalc,
 866 };
 867
 868 static struct clk omap_12m_fck = {
 869         .name           = "omap_12m_fck",
 870         .parent         = &omap_48m_fck,
 871         .fixed_div      = 4,
 872         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 873                                 PARENT_CONTROLS_CLOCK,
 874         .clkdm          = { .name = "cm_clkdm" },
 875         .recalc         = &omap2_fixed_divisor_recalc,
 876 };
 877
 878 /* This virstual clock is the source for dpll4_m4x2_ck */
 879 static struct clk dpll4_m4_ck = {
 880         .name           = "dpll4_m4_ck",
 881         .parent         = &dpll4_ck,
 882         .init           = &omap2_init_clksel_parent,
 883         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 884         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 885         .clksel         = div16_dpll4_clksel,
 886         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 887                                 PARENT_CONTROLS_CLOCK,
 888         .clkdm          = { .name = "dpll4_clkdm" },
 889         .recalc         = &omap2_clksel_recalc,
 890 };
 891
 892 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 893 static struct clk dpll4_m4x2_ck = {
 894         .name           = "dpll4_m4x2_ck",
 895         .parent         = &dpll4_m4_ck,
 896         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 897         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 898         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 899         .clkdm          = { .name = "dpll4_clkdm" },
 900         .recalc         = &omap3_clkoutx2_recalc,
 901 };
 902
 903 /* This virtual clock is the source for dpll4_m5x2_ck */
 904 static struct clk dpll4_m5_ck = {
 905         .name           = "dpll4_m5_ck",
 906         .parent         = &dpll4_ck,
 907         .init           = &omap2_init_clksel_parent,
 908         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 909         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 910         .clksel         = div16_dpll4_clksel,
 911         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 912                                 PARENT_CONTROLS_CLOCK,
 913         .clkdm          = { .name = "dpll4_clkdm" },
 914         .recalc         = &omap2_clksel_recalc,
 915 };
 916
 917 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 918 static struct clk dpll4_m5x2_ck = {
 919         .name           = "dpll4_m5x2_ck",
 920         .parent         = &dpll4_m5_ck,
 921         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 922         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 923         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 924         .clkdm          = { .name = "dpll4_clkdm" },
 925         .recalc         = &omap3_clkoutx2_recalc,
 926 };
 927
 928 /* This virtual clock is the source for dpll4_m6x2_ck */
 929 static struct clk dpll4_m6_ck = {
 930         .name           = "dpll4_m6_ck",
 931         .parent         = &dpll4_ck,
 932         .init           = &omap2_init_clksel_parent,
 933         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 934         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 935         .clksel         = div16_dpll4_clksel,
 936         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 937                                 PARENT_CONTROLS_CLOCK,
 938         .clkdm          = { .name = "dpll4_clkdm" },
 939         .recalc         = &omap2_clksel_recalc,
 940 };
 941
 942 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 943 static struct clk dpll4_m6x2_ck = {
 944         .name           = "dpll4_m6x2_ck",
 945         .parent         = &dpll4_m6_ck,
 946         .init           = &omap2_init_clksel_parent,
 947         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 948         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 949         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 950         .clkdm          = { .name = "dpll4_clkdm" },
 951         .recalc         = &omap3_clkoutx2_recalc,
 952 };
 953
 954 static struct clk emu_per_alwon_ck = {
 955         .name           = "emu_per_alwon_ck",
 956         .parent         = &dpll4_m6x2_ck,
 957         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 958                                 PARENT_CONTROLS_CLOCK,
 959         .clkdm          = { .name = "dpll4_clkdm" },
 960         .recalc         = &followparent_recalc,
 961 };
 962
 963 /* DPLL5 */
 964 /* Supplies 120MHz clock, USIM source clock */
 965 /* Type: DPLL */
 966 /* 3430ES2 only */
 967 static struct dpll_data dpll5_dd = {
 968         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 969         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 970         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 971         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 972         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 973         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 974         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 975         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 976         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 977         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 978         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 979         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 980         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 981         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 982         .bypass_clk     = &sys_ck,
 983         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 984         .max_divider    = OMAP3_MAX_DPLL_DIV,
 985         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 986 };
 987
 988 static struct clk dpll5_ck = {
 989         .name           = "dpll5_ck",
 990         .parent         = &sys_ck,
 991         .dpll_data      = &dpll5_dd,
 992         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 993         .enable         = &omap3_noncore_dpll_enable,
 994         .disable        = &omap3_noncore_dpll_disable,
 995         .round_rate     = &omap2_dpll_round_rate,
 996         .set_rate       = &omap3_noncore_dpll_set_rate,
 997         .clkdm          = { .name = "dpll5_clkdm" },
 998         .recalc         = &omap3_dpll_recalc,
 999 };
1000
1001 static const struct clksel div16_dpll5_clksel[] = {
1002         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
1003         { .parent = NULL }
1004 };
1005
1006 static struct clk dpll5_m2_ck = {
1007         .name           = "dpll5_m2_ck",
1008         .parent         = &dpll5_ck,
1009         .init           = &omap2_init_clksel_parent,
1010         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1011         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
1012         .clksel         = div16_dpll5_clksel,
1013         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1014                                 PARENT_CONTROLS_CLOCK,
1015         .clkdm          = { .name = "dpll5_clkdm" },
1016         .recalc         = &omap2_clksel_recalc,
1017 };
1018
1019 static const struct clksel omap_120m_fck_clksel[] = {
1020         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
1021         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
1022         { .parent = NULL }
1023 };
1024
1025 static struct clk omap_120m_fck = {
1026         .name           = "omap_120m_fck",
1027         .parent         = &dpll5_m2_ck,
1028         .init           = &omap2_init_clksel_parent,
1029         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1030         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1031         .clksel         = omap_120m_fck_clksel,
1032         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1033                                 PARENT_CONTROLS_CLOCK,
1034         .clkdm          = { .name = "dpll5_clkdm" },
1035         .recalc         = &omap2_clksel_recalc,
1036 };
1037
1038 /* CM EXTERNAL CLOCK OUTPUTS */
1039
1040 static const struct clksel_rate clkout2_src_core_rates[] = {
1041         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1042         { .div = 0 }
1043 };
1044
1045 static const struct clksel_rate clkout2_src_sys_rates[] = {
1046         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1047         { .div = 0 }
1048 };
1049
1050 static const struct clksel_rate clkout2_src_96m_rates[] = {
1051         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1052         { .div = 0 }
1053 };
1054
1055 static const struct clksel_rate clkout2_src_54m_rates[] = {
1056         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1057         { .div = 0 }
1058 };
1059
1060 static const struct clksel clkout2_src_clksel[] = {
1061         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1062         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1063         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1064         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1065         { .parent = NULL }
1066 };
1067
1068 static struct clk clkout2_src_ck = {
1069         .name           = "clkout2_src_ck",
1070         .init           = &omap2_init_clksel_parent,
1071         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1072         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1073         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1074         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1075         .clksel         = clkout2_src_clksel,
1076         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1077         .clkdm          = { .name = "cm_clkdm" },
1078         .recalc         = &omap2_clksel_recalc,
1079 };
1080
1081 static const struct clksel_rate sys_clkout2_rates[] = {
1082         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1083         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1084         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1085         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1086         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1087         { .div = 0 },
1088 };
1089
1090 static const struct clksel sys_clkout2_clksel[] = {
1091         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1092         { .parent = NULL },
1093 };
1094
1095 static struct clk sys_clkout2 = {
1096         .name           = "sys_clkout2",
1097         .init           = &omap2_init_clksel_parent,
1098         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1099         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1100         .clksel         = sys_clkout2_clksel,
1101         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1102         .clkdm          = { .name = "cm_clkdm" },
1103         .recalc         = &omap2_clksel_recalc,
1104 };
1105
1106 /* CM OUTPUT CLOCKS */
1107
1108 static struct clk corex2_fck = {
1109         .name           = "corex2_fck",
1110         .parent         = &dpll3_m2x2_ck,
1111         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1112                                 PARENT_CONTROLS_CLOCK,
1113         .clkdm          = { .name = "cm_clkdm" },
1114         .recalc         = &followparent_recalc,
1115 };
1116
1117 /* DPLL power domain clock controls */
1118
1119 static const struct clksel_rate div4_rates[] = {
1120         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1121         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1122         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1123         { .div = 0 }
1124 };
1125
1126 static const struct clksel div4_core_clksel[] = {
1127         { .parent = &core_ck, .rates = div4_rates },
1128         { .parent = NULL }
1129 };
1130
1131 static struct clk dpll1_fck = {
1132         .name           = "dpll1_fck",
1133         .parent         = &core_ck,
1134         .init           = &omap2_init_clksel_parent,
1135         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1136         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1137         .clksel         = div4_core_clksel,
1138         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1139                                 PARENT_CONTROLS_CLOCK,
1140         .clkdm          = { .name = "cm_clkdm" },
1141         .recalc         = &omap2_clksel_recalc,
1142 };
1143
1144 /*
1145  * MPU clksel:
1146  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1147  * derives from the high-frequency bypass clock originating from DPLL3,
1148  * called 'dpll1_fck'
1149  */
1150 static const struct clksel mpu_clksel[] = {
1151         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1152         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1153         { .parent = NULL }
1154 };
1155
1156 static struct clk mpu_ck = {
1157         .name           = "mpu_ck",
1158         .parent         = &dpll1_x2m2_ck,
1159         .init           = &omap2_init_clksel_parent,
1160         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1161         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1162         .clksel         = mpu_clksel,
1163         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1164                                 PARENT_CONTROLS_CLOCK,
1165         .clkdm          = { .name = "mpu_clkdm" },
1166         .recalc         = &omap2_clksel_recalc,
1167 };
1168
1169 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1170 static const struct clksel_rate arm_fck_rates[] = {
1171         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1172         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1173         { .div = 0 },
1174 };
1175
1176 static const struct clksel arm_fck_clksel[] = {
1177         { .parent = &mpu_ck, .rates = arm_fck_rates },
1178         { .parent = NULL }
1179 };
1180
1181 static struct clk arm_fck = {
1182         .name           = "arm_fck",
1183         .parent         = &mpu_ck,
1184         .init           = &omap2_init_clksel_parent,
1185         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1186         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1187         .clksel         = arm_fck_clksel,
1188         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1189                                 PARENT_CONTROLS_CLOCK,
1190         .clkdm          = { .name = "mpu_clkdm" },
1191         .recalc         = &omap2_clksel_recalc,
1192 };
1193
1194 /* XXX What about neon_clkdm ? */
1195
1196 /*
1197  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1198  * although it is referenced - so this is a guess
1199  */
1200 static struct clk emu_mpu_alwon_ck = {
1201         .name           = "emu_mpu_alwon_ck",
1202         .parent         = &mpu_ck,
1203         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1204                                 PARENT_CONTROLS_CLOCK,
1205         .clkdm          = { .name = "mpu_clkdm" },
1206         .recalc         = &followparent_recalc,
1207 };
1208
1209 static struct clk dpll2_fck = {
1210         .name           = "dpll2_fck",
1211         .parent         = &core_ck,
1212         .init           = &omap2_init_clksel_parent,
1213         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1214         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1215         .clksel         = div4_core_clksel,
1216         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1217                                 PARENT_CONTROLS_CLOCK,
1218         .clkdm          = { .name = "cm_clkdm" },
1219         .recalc         = &omap2_clksel_recalc,
1220 };
1221
1222 /*
1223  * IVA2 clksel:
1224  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1225  * derives from the high-frequency bypass clock originating from DPLL3,
1226  * called 'dpll2_fck'
1227  */
1228
1229 static const struct clksel iva2_clksel[] = {
1230         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1231         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1232         { .parent = NULL }
1233 };
1234
1235 static struct clk iva2_ck = {
1236         .name           = "iva2_ck",
1237         .parent         = &dpll2_m2_ck,
1238         .init           = &omap2_init_clksel_parent,
1239         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1240         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1241         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1242                                           OMAP3430_CM_IDLEST_PLL),
1243         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1244         .clksel         = iva2_clksel,
1245         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1246         .clkdm          = { .name = "iva2_clkdm" },
1247         .recalc         = &omap2_clksel_recalc,
1248 };
1249
1250 /* Common interface clocks */
1251
1252 static const struct clksel div2_core_clksel[] = {
1253         { .parent = &core_ck, .rates = div2_rates },
1254         { .parent = NULL }
1255 };
1256
1257 static struct clk l3_ick = {
1258         .name           = "l3_ick",
1259         .parent         = &core_ck,
1260         .init           = &omap2_init_clksel_parent,
1261         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1262         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1263         .clksel         = div2_core_clksel,
1264         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1265                                 PARENT_CONTROLS_CLOCK,
1266         .clkdm          = { .name = "core_l3_clkdm" },
1267         .recalc         = &omap2_clksel_recalc,
1268 };
1269
1270 static const struct clksel div2_l3_clksel[] = {
1271         { .parent = &l3_ick, .rates = div2_rates },
1272         { .parent = NULL }
1273 };
1274
1275 static struct clk l4_ick = {
1276         .name           = "l4_ick",
1277         .parent         = &l3_ick,
1278         .init           = &omap2_init_clksel_parent,
1279         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1280         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1281         .clksel         = div2_l3_clksel,
1282         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1283                                 PARENT_CONTROLS_CLOCK,
1284         .clkdm          = { .name = "core_l4_clkdm" },
1285         .recalc         = &omap2_clksel_recalc,
1286
1287 };
1288
1289 static const struct clksel div2_l4_clksel[] = {
1290         { .parent = &l4_ick, .rates = div2_rates },
1291         { .parent = NULL }
1292 };
1293
1294 static struct clk rm_ick = {
1295         .name           = "rm_ick",
1296         .parent         = &l4_ick,
1297         .init           = &omap2_init_clksel_parent,
1298         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1299         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1300         .clksel         = div2_l4_clksel,
1301         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1302         .clkdm          = { .name = "cm_clkdm" },
1303         .recalc         = &omap2_clksel_recalc,
1304 };
1305
1306 /* GFX power domain */
1307
1308 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1309
1310 static const struct clksel gfx_l3_clksel[] = {
1311         { .parent = &l3_ick, .rates = gfx_l3_rates },
1312         { .parent = NULL }
1313 };
1314
1315 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1316 static struct clk gfx_l3_ck = {
1317         .name           = "gfx_l3_ck",
1318         .parent         = &l3_ick,
1319         .init           = &omap2_init_clksel_parent,
1320         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1321         .enable_bit     = OMAP_EN_GFX_SHIFT,
1322         .flags          = CLOCK_IN_OMAP3430ES1,
1323         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1324         .recalc         = &followparent_recalc,
1325 };
1326
1327 static struct clk gfx_l3_fck = {
1328         .name           = "gfx_l3_fck",
1329         .parent         = &gfx_l3_ck,
1330         .init           = &omap2_init_clksel_parent,
1331         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1332         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1333         .clksel         = gfx_l3_clksel,
1334         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1335                                 PARENT_CONTROLS_CLOCK,
1336         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1337         .recalc         = &omap2_clksel_recalc,
1338 };
1339
1340 static struct clk gfx_l3_ick = {
1341         .name           = "gfx_l3_ick",
1342         .parent         = &gfx_l3_ck,
1343         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1344         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1345         .recalc         = &followparent_recalc,
1346 };
1347
1348 static struct clk gfx_cg1_ck = {
1349         .name           = "gfx_cg1_ck",
1350         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1351         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1352         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1353         .flags          = CLOCK_IN_OMAP3430ES1,
1354         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1355         .recalc         = &followparent_recalc,
1356 };
1357
1358 static struct clk gfx_cg2_ck = {
1359         .name           = "gfx_cg2_ck",
1360         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1361         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1362         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1363         .flags          = CLOCK_IN_OMAP3430ES1,
1364         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1365         .recalc         = &followparent_recalc,
1366 };
1367
1368 /* SGX power domain - 3430ES2 only */
1369
1370 static const struct clksel_rate sgx_core_rates[] = {
1371         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1372         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1373         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1374         { .div = 0 },
1375 };
1376
1377 static const struct clksel_rate sgx_96m_rates[] = {
1378         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1379         { .div = 0 },
1380 };
1381
1382 static const struct clksel sgx_clksel[] = {
1383         { .parent = &core_ck,    .rates = sgx_core_rates },
1384         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1385         { .parent = NULL },
1386 };
1387
1388 static struct clk sgx_fck = {
1389         .name           = "sgx_fck",
1390         .init           = &omap2_init_clksel_parent,
1391         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1392         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1393         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1394         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1395         .clksel         = sgx_clksel,
1396         .flags          = CLOCK_IN_OMAP3430ES2,
1397         .clkdm          = { .name = "sgx_clkdm" },
1398         .recalc         = &omap2_clksel_recalc,
1399 };
1400
1401 static struct clk sgx_ick = {
1402         .name           = "sgx_ick",
1403         .parent         = &l3_ick,
1404         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1405         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1406         .flags          = CLOCK_IN_OMAP3430ES2,
1407         .clkdm          = { .name = "sgx_clkdm" },
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 /* CORE power domain */
1412
1413 static struct clk d2d_26m_fck = {
1414         .name           = "d2d_26m_fck",
1415         .parent         = &sys_ck,
1416         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1418         .flags          = CLOCK_IN_OMAP3430ES1,
1419         .clkdm          = { .name = "d2d_clkdm" },
1420         .recalc         = &followparent_recalc,
1421 };
1422
1423 static const struct clksel omap343x_gpt_clksel[] = {
1424         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1425         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1426         { .parent = NULL}
1427 };
1428
1429 static struct clk gpt10_fck = {
1430         .name           = "gpt10_fck",
1431         .parent         = &sys_ck,
1432         .init           = &omap2_init_clksel_parent,
1433         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1435         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1436         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1437         .clksel         = omap343x_gpt_clksel,
1438         .flags          = CLOCK_IN_OMAP343X,
1439         .clkdm          = { .name = "core_l4_clkdm" },
1440         .recalc         = &omap2_clksel_recalc,
1441 };
1442
1443 static struct clk gpt11_fck = {
1444         .name           = "gpt11_fck",
1445         .parent         = &sys_ck,
1446         .init           = &omap2_init_clksel_parent,
1447         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1449         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1450         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1451         .clksel         = omap343x_gpt_clksel,
1452         .flags          = CLOCK_IN_OMAP343X,
1453         .clkdm          = { .name = "core_l4_clkdm" },
1454         .recalc         = &omap2_clksel_recalc,
1455 };
1456
1457 static struct clk cpefuse_fck = {
1458         .name           = "cpefuse_fck",
1459         .parent         = &sys_ck,
1460         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1461         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1462         .flags          = CLOCK_IN_OMAP3430ES2,
1463         .clkdm          = { .name = "cm_clkdm" },
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk ts_fck = {
1468         .name           = "ts_fck",
1469         .parent         = &omap_32k_fck,
1470         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1471         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1472         .flags          = CLOCK_IN_OMAP3430ES2,
1473         .clkdm          = { .name = "core_l4_clkdm" },
1474         .recalc         = &followparent_recalc,
1475 };
1476
1477 static struct clk usbtll_fck = {
1478         .name           = "usbtll_fck",
1479         .parent         = &omap_120m_fck,
1480         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1481         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1482         .flags          = CLOCK_IN_OMAP3430ES2,
1483         .clkdm          = { .name = "core_l4_clkdm" },
1484         .recalc         = &followparent_recalc,
1485 };
1486
1487 /* CORE 96M FCLK-derived clocks */
1488
1489 static struct clk core_96m_fck = {
1490         .name           = "core_96m_fck",
1491         .parent         = &omap_96m_fck,
1492         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1493                                 PARENT_CONTROLS_CLOCK,
1494         .clkdm          = { .name = "core_l4_clkdm" },
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk mmchs3_fck = {
1499         .name           = "mmchs_fck",
1500         .id             = 3,
1501         .parent         = &core_96m_fck,
1502         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1503         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1504         .flags          = CLOCK_IN_OMAP3430ES2,
1505         .clkdm          = { .name = "core_l4_clkdm" },
1506         .recalc         = &followparent_recalc,
1507 };
1508
1509 static struct clk mmchs2_fck = {
1510         .name           = "mmchs_fck",
1511         .id             = 2,
1512         .parent         = &core_96m_fck,
1513         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1515         .flags          = CLOCK_IN_OMAP343X,
1516         .clkdm          = { .name = "core_l4_clkdm" },
1517         .recalc         = &followparent_recalc,
1518 };
1519
1520 static struct clk mspro_fck = {
1521         .name           = "mspro_fck",
1522         .parent         = &core_96m_fck,
1523         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1525         .flags          = CLOCK_IN_OMAP343X,
1526         .clkdm          = { .name = "core_l4_clkdm" },
1527         .recalc         = &followparent_recalc,
1528 };
1529
1530 static struct clk mmchs1_fck = {
1531         .name           = "mmchs_fck",
1532         .id             = 1,
1533         .parent         = &core_96m_fck,
1534         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1535         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1536         .flags          = CLOCK_IN_OMAP343X,
1537         .clkdm          = { .name = "core_l4_clkdm" },
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk i2c3_fck = {
1542         .name           = "i2c_fck",
1543         .id             = 3,
1544         .parent         = &core_96m_fck,
1545         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1546         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1547         .flags          = CLOCK_IN_OMAP343X,
1548         .clkdm          = { .name = "core_l4_clkdm" },
1549         .recalc         = &followparent_recalc,
1550 };
1551
1552 static struct clk i2c2_fck = {
1553         .name           = "i2c_fck",
1554         .id             = 2,
1555         .parent         = &core_96m_fck,
1556         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1557         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1558         .flags          = CLOCK_IN_OMAP343X,
1559         .clkdm          = { .name = "core_l4_clkdm" },
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 static struct clk i2c1_fck = {
1564         .name           = "i2c_fck",
1565         .id             = 1,
1566         .parent         = &core_96m_fck,
1567         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1568         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1569         .flags          = CLOCK_IN_OMAP343X,
1570         .clkdm          = { .name = "core_l4_clkdm" },
1571         .recalc         = &followparent_recalc,
1572 };
1573
1574 /*
1575  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1576  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1577  */
1578 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1579         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1580         { .div = 0 }
1581 };
1582
1583 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1584         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1585         { .div = 0 }
1586 };
1587
1588 static const struct clksel mcbsp_15_clksel[] = {
1589         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1590         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1591         { .parent = NULL }
1592 };
1593
1594 static struct clk mcbsp5_fck = {
1595         .name           = "mcbsp_fck",
1596         .id             = 5,
1597         .init           = &omap2_init_clksel_parent,
1598         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1600         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1601         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1602         .clksel         = mcbsp_15_clksel,
1603         .flags          = CLOCK_IN_OMAP343X,
1604         .clkdm          = { .name = "core_l4_clkdm" },
1605         .recalc         = &omap2_clksel_recalc,
1606 };
1607
1608 static struct clk mcbsp1_fck = {
1609         .name           = "mcbsp_fck",
1610         .id             = 1,
1611         .init           = &omap2_init_clksel_parent,
1612         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1613         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1614         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1615         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1616         .clksel         = mcbsp_15_clksel,
1617         .flags          = CLOCK_IN_OMAP343X,
1618         .clkdm          = { .name = "core_l4_clkdm" },
1619         .recalc         = &omap2_clksel_recalc,
1620 };
1621
1622 /* CORE_48M_FCK-derived clocks */
1623
1624 static struct clk core_48m_fck = {
1625         .name           = "core_48m_fck",
1626         .parent         = &omap_48m_fck,
1627         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1628                                 PARENT_CONTROLS_CLOCK,
1629         .clkdm          = { .name = "core_l4_clkdm" },
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 static struct clk mcspi4_fck = {
1634         .name           = "mcspi_fck",
1635         .id             = 4,
1636         .parent         = &core_48m_fck,
1637         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1639         .flags          = CLOCK_IN_OMAP343X,
1640         .clkdm          = { .name = "core_l4_clkdm" },
1641         .recalc         = &followparent_recalc,
1642 };
1643
1644 static struct clk mcspi3_fck = {
1645         .name           = "mcspi_fck",
1646         .id             = 3,
1647         .parent         = &core_48m_fck,
1648         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1649         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1650         .flags          = CLOCK_IN_OMAP343X,
1651         .clkdm          = { .name = "core_l4_clkdm" },
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk mcspi2_fck = {
1656         .name           = "mcspi_fck",
1657         .id             = 2,
1658         .parent         = &core_48m_fck,
1659         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1661         .flags          = CLOCK_IN_OMAP343X,
1662         .clkdm          = { .name = "core_l4_clkdm" },
1663         .recalc         = &followparent_recalc,
1664 };
1665
1666 static struct clk mcspi1_fck = {
1667         .name           = "mcspi_fck",
1668         .id             = 1,
1669         .parent         = &core_48m_fck,
1670         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1671         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1672         .flags          = CLOCK_IN_OMAP343X,
1673         .clkdm          = { .name = "core_l4_clkdm" },
1674         .recalc         = &followparent_recalc,
1675 };
1676
1677 static struct clk uart2_fck = {
1678         .name           = "uart2_fck",
1679         .parent         = &core_48m_fck,
1680         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1681         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1682         .flags          = CLOCK_IN_OMAP343X,
1683         .clkdm          = { .name = "core_l4_clkdm" },
1684         .recalc         = &followparent_recalc,
1685 };
1686
1687 static struct clk uart1_fck = {
1688         .name           = "uart1_fck",
1689         .parent         = &core_48m_fck,
1690         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1691         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1692         .flags          = CLOCK_IN_OMAP343X,
1693         .clkdm          = { .name = "core_l4_clkdm" },
1694         .recalc         = &followparent_recalc,
1695 };
1696
1697 static struct clk fshostusb_fck = {
1698         .name           = "fshostusb_fck",
1699         .parent         = &core_48m_fck,
1700         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1701         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1702         .flags          = CLOCK_IN_OMAP3430ES1,
1703         .clkdm          = { .name = "core_l4_clkdm" },
1704         .recalc         = &followparent_recalc,
1705 };
1706
1707 /* CORE_12M_FCK based clocks */
1708
1709 static struct clk core_12m_fck = {
1710         .name           = "core_12m_fck",
1711         .parent         = &omap_12m_fck,
1712         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1713                                 PARENT_CONTROLS_CLOCK,
1714         .clkdm          = { .name = "core_l4_clkdm" },
1715         .recalc         = &followparent_recalc,
1716 };
1717
1718 static struct clk hdq_fck = {
1719         .name           = "hdq_fck",
1720         .parent         = &core_12m_fck,
1721         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1722         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1723         .flags          = CLOCK_IN_OMAP343X,
1724         .clkdm          = { .name = "core_l4_clkdm" },
1725         .recalc         = &followparent_recalc,
1726 };
1727
1728 /* DPLL3-derived clock */
1729
1730 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1731         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1732         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1733         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1734         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1735         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1736         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1737         { .div = 0 }
1738 };
1739
1740 static const struct clksel ssi_ssr_clksel[] = {
1741         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1742         { .parent = NULL }
1743 };
1744
1745 static struct clk ssi_ssr_fck = {
1746         .name           = "ssi_ssr_fck",
1747         .init           = &omap2_init_clksel_parent,
1748         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1749         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1750         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1751         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1752         .clksel         = ssi_ssr_clksel,
1753         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1754         .clkdm          = { .name = "core_l4_clkdm" },
1755         .recalc         = &omap2_clksel_recalc,
1756 };
1757
1758 static struct clk ssi_sst_fck = {
1759         .name           = "ssi_sst_fck",
1760         .parent         = &ssi_ssr_fck,
1761         .fixed_div      = 2,
1762         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1763         .clkdm          = { .name = "core_l4_clkdm" },
1764         .recalc         = &omap2_fixed_divisor_recalc,
1765 };
1766
1767
1768
1769 /* CORE_L3_ICK based clocks */
1770
1771 /*
1772  * XXX must add clk_enable/clk_disable for these if standard code won't
1773  * handle it
1774  */
1775 static struct clk core_l3_ick = {
1776         .name           = "core_l3_ick",
1777         .parent         = &l3_ick,
1778         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1779                                 PARENT_CONTROLS_CLOCK,
1780         .clkdm          = { .name = "core_l3_clkdm" },
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 static struct clk hsotgusb_ick = {
1785         .name           = "hsotgusb_ick",
1786         .parent         = &core_l3_ick,
1787         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1789         .flags          = CLOCK_IN_OMAP343X,
1790         .clkdm          = { .name = "core_l3_clkdm" },
1791         .recalc         = &followparent_recalc,
1792 };
1793
1794 static struct clk sdrc_ick = {
1795         .name           = "sdrc_ick",
1796         .parent         = &core_l3_ick,
1797         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1799         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1800         .clkdm          = { .name = "core_l3_clkdm" },
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk gpmc_fck = {
1805         .name           = "gpmc_fck",
1806         .parent         = &core_l3_ick,
1807         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1808                                 ENABLE_ON_INIT,
1809         .clkdm          = { .name = "core_l3_clkdm" },
1810         .recalc         = &followparent_recalc,
1811 };
1812
1813 /* SECURITY_L3_ICK based clocks */
1814
1815 static struct clk security_l3_ick = {
1816         .name           = "security_l3_ick",
1817         .parent         = &l3_ick,
1818         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1819                                 PARENT_CONTROLS_CLOCK,
1820         .clkdm          = { .name = "core_l3_clkdm" },
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk pka_ick = {
1825         .name           = "pka_ick",
1826         .parent         = &security_l3_ick,
1827         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1828         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1829         .flags          = CLOCK_IN_OMAP343X,
1830         .clkdm          = { .name = "core_l3_clkdm" },
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 /* CORE_L4_ICK based clocks */
1835
1836 static struct clk core_l4_ick = {
1837         .name           = "core_l4_ick",
1838         .parent         = &l4_ick,
1839         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1840                                 PARENT_CONTROLS_CLOCK,
1841         .clkdm          = { .name = "core_l4_clkdm" },
1842         .recalc         = &followparent_recalc,
1843 };
1844
1845 static struct clk usbtll_ick = {
1846         .name           = "usbtll_ick",
1847         .parent         = &core_l4_ick,
1848         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1849         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1850         .flags          = CLOCK_IN_OMAP3430ES2,
1851         .clkdm          = { .name = "core_l4_clkdm" },
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk mmchs3_ick = {
1856         .name           = "mmchs_ick",
1857         .id             = 3,
1858         .parent         = &core_l4_ick,
1859         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1860         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1861         .flags          = CLOCK_IN_OMAP3430ES2,
1862         .clkdm          = { .name = "core_l4_clkdm" },
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 /* Intersystem Communication Registers - chassis mode only */
1867 static struct clk icr_ick = {
1868         .name           = "icr_ick",
1869         .parent         = &core_l4_ick,
1870         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1871         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1872         .flags          = CLOCK_IN_OMAP343X,
1873         .clkdm          = { .name = "core_l4_clkdm" },
1874         .recalc         = &followparent_recalc,
1875 };
1876
1877 static struct clk aes2_ick = {
1878         .name           = "aes2_ick",
1879         .parent         = &core_l4_ick,
1880         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1882         .flags          = CLOCK_IN_OMAP343X,
1883         .clkdm          = { .name = "core_l4_clkdm" },
1884         .recalc         = &followparent_recalc,
1885 };
1886
1887 static struct clk sha12_ick = {
1888         .name           = "sha12_ick",
1889         .parent         = &core_l4_ick,
1890         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1891         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1892         .flags          = CLOCK_IN_OMAP343X,
1893         .clkdm          = { .name = "core_l4_clkdm" },
1894         .recalc         = &followparent_recalc,
1895 };
1896
1897 static struct clk des2_ick = {
1898         .name           = "des2_ick",
1899         .parent         = &core_l4_ick,
1900         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1902         .flags          = CLOCK_IN_OMAP343X,
1903         .clkdm          = { .name = "core_l4_clkdm" },
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mmchs2_ick = {
1908         .name           = "mmchs_ick",
1909         .id             = 2,
1910         .parent         = &core_l4_ick,
1911         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1913         .flags          = CLOCK_IN_OMAP343X,
1914         .clkdm          = { .name = "core_l4_clkdm" },
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk mmchs1_ick = {
1919         .name           = "mmchs_ick",
1920         .id             = 1,
1921         .parent         = &core_l4_ick,
1922         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1924         .flags          = CLOCK_IN_OMAP343X,
1925         .clkdm          = { .name = "core_l4_clkdm" },
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk mspro_ick = {
1930         .name           = "mspro_ick",
1931         .parent         = &core_l4_ick,
1932         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1934         .flags          = CLOCK_IN_OMAP343X,
1935         .clkdm          = { .name = "core_l4_clkdm" },
1936         .recalc         = &followparent_recalc,
1937 };
1938
1939 static struct clk hdq_ick = {
1940         .name           = "hdq_ick",
1941         .parent         = &core_l4_ick,
1942         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1944         .flags          = CLOCK_IN_OMAP343X,
1945         .clkdm          = { .name = "core_l4_clkdm" },
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk mcspi4_ick = {
1950         .name           = "mcspi_ick",
1951         .id             = 4,
1952         .parent         = &core_l4_ick,
1953         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1954         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1955         .flags          = CLOCK_IN_OMAP343X,
1956         .clkdm          = { .name = "core_l4_clkdm" },
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk mcspi3_ick = {
1961         .name           = "mcspi_ick",
1962         .id             = 3,
1963         .parent         = &core_l4_ick,
1964         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1966         .flags          = CLOCK_IN_OMAP343X,
1967         .clkdm          = { .name = "core_l4_clkdm" },
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk mcspi2_ick = {
1972         .name           = "mcspi_ick",
1973         .id             = 2,
1974         .parent         = &core_l4_ick,
1975         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1976         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1977         .flags          = CLOCK_IN_OMAP343X,
1978         .clkdm          = { .name = "core_l4_clkdm" },
1979         .recalc         = &followparent_recalc,
1980 };
1981
1982 static struct clk mcspi1_ick = {
1983         .name           = "mcspi_ick",
1984         .id             = 1,
1985         .parent         = &core_l4_ick,
1986         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1988         .flags          = CLOCK_IN_OMAP343X,
1989         .clkdm          = { .name = "core_l4_clkdm" },
1990         .recalc         = &followparent_recalc,
1991 };
1992
1993 static struct clk i2c3_ick = {
1994         .name           = "i2c_ick",
1995         .id             = 3,
1996         .parent         = &core_l4_ick,
1997         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1999         .flags          = CLOCK_IN_OMAP343X,
2000         .clkdm          = { .name = "core_l4_clkdm" },
2001         .recalc         = &followparent_recalc,
2002 };
2003
2004 static struct clk i2c2_ick = {
2005         .name           = "i2c_ick",
2006         .id             = 2,
2007         .parent         = &core_l4_ick,
2008         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2009         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2010         .flags          = CLOCK_IN_OMAP343X,
2011         .clkdm          = { .name = "core_l4_clkdm" },
2012         .recalc         = &followparent_recalc,
2013 };
2014
2015 static struct clk i2c1_ick = {
2016         .name           = "i2c_ick",
2017         .id             = 1,
2018         .parent         = &core_l4_ick,
2019         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2020         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2021         .flags          = CLOCK_IN_OMAP343X,
2022         .clkdm          = { .name = "core_l4_clkdm" },
2023         .recalc         = &followparent_recalc,
2024 };
2025
2026 static struct clk uart2_ick = {
2027         .name           = "uart2_ick",
2028         .parent         = &core_l4_ick,
2029         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2030         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2031         .flags          = CLOCK_IN_OMAP343X,
2032         .clkdm          = { .name = "core_l4_clkdm" },
2033         .recalc         = &followparent_recalc,
2034 };
2035
2036 static struct clk uart1_ick = {
2037         .name           = "uart1_ick",
2038         .parent         = &core_l4_ick,
2039         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2040         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2041         .flags          = CLOCK_IN_OMAP343X,
2042         .clkdm          = { .name = "core_l4_clkdm" },
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static struct clk gpt11_ick = {
2047         .name           = "gpt11_ick",
2048         .parent         = &core_l4_ick,
2049         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2050         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2051         .flags          = CLOCK_IN_OMAP343X,
2052         .clkdm          = { .name = "core_l4_clkdm" },
2053         .recalc         = &followparent_recalc,
2054 };
2055
2056 static struct clk gpt10_ick = {
2057         .name           = "gpt10_ick",
2058         .parent         = &core_l4_ick,
2059         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2060         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2061         .flags          = CLOCK_IN_OMAP343X,
2062         .clkdm          = { .name = "core_l4_clkdm" },
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk mcbsp5_ick = {
2067         .name           = "mcbsp_ick",
2068         .id             = 5,
2069         .parent         = &core_l4_ick,
2070         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2072         .flags          = CLOCK_IN_OMAP343X,
2073         .clkdm          = { .name = "core_l4_clkdm" },
2074         .recalc         = &followparent_recalc,
2075 };
2076
2077 static struct clk mcbsp1_ick = {
2078         .name           = "mcbsp_ick",
2079         .id             = 1,
2080         .parent         = &core_l4_ick,
2081         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2082         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2083         .flags          = CLOCK_IN_OMAP343X,
2084         .clkdm          = { .name = "core_l4_clkdm" },
2085         .recalc         = &followparent_recalc,
2086 };
2087
2088 static struct clk fac_ick = {
2089         .name           = "fac_ick",
2090         .parent         = &core_l4_ick,
2091         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2092         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2093         .flags          = CLOCK_IN_OMAP3430ES1,
2094         .clkdm          = { .name = "core_l4_clkdm" },
2095         .recalc         = &followparent_recalc,
2096 };
2097
2098 static struct clk mailboxes_ick = {
2099         .name           = "mailboxes_ick",
2100         .parent         = &core_l4_ick,
2101         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2102         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2103         .flags          = CLOCK_IN_OMAP343X,
2104         .clkdm          = { .name = "core_l4_clkdm" },
2105         .recalc         = &followparent_recalc,
2106 };
2107
2108 static struct clk omapctrl_ick = {
2109         .name           = "omapctrl_ick",
2110         .parent         = &core_l4_ick,
2111         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2112         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2113         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2114         .clkdm          = { .name = "core_l4_clkdm" },
2115         .recalc         = &followparent_recalc,
2116 };
2117
2118 /* SSI_L4_ICK based clocks */
2119
2120 static struct clk ssi_l4_ick = {
2121         .name           = "ssi_l4_ick",
2122         .parent         = &l4_ick,
2123         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2124                                 PARENT_CONTROLS_CLOCK,
2125         .clkdm          = { .name = "core_l4_clkdm" },
2126         .recalc         = &followparent_recalc,
2127 };
2128
2129 static struct clk ssi_ick = {
2130         .name           = "ssi_ick",
2131         .parent         = &ssi_l4_ick,
2132         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2133         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2134         .flags          = CLOCK_IN_OMAP343X,
2135         .clkdm          = { .name = "core_l4_clkdm" },
2136         .recalc         = &followparent_recalc,
2137 };
2138
2139 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2140  * but l4_ick makes more sense to me */
2141
2142 static const struct clksel usb_l4_clksel[] = {
2143         { .parent = &l4_ick, .rates = div2_rates },
2144         { .parent = NULL },
2145 };
2146
2147 static struct clk usb_l4_ick = {
2148         .name           = "usb_l4_ick",
2149         .parent         = &l4_ick,
2150         .init           = &omap2_init_clksel_parent,
2151         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2152         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2153         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2154         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2155         .clksel         = usb_l4_clksel,
2156         .flags          = CLOCK_IN_OMAP3430ES1,
2157         .clkdm          = { .name = "core_l4_clkdm" },
2158         .recalc         = &omap2_clksel_recalc,
2159 };
2160
2161 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2162
2163 /* SECURITY_L4_ICK2 based clocks */
2164
2165 static struct clk security_l4_ick2 = {
2166         .name           = "security_l4_ick2",
2167         .parent         = &l4_ick,
2168         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2169                                 PARENT_CONTROLS_CLOCK,
2170         .clkdm          = { .name = "core_l4_clkdm" },
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk aes1_ick = {
2175         .name           = "aes1_ick",
2176         .parent         = &security_l4_ick2,
2177         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2178         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2179         .flags          = CLOCK_IN_OMAP343X,
2180         .clkdm          = { .name = "core_l4_clkdm" },
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 static struct clk rng_ick = {
2185         .name           = "rng_ick",
2186         .parent         = &security_l4_ick2,
2187         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2188         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2189         .flags          = CLOCK_IN_OMAP343X,
2190         .clkdm          = { .name = "core_l4_clkdm" },
2191         .recalc         = &followparent_recalc,
2192 };
2193
2194 static struct clk sha11_ick = {
2195         .name           = "sha11_ick",
2196         .parent         = &security_l4_ick2,
2197         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2198         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2199         .flags          = CLOCK_IN_OMAP343X,
2200         .clkdm          = { .name = "core_l4_clkdm" },
2201         .recalc         = &followparent_recalc,
2202 };
2203
2204 static struct clk des1_ick = {
2205         .name           = "des1_ick",
2206         .parent         = &security_l4_ick2,
2207         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2208         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2209         .flags          = CLOCK_IN_OMAP343X,
2210         .clkdm          = { .name = "core_l4_clkdm" },
2211         .recalc         = &followparent_recalc,
2212 };
2213
2214 /* DSS */
2215 static const struct clksel dss1_alwon_fck_clksel[] = {
2216         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2217         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2218         { .parent = NULL }
2219 };
2220
2221 static struct clk dss1_alwon_fck = {
2222         .name           = "dss1_alwon_fck",
2223         .parent         = &dpll4_m4x2_ck,
2224         .init           = &omap2_init_clksel_parent,
2225         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2226         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2227         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2228         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2229         .clksel         = dss1_alwon_fck_clksel,
2230         .flags          = CLOCK_IN_OMAP343X,
2231         .clkdm          = { .name = "dss_clkdm" },
2232         .recalc         = &omap2_clksel_recalc,
2233 };
2234
2235 static struct clk dss_tv_fck = {
2236         .name           = "dss_tv_fck",
2237         .parent         = &omap_54m_fck,
2238         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2239         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2240         .flags          = CLOCK_IN_OMAP343X,
2241         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk dss_96m_fck = {
2246         .name           = "dss_96m_fck",
2247         .parent         = &omap_96m_fck,
2248         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2249         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2250         .flags          = CLOCK_IN_OMAP343X,
2251         .clkdm          = { .name = "dss_clkdm" },
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 static struct clk dss2_alwon_fck = {
2256         .name           = "dss2_alwon_fck",
2257         .parent         = &sys_ck,
2258         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2259         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2260         .flags          = CLOCK_IN_OMAP343X,
2261         .clkdm          = { .name = "dss_clkdm" },
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 static struct clk dss_ick = {
2266         /* Handles both L3 and L4 clocks */
2267         .name           = "dss_ick",
2268         .parent         = &l4_ick,
2269         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2270         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2271         .flags          = CLOCK_IN_OMAP343X,
2272         .clkdm          = { .name = "dss_clkdm" },
2273         .recalc         = &followparent_recalc,
2274 };
2275
2276 /* CAM */
2277
2278 static const struct clksel cam_mclk_clksel[] = {
2279         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2280         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2281         { .parent = NULL }
2282 };
2283
2284 static struct clk cam_mclk = {
2285         .name           = "cam_mclk",
2286         .parent         = &dpll4_m5x2_ck,
2287         .init           = &omap2_init_clksel_parent,
2288         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2289         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2290         .clksel         = cam_mclk_clksel,
2291         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2292         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2293         .flags          = CLOCK_IN_OMAP343X,
2294         .clkdm          = { .name = "cam_clkdm" },
2295         .recalc         = &omap2_clksel_recalc,
2296 };
2297
2298 static struct clk cam_ick = {
2299         /* Handles both L3 and L4 clocks */
2300         .name           = "cam_ick",
2301         .parent         = &l4_ick,
2302         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2303         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2304         .flags          = CLOCK_IN_OMAP343X,
2305         .clkdm          = { .name = "cam_clkdm" },
2306         .recalc         = &followparent_recalc,
2307 };
2308
2309 static struct clk csi2_96m_fck = {
2310         .name           = "csi2_96m_fck",
2311         .parent         = &core_96m_fck,
2312         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2313         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2314         .flags          = CLOCK_IN_OMAP343X,
2315         .clkdm          = { .name = "cam_clkdm" },
2316         .recalc         = &followparent_recalc,
2317 };
2318
2319 /* USBHOST - 3430ES2 only */
2320
2321 static struct clk usbhost_120m_fck = {
2322         .name           = "usbhost_120m_fck",
2323         .parent         = &omap_120m_fck,
2324         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2325         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2326         .flags          = CLOCK_IN_OMAP3430ES2,
2327         .clkdm          = { .name = "usbhost_clkdm" },
2328         .recalc         = &followparent_recalc,
2329 };
2330
2331 static struct clk usbhost_48m_fck = {
2332         .name           = "usbhost_48m_fck",
2333         .parent         = &omap_48m_fck,
2334         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2335         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2336         .flags          = CLOCK_IN_OMAP3430ES2,
2337         .clkdm          = { .name = "usbhost_clkdm" },
2338         .recalc         = &followparent_recalc,
2339 };
2340
2341 static struct clk usbhost_ick = {
2342         /* Handles both L3 and L4 clocks */
2343         .name           = "usbhost_ick",
2344         .parent         = &l4_ick,
2345         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2346         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2347         .flags          = CLOCK_IN_OMAP3430ES2,
2348         .clkdm          = { .name = "usbhost_clkdm" },
2349         .recalc         = &followparent_recalc,
2350 };
2351
2352 /* WKUP */
2353
2354 static const struct clksel_rate usim_96m_rates[] = {
2355         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2356         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2357         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2358         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2359         { .div = 0 },
2360 };
2361
2362 static const struct clksel_rate usim_120m_rates[] = {
2363         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2364         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2365         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2366         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2367         { .div = 0 },
2368 };
2369
2370 static const struct clksel usim_clksel[] = {
2371         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2372         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2373         { .parent = &sys_ck,            .rates = div2_rates },
2374         { .parent = NULL },
2375 };
2376
2377 /* 3430ES2 only */
2378 static struct clk usim_fck = {
2379         .name           = "usim_fck",
2380         .init           = &omap2_init_clksel_parent,
2381         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2382         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2383         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2384         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2385         .clksel         = usim_clksel,
2386         .flags          = CLOCK_IN_OMAP3430ES2,
2387         .clkdm          = { .name = "prm_clkdm" },
2388         .recalc         = &omap2_clksel_recalc,
2389 };
2390
2391 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2392 static struct clk gpt1_fck = {
2393         .name           = "gpt1_fck",
2394         .init           = &omap2_init_clksel_parent,
2395         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2396         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2397         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2398         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2399         .clksel         = omap343x_gpt_clksel,
2400         .flags          = CLOCK_IN_OMAP343X,
2401         .clkdm          = { .name = "prm_clkdm" },
2402         .recalc         = &omap2_clksel_recalc,
2403 };
2404
2405 static struct clk wkup_32k_fck = {
2406         .name           = "wkup_32k_fck",
2407         .parent         = &omap_32k_fck,
2408         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2409         .clkdm          = { .name = "prm_clkdm" },
2410         .recalc         = &followparent_recalc,
2411 };
2412
2413 static struct clk gpio1_fck = {
2414         .name           = "gpio1_fck",
2415         .parent         = &wkup_32k_fck,
2416         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2417         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2418         .flags          = CLOCK_IN_OMAP343X,
2419         .clkdm          = { .name = "prm_clkdm" },
2420         .recalc         = &followparent_recalc,
2421 };
2422
2423 static struct clk wdt2_fck = {
2424         .name           = "wdt2_fck",
2425         .parent         = &wkup_32k_fck,
2426         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2427         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2428         .flags          = CLOCK_IN_OMAP343X,
2429         .clkdm          = { .name = "prm_clkdm" },
2430         .recalc         = &followparent_recalc,
2431 };
2432
2433 static struct clk wkup_l4_ick = {
2434         .name           = "wkup_l4_ick",
2435         .parent         = &sys_ck,
2436         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2437         .clkdm          = { .name = "prm_clkdm" },
2438         .recalc         = &followparent_recalc,
2439 };
2440
2441 /* 3430ES2 only */
2442 /* Never specifically named in the TRM, so we have to infer a likely name */
2443 static struct clk usim_ick = {
2444         .name           = "usim_ick",
2445         .parent         = &wkup_l4_ick,
2446         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2447         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2448         .flags          = CLOCK_IN_OMAP3430ES2,
2449         .clkdm          = { .name = "prm_clkdm" },
2450         .recalc         = &followparent_recalc,
2451 };
2452
2453 static struct clk wdt2_ick = {
2454         .name           = "wdt2_ick",
2455         .parent         = &wkup_l4_ick,
2456         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2457         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2458         .flags          = CLOCK_IN_OMAP343X,
2459         .clkdm          = { .name = "prm_clkdm" },
2460         .recalc         = &followparent_recalc,
2461 };
2462
2463 static struct clk wdt1_ick = {
2464         .name           = "wdt1_ick",
2465         .parent         = &wkup_l4_ick,
2466         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2467         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2468         .flags          = CLOCK_IN_OMAP343X,
2469         .clkdm          = { .name = "prm_clkdm" },
2470         .recalc         = &followparent_recalc,
2471 };
2472
2473 static struct clk gpio1_ick = {
2474         .name           = "gpio1_ick",
2475         .parent         = &wkup_l4_ick,
2476         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2477         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2478         .flags          = CLOCK_IN_OMAP343X,
2479         .clkdm          = { .name = "prm_clkdm" },
2480         .recalc         = &followparent_recalc,
2481 };
2482
2483 static struct clk omap_32ksync_ick = {
2484         .name           = "omap_32ksync_ick",
2485         .parent         = &wkup_l4_ick,
2486         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2487         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2488         .flags          = CLOCK_IN_OMAP343X,
2489         .clkdm          = { .name = "prm_clkdm" },
2490         .recalc         = &followparent_recalc,
2491 };
2492
2493 static struct clk gpt12_ick = {
2494         .name           = "gpt12_ick",
2495         .parent         = &wkup_l4_ick,
2496         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2497         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2498         .flags          = CLOCK_IN_OMAP343X,
2499         .clkdm          = { .name = "prm_clkdm" },
2500         .recalc         = &followparent_recalc,
2501 };
2502
2503 static struct clk gpt1_ick = {
2504         .name           = "gpt1_ick",
2505         .parent         = &wkup_l4_ick,
2506         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2507         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2508         .flags          = CLOCK_IN_OMAP343X,
2509         .clkdm          = { .name = "prm_clkdm" },
2510         .recalc         = &followparent_recalc,
2511 };
2512
2513
2514
2515 /* PER clock domain */
2516
2517 static struct clk per_96m_fck = {
2518         .name           = "per_96m_fck",
2519         .parent         = &omap_96m_alwon_fck,
2520         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2521                                 PARENT_CONTROLS_CLOCK,
2522         .clkdm          = { .name = "per_clkdm" },
2523         .recalc         = &followparent_recalc,
2524 };
2525
2526 static struct clk per_48m_fck = {
2527         .name           = "per_48m_fck",
2528         .parent         = &omap_48m_fck,
2529         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2530                                 PARENT_CONTROLS_CLOCK,
2531         .clkdm          = { .name = "per_clkdm" },
2532         .recalc         = &followparent_recalc,
2533 };
2534
2535 static struct clk uart3_fck = {
2536         .name           = "uart3_fck",
2537         .parent         = &per_48m_fck,
2538         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2539         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2540         .flags          = CLOCK_IN_OMAP343X,
2541         .clkdm          = { .name = "per_clkdm" },
2542         .recalc         = &followparent_recalc,
2543 };
2544
2545 static struct clk gpt2_fck = {
2546         .name           = "gpt2_fck",
2547         .init           = &omap2_init_clksel_parent,
2548         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2549         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2550         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2551         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2552         .clksel         = omap343x_gpt_clksel,
2553         .flags          = CLOCK_IN_OMAP343X,
2554         .clkdm          = { .name = "per_clkdm" },
2555         .recalc         = &omap2_clksel_recalc,
2556 };
2557
2558 static struct clk gpt3_fck = {
2559         .name           = "gpt3_fck",
2560         .init           = &omap2_init_clksel_parent,
2561         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2562         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2563         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2564         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2565         .clksel         = omap343x_gpt_clksel,
2566         .flags          = CLOCK_IN_OMAP343X,
2567         .clkdm          = { .name = "per_clkdm" },
2568         .recalc         = &omap2_clksel_recalc,
2569 };
2570
2571 static struct clk gpt4_fck = {
2572         .name           = "gpt4_fck",
2573         .init           = &omap2_init_clksel_parent,
2574         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2575         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2576         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2577         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2578         .clksel         = omap343x_gpt_clksel,
2579         .flags          = CLOCK_IN_OMAP343X,
2580         .clkdm          = { .name = "per_clkdm" },
2581         .recalc         = &omap2_clksel_recalc,
2582 };
2583
2584 static struct clk gpt5_fck = {
2585         .name           = "gpt5_fck",
2586         .init           = &omap2_init_clksel_parent,
2587         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2588         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2589         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2590         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2591         .clksel         = omap343x_gpt_clksel,
2592         .flags          = CLOCK_IN_OMAP343X,
2593         .clkdm          = { .name = "per_clkdm" },
2594         .recalc         = &omap2_clksel_recalc,
2595 };
2596
2597 static struct clk gpt6_fck = {
2598         .name           = "gpt6_fck",
2599         .init           = &omap2_init_clksel_parent,
2600         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2601         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2602         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2603         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2604         .clksel         = omap343x_gpt_clksel,
2605         .flags          = CLOCK_IN_OMAP343X,
2606         .clkdm          = { .name = "per_clkdm" },
2607         .recalc         = &omap2_clksel_recalc,
2608 };
2609
2610 static struct clk gpt7_fck = {
2611         .name           = "gpt7_fck",
2612         .init           = &omap2_init_clksel_parent,
2613         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2614         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2615         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2616         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2617         .clksel         = omap343x_gpt_clksel,
2618         .flags          = CLOCK_IN_OMAP343X,
2619         .clkdm          = { .name = "per_clkdm" },
2620         .recalc         = &omap2_clksel_recalc,
2621 };
2622
2623 static struct clk gpt8_fck = {
2624         .name           = "gpt8_fck",
2625         .init           = &omap2_init_clksel_parent,
2626         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2627         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2628         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2629         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2630         .clksel         = omap343x_gpt_clksel,
2631         .flags          = CLOCK_IN_OMAP343X,
2632         .clkdm          = { .name = "per_clkdm" },
2633         .recalc         = &omap2_clksel_recalc,
2634 };
2635
2636 static struct clk gpt9_fck = {
2637         .name           = "gpt9_fck",
2638         .init           = &omap2_init_clksel_parent,
2639         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2640         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2641         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2642         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2643         .clksel         = omap343x_gpt_clksel,
2644         .flags          = CLOCK_IN_OMAP343X,
2645         .clkdm          = { .name = "per_clkdm" },
2646         .recalc         = &omap2_clksel_recalc,
2647 };
2648
2649 static struct clk per_32k_alwon_fck = {
2650         .name           = "per_32k_alwon_fck",
2651         .parent         = &omap_32k_fck,
2652         .clkdm          = { .name = "per_clkdm" },
2653         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2654         .recalc         = &followparent_recalc,
2655 };
2656
2657 static struct clk gpio6_fck = {
2658         .name           = "gpio6_fck",
2659         .parent         = &per_32k_alwon_fck,
2660         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2661         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2662         .flags          = CLOCK_IN_OMAP343X,
2663         .clkdm          = { .name = "per_clkdm" },
2664         .recalc         = &followparent_recalc,
2665 };
2666
2667 static struct clk gpio5_fck = {
2668         .name           = "gpio5_fck",
2669         .parent         = &per_32k_alwon_fck,
2670         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2671         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2672         .flags          = CLOCK_IN_OMAP343X,
2673         .clkdm          = { .name = "per_clkdm" },
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static struct clk gpio4_fck = {
2678         .name           = "gpio4_fck",
2679         .parent         = &per_32k_alwon_fck,
2680         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2681         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2682         .flags          = CLOCK_IN_OMAP343X,
2683         .clkdm          = { .name = "per_clkdm" },
2684         .recalc         = &followparent_recalc,
2685 };
2686
2687 static struct clk gpio3_fck = {
2688         .name           = "gpio3_fck",
2689         .parent         = &per_32k_alwon_fck,
2690         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2691         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2692         .flags          = CLOCK_IN_OMAP343X,
2693         .clkdm          = { .name = "per_clkdm" },
2694         .recalc         = &followparent_recalc,
2695 };
2696
2697 static struct clk gpio2_fck = {
2698         .name           = "gpio2_fck",
2699         .parent         = &per_32k_alwon_fck,
2700         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2701         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2702         .flags          = CLOCK_IN_OMAP343X,
2703         .clkdm          = { .name = "per_clkdm" },
2704         .recalc         = &followparent_recalc,
2705 };
2706
2707 static struct clk wdt3_fck = {
2708         .name           = "wdt3_fck",
2709         .parent         = &per_32k_alwon_fck,
2710         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2711         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2712         .flags          = CLOCK_IN_OMAP343X,
2713         .clkdm          = { .name = "per_clkdm" },
2714         .recalc         = &followparent_recalc,
2715 };
2716
2717 static struct clk per_l4_ick = {
2718         .name           = "per_l4_ick",
2719         .parent         = &l4_ick,
2720         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2721                                 PARENT_CONTROLS_CLOCK,
2722         .clkdm          = { .name = "per_clkdm" },
2723         .recalc         = &followparent_recalc,
2724 };
2725
2726 static struct clk gpio6_ick = {
2727         .name           = "gpio6_ick",
2728         .parent         = &per_l4_ick,
2729         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2730         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2731         .flags          = CLOCK_IN_OMAP343X,
2732         .clkdm          = { .name = "per_clkdm" },
2733         .recalc         = &followparent_recalc,
2734 };
2735
2736 static struct clk gpio5_ick = {
2737         .name           = "gpio5_ick",
2738         .parent         = &per_l4_ick,
2739         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2740         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2741         .flags          = CLOCK_IN_OMAP343X,
2742         .clkdm          = { .name = "per_clkdm" },
2743         .recalc         = &followparent_recalc,
2744 };
2745
2746 static struct clk gpio4_ick = {
2747         .name           = "gpio4_ick",
2748         .parent         = &per_l4_ick,
2749         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2750         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2751         .flags          = CLOCK_IN_OMAP343X,
2752         .clkdm          = { .name = "per_clkdm" },
2753         .recalc         = &followparent_recalc,
2754 };
2755
2756 static struct clk gpio3_ick = {
2757         .name           = "gpio3_ick",
2758         .parent         = &per_l4_ick,
2759         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2760         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2761         .flags          = CLOCK_IN_OMAP343X,
2762         .clkdm          = { .name = "per_clkdm" },
2763         .recalc         = &followparent_recalc,
2764 };
2765
2766 static struct clk gpio2_ick = {
2767         .name           = "gpio2_ick",
2768         .parent         = &per_l4_ick,
2769         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2770         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2771         .flags          = CLOCK_IN_OMAP343X,
2772         .clkdm          = { .name = "per_clkdm" },
2773         .recalc         = &followparent_recalc,
2774 };
2775
2776 static struct clk wdt3_ick = {
2777         .name           = "wdt3_ick",
2778         .parent         = &per_l4_ick,
2779         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2780         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2781         .flags          = CLOCK_IN_OMAP343X,
2782         .clkdm          = { .name = "per_clkdm" },
2783         .recalc         = &followparent_recalc,
2784 };
2785
2786 static struct clk uart3_ick = {
2787         .name           = "uart3_ick",
2788         .parent         = &per_l4_ick,
2789         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2790         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2791         .flags          = CLOCK_IN_OMAP343X,
2792         .clkdm          = { .name = "per_clkdm" },
2793         .recalc         = &followparent_recalc,
2794 };
2795
2796 static struct clk gpt9_ick = {
2797         .name           = "gpt9_ick",
2798         .parent         = &per_l4_ick,
2799         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2800         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2801         .flags          = CLOCK_IN_OMAP343X,
2802         .clkdm          = { .name = "per_clkdm" },
2803         .recalc         = &followparent_recalc,
2804 };
2805
2806 static struct clk gpt8_ick = {
2807         .name           = "gpt8_ick",
2808         .parent         = &per_l4_ick,
2809         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2810         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2811         .flags          = CLOCK_IN_OMAP343X,
2812         .clkdm          = { .name = "per_clkdm" },
2813         .recalc         = &followparent_recalc,
2814 };
2815
2816 static struct clk gpt7_ick = {
2817         .name           = "gpt7_ick",
2818         .parent         = &per_l4_ick,
2819         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2820         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2821         .flags          = CLOCK_IN_OMAP343X,
2822         .clkdm          = { .name = "per_clkdm" },
2823         .recalc         = &followparent_recalc,
2824 };
2825
2826 static struct clk gpt6_ick = {
2827         .name           = "gpt6_ick",
2828         .parent         = &per_l4_ick,
2829         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2830         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2831         .flags          = CLOCK_IN_OMAP343X,
2832         .clkdm          = { .name = "per_clkdm" },
2833         .recalc         = &followparent_recalc,
2834 };
2835
2836 static struct clk gpt5_ick = {
2837         .name           = "gpt5_ick",
2838         .parent         = &per_l4_ick,
2839         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2840         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2841         .flags          = CLOCK_IN_OMAP343X,
2842         .clkdm          = { .name = "per_clkdm" },
2843         .recalc         = &followparent_recalc,
2844 };
2845
2846 static struct clk gpt4_ick = {
2847         .name           = "gpt4_ick",
2848         .parent         = &per_l4_ick,
2849         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2850         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2851         .flags          = CLOCK_IN_OMAP343X,
2852         .clkdm          = { .name = "per_clkdm" },
2853         .recalc         = &followparent_recalc,
2854 };
2855
2856 static struct clk gpt3_ick = {
2857         .name           = "gpt3_ick",
2858         .parent         = &per_l4_ick,
2859         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2860         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2861         .flags          = CLOCK_IN_OMAP343X,
2862         .clkdm          = { .name = "per_clkdm" },
2863         .recalc         = &followparent_recalc,
2864 };
2865
2866 static struct clk gpt2_ick = {
2867         .name           = "gpt2_ick",
2868         .parent         = &per_l4_ick,
2869         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2870         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2871         .flags          = CLOCK_IN_OMAP343X,
2872         .clkdm          = { .name = "per_clkdm" },
2873         .recalc         = &followparent_recalc,
2874 };
2875
2876 static struct clk mcbsp2_ick = {
2877         .name           = "mcbsp_ick",
2878         .id             = 2,
2879         .parent         = &per_l4_ick,
2880         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2881         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2882         .flags          = CLOCK_IN_OMAP343X,
2883         .clkdm          = { .name = "per_clkdm" },
2884         .recalc         = &followparent_recalc,
2885 };
2886
2887 static struct clk mcbsp3_ick = {
2888         .name           = "mcbsp_ick",
2889         .id             = 3,
2890         .parent         = &per_l4_ick,
2891         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2892         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2893         .flags          = CLOCK_IN_OMAP343X,
2894         .clkdm          = { .name = "per_clkdm" },
2895         .recalc         = &followparent_recalc,
2896 };
2897
2898 static struct clk mcbsp4_ick = {
2899         .name           = "mcbsp_ick",
2900         .id             = 4,
2901         .parent         = &per_l4_ick,
2902         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2903         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2904         .flags          = CLOCK_IN_OMAP343X,
2905         .clkdm          = { .name = "per_clkdm" },
2906         .recalc         = &followparent_recalc,
2907 };
2908
2909 static const struct clksel mcbsp_234_clksel[] = {
2910         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2911         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2912         { .parent = NULL }
2913 };
2914
2915 static struct clk mcbsp2_fck = {
2916         .name           = "mcbsp_fck",
2917         .id             = 2,
2918         .init           = &omap2_init_clksel_parent,
2919         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2920         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2921         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2922         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2923         .clksel         = mcbsp_234_clksel,
2924         .flags          = CLOCK_IN_OMAP343X,
2925         .clkdm          = { .name = "per_clkdm" },
2926         .recalc         = &omap2_clksel_recalc,
2927 };
2928
2929 static struct clk mcbsp3_fck = {
2930         .name           = "mcbsp_fck",
2931         .id             = 3,
2932         .init           = &omap2_init_clksel_parent,
2933         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2934         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2935         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2936         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2937         .clksel         = mcbsp_234_clksel,
2938         .flags          = CLOCK_IN_OMAP343X,
2939         .clkdm          = { .name = "per_clkdm" },
2940         .recalc         = &omap2_clksel_recalc,
2941 };
2942
2943 static struct clk mcbsp4_fck = {
2944         .name           = "mcbsp_fck",
2945         .id             = 4,
2946         .init           = &omap2_init_clksel_parent,
2947         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2948         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2949         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2950         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2951         .clksel         = mcbsp_234_clksel,
2952         .flags          = CLOCK_IN_OMAP343X,
2953         .clkdm          = { .name = "per_clkdm" },
2954         .recalc         = &omap2_clksel_recalc,
2955 };
2956
2957 /* EMU clocks */
2958
2959 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2960
2961 static const struct clksel_rate emu_src_sys_rates[] = {
2962         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2963         { .div = 0 },
2964 };
2965
2966 static const struct clksel_rate emu_src_core_rates[] = {
2967         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2968         { .div = 0 },
2969 };
2970
2971 static const struct clksel_rate emu_src_per_rates[] = {
2972         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2973         { .div = 0 },
2974 };
2975
2976 static const struct clksel_rate emu_src_mpu_rates[] = {
2977         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2978         { .div = 0 },
2979 };
2980
2981 static const struct clksel emu_src_clksel[] = {
2982         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2983         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2984         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2985         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2986         { .parent = NULL },
2987 };
2988
2989 /*
2990  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2991  * to switch the source of some of the EMU clocks.
2992  * XXX Are there CLKEN bits for these EMU clks?
2993  */
2994 static struct clk emu_src_ck = {
2995         .name           = "emu_src_ck",
2996         .init           = &omap2_init_clksel_parent,
2997         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2998         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2999         .clksel         = emu_src_clksel,
3000         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3001         .clkdm          = { .name = "emu_clkdm" },
3002         .recalc         = &omap2_clksel_recalc,
3003 };
3004
3005 static const struct clksel_rate pclk_emu_rates[] = {
3006         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3007         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3008         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3009         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3010         { .div = 0 },
3011 };
3012
3013 static const struct clksel pclk_emu_clksel[] = {
3014         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3015         { .parent = NULL },
3016 };
3017
3018 static struct clk pclk_fck = {
3019         .name           = "pclk_fck",
3020         .init           = &omap2_init_clksel_parent,
3021         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3022         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3023         .clksel         = pclk_emu_clksel,
3024         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3025         .clkdm          = { .name = "emu_clkdm" },
3026         .recalc         = &omap2_clksel_recalc,
3027 };
3028
3029 static const struct clksel_rate pclkx2_emu_rates[] = {
3030         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3031         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3032         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3033         { .div = 0 },
3034 };
3035
3036 static const struct clksel pclkx2_emu_clksel[] = {
3037         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3038         { .parent = NULL },
3039 };
3040
3041 static struct clk pclkx2_fck = {
3042         .name           = "pclkx2_fck",
3043         .init           = &omap2_init_clksel_parent,
3044         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3045         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3046         .clksel         = pclkx2_emu_clksel,
3047         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3048         .clkdm          = { .name = "emu_clkdm" },
3049         .recalc         = &omap2_clksel_recalc,
3050 };
3051
3052 static const struct clksel atclk_emu_clksel[] = {
3053         { .parent = &emu_src_ck, .rates = div2_rates },
3054         { .parent = NULL },
3055 };
3056
3057 static struct clk atclk_fck = {
3058         .name           = "atclk_fck",
3059         .init           = &omap2_init_clksel_parent,
3060         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3061         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3062         .clksel         = atclk_emu_clksel,
3063         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3064         .clkdm          = { .name = "emu_clkdm" },
3065         .recalc         = &omap2_clksel_recalc,
3066 };
3067
3068 static struct clk traceclk_src_fck = {
3069         .name           = "traceclk_src_fck",
3070         .init           = &omap2_init_clksel_parent,
3071         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3072         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3073         .clksel         = emu_src_clksel,
3074         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3075         .clkdm          = { .name = "emu_clkdm" },
3076         .recalc         = &omap2_clksel_recalc,
3077 };
3078
3079 static const struct clksel_rate traceclk_rates[] = {
3080         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3081         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3082         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3083         { .div = 0 },
3084 };
3085
3086 static const struct clksel traceclk_clksel[] = {
3087         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3088         { .parent = NULL },
3089 };
3090
3091 static struct clk traceclk_fck = {
3092         .name           = "traceclk_fck",
3093         .init           = &omap2_init_clksel_parent,
3094         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3095         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3096         .clksel         = traceclk_clksel,
3097         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3098         .clkdm          = { .name = "emu_clkdm" },
3099         .recalc         = &omap2_clksel_recalc,
3100 };
3101
3102 /* SR clocks */
3103
3104 /* SmartReflex fclk (VDD1) */
3105 static struct clk sr1_fck = {
3106         .name           = "sr1_fck",
3107         .parent         = &sys_ck,
3108         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3109         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3110         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3111         .clkdm          = { .name = "prm_clkdm" },
3112         .recalc         = &followparent_recalc,
3113 };
3114
3115 /* SmartReflex fclk (VDD2) */
3116 static struct clk sr2_fck = {
3117         .name           = "sr2_fck",
3118         .parent         = &sys_ck,
3119         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3120         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3121         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3122         .clkdm          = { .name = "prm_clkdm" },
3123         .recalc         = &followparent_recalc,
3124 };
3125
3126 static struct clk sr_l4_ick = {
3127         .name           = "sr_l4_ick",
3128         .parent         = &l4_ick,
3129         .flags          = CLOCK_IN_OMAP343X,
3130         .clkdm          = { .name = "core_l4_clkdm" },
3131         .recalc         = &followparent_recalc,
3132 };
3133
3134 /* SECURE_32K_FCK clocks */
3135
3136 /* XXX This clock no longer exists in 3430 TRM rev F */
3137 static struct clk gpt12_fck = {
3138         .name           = "gpt12_fck",
3139         .parent         = &secure_32k_fck,
3140         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3141         .clkdm          = { .name = "prm_clkdm" },
3142         .recalc         = &followparent_recalc,
3143 };
3144
3145 static struct clk wdt1_fck = {
3146         .name           = "wdt1_fck",
3147         .parent         = &secure_32k_fck,
3148         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3149         .clkdm          = { .name = "prm_clkdm" },
3150         .recalc         = &followparent_recalc,
3151 };
3152
3153 static struct clk *onchip_34xx_clks[] __initdata = {
3154         &omap_32k_fck,
3155         &virt_12m_ck,
3156         &virt_13m_ck,
3157         &virt_16_8m_ck,
3158         &virt_19_2m_ck,
3159         &virt_26m_ck,
3160         &virt_38_4m_ck,
3161         &osc_sys_ck,
3162         &sys_ck,
3163         &sys_altclk,
3164         &mcbsp_clks,
3165         &sys_clkout1,
3166         &dpll1_ck,
3167         &dpll1_x2_ck,
3168         &dpll1_x2m2_ck,
3169         &dpll2_ck,
3170         &dpll2_m2_ck,
3171         &dpll3_ck,
3172         &core_ck,
3173         &dpll3_x2_ck,
3174         &dpll3_m2_ck,
3175         &dpll3_m2x2_ck,
3176         &dpll3_m3_ck,
3177         &dpll3_m3x2_ck,
3178         &emu_core_alwon_ck,
3179         &dpll4_ck,
3180         &dpll4_x2_ck,
3181         &omap_96m_alwon_fck,
3182         &omap_96m_fck,
3183         &cm_96m_fck,
3184         &virt_omap_54m_fck,
3185         &omap_54m_fck,
3186         &omap_48m_fck,
3187         &omap_12m_fck,
3188         &dpll4_m2_ck,
3189         &dpll4_m2x2_ck,
3190         &dpll4_m3_ck,
3191         &dpll4_m3x2_ck,
3192         &dpll4_m4_ck,
3193         &dpll4_m4x2_ck,
3194         &dpll4_m5_ck,
3195         &dpll4_m5x2_ck,
3196         &dpll4_m6_ck,
3197         &dpll4_m6x2_ck,
3198         &emu_per_alwon_ck,
3199         &dpll5_ck,
3200         &dpll5_m2_ck,
3201         &omap_120m_fck,
3202         &clkout2_src_ck,
3203         &sys_clkout2,
3204         &corex2_fck,
3205         &dpll1_fck,
3206         &mpu_ck,
3207         &arm_fck,
3208         &emu_mpu_alwon_ck,
3209         &dpll2_fck,
3210         &iva2_ck,
3211         &l3_ick,
3212         &l4_ick,
3213         &rm_ick,
3214         &gfx_l3_ck,
3215         &gfx_l3_fck,
3216         &gfx_l3_ick,
3217         &gfx_cg1_ck,
3218         &gfx_cg2_ck,
3219         &sgx_fck,
3220         &sgx_ick,
3221         &d2d_26m_fck,
3222         &gpt10_fck,
3223         &gpt11_fck,
3224         &cpefuse_fck,
3225         &ts_fck,
3226         &usbtll_fck,
3227         &core_96m_fck,
3228         &mmchs3_fck,
3229         &mmchs2_fck,
3230         &mspro_fck,
3231         &mmchs1_fck,
3232         &i2c3_fck,
3233         &i2c2_fck,
3234         &i2c1_fck,
3235         &mcbsp5_fck,
3236         &mcbsp1_fck,
3237         &core_48m_fck,
3238         &mcspi4_fck,
3239         &mcspi3_fck,
3240         &mcspi2_fck,
3241         &mcspi1_fck,
3242         &uart2_fck,
3243         &uart1_fck,
3244         &fshostusb_fck,
3245         &core_12m_fck,
3246         &hdq_fck,
3247         &ssi_ssr_fck,
3248         &ssi_sst_fck,
3249         &core_l3_ick,
3250         &hsotgusb_ick,
3251         &sdrc_ick,
3252         &gpmc_fck,
3253         &security_l3_ick,
3254         &pka_ick,
3255         &core_l4_ick,
3256         &usbtll_ick,
3257         &mmchs3_ick,
3258         &icr_ick,
3259         &aes2_ick,
3260         &sha12_ick,
3261         &des2_ick,
3262         &mmchs2_ick,
3263         &mmchs1_ick,
3264         &mspro_ick,
3265         &hdq_ick,
3266         &mcspi4_ick,
3267         &mcspi3_ick,
3268         &mcspi2_ick,
3269         &mcspi1_ick,
3270         &i2c3_ick,
3271         &i2c2_ick,
3272         &i2c1_ick,
3273         &uart2_ick,
3274         &uart1_ick,
3275         &gpt11_ick,
3276         &gpt10_ick,
3277         &mcbsp5_ick,
3278         &mcbsp1_ick,
3279         &fac_ick,
3280         &mailboxes_ick,
3281         &omapctrl_ick,
3282         &ssi_l4_ick,
3283         &ssi_ick,
3284         &usb_l4_ick,
3285         &security_l4_ick2,
3286         &aes1_ick,
3287         &rng_ick,
3288         &sha11_ick,
3289         &des1_ick,
3290         &dss1_alwon_fck,
3291         &dss_tv_fck,
3292         &dss_96m_fck,
3293         &dss2_alwon_fck,
3294         &dss_ick,
3295         &cam_mclk,
3296         &cam_ick,
3297         &csi2_96m_fck,
3298         &usbhost_120m_fck,
3299         &usbhost_48m_fck,
3300         &usbhost_ick,
3301         &usim_fck,
3302         &gpt1_fck,
3303         &wkup_32k_fck,
3304         &gpio1_fck,
3305         &wdt2_fck,
3306         &wkup_l4_ick,
3307         &usim_ick,
3308         &wdt2_ick,
3309         &wdt1_ick,
3310         &gpio1_ick,
3311         &omap_32ksync_ick,
3312         &gpt12_ick,
3313         &gpt1_ick,
3314         &per_96m_fck,
3315         &per_48m_fck,
3316         &uart3_fck,
3317         &gpt2_fck,
3318         &gpt3_fck,
3319         &gpt4_fck,
3320         &gpt5_fck,
3321         &gpt6_fck,
3322         &gpt7_fck,
3323         &gpt8_fck,
3324         &gpt9_fck,
3325         &per_32k_alwon_fck,
3326         &gpio6_fck,
3327         &gpio5_fck,
3328         &gpio4_fck,
3329         &gpio3_fck,
3330         &gpio2_fck,
3331         &wdt3_fck,
3332         &per_l4_ick,
3333         &gpio6_ick,
3334         &gpio5_ick,
3335         &gpio4_ick,
3336         &gpio3_ick,
3337         &gpio2_ick,
3338         &wdt3_ick,
3339         &uart3_ick,
3340         &gpt9_ick,
3341         &gpt8_ick,
3342         &gpt7_ick,
3343         &gpt6_ick,
3344         &gpt5_ick,
3345         &gpt4_ick,
3346         &gpt3_ick,
3347         &gpt2_ick,
3348         &mcbsp2_ick,
3349         &mcbsp3_ick,
3350         &mcbsp4_ick,
3351         &mcbsp2_fck,
3352         &mcbsp3_fck,
3353         &mcbsp4_fck,
3354         &emu_src_ck,
3355         &pclk_fck,
3356         &pclkx2_fck,
3357         &atclk_fck,
3358         &traceclk_src_fck,
3359         &traceclk_fck,
3360         &sr1_fck,
3361         &sr2_fck,
3362         &sr_l4_ick,
3363         &secure_32k_fck,
3364         &gpt12_fck,
3365         &wdt1_fck,
3366 };
3367
3368 #endif