arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  */
   9
  10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  11 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  12
  13 #include "clock.h"
  14 #include "cm.h"
  15 #include "cm_regbits_34xx.h"
  16 #include "prm.h"
  17 #include "prm_regbits_34xx.h"
  18 #include "control.h"
  19
  20 static void omap3_dpll_recalc(struct clk *clk);
  21 static void omap3_clkoutx2_recalc(struct clk *clk);
  22
  23 /*
  24  * DPLL1 supplies clock to the MPU.
  25  * DPLL2 supplies clock to the IVA2.
  26  * DPLL3 supplies CORE domain clocks.
  27  * DPLL4 supplies peripheral clocks.
  28  */
  29
  30 /* PRM CLOCKS */
  31
  32 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  33 static struct clk omap_32k_fck = {
  34         .name           = "omap_32k_fck",
  35         .rate           = 32768,
  36         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  37                                 ALWAYS_ENABLED,
  38         .recalc         = &propagate_rate,
  39 };
  40
  41 static struct clk secure_32k_fck = {
  42         .name           = "secure_32k_fck",
  43         .rate           = 32768,
  44         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  45                                 ALWAYS_ENABLED,
  46         .recalc         = &propagate_rate,
  47 };
  48
  49 /* Virtual source clocks for osc_sys_ck */
  50 static struct clk virt_12m_ck = {
  51         .name           = "virt_12m_ck",
  52         .rate           = 12000000,
  53         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  54                                 ALWAYS_ENABLED,
  55         .recalc         = &propagate_rate,
  56 };
  57
  58 static struct clk virt_13m_ck = {
  59         .name           = "virt_13m_ck",
  60         .rate           = 13000000,
  61         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  62                                 ALWAYS_ENABLED,
  63         .recalc         = &propagate_rate,
  64 };
  65
  66 /* 3430ES2 only */
  67 static struct clk virt_16_8m_ck = {
  68         .name           = "virt_16_8m_ck",
  69         .rate           = 16800000,
  70         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  71                                 ALWAYS_ENABLED,
  72         .recalc         = &propagate_rate,
  73 };
  74
  75 static struct clk virt_19_2m_ck = {
  76         .name           = "virt_19_2m_ck",
  77         .rate           = 19200000,
  78         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  79                                 ALWAYS_ENABLED,
  80         .recalc         = &propagate_rate,
  81 };
  82
  83 static struct clk virt_26m_ck = {
  84         .name           = "virt_26m_ck",
  85         .rate           = 26000000,
  86         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  87                                 ALWAYS_ENABLED,
  88         .recalc         = &propagate_rate,
  89 };
  90
  91 static struct clk virt_38_4m_ck = {
  92         .name           = "virt_38_4m_ck",
  93         .rate           = 38400000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .recalc         = &propagate_rate,
  97 };
  98
  99 static const struct clksel_rate osc_sys_12m_rates[] = {
 100         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 101         { .div = 0 }
 102 };
 103
 104 static const struct clksel_rate osc_sys_13m_rates[] = {
 105         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 106         { .div = 0 }
 107 };
 108
 109 /* 3430ES2 only */
 110 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 111         { .div = 1, .val = 5, .flags = RATE_IN_343X | DEFAULT_RATE },
 112         { .div = 0 }
 113 };
 114
 115 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 116         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 117         { .div = 0 }
 118 };
 119
 120 static const struct clksel_rate osc_sys_26m_rates[] = {
 121         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 122         { .div = 0 }
 123 };
 124
 125 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 126         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 127         { .div = 0 }
 128 };
 129
 130 static const struct clksel osc_sys_clksel[] = {
 131         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 132         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 133         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 134         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 135         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 136         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 137         { .parent = NULL },
 138 };
 139
 140 /* Oscillator clock */
 141 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 142 static struct clk osc_sys_ck = {
 143         .name           = "osc_sys_ck",
 144         .init           = &omap2_init_clksel_parent,
 145         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 146         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 147         .clksel         = osc_sys_clksel,
 148         /* REVISIT: deal with autoextclkmode? */
 149         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 150                                 ALWAYS_ENABLED,
 151         .recalc         = &omap2_clksel_recalc,
 152 };
 153
 154 static const struct clksel_rate sys_osc_rates[] = {
 155         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 156         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel sys_clksel[] = {
 161         { .parent = &osc_sys_ck, .rates = sys_osc_rates },
 162         { .parent = NULL }
 163 };
 164
 165 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 166 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 167 static struct clk sys_ck = {
 168         .name           = "sys_ck",
 169         .parent         = &osc_sys_ck,
 170         .init           = &omap2_init_clksel_parent,
 171         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 172         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 173         .clksel         = sys_clksel,
 174         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 175         .recalc         = &omap2_clksel_recalc,
 176 };
 177
 178 static struct clk sys_altclk = {
 179         .name           = "sys_altclk",
 180         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 181         .recalc         = &propagate_rate,
 182 };
 183
 184 /* Optional external clock input for some McBSPs */
 185 static struct clk mcbsp_clks = {
 186         .name           = "mcbsp_clks",
 187         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 188         .recalc         = &propagate_rate,
 189 };
 190
 191 /* PRM EXTERNAL CLOCK OUTPUT */
 192
 193 static struct clk sys_clkout1 = {
 194         .name           = "sys_clkout1",
 195         .parent         = &osc_sys_ck,
 196         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 197         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 198         .flags          = CLOCK_IN_OMAP343X,
 199         .recalc         = &followparent_recalc,
 200 };
 201
 202 /* DPLLS */
 203
 204 /* CM CLOCKS */
 205
 206 /* DPLL1 */
 207 /* MPU clock source */
 208 /* Type: DPLL */
 209 static const struct dpll_data dpll1_dd = {
 210         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 211         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 212         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 213         .div2_reg       = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 214         .div2_mask      = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 215         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 216         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 217         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 218         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 219         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 220 };
 221
 222 static struct clk dpll1_ck = {
 223         .name           = "dpll1_ck",
 224         .parent         = &sys_ck,
 225         .dpll_data      = &dpll1_dd,
 226         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 227         .recalc         = &omap3_dpll_recalc,
 228 };
 229
 230 /*
 231  * REVISIT: This clock is never specifically defined in the 3430 TRM,
 232  * although it is referenced - so this is a guess
 233  */
 234 static struct clk emu_mpu_alwon_ck = {
 235         .name           = "emu_mpu_alwon_ck",
 236         .parent         = &dpll1_ck,
 237         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 238         .recalc         = &followparent_recalc,
 239 };
 240
 241 /* DPLL2 */
 242 /* IVA2 clock source */
 243 /* Type: DPLL */
 244
 245 static const struct dpll_data dpll2_dd = {
 246         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 247         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 248         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 249         .div2_reg       = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
 250         .div2_mask      = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 251         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 252         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 253         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 254         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 255         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 256 };
 257
 258 static struct clk dpll2_ck = {
 259         .name           = "dpll2_ck",
 260         .parent         = &sys_ck,
 261         .dpll_data      = &dpll2_dd,
 262         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 263         .recalc         = &omap3_dpll_recalc,
 264 };
 265
 266 /* DPLL3 */
 267 /* Source clock for all interfaces and for some device fclks */
 268 /* Type: DPLL */
 269 static const struct dpll_data dpll3_dd = {
 270         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 271         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 272         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 273         .div2_reg       = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 274         .div2_mask      = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 275         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 276         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 277         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 278         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 279         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 280 };
 281
 282 static struct clk dpll3_ck = {
 283         .name           = "dpll3_ck",
 284         .parent         = &sys_ck,
 285         .dpll_data      = &dpll3_dd,
 286         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 287         .recalc         = &omap3_dpll_recalc,
 288 };
 289
 290 static const struct clksel_rate div16_dpll_rates[] = {
 291         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 292         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 293         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 294         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 295         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 296         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 297         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 298         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 299         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 300         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 301         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 302         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 303         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 304         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 305         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 306         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 307         { .div = 0 }
 308 };
 309
 310 static const struct clksel_rate div2_rates[] = {
 311         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 312         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 313         { .div = 0 },
 314 };
 315
 316 static const struct clksel div2_dpll3m2_clksel[] = {
 317         { .parent = &dpll3_ck, .rates = div2_rates },
 318         { .parent = NULL }
 319 };
 320
 321 /*
 322  * REVISIT: Not sure what to do about clksel & these M2 divider clocks.
 323  * Shouldn't they be changed in SRAM?
 324  * This should probably remain a 'read-only' clksel clock.
 325  */
 326 static struct clk dpll3_m2_ck = {
 327         .name           = "dpll3_m2_ck",
 328         .parent         = &dpll3_ck,
 329         .init           = &omap2_init_clksel_parent,
 330         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 331         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 332         .clksel         = div2_dpll3m2_clksel,
 333         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 334         .recalc         = &omap2_clksel_recalc,
 335 };
 336
 337 static struct clk core_ck = {
 338         .name           = "core_ck",
 339         .parent         = &dpll3_m2_ck,
 340         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 341         .recalc         = &followparent_recalc,
 342 };
 343
 344 /*
 345  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 346  * DPLL isn't bypassed
 347  */
 348 static struct clk dpll3_x2_ck = {
 349         .name           = "dpll3_x2_ck",
 350         .parent         = &core_ck,
 351         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 352         .recalc         = &omap3_clkoutx2_recalc,
 353 };
 354
 355 static struct clk dpll3_m2x2_ck = {
 356         .name           = "dpll3_m2x2_ck",
 357         .parent         = &dpll3_x2_ck,
 358         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 359         .recalc         = &followparent_recalc,
 360 };
 361
 362 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 363 static struct clk dpll3_m3x2_ck = {
 364         .name           = "dpll3_m3x2_ck",
 365         .parent         = &dpll3_x2_ck,
 366         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 367         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 368         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 369         .recalc         = &followparent_recalc,
 370 };
 371
 372 static const struct clksel div16_dpll3_clksel[] = {
 373         { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates },
 374         { .parent = NULL }
 375 };
 376
 377 static struct clk emu_core_alwon_ck = {
 378         .name           = "emu_core_alwon_ck",
 379         .parent         = &dpll3_x2_ck,
 380         .init           = &omap2_init_clksel_parent,
 381         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 382         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 383         .clksel         = div16_dpll3_clksel,
 384         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 385         .recalc         = &followparent_recalc,
 386 };
 387
 388 /* DPLL4 */
 389 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 390 /* Type: DPLL */
 391 static const struct dpll_data dpll4_dd = {
 392         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 393         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 394         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 395         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 396         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 397         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 398         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 399         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 400 };
 401
 402 static struct clk dpll4_ck = {
 403         .name           = "dpll4_ck",
 404         .parent         = &sys_ck,
 405         .dpll_data      = &dpll4_dd,
 406         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 407         .recalc         = &omap3_dpll_recalc,
 408 };
 409
 410 /*
 411  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 412  * DPLL isn't bypassed
 413  */
 414 static struct clk dpll4_x2_ck = {
 415         .name           = "dpll4_x2_ck",
 416         .parent         = &dpll4_ck,
 417         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 418         .recalc         = &omap3_clkoutx2_recalc,
 419 };
 420
 421 static const struct clksel div16_dpll4_clksel[] = {
 422         { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates },
 423         { .parent = NULL }
 424 };
 425
 426 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 427 static struct clk dpll4_m2x2_ck = {
 428         .name           = "dpll4_m2x2_ck",
 429         .parent         = &dpll4_x2_ck,
 430         .init           = &omap2_init_clksel_parent,
 431         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 432         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 433         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 434         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 435         .clksel         = div16_dpll4_clksel,
 436         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 437         .recalc         = &omap2_clksel_recalc,
 438 };
 439
 440 static struct clk omap_96m_alwon_fck = {
 441         .name           = "omap_96m_alwon_fck",
 442         .parent         = &dpll4_m2x2_ck,
 443         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 444                                  PARENT_CONTROLS_CLOCK,
 445         .recalc         = &followparent_recalc,
 446 };
 447
 448 static struct clk omap_96m_fck = {
 449         .name           = "omap_96m_fck",
 450         .parent         = &omap_96m_alwon_fck,
 451         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 452                                 PARENT_CONTROLS_CLOCK,
 453         .recalc         = &followparent_recalc,
 454 };
 455
 456 static struct clk cm_96m_fck = {
 457         .name           = "cm_96m_fck",
 458         .parent         = &dpll4_m2x2_ck,
 459         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 460         .recalc         = &followparent_recalc,
 461 };
 462
 463 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 464 static struct clk dpll4_m3x2_ck = {
 465         .name           = "dpll4_m3x2_ck",
 466         .parent         = &dpll4_x2_ck,
 467         .init           = &omap2_init_clksel_parent,
 468         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 469         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 470         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 471         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 472         .clksel         = div16_dpll4_clksel,
 473         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 474         .recalc         = &omap2_clksel_recalc,
 475 };
 476
 477 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 478         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 479         { .div = 0 }
 480 };
 481
 482 static const struct clksel_rate omap_54m_alt_rates[] = {
 483         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 484         { .div = 0 }
 485 };
 486
 487 static const struct clksel omap_54m_clksel[] = {
 488         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 489         { .parent = &sys_altclk,     .rates = omap_54m_alt_rates },
 490         { .parent = NULL }
 491 };
 492
 493 static struct clk omap_54m_fck = {
 494         .name           = "omap_54m_fck",
 495         .init           = &omap2_init_clksel_parent,
 496         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 497         .clksel_mask    = OMAP3430_SOURCE_54M,
 498         .clksel         = omap_54m_clksel,
 499         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 500         .recalc         = &omap2_clksel_recalc,
 501 };
 502
 503 static const struct clksel_rate omap_48m_96md2_rates[] = {
 504         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 505         { .div = 0 }
 506 };
 507
 508 static const struct clksel_rate omap_48m_alt_rates[] = {
 509         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 510         { .div = 0 }
 511 };
 512
 513 static const struct clksel omap_48m_clksel[] = {
 514         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 515         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 516         { .parent = NULL }
 517 };
 518
 519 static struct clk omap_48m_fck = {
 520         .name           = "omap_48m_fck",
 521         .init           = &omap2_init_clksel_parent,
 522         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 523         .clksel_mask    = OMAP3430_SOURCE_48M,
 524         .clksel         = omap_48m_clksel,
 525         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 526         .recalc         = &omap2_clksel_recalc,
 527 };
 528
 529 static struct clk omap_12m_fck = {
 530         .name           = "omap_12m_fck",
 531         .parent         = &omap_48m_fck,
 532         .fixed_div      = 4,
 533         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 534         .recalc         = &omap2_fixed_divisor_recalc,
 535 };
 536
 537 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 538 static struct clk dpll4_m4x2_ck = {
 539         .name           = "dpll4_m4x2_ck",
 540         .parent         = &dpll4_x2_ck,
 541         .init           = &omap2_init_clksel_parent,
 542         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 543         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 544         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 545         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 546         .clksel         = div16_dpll4_clksel,
 547         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 548         .recalc         = &omap2_clksel_recalc,
 549 };
 550
 551 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 552 static struct clk dpll4_m5x2_ck = {
 553         .name           = "dpll4_m5x2_ck",
 554         .parent         = &dpll4_x2_ck,
 555         .init           = &omap2_init_clksel_parent,
 556         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 557         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 558         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 559         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 560         .clksel         = div16_dpll4_clksel,
 561         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 562         .recalc         = &omap2_clksel_recalc,
 563 };
 564
 565 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 566 static struct clk dpll4_m6x2_ck = {
 567         .name           = "dpll4_m6x2_ck",
 568         .parent         = &dpll4_x2_ck,
 569         .init           = &omap2_init_clksel_parent,
 570         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 571         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 572         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 573         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 574         .clksel         = div16_dpll4_clksel,
 575         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 576         .recalc         = &omap2_clksel_recalc,
 577 };
 578
 579 static struct clk emu_per_alwon_ck = {
 580         .name           = "emu_per_alwon_ck",
 581         .parent         = &dpll4_m6x2_ck,
 582         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 583         .recalc         = &followparent_recalc,
 584 };
 585
 586
 587 /* CM EXTERNAL CLOCK OUTPUTS */
 588
 589 static const struct clksel_rate clkout2_src_core_rates[] = {
 590         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 591         { .div = 0 }
 592 };
 593
 594 static const struct clksel_rate clkout2_src_sys_rates[] = {
 595         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 596         { .div = 0 }
 597 };
 598
 599 static const struct clksel_rate clkout2_src_96m_rates[] = {
 600         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 601         { .div = 0 }
 602 };
 603
 604 static const struct clksel_rate clkout2_src_54m_rates[] = {
 605         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 606         { .div = 0 }
 607 };
 608
 609 static const struct clksel clkout2_src_clksel[] = {
 610         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 611         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 612         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 613         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 614         { .parent = NULL }
 615 };
 616
 617 static struct clk clkout2_src_ck = {
 618         .name           = "clkout2_src_ck",
 619         .init           = &omap2_init_clksel_parent,
 620         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 621         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 622         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 623         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 624         .clksel         = clkout2_src_clksel,
 625         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 626         .recalc         = &omap2_clksel_recalc,
 627 };
 628
 629 static const struct clksel_rate sys_clkout2_rates[] = {
 630         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 631         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 632         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 633         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 634         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 635         { .div = 0 },
 636 };
 637
 638 static const struct clksel sys_clkout2_clksel[] = {
 639         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 640         { .parent = NULL },
 641 };
 642
 643 static struct clk sys_clkout2 = {
 644         .name           = "sys_clkout2",
 645         .init           = &omap2_init_clksel_parent,
 646         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 647         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 648         .clksel         = sys_clkout2_clksel,
 649         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 650         .recalc         = &omap2_clksel_recalc,
 651 };
 652
 653 /* CM OUTPUT CLOCKS */
 654
 655 static struct clk corex2_fck = {
 656         .name           = "corex2_fck",
 657         .parent         = &dpll3_m2x2_ck,
 658         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 659         .recalc         = &followparent_recalc,
 660 };
 661
 662 /* DPLL power domain clock controls */
 663
 664 static const struct clksel div2_core_clksel[] = {
 665         { .parent = &core_ck, .rates = div2_rates },
 666         { .parent = NULL }
 667 };
 668
 669 /* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK,
 670    but presuming that is an error, or at least an overgeneralization */
 671 /* REVISIT: Are these in DPLL power domain or CM power domain?  docs
 672    may be inconsistent here? */
 673 static struct clk dpll1_fck = {
 674         .name           = "dpll1_fck",
 675         .parent         = &core_ck,
 676         .init           = &omap2_init_clksel_parent,
 677         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 678         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 679         .clksel         = div2_core_clksel,
 680         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 681         .recalc         = &omap2_clksel_recalc,
 682 };
 683
 684 static struct clk dpll2_fck = {
 685         .name           = "dpll2_fck",
 686         .parent         = &core_ck,
 687         .init           = &omap2_init_clksel_parent,
 688         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 689         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
 690         .clksel         = div2_core_clksel,
 691         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 692         .recalc         = &omap2_clksel_recalc,
 693 };
 694
 695 /* Common interface clocks */
 696
 697 static struct clk l3_ick = {
 698         .name           = "l3_ick",
 699         .parent         = &core_ck,
 700         .init           = &omap2_init_clksel_parent,
 701         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 702         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
 703         .clksel         = div2_core_clksel,
 704         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 705         .recalc         = &omap2_clksel_recalc,
 706 };
 707
 708 static const struct clksel div2_l3_clksel[] = {
 709         { .parent = &l3_ick, .rates = div2_rates },
 710         { .parent = NULL }
 711 };
 712
 713 static struct clk l4_ick = {
 714         .name           = "l4_ick",
 715         .parent         = &l3_ick,
 716         .init           = &omap2_init_clksel_parent,
 717         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 718         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
 719         .clksel         = div2_l3_clksel,
 720         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 721         .recalc         = &omap2_clksel_recalc,
 722
 723 };
 724
 725 static const struct clksel div2_l4_clksel[] = {
 726         { .parent = &l4_ick, .rates = div2_rates },
 727         { .parent = NULL }
 728 };
 729
 730 static struct clk rm_ick = {
 731         .name           = "rm_ick",
 732         .parent         = &l4_ick,
 733         .init           = &omap2_init_clksel_parent,
 734         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 735         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
 736         .clksel         = div2_l4_clksel,
 737         .flags          = CLOCK_IN_OMAP343X,
 738         .recalc         = &omap2_clksel_recalc,
 739 };
 740
 741 /* GFX power domain */
 742
 743 /* REVISIT: These clocks have disappeared in the 3430 ES2 TRM ?? */
 744
 745 static const struct clksel gfx_l3_clksel[] = {
 746         { .parent = &l3_ick, .rates = gfx_l3_rates },
 747         { .parent = NULL }
 748 };
 749
 750 static struct clk gfx_l3_fck = {
 751         .name           = "gfx_l3_fck",
 752         .parent         = &l3_ick,
 753         .init           = &omap2_init_clksel_parent,
 754         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 755         .enable_bit     = OMAP_EN_GFX_SHIFT,
 756         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 757         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 758         .clksel         = gfx_l3_clksel,
 759         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 760         .recalc         = &omap2_clksel_recalc,
 761 };
 762
 763 static struct clk gfx_l3_ick = {
 764         .name           = "gfx_l3_ick",
 765         .parent         = &l3_ick,
 766         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 767         .enable_bit     = OMAP_EN_GFX_SHIFT,
 768         .flags          = CLOCK_IN_OMAP343X,
 769         .recalc         = &followparent_recalc,
 770 };
 771
 772 static struct clk gfx_cg1_ck = {
 773         .name           = "gfx_cg1_ck",
 774         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
 775         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 776         .enable_bit     = OMAP3430_EN_2D_SHIFT,
 777         .flags          = CLOCK_IN_OMAP343X,
 778         .recalc         = &followparent_recalc,
 779 };
 780
 781 static struct clk gfx_cg2_ck = {
 782         .name           = "gfx_cg2_ck",
 783         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
 784         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 785         .enable_bit     = OMAP3430_EN_3D_SHIFT,
 786         .flags          = CLOCK_IN_OMAP343X,
 787         .recalc         = &followparent_recalc,
 788 };
 789
 790 /* CORE power domain */
 791
 792 static struct clk d2d_26m_fck = {
 793         .name           = "d2d_26m_fck",
 794         .parent         = &sys_ck,
 795         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 796         .enable_bit     = OMAP3430_EN_D2D_SHIFT,
 797         .flags          = CLOCK_IN_OMAP343X,
 798         .recalc         = &followparent_recalc,
 799 };
 800
 801 static const struct clksel omap343x_gpt_clksel[] = {
 802         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
 803         { .parent = &sys_ck,       .rates = gpt_sys_rates },
 804         { .parent = NULL}
 805 };
 806
 807 static struct clk gpt10_fck = {
 808         .name           = "gpt10_fck",
 809         .parent         = &sys_ck,
 810         .init           = &omap2_init_clksel_parent,
 811         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 812         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
 813         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 814         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
 815         .clksel         = omap343x_gpt_clksel,
 816         .flags          = CLOCK_IN_OMAP343X,
 817         .recalc         = &omap2_clksel_recalc,
 818 };
 819
 820 static struct clk gpt11_fck = {
 821         .name           = "gpt11_fck",
 822         .parent         = &sys_ck,
 823         .init           = &omap2_init_clksel_parent,
 824         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 825         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
 826         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 827         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
 828         .clksel         = omap343x_gpt_clksel,
 829         .flags          = CLOCK_IN_OMAP343X,
 830         .recalc         = &omap2_clksel_recalc,
 831 };
 832
 833 /* CORE 96M FCLK-derived clocks */
 834
 835 static struct clk core_96m_fck = {
 836         .name           = "core_96m_fck",
 837         .parent         = &omap_96m_fck,
 838         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 839                                 PARENT_CONTROLS_CLOCK,
 840         .recalc         = &followparent_recalc,
 841 };
 842
 843 static struct clk mmc2_fck = {
 844         .name           = "mmc2_fck",
 845         .parent         = &core_96m_fck,
 846         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 847         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
 848         .flags          = CLOCK_IN_OMAP343X,
 849         .recalc         = &followparent_recalc,
 850 };
 851
 852 static struct clk mspro_fck = {
 853         .name           = "mspro_fck",
 854         .parent         = &core_96m_fck,
 855         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 856         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
 857         .flags          = CLOCK_IN_OMAP343X,
 858         .recalc         = &followparent_recalc,
 859 };
 860
 861 static struct clk mmc1_fck = {
 862         .name           = "mmc1_fck",
 863         .parent         = &core_96m_fck,
 864         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 865         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
 866         .flags          = CLOCK_IN_OMAP343X,
 867         .recalc         = &followparent_recalc,
 868 };
 869
 870 static struct clk i2c3_fck = {
 871         .name           = "i2c_fck",
 872         .id             = 3,
 873         .parent         = &core_96m_fck,
 874         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 875         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
 876         .flags          = CLOCK_IN_OMAP343X,
 877         .recalc         = &followparent_recalc,
 878 };
 879
 880 static struct clk i2c2_fck = {
 881         .name           = "i2c_fck",
 882         .id             = 2,
 883         .parent         = &core_96m_fck,
 884         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 885         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
 886         .flags          = CLOCK_IN_OMAP343X,
 887         .recalc         = &followparent_recalc,
 888 };
 889
 890 static struct clk i2c1_fck = {
 891         .name           = "i2c_fck",
 892         .id             = 1,
 893         .parent         = &core_96m_fck,
 894         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 895         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
 896         .flags          = CLOCK_IN_OMAP343X,
 897         .recalc         = &followparent_recalc,
 898 };
 899
 900 /*
 901  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
 902  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
 903  */
 904 static const struct clksel_rate common_mcbsp_96m_rates[] = {
 905         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 906         { .div = 0 }
 907 };
 908
 909 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
 910         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 911         { .div = 0 }
 912 };
 913
 914 static const struct clksel mcbsp_15_clksel[] = {
 915         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
 916         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
 917         { .parent = NULL }
 918 };
 919
 920 static struct clk mcbsp5_fck = {
 921         .name           = "mcbsp5_fck",
 922         .init           = &omap2_init_clksel_parent,
 923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 924         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
 925         .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
 926         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
 927         .clksel         = mcbsp_15_clksel,
 928         .flags          = CLOCK_IN_OMAP343X,
 929         .recalc         = &omap2_clksel_recalc,
 930 };
 931
 932 static struct clk mcbsp1_fck = {
 933         .name           = "mcbsp1_fck",
 934         .init           = &omap2_init_clksel_parent,
 935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 936         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
 937         .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF0),
 938         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
 939         .clksel         = mcbsp_15_clksel,
 940         .flags          = CLOCK_IN_OMAP343X,
 941         .recalc         = &omap2_clksel_recalc,
 942 };
 943
 944 /* CORE_48M_FCK-derived clocks */
 945
 946 static struct clk core_48m_fck = {
 947         .name           = "core_48m_fck",
 948         .parent         = &omap_48m_fck,
 949         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 950         .recalc         = &followparent_recalc,
 951 };
 952
 953 static struct clk mcspi4_fck = {
 954         .name           = "mcspi4_fck",
 955         .parent         = &core_48m_fck,
 956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 957         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
 958         .flags          = CLOCK_IN_OMAP343X,
 959         .recalc         = &followparent_recalc,
 960 };
 961
 962 static struct clk mcspi3_fck = {
 963         .name           = "mcspi3_fck",
 964         .parent         = &core_48m_fck,
 965         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 966         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
 967         .flags          = CLOCK_IN_OMAP343X,
 968         .recalc         = &followparent_recalc,
 969 };
 970
 971 static struct clk mcspi2_fck = {
 972         .name           = "mcspi2_fck",
 973         .parent         = &core_48m_fck,
 974         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 975         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
 976         .flags          = CLOCK_IN_OMAP343X,
 977         .recalc         = &followparent_recalc,
 978 };
 979
 980 static struct clk mcspi1_fck = {
 981         .name           = "mcspi1_fck",
 982         .parent         = &core_48m_fck,
 983         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 984         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
 985         .flags          = CLOCK_IN_OMAP343X,
 986         .recalc         = &followparent_recalc,
 987 };
 988
 989 static struct clk uart2_fck = {
 990         .name           = "uart2_fck",
 991         .parent         = &core_48m_fck,
 992         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 993         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
 994         .flags          = CLOCK_IN_OMAP343X,
 995         .recalc         = &followparent_recalc,
 996 };
 997
 998 static struct clk uart1_fck = {
 999         .name           = "uart1_fck",
1000         .parent         = &core_48m_fck,
1001         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1002         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1003         .flags          = CLOCK_IN_OMAP343X,
1004         .recalc         = &followparent_recalc,
1005 };
1006
1007 static struct clk fshostusb_fck = {
1008         .name           = "fshostusb_fck",
1009         .parent         = &core_48m_fck,
1010         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1011         .enable_bit     = OMAP3430_EN_FSHOSTUSB_SHIFT,
1012         .flags          = CLOCK_IN_OMAP343X,
1013         .recalc         = &followparent_recalc,
1014 };
1015
1016 /* CORE_12M_FCK based clocks */
1017
1018 static struct clk core_12m_fck = {
1019         .name           = "core_12m_fck",
1020         .parent         = &omap_12m_fck,
1021         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1022         .recalc         = &followparent_recalc,
1023 };
1024
1025 static struct clk hdq_fck = {
1026         .name           = "hdq_fck",
1027         .parent         = &core_12m_fck,
1028         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1029         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1030         .flags          = CLOCK_IN_OMAP343X,
1031         .recalc         = &followparent_recalc,
1032 };
1033
1034 /* DPLL3-derived clock */
1035
1036 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1037         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1038         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1039         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1040         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1041         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1042         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1043         { .div = 0 }
1044 };
1045
1046 static const struct clksel ssi_ssr_clksel[] = {
1047         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1048         { .parent = NULL }
1049 };
1050
1051 static struct clk ssi_ssr_fck = {
1052         .name           = "ssi_ssr_fck",
1053         .init           = &omap2_init_clksel_parent,
1054         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1055         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1056         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1057         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1058         .clksel         = ssi_ssr_clksel,
1059         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1060         .recalc         = &omap2_clksel_recalc,
1061 };
1062
1063 static struct clk ssi_sst_fck = {
1064         .name           = "ssi_sst_fck",
1065         .parent         = &ssi_ssr_fck,
1066         .fixed_div      = 2,
1067         .flags          = CLOCK_IN_OMAP343X,
1068         .recalc         = &omap2_fixed_divisor_recalc,
1069 };
1070
1071
1072
1073 /* CORE_L3_ICK based clocks */
1074
1075 static struct clk core_l3_ick = {
1076         .name           = "core_l3_ick",
1077         .parent         = &l3_ick,
1078         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1079         .recalc         = &followparent_recalc,
1080 };
1081
1082 static struct clk hsotgusb_ick = {
1083         .name           = "hsotgusb_ick",
1084         .parent         = &core_l3_ick,
1085         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1086         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1087         .flags          = CLOCK_IN_OMAP343X,
1088         .recalc         = &followparent_recalc,
1089 };
1090
1091 static struct clk sdrc_ick = {
1092         .name           = "sdrc_ick",
1093         .parent         = &core_l3_ick,
1094         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1095         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1096         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1097         .recalc         = &followparent_recalc,
1098 };
1099
1100 static struct clk gpmc_fck = {
1101         .name           = "gpmc_fck",
1102         .parent         = &core_l3_ick,
1103         .flags          = CLOCK_IN_OMAP343X,
1104         .recalc         = &followparent_recalc,
1105 };
1106
1107 /* SECURITY_L3_ICK based clocks */
1108
1109 static struct clk security_l3_ick = {
1110         .name           = "security_l3_ick",
1111         .parent         = &l3_ick,
1112         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1113         .recalc         = &followparent_recalc,
1114 };
1115
1116 static struct clk pka_ick = {
1117         .name           = "pka_ick",
1118         .parent         = &security_l3_ick,
1119         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1120         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1121         .flags          = CLOCK_IN_OMAP343X,
1122         .recalc         = &followparent_recalc,
1123 };
1124
1125 /* CORE_L4_ICK based clocks */
1126
1127 static struct clk core_l4_ick = {
1128         .name           = "core_l4_ick",
1129         .parent         = &l4_ick,
1130         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1131         .recalc         = &followparent_recalc,
1132 };
1133
1134 static struct clk aes2_ick = {
1135         .name           = "aes2_ick",
1136         .parent         = &core_l4_ick,
1137         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1138         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1139         .flags          = CLOCK_IN_OMAP343X,
1140         .recalc         = &followparent_recalc,
1141 };
1142
1143 static struct clk sha12_ick = {
1144         .name           = "sha12_ick",
1145         .parent         = &core_l4_ick,
1146         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1147         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1148         .flags          = CLOCK_IN_OMAP343X,
1149         .recalc         = &followparent_recalc,
1150 };
1151
1152 static struct clk des2_ick = {
1153         .name           = "des2_ick",
1154         .parent         = &core_l4_ick,
1155         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1156         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1157         .flags          = CLOCK_IN_OMAP343X,
1158         .recalc         = &followparent_recalc,
1159 };
1160
1161 static struct clk mmc2_ick = {
1162         .name           = "mmc2_ick",
1163         .parent         = &core_l4_ick,
1164         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1165         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1166         .flags          = CLOCK_IN_OMAP343X,
1167         .recalc         = &followparent_recalc,
1168 };
1169
1170 static struct clk mmc1_ick = {
1171         .name           = "mmc1_ick",
1172         .parent         = &core_l4_ick,
1173         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1174         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1175         .flags          = CLOCK_IN_OMAP343X,
1176         .recalc         = &followparent_recalc,
1177 };
1178
1179 static struct clk mspro_ick = {
1180         .name           = "mspro_ick",
1181         .parent         = &core_l4_ick,
1182         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1183         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1184         .flags          = CLOCK_IN_OMAP343X,
1185         .recalc         = &followparent_recalc,
1186 };
1187
1188 static struct clk hdq_ick = {
1189         .name           = "hdq_ick",
1190         .parent         = &core_l4_ick,
1191         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1192         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1193         .flags          = CLOCK_IN_OMAP343X,
1194         .recalc         = &followparent_recalc,
1195 };
1196
1197 static struct clk mcspi4_ick = {
1198         .name           = "mcspi4_ick",
1199         .parent         = &core_l4_ick,
1200         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1201         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1202         .flags          = CLOCK_IN_OMAP343X,
1203         .recalc         = &followparent_recalc,
1204 };
1205
1206 static struct clk mcspi3_ick = {
1207         .name           = "mcspi3_ick",
1208         .parent         = &core_l4_ick,
1209         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1210         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1211         .flags          = CLOCK_IN_OMAP343X,
1212         .recalc         = &followparent_recalc,
1213 };
1214
1215 static struct clk mcspi2_ick = {
1216         .name           = "mcspi2_ick",
1217         .parent         = &core_l4_ick,
1218         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1219         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1220         .flags          = CLOCK_IN_OMAP343X,
1221         .recalc         = &followparent_recalc,
1222 };
1223
1224 static struct clk mcspi1_ick = {
1225         .name           = "mcspi1_ick",
1226         .parent         = &core_l4_ick,
1227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1228         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1229         .flags          = CLOCK_IN_OMAP343X,
1230         .recalc         = &followparent_recalc,
1231 };
1232
1233 static struct clk i2c3_ick = {
1234         .name           = "i2c_ick",
1235         .id             = 3,
1236         .parent         = &core_l4_ick,
1237         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1238         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1239         .flags          = CLOCK_IN_OMAP343X,
1240         .recalc         = &followparent_recalc,
1241 };
1242
1243 static struct clk i2c2_ick = {
1244         .name           = "i2c_ick",
1245         .id             = 2,
1246         .parent         = &core_l4_ick,
1247         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1248         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1249         .flags          = CLOCK_IN_OMAP343X,
1250         .recalc         = &followparent_recalc,
1251 };
1252
1253 static struct clk i2c1_ick = {
1254         .name           = "i2c_ick",
1255         .id             = 1,
1256         .parent         = &core_l4_ick,
1257         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1258         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1259         .flags          = CLOCK_IN_OMAP343X,
1260         .recalc         = &followparent_recalc,
1261 };
1262
1263 static struct clk uart2_ick = {
1264         .name           = "uart2_ick",
1265         .parent         = &core_l4_ick,
1266         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1267         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1268         .flags          = CLOCK_IN_OMAP343X,
1269         .recalc         = &followparent_recalc,
1270 };
1271
1272 static struct clk uart1_ick = {
1273         .name           = "uart1_ick",
1274         .parent         = &core_l4_ick,
1275         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1276         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1277         .flags          = CLOCK_IN_OMAP343X,
1278         .recalc         = &followparent_recalc,
1279 };
1280
1281 static struct clk gpt11_ick = {
1282         .name           = "gpt11_ick",
1283         .parent         = &core_l4_ick,
1284         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1285         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1286         .flags          = CLOCK_IN_OMAP343X,
1287         .recalc         = &followparent_recalc,
1288 };
1289
1290 static struct clk gpt10_ick = {
1291         .name           = "gpt10_ick",
1292         .parent         = &core_l4_ick,
1293         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1294         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1295         .flags          = CLOCK_IN_OMAP343X,
1296         .recalc         = &followparent_recalc,
1297 };
1298
1299 static struct clk mcbsp5_ick = {
1300         .name           = "mcbsp5_ick",
1301         .parent         = &core_l4_ick,
1302         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1303         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1304         .flags          = CLOCK_IN_OMAP343X,
1305         .recalc         = &followparent_recalc,
1306 };
1307
1308 static struct clk mcbsp1_ick = {
1309         .name           = "mcbsp1_ick",
1310         .parent         = &core_l4_ick,
1311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1312         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1313         .flags          = CLOCK_IN_OMAP343X,
1314         .recalc         = &followparent_recalc,
1315 };
1316
1317 static struct clk fac_ick = {
1318         .name           = "fac_ick",
1319         .parent         = &core_l4_ick,
1320         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1321         .enable_bit     = OMAP3430_EN_FAC_SHIFT,
1322         .flags          = CLOCK_IN_OMAP343X,
1323         .recalc         = &followparent_recalc,
1324 };
1325
1326 static struct clk mailboxes_ick = {
1327         .name           = "mailboxes_ick",
1328         .parent         = &core_l4_ick,
1329         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1330         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1331         .flags          = CLOCK_IN_OMAP343X,
1332         .recalc         = &followparent_recalc,
1333 };
1334
1335 static struct clk omapctrl_ick = {
1336         .name           = "omapctrl_ick",
1337         .parent         = &core_l4_ick,
1338         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1339         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1340         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1341         .recalc         = &followparent_recalc,
1342 };
1343
1344 /* SSI_L4_ICK based clocks */
1345
1346 static struct clk ssi_l4_ick = {
1347         .name           = "ssi_l4_ick",
1348         .parent         = &l4_ick,
1349         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1350         .recalc         = &followparent_recalc,
1351 };
1352
1353 static struct clk ssi_ick = {
1354         .name           = "ssi_ick",
1355         .parent         = &ssi_l4_ick,
1356         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1357         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1358         .flags          = CLOCK_IN_OMAP343X,
1359         .recalc         = &followparent_recalc,
1360 };
1361
1362 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1363  * but l4_ick makes more sense to me */
1364
1365 static const struct clksel_rate usb_l4_l4_rates[] = {
1366         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1367         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1368         { .div = 0 }
1369 };
1370
1371 static const struct clksel usb_l4_clksel[] = {
1372         { .parent = &l4_ick, .rates = usb_l4_l4_rates },
1373         { .parent = NULL },
1374 };
1375
1376 static struct clk usb_l4_ick = {
1377         .name           = "usb_l4_ick",
1378         .parent         = &l4_ick,
1379         .init           = &omap2_init_clksel_parent,
1380         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1381         .enable_bit     = OMAP3430_EN_FSHOSTUSB_SHIFT,
1382         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1383         .clksel_mask    = OMAP3430_CLKSEL_FSHOSTUSB_MASK,
1384         .clksel         = usb_l4_clksel,
1385         .flags          = CLOCK_IN_OMAP343X,
1386         .recalc         = &omap2_clksel_recalc,
1387 };
1388
1389 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1390
1391 /* SECURITY_L4_ICK2 based clocks */
1392
1393 static struct clk security_l4_ick2 = {
1394         .name           = "security_l4_ick2",
1395         .parent         = &l4_ick,
1396         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 static struct clk aes1_ick = {
1401         .name           = "aes1_ick",
1402         .parent         = &security_l4_ick2,
1403         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1404         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1405         .flags          = CLOCK_IN_OMAP343X,
1406         .recalc         = &followparent_recalc,
1407 };
1408
1409 static struct clk rng_ick = {
1410         .name           = "rng_ick",
1411         .parent         = &security_l4_ick2,
1412         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1413         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1414         .flags          = CLOCK_IN_OMAP343X,
1415         .recalc         = &followparent_recalc,
1416 };
1417
1418 static struct clk sha11_ick = {
1419         .name           = "sha11_ick",
1420         .parent         = &security_l4_ick2,
1421         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1422         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1423         .flags          = CLOCK_IN_OMAP343X,
1424         .recalc         = &followparent_recalc,
1425 };
1426
1427 static struct clk des1_ick = {
1428         .name           = "des1_ick",
1429         .parent         = &security_l4_ick2,
1430         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1431         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1432         .flags          = CLOCK_IN_OMAP343X,
1433         .recalc         = &followparent_recalc,
1434 };
1435
1436 /* DSS */
1437
1438 static struct clk dss1_alwon_fck = {
1439         .name           = "dss1_alwon_fck",
1440         .parent         = &dpll4_m4x2_ck,
1441         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1442         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1443         .flags          = CLOCK_IN_OMAP343X,
1444         .recalc         = &followparent_recalc,
1445 };
1446
1447 static struct clk dss_tv_fck = {
1448         .name           = "dss_tv_fck",
1449         .parent         = &omap_54m_fck,
1450         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1451         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1452         .flags          = CLOCK_IN_OMAP343X,
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 static struct clk dss_96m_fck = {
1457         .name           = "dss_96m_fck",
1458         .parent         = &omap_96m_fck,
1459         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1460         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1461         .flags          = CLOCK_IN_OMAP343X,
1462         .recalc         = &followparent_recalc,
1463 };
1464
1465 static struct clk dss2_alwon_fck = {
1466         .name           = "dss2_alwon_fck",
1467         .parent         = &sys_ck,
1468         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1469         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
1470         .flags          = CLOCK_IN_OMAP343X,
1471         .recalc         = &followparent_recalc,
1472 };
1473
1474 static struct clk dss_l3_ick = {
1475         .name           = "dss_l3_ick",
1476         .parent         = &l3_ick,
1477         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1478         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1479         .flags          = CLOCK_IN_OMAP343X,
1480         .recalc         = &followparent_recalc,
1481 };
1482
1483 static struct clk dss_l4_ick = {
1484         .name           = "dss_l4_ick",
1485         .parent         = &l4_ick,
1486         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1487         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1488         .flags          = CLOCK_IN_OMAP343X,
1489         .recalc         = &followparent_recalc,
1490 };
1491
1492 /* CAM */
1493
1494 static struct clk cam_mclk = {
1495         .name           = "cam_mclk",
1496         .parent         = &dpll4_m5x2_ck,
1497         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1498         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1499         .flags          = CLOCK_IN_OMAP343X,
1500         .recalc         = &followparent_recalc,
1501 };
1502
1503 static struct clk cam_l3_ick = {
1504         .name           = "cam_l3_ick",
1505         .parent         = &l3_ick,
1506         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1507         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1508         .flags          = CLOCK_IN_OMAP343X,
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static struct clk cam_l4_ick = {
1513         .name           = "cam_l4_ick",
1514         .parent         = &l4_ick,
1515         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1516         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1517         .flags          = CLOCK_IN_OMAP343X,
1518         .recalc         = &followparent_recalc,
1519 };
1520
1521 /* WKUP */
1522
1523 static struct clk gpt1_fck = {
1524         .name           = "gpt1_fck",
1525         .init           = &omap2_init_clksel_parent,
1526         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1527         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1528         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1529         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
1530         .clksel         = omap343x_gpt_clksel,
1531         .flags          = CLOCK_IN_OMAP343X,
1532         .recalc         = &omap2_clksel_recalc,
1533 };
1534
1535 static struct clk wkup_32k_fck = {
1536         .name           = "wkup_32k_fck",
1537         .parent         = &omap_32k_fck,
1538         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1539         .recalc         = &followparent_recalc,
1540 };
1541
1542 static struct clk gpio1_fck = {
1543         .name           = "gpio1_fck",
1544         .parent         = &wkup_32k_fck,
1545         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1546         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1547         .flags          = CLOCK_IN_OMAP343X,
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk wdt2_fck = {
1552         .name           = "wdt2_fck",
1553         .parent         = &wkup_32k_fck,
1554         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1555         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
1556         .flags          = CLOCK_IN_OMAP343X,
1557         .recalc         = &followparent_recalc,
1558 };
1559
1560 static struct clk wkup_l4_ick = {
1561         .name           = "wkup_l4_ick",
1562         .parent         = &sys_ck,
1563         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk wdt2_ick = {
1568         .name           = "wdt2_ick",
1569         .parent         = &wkup_l4_ick,
1570         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1571         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
1572         .flags          = CLOCK_IN_OMAP343X,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk wdt1_ick = {
1577         .name           = "wdt1_ick",
1578         .parent         = &wkup_l4_ick,
1579         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1580         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
1581         .flags          = CLOCK_IN_OMAP343X,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk gpio1_ick = {
1586         .name           = "gpio1_ick",
1587         .parent         = &wkup_l4_ick,
1588         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1589         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1590         .flags          = CLOCK_IN_OMAP343X,
1591         .recalc         = &followparent_recalc,
1592 };
1593
1594 static struct clk omap_32ksync_ick = {
1595         .name           = "omap_32ksync_ick",
1596         .parent         = &wkup_l4_ick,
1597         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1598         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
1599         .flags          = CLOCK_IN_OMAP343X,
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 static struct clk gpt12_ick = {
1604         .name           = "gpt12_ick",
1605         .parent         = &wkup_l4_ick,
1606         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1607         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
1608         .flags          = CLOCK_IN_OMAP343X,
1609         .recalc         = &followparent_recalc,
1610 };
1611
1612 static struct clk gpt1_ick = {
1613         .name           = "gpt1_ick",
1614         .parent         = &wkup_l4_ick,
1615         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1616         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1617         .flags          = CLOCK_IN_OMAP343X,
1618         .recalc         = &followparent_recalc,
1619 };
1620
1621
1622
1623 /* PER clock domain */
1624
1625 static struct clk per_96m_fck = {
1626         .name           = "per_96m_fck",
1627         .parent         = &omap_96m_alwon_fck,
1628         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1629         .recalc         = &followparent_recalc,
1630 };
1631
1632 static struct clk per_48m_fck = {
1633         .name           = "per_48m_fck",
1634         .parent         = &omap_48m_fck,
1635         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1636         .recalc         = &followparent_recalc,
1637 };
1638
1639 static struct clk uart3_fck = {
1640         .name           = "uart3_fck",
1641         .parent         = &per_48m_fck,
1642         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1643         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
1644         .flags          = CLOCK_IN_OMAP343X,
1645         .recalc         = &followparent_recalc,
1646 };
1647
1648 static struct clk gpt2_fck = {
1649         .name           = "gpt2_fck",
1650         .init           = &omap2_init_clksel_parent,
1651         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1652         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1653         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1654         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
1655         .clksel         = omap343x_gpt_clksel,
1656         .flags          = CLOCK_IN_OMAP343X,
1657         .recalc         = &omap2_clksel_recalc,
1658 };
1659
1660 static struct clk gpt3_fck = {
1661         .name           = "gpt3_fck",
1662         .init           = &omap2_init_clksel_parent,
1663         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1664         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1665         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1666         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
1667         .clksel         = omap343x_gpt_clksel,
1668         .flags          = CLOCK_IN_OMAP343X,
1669         .recalc         = &omap2_clksel_recalc,
1670 };
1671
1672 static struct clk gpt4_fck = {
1673         .name           = "gpt4_fck",
1674         .init           = &omap2_init_clksel_parent,
1675         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1676         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1677         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1678         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
1679         .clksel         = omap343x_gpt_clksel,
1680         .flags          = CLOCK_IN_OMAP343X,
1681         .recalc         = &omap2_clksel_recalc,
1682 };
1683
1684 static struct clk gpt5_fck = {
1685         .name           = "gpt5_fck",
1686         .init           = &omap2_init_clksel_parent,
1687         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1688         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1689         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1690         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
1691         .clksel         = omap343x_gpt_clksel,
1692         .flags          = CLOCK_IN_OMAP343X,
1693         .recalc         = &omap2_clksel_recalc,
1694 };
1695
1696 static struct clk gpt6_fck = {
1697         .name           = "gpt6_fck",
1698         .init           = &omap2_init_clksel_parent,
1699         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1700         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1701         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1702         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
1703         .clksel         = omap343x_gpt_clksel,
1704         .flags          = CLOCK_IN_OMAP343X,
1705         .recalc         = &omap2_clksel_recalc,
1706 };
1707
1708 static struct clk gpt7_fck = {
1709         .name           = "gpt7_fck",
1710         .init           = &omap2_init_clksel_parent,
1711         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1712         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1713         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1714         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
1715         .clksel         = omap343x_gpt_clksel,
1716         .flags          = CLOCK_IN_OMAP343X,
1717         .recalc         = &omap2_clksel_recalc,
1718 };
1719
1720 static struct clk gpt8_fck = {
1721         .name           = "gpt8_fck",
1722         .init           = &omap2_init_clksel_parent,
1723         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1724         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1725         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1726         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
1727         .clksel         = omap343x_gpt_clksel,
1728         .flags          = CLOCK_IN_OMAP343X,
1729         .recalc         = &omap2_clksel_recalc,
1730 };
1731
1732 static struct clk gpt9_fck = {
1733         .name           = "gpt9_fck",
1734         .init           = &omap2_init_clksel_parent,
1735         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1736         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1737         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1738         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
1739         .clksel         = omap343x_gpt_clksel,
1740         .flags          = CLOCK_IN_OMAP343X,
1741         .recalc         = &omap2_clksel_recalc,
1742 };
1743
1744 static struct clk per_32k_alwon_fck = {
1745         .name           = "per_32k_alwon_fck",
1746         .parent         = &omap_32k_fck,
1747         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 static struct clk gpio6_fck = {
1752         .name           = "gpio6_fck",
1753         .parent         = &per_32k_alwon_fck,
1754         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1755         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1756         .flags          = CLOCK_IN_OMAP343X,
1757         .recalc         = &followparent_recalc,
1758 };
1759
1760 static struct clk gpio5_fck = {
1761         .name           = "gpio5_fck",
1762         .parent         = &per_32k_alwon_fck,
1763         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1764         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1765         .flags          = CLOCK_IN_OMAP343X,
1766         .recalc         = &followparent_recalc,
1767 };
1768
1769 static struct clk gpio4_fck = {
1770         .name           = "gpio4_fck",
1771         .parent         = &per_32k_alwon_fck,
1772         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1773         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1774         .flags          = CLOCK_IN_OMAP343X,
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 static struct clk gpio3_fck = {
1779         .name           = "gpio3_fck",
1780         .parent         = &per_32k_alwon_fck,
1781         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1782         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1783         .flags          = CLOCK_IN_OMAP343X,
1784         .recalc         = &followparent_recalc,
1785 };
1786
1787 static struct clk gpio2_fck = {
1788         .name           = "gpio2_fck",
1789         .parent         = &per_32k_alwon_fck,
1790         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1791         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1792         .flags          = CLOCK_IN_OMAP343X,
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk wdt3_fck = {
1797         .name           = "wdt3_fck",
1798         .parent         = &per_32k_alwon_fck,
1799         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1800         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
1801         .flags          = CLOCK_IN_OMAP343X,
1802         .recalc         = &followparent_recalc,
1803 };
1804
1805 static struct clk per_l4_ick = {
1806         .name           = "per_l4_ick",
1807         .parent         = &l4_ick,
1808         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1809         .recalc         = &followparent_recalc,
1810 };
1811
1812 static struct clk gpio6_ick = {
1813         .name           = "gpio6_ick",
1814         .parent         = &per_l4_ick,
1815         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1816         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1817         .flags          = CLOCK_IN_OMAP343X,
1818         .recalc         = &followparent_recalc,
1819 };
1820
1821 static struct clk gpio5_ick = {
1822         .name           = "gpio5_ick",
1823         .parent         = &per_l4_ick,
1824         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1825         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1826         .flags          = CLOCK_IN_OMAP343X,
1827         .recalc         = &followparent_recalc,
1828 };
1829
1830 static struct clk gpio4_ick = {
1831         .name           = "gpio4_ick",
1832         .parent         = &per_l4_ick,
1833         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1834         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1835         .flags          = CLOCK_IN_OMAP343X,
1836         .recalc         = &followparent_recalc,
1837 };
1838
1839 static struct clk gpio3_ick = {
1840         .name           = "gpio3_ick",
1841         .parent         = &per_l4_ick,
1842         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1843         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1844         .flags          = CLOCK_IN_OMAP343X,
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk gpio2_ick = {
1849         .name           = "gpio2_ick",
1850         .parent         = &per_l4_ick,
1851         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1852         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1853         .flags          = CLOCK_IN_OMAP343X,
1854         .recalc         = &followparent_recalc,
1855 };
1856
1857 static struct clk wdt3_ick = {
1858         .name           = "wdt3_ick",
1859         .parent         = &per_l4_ick,
1860         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1861         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
1862         .flags          = CLOCK_IN_OMAP343X,
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 static struct clk uart3_ick = {
1867         .name           = "uart3_ick",
1868         .parent         = &per_l4_ick,
1869         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1870         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
1871         .flags          = CLOCK_IN_OMAP343X,
1872         .recalc         = &followparent_recalc,
1873 };
1874
1875 static struct clk gpt9_ick = {
1876         .name           = "gpt9_ick",
1877         .parent         = &per_l4_ick,
1878         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1879         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1880         .flags          = CLOCK_IN_OMAP343X,
1881         .recalc         = &followparent_recalc,
1882 };
1883
1884 static struct clk gpt8_ick = {
1885         .name           = "gpt8_ick",
1886         .parent         = &per_l4_ick,
1887         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1888         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1889         .flags          = CLOCK_IN_OMAP343X,
1890         .recalc         = &followparent_recalc,
1891 };
1892
1893 static struct clk gpt7_ick = {
1894         .name           = "gpt7_ick",
1895         .parent         = &per_l4_ick,
1896         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1897         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1898         .flags          = CLOCK_IN_OMAP343X,
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk gpt6_ick = {
1903         .name           = "gpt6_ick",
1904         .parent         = &per_l4_ick,
1905         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1906         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1907         .flags          = CLOCK_IN_OMAP343X,
1908         .recalc         = &followparent_recalc,
1909 };
1910
1911 static struct clk gpt5_ick = {
1912         .name           = "gpt5_ick",
1913         .parent         = &per_l4_ick,
1914         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1915         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1916         .flags          = CLOCK_IN_OMAP343X,
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk gpt4_ick = {
1921         .name           = "gpt4_ick",
1922         .parent         = &per_l4_ick,
1923         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1924         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1925         .flags          = CLOCK_IN_OMAP343X,
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk gpt3_ick = {
1930         .name           = "gpt3_ick",
1931         .parent         = &per_l4_ick,
1932         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1933         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1934         .flags          = CLOCK_IN_OMAP343X,
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk gpt2_ick = {
1939         .name           = "gpt2_ick",
1940         .parent         = &per_l4_ick,
1941         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1942         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1943         .flags          = CLOCK_IN_OMAP343X,
1944         .recalc         = &followparent_recalc,
1945 };
1946
1947 static struct clk mcbsp2_ick = {
1948         .name           = "mcbsp2_ick",
1949         .parent         = &per_l4_ick,
1950         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1951         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
1952         .flags          = CLOCK_IN_OMAP343X,
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk mcbsp3_ick = {
1957         .name           = "mcbsp3_ick",
1958         .parent         = &per_l4_ick,
1959         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1960         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
1961         .flags          = CLOCK_IN_OMAP343X,
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk mcbsp4_ick = {
1966         .name           = "mcbsp4_ick",
1967         .parent         = &per_l4_ick,
1968         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1969         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
1970         .flags          = CLOCK_IN_OMAP343X,
1971         .recalc         = &followparent_recalc,
1972 };
1973
1974 static const struct clksel mcbsp_234_clksel[] = {
1975         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
1976         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1977         { .parent = NULL }
1978 };
1979
1980 static struct clk mcbsp2_fck = {
1981         .name           = "mcbsp2_fck",
1982         .init           = &omap2_init_clksel_parent,
1983         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1984         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
1985         .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF0),
1986         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
1987         .clksel         = mcbsp_234_clksel,
1988         .flags          = CLOCK_IN_OMAP343X,
1989         .recalc         = &omap2_clksel_recalc,
1990 };
1991
1992 static struct clk mcbsp3_fck = {
1993         .name           = "mcbsp3_fck",
1994         .init           = &omap2_init_clksel_parent,
1995         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1996         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
1997         .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
1998         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
1999         .clksel         = mcbsp_234_clksel,
2000         .flags          = CLOCK_IN_OMAP343X,
2001         .recalc         = &omap2_clksel_recalc,
2002 };
2003
2004 static struct clk mcbsp4_fck = {
2005         .name           = "mcbsp4_fck",
2006         .init           = &omap2_init_clksel_parent,
2007         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2008         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2009         .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
2010         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2011         .clksel         = mcbsp_234_clksel,
2012         .flags          = CLOCK_IN_OMAP343X,
2013         .recalc         = &omap2_clksel_recalc,
2014 };
2015
2016 /* EMU clocks */
2017
2018 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2019
2020 static const struct clksel_rate emu_src_sys_rates[] = {
2021         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2022         { .div = 0 },
2023 };
2024
2025 static const struct clksel_rate emu_src_core_rates[] = {
2026         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2027         { .div = 0 },
2028 };
2029
2030 static const struct clksel_rate emu_src_per_rates[] = {
2031         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2032         { .div = 0 },
2033 };
2034
2035 static const struct clksel_rate emu_src_mpu_rates[] = {
2036         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2037         { .div = 0 },
2038 };
2039
2040 static const struct clksel emu_src_clksel[] = {
2041         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2042         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2043         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2044         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2045         { .parent = NULL },
2046 };
2047
2048 /*
2049  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2050  * to switch the source of some of the EMU clocks.
2051  * XXX Are there CLKEN bits for these EMU clks?
2052  */
2053 static struct clk emu_src_ck = {
2054         .name           = "emu_src_ck",
2055         .init           = &omap2_init_clksel_parent,
2056         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2057         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2058         .clksel         = emu_src_clksel,
2059         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2060         .recalc         = &omap2_clksel_recalc,
2061 };
2062
2063 static const struct clksel_rate pclk_emu_rates[] = {
2064         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2065         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2066         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2067         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2068         { .div = 0 },
2069 };
2070
2071 static const struct clksel pclk_emu_clksel[] = {
2072         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2073         { .parent = NULL },
2074 };
2075
2076 static struct clk pclk_fck = {
2077         .name           = "pclk_fck",
2078         .init           = &omap2_init_clksel_parent,
2079         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2080         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2081         .clksel         = pclk_emu_clksel,
2082         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2083         .recalc         = &omap2_clksel_recalc,
2084 };
2085
2086 static const struct clksel_rate pclkx2_emu_rates[] = {
2087         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2088         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2089         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2090         { .div = 0 },
2091 };
2092
2093 static const struct clksel pclkx2_emu_clksel[] = {
2094         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2095         { .parent = NULL },
2096 };
2097
2098 static struct clk pclkx2_fck = {
2099         .name           = "pclkx2_fck",
2100         .init           = &omap2_init_clksel_parent,
2101         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2102         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2103         .clksel         = pclkx2_emu_clksel,
2104         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2105         .recalc         = &omap2_clksel_recalc,
2106 };
2107
2108 static const struct clksel atclk_emu_clksel[] = {
2109         { .parent = &emu_src_ck, .rates = div2_rates },
2110         { .parent = NULL },
2111 };
2112
2113 static struct clk atclk_fck = {
2114         .name           = "atclk_fck",
2115         .init           = &omap2_init_clksel_parent,
2116         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2117         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2118         .clksel         = atclk_emu_clksel,
2119         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2120         .recalc         = &omap2_clksel_recalc,
2121 };
2122
2123 static struct clk traceclk_src_fck = {
2124         .name           = "traceclk_src_fck",
2125         .init           = &omap2_init_clksel_parent,
2126         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2127         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2128         .clksel         = emu_src_clksel,
2129         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2130         .recalc         = &omap2_clksel_recalc,
2131 };
2132
2133 static const struct clksel_rate traceclk_rates[] = {
2134         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2135         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2136         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2137         { .div = 0 },
2138 };
2139
2140 static const struct clksel traceclk_clksel[] = {
2141         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2142         { .parent = NULL },
2143 };
2144
2145 static struct clk traceclk_fck = {
2146         .name           = "traceclk_fck",
2147         .init           = &omap2_init_clksel_parent,
2148         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2149         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2150         .clksel         = traceclk_clksel,
2151         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2152         .recalc         = &omap2_clksel_recalc,
2153 };
2154
2155 /* SR clocks */
2156
2157 /* SmartReflex fclk (VDD1) */
2158 static struct clk sr1_fck = {
2159         .name           = "sr1_fck",
2160         .parent         = &sys_ck,
2161         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2162         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2163         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2164         .recalc         = &followparent_recalc,
2165 };
2166
2167 /* SmartReflex fclk (VDD2) */
2168 static struct clk sr2_fck = {
2169         .name           = "sr2_fck",
2170         .parent         = &sys_ck,
2171         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2172         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2173         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2174         .recalc         = &followparent_recalc,
2175 };
2176
2177 static struct clk sr_l4_ick = {
2178         .name           = "sr_l4_ick",
2179         .parent         = &l4_ick,
2180         .flags          = CLOCK_IN_OMAP343X,
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 /* SECURE_32K_FCK clocks */
2185
2186 static struct clk gpt12_fck = {
2187         .name           = "gpt12_fck",
2188         .parent         = &secure_32k_fck,
2189         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk wdt1_fck = {
2194         .name           = "wdt1_fck",
2195         .parent         = &secure_32k_fck,
2196         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2197         .recalc         = &followparent_recalc,
2198 };
2199
2200
2201 static struct clk *onchip_34xx_clks[] __initdata = {
2202         &omap_32k_fck,
2203         &virt_12m_ck,
2204         &virt_13m_ck,
2205         &virt_16_8m_ck,
2206         &virt_19_2m_ck,
2207         &virt_26m_ck,
2208         &virt_38_4m_ck,
2209         &osc_sys_ck,
2210         &sys_ck,
2211         &sys_altclk,
2212         &sys_clkout1,
2213         &dpll1_ck,
2214         &emu_mpu_alwon_ck,
2215         &dpll2_ck,
2216         &dpll3_ck,
2217         &core_ck,
2218         &dpll3_x2_ck,
2219         &dpll3_m2_ck,
2220         &dpll3_m2x2_ck,
2221         &dpll3_m3x2_ck,
2222         &emu_core_alwon_ck,
2223         &dpll4_ck,
2224         &dpll4_x2_ck,
2225         &omap_96m_alwon_fck,
2226         &omap_96m_fck,
2227         &cm_96m_fck,
2228         &omap_54m_fck,
2229         &omap_48m_fck,
2230         &omap_12m_fck,
2231         &dpll4_m2x2_ck,
2232         &dpll4_m3x2_ck,
2233         &dpll4_m4x2_ck,
2234         &dpll4_m5x2_ck,
2235         &dpll4_m6x2_ck,
2236         &emu_per_alwon_ck,
2237         &clkout2_src_ck,
2238         &sys_clkout2,
2239         &corex2_fck,
2240         &dpll1_fck,
2241         &dpll2_fck,
2242         &l3_ick,
2243         &l4_ick,
2244         &rm_ick,
2245         &gfx_l3_fck,
2246         &gfx_l3_ick,
2247         &gfx_cg1_ck,
2248         &gfx_cg2_ck,
2249         &d2d_26m_fck,
2250         &gpt10_fck,
2251         &gpt11_fck,
2252         &core_96m_fck,
2253         &mmc2_fck,
2254         &mspro_fck,
2255         &mmc1_fck,
2256         &i2c3_fck,
2257         &i2c2_fck,
2258         &i2c1_fck,
2259         &mcbsp5_fck,
2260         &mcbsp1_fck,
2261         &core_48m_fck,
2262         &mcspi4_fck,
2263         &mcspi3_fck,
2264         &mcspi2_fck,
2265         &mcspi1_fck,
2266         &uart2_fck,
2267         &uart1_fck,
2268         &fshostusb_fck,
2269         &core_12m_fck,
2270         &hdq_fck,
2271         &ssi_ssr_fck,
2272         &ssi_sst_fck,
2273         &core_l3_ick,
2274         &hsotgusb_ick,
2275         &sdrc_ick,
2276         &gpmc_fck,
2277         &security_l3_ick,
2278         &pka_ick,
2279         &core_l4_ick,
2280         &aes2_ick,
2281         &sha12_ick,
2282         &des2_ick,
2283         &mmc2_ick,
2284         &mmc1_ick,
2285         &mspro_ick,
2286         &hdq_ick,
2287         &mcspi4_ick,
2288         &mcspi3_ick,
2289         &mcspi2_ick,
2290         &mcspi1_ick,
2291         &i2c3_ick,
2292         &i2c2_ick,
2293         &i2c1_ick,
2294         &uart2_ick,
2295         &uart1_ick,
2296         &gpt11_ick,
2297         &gpt10_ick,
2298         &mcbsp5_ick,
2299         &mcbsp1_ick,
2300         &fac_ick,
2301         &mailboxes_ick,
2302         &omapctrl_ick,
2303         &ssi_l4_ick,
2304         &ssi_ick,
2305         &usb_l4_ick,
2306         &security_l4_ick2,
2307         &aes1_ick,
2308         &rng_ick,
2309         &sha11_ick,
2310         &des1_ick,
2311         &dss1_alwon_fck,
2312         &dss_tv_fck,
2313         &dss_96m_fck,
2314         &dss2_alwon_fck,
2315         &dss_l3_ick,
2316         &dss_l4_ick,
2317         &cam_mclk,
2318         &cam_l3_ick,
2319         &cam_l4_ick,
2320         &gpt1_fck,
2321         &wkup_32k_fck,
2322         &gpio1_fck,
2323         &wdt2_fck,
2324         &wkup_l4_ick,
2325         &wdt2_ick,
2326         &wdt1_ick,
2327         &gpio1_ick,
2328         &omap_32ksync_ick,
2329         &gpt12_ick,
2330         &gpt1_ick,
2331         &per_96m_fck,
2332         &per_48m_fck,
2333         &uart3_fck,
2334         &gpt2_fck,
2335         &gpt3_fck,
2336         &gpt4_fck,
2337         &gpt5_fck,
2338         &gpt6_fck,
2339         &gpt7_fck,
2340         &gpt8_fck,
2341         &gpt9_fck,
2342         &per_32k_alwon_fck,
2343         &gpio6_fck,
2344         &gpio5_fck,
2345         &gpio4_fck,
2346         &gpio3_fck,
2347         &gpio2_fck,
2348         &wdt3_fck,
2349         &per_l4_ick,
2350         &gpio6_ick,
2351         &gpio5_ick,
2352         &gpio4_ick,
2353         &gpio3_ick,
2354         &gpio2_ick,
2355         &wdt3_ick,
2356         &uart3_ick,
2357         &gpt9_ick,
2358         &gpt8_ick,
2359         &gpt7_ick,
2360         &gpt6_ick,
2361         &gpt5_ick,
2362         &gpt4_ick,
2363         &gpt3_ick,
2364         &gpt2_ick,
2365         &mcbsp2_ick,
2366         &mcbsp3_ick,
2367         &mcbsp4_ick,
2368         &mcbsp2_fck,
2369         &mcbsp3_fck,
2370         &mcbsp4_fck,
2371         &emu_src_ck,
2372         &pclk_fck,
2373         &pclkx2_fck,
2374         &atclk_fck,
2375         &traceclk_src_fck,
2376         &traceclk_fck,
2377         &sr1_fck,
2378         &sr2_fck,
2379         &sr_l4_ick,
2380         &secure_32k_fck,
2381         &gpt12_fck,
2382         &wdt1_fck,
2383 };
2384
2385 #endif