arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <asm/arch/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  52 #define DPLL_LOW_POWER_STOP             0x1
  53 #define DPLL_LOW_POWER_BYPASS           0x5
  54 #define DPLL_LOCKED                     0x7
  55
  56 /* PRM CLOCKS */
  57
  58 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  59 static struct clk omap_32k_fck = {
  60         .name           = "omap_32k_fck",
  61         .rate           = 32768,
  62         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  63                                 ALWAYS_ENABLED,
  64         .recalc         = &propagate_rate,
  65 };
  66
  67 static struct clk secure_32k_fck = {
  68         .name           = "secure_32k_fck",
  69         .rate           = 32768,
  70         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  71                                 ALWAYS_ENABLED,
  72         .recalc         = &propagate_rate,
  73 };
  74
  75 /* Virtual source clocks for osc_sys_ck */
  76 static struct clk virt_12m_ck = {
  77         .name           = "virt_12m_ck",
  78         .rate           = 12000000,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .recalc         = &propagate_rate,
  82 };
  83
  84 static struct clk virt_13m_ck = {
  85         .name           = "virt_13m_ck",
  86         .rate           = 13000000,
  87         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  88                                 ALWAYS_ENABLED,
  89         .recalc         = &propagate_rate,
  90 };
  91
  92 static struct clk virt_16_8m_ck = {
  93         .name           = "virt_16_8m_ck",
  94         .rate           = 16800000,
  95         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  96                                 ALWAYS_ENABLED,
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_19_2m_ck = {
 101         .name           = "virt_19_2m_ck",
 102         .rate           = 19200000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .recalc         = &propagate_rate,
 106 };
 107
 108 static struct clk virt_26m_ck = {
 109         .name           = "virt_26m_ck",
 110         .rate           = 26000000,
 111         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 112                                 ALWAYS_ENABLED,
 113         .recalc         = &propagate_rate,
 114 };
 115
 116 static struct clk virt_38_4m_ck = {
 117         .name           = "virt_38_4m_ck",
 118         .rate           = 38400000,
 119         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 120                                 ALWAYS_ENABLED,
 121         .recalc         = &propagate_rate,
 122 };
 123
 124 static const struct clksel_rate osc_sys_12m_rates[] = {
 125         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 126         { .div = 0 }
 127 };
 128
 129 static const struct clksel_rate osc_sys_13m_rates[] = {
 130         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 131         { .div = 0 }
 132 };
 133
 134 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 135         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 136         { .div = 0 }
 137 };
 138
 139 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 141         { .div = 0 }
 142 };
 143
 144 static const struct clksel_rate osc_sys_26m_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 146         { .div = 0 }
 147 };
 148
 149 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 151         { .div = 0 }
 152 };
 153
 154 static const struct clksel osc_sys_clksel[] = {
 155         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 156         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 157         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 158         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 159         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 160         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 161         { .parent = NULL },
 162 };
 163
 164 /* Oscillator clock */
 165 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 166 static struct clk osc_sys_ck = {
 167         .name           = "osc_sys_ck",
 168         .init           = &omap2_init_clksel_parent,
 169         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 170         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 171         .clksel         = osc_sys_clksel,
 172         /* REVISIT: deal with autoextclkmode? */
 173         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 174                                 ALWAYS_ENABLED,
 175         .recalc         = &omap2_clksel_recalc,
 176 };
 177
 178 static const struct clksel_rate div2_rates[] = {
 179         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 180         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 181         { .div = 0 }
 182 };
 183
 184 static const struct clksel sys_clksel[] = {
 185         { .parent = &osc_sys_ck, .rates = div2_rates },
 186         { .parent = NULL }
 187 };
 188
 189 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 190 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 191 static struct clk sys_ck = {
 192         .name           = "sys_ck",
 193         .parent         = &osc_sys_ck,
 194         .init           = &omap2_init_clksel_parent,
 195         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 196         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 197         .clksel         = sys_clksel,
 198         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 199         .recalc         = &omap2_clksel_recalc,
 200 };
 201
 202 static struct clk sys_altclk = {
 203         .name           = "sys_altclk",
 204         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 205         .recalc         = &propagate_rate,
 206 };
 207
 208 /* Optional external clock input for some McBSPs */
 209 static struct clk mcbsp_clks = {
 210         .name           = "mcbsp_clks",
 211         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 212         .recalc         = &propagate_rate,
 213 };
 214
 215 /* PRM EXTERNAL CLOCK OUTPUT */
 216
 217 static struct clk sys_clkout1 = {
 218         .name           = "sys_clkout1",
 219         .parent         = &osc_sys_ck,
 220         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 221         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 222         .flags          = CLOCK_IN_OMAP343X,
 223         .recalc         = &followparent_recalc,
 224 };
 225
 226 /* DPLLS */
 227
 228 /* CM CLOCKS */
 229
 230 static const struct clksel_rate dpll_bypass_rates[] = {
 231         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 232         { .div = 0 }
 233 };
 234
 235 static const struct clksel_rate dpll_locked_rates[] = {
 236         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 237         { .div = 0 }
 238 };
 239
 240 static const struct clksel_rate div16_dpll_rates[] = {
 241         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 242         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 243         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 244         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 245         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 246         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 247         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 248         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 249         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 250         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 251         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 252         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 253         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 254         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 255         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 256         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 257         { .div = 0 }
 258 };
 259
 260 /* DPLL1 */
 261 /* MPU clock source */
 262 /* Type: DPLL */
 263 static struct dpll_data dpll1_dd = {
 264         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 265         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 266         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 267         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 268         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 269         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 270         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 271         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 272         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 273         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 274         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 275         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 276         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 277         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 278         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 279         .max_divider    = OMAP3_MAX_DPLL_DIV,
 280         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 281 };
 282
 283 static struct clk dpll1_ck = {
 284         .name           = "dpll1_ck",
 285         .parent         = &sys_ck,
 286         .dpll_data      = &dpll1_dd,
 287         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 288         .round_rate     = &omap2_dpll_round_rate,
 289         .set_rate       = &omap3_noncore_dpll_set_rate,
 290         .recalc         = &omap3_dpll_recalc,
 291 };
 292
 293 /*
 294  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 295  * DPLL isn't bypassed.
 296  */
 297 static struct clk dpll1_x2_ck = {
 298         .name           = "dpll1_x2_ck",
 299         .parent         = &dpll1_ck,
 300         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 301                                 PARENT_CONTROLS_CLOCK,
 302         .recalc         = &omap3_clkoutx2_recalc,
 303 };
 304
 305 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 306 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 307         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 308         { .parent = NULL }
 309 };
 310
 311 /*
 312  * Does not exist in the TRM - needed to separate the M2 divider from
 313  * bypass selection in mpu_ck
 314  */
 315 static struct clk dpll1_x2m2_ck = {
 316         .name           = "dpll1_x2m2_ck",
 317         .parent         = &dpll1_x2_ck,
 318         .init           = &omap2_init_clksel_parent,
 319         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 320         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 321         .clksel         = div16_dpll1_x2m2_clksel,
 322         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 323                                 PARENT_CONTROLS_CLOCK,
 324         .recalc         = &omap2_clksel_recalc,
 325 };
 326
 327 /* DPLL2 */
 328 /* IVA2 clock source */
 329 /* Type: DPLL */
 330
 331 static struct dpll_data dpll2_dd = {
 332         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 333         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 334         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 335         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 336         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 337         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 338         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 339                                 (1 << DPLL_LOW_POWER_BYPASS),
 340         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 341         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 342         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 343         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 344         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 345         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 346         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 347         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 348         .max_divider    = OMAP3_MAX_DPLL_DIV,
 349         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 350 };
 351
 352 static struct clk dpll2_ck = {
 353         .name           = "dpll2_ck",
 354         .parent         = &sys_ck,
 355         .dpll_data      = &dpll2_dd,
 356         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 357         .enable         = &omap3_noncore_dpll_enable,
 358         .disable        = &omap3_noncore_dpll_disable,
 359         .round_rate     = &omap2_dpll_round_rate,
 360         .set_rate       = &omap3_noncore_dpll_set_rate,
 361         .recalc         = &omap3_dpll_recalc,
 362 };
 363
 364 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 365         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 366         { .parent = NULL }
 367 };
 368
 369 /*
 370  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 371  * or CLKOUTX2. CLKOUT seems most plausible.
 372  */
 373 static struct clk dpll2_m2_ck = {
 374         .name           = "dpll2_m2_ck",
 375         .parent         = &dpll2_ck,
 376         .init           = &omap2_init_clksel_parent,
 377         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 378                                           OMAP3430_CM_CLKSEL2_PLL),
 379         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 380         .clksel         = div16_dpll2_m2x2_clksel,
 381         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 382                                 PARENT_CONTROLS_CLOCK,
 383         .recalc         = &omap2_clksel_recalc,
 384 };
 385
 386 /*
 387  * DPLL3
 388  * Source clock for all interfaces and for some device fclks
 389  * REVISIT: Also supports fast relock bypass - not included below
 390  */
 391 static struct dpll_data dpll3_dd = {
 392         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 393         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 394         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 395         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 396         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 397         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 398         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 399         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 400         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 401         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 402         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 403         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 404         .max_divider    = OMAP3_MAX_DPLL_DIV,
 405         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 406 };
 407
 408 static struct clk dpll3_ck = {
 409         .name           = "dpll3_ck",
 410         .parent         = &sys_ck,
 411         .dpll_data      = &dpll3_dd,
 412         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 413         .round_rate     = &omap2_dpll_round_rate,
 414         .set_rate       = &omap3_noncore_dpll_set_rate,
 415         .recalc         = &omap3_dpll_recalc,
 416 };
 417
 418 /*
 419  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 420  * DPLL isn't bypassed
 421  */
 422 static struct clk dpll3_x2_ck = {
 423         .name           = "dpll3_x2_ck",
 424         .parent         = &dpll3_ck,
 425         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 426                                 PARENT_CONTROLS_CLOCK,
 427         .recalc         = &omap3_clkoutx2_recalc,
 428 };
 429
 430 static const struct clksel_rate div31_dpll3_rates[] = {
 431         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 432         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 433         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 434         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 435         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 436         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 437         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 438         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 439         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 440         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 441         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 442         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 443         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 444         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 445         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 446         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 447         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 448         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 449         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 450         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 451         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 452         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 453         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 454         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 455         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 456         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 457         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 458         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 459         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 460         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 461         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 462         { .div = 0 },
 463 };
 464
 465 static const struct clksel div31_dpll3m2_clksel[] = {
 466         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 467         { .parent = NULL }
 468 };
 469
 470 /*
 471  * DPLL3 output M2
 472  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 473  * that code is ready, this should remain a 'read-only' clksel clock.
 474  */
 475 static struct clk dpll3_m2_ck = {
 476         .name           = "dpll3_m2_ck",
 477         .parent         = &dpll3_ck,
 478         .init           = &omap2_init_clksel_parent,
 479         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 480         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 481         .clksel         = div31_dpll3m2_clksel,
 482         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 483                                 PARENT_CONTROLS_CLOCK,
 484         .recalc         = &omap2_clksel_recalc,
 485 };
 486
 487 static const struct clksel core_ck_clksel[] = {
 488         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 489         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 490         { .parent = NULL }
 491 };
 492
 493 static struct clk core_ck = {
 494         .name           = "core_ck",
 495         .init           = &omap2_init_clksel_parent,
 496         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 497         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 498         .clksel         = core_ck_clksel,
 499         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 500                                 PARENT_CONTROLS_CLOCK,
 501         .recalc         = &omap2_clksel_recalc,
 502 };
 503
 504 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 505         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 506         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 507         { .parent = NULL }
 508 };
 509
 510 static struct clk dpll3_m2x2_ck = {
 511         .name           = "dpll3_m2x2_ck",
 512         .init           = &omap2_init_clksel_parent,
 513         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 514         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 515         .clksel         = dpll3_m2x2_ck_clksel,
 516         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 517                                 PARENT_CONTROLS_CLOCK,
 518         .recalc         = &omap2_clksel_recalc,
 519 };
 520
 521 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 522 static const struct clksel div16_dpll3_clksel[] = {
 523         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 524         { .parent = NULL }
 525 };
 526
 527 /* This virtual clock is the source for dpll3_m3x2_ck */
 528 static struct clk dpll3_m3_ck = {
 529         .name           = "dpll3_m3_ck",
 530         .parent         = &dpll3_ck,
 531         .init           = &omap2_init_clksel_parent,
 532         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 533         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 534         .clksel         = div16_dpll3_clksel,
 535         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 536                                 PARENT_CONTROLS_CLOCK,
 537         .recalc         = &omap2_clksel_recalc,
 538 };
 539
 540 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 541 static struct clk dpll3_m3x2_ck = {
 542         .name           = "dpll3_m3x2_ck",
 543         .parent         = &dpll3_m3_ck,
 544         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 545         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 546         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 547         .recalc         = &omap3_clkoutx2_recalc,
 548 };
 549
 550 static const struct clksel emu_core_alwon_ck_clksel[] = {
 551         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 552         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 553         { .parent = NULL }
 554 };
 555
 556 static struct clk emu_core_alwon_ck = {
 557         .name           = "emu_core_alwon_ck",
 558         .parent         = &dpll3_m3x2_ck,
 559         .init           = &omap2_init_clksel_parent,
 560         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 561         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 562         .clksel         = emu_core_alwon_ck_clksel,
 563         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 564                                 PARENT_CONTROLS_CLOCK,
 565         .recalc         = &omap2_clksel_recalc,
 566 };
 567
 568 /* DPLL4 */
 569 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 570 /* Type: DPLL */
 571 static struct dpll_data dpll4_dd = {
 572         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 573         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 574         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 575         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 576         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 577         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 578         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 579         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 580         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 581         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 582         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 583         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 584         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 585         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 586         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 587         .max_divider    = OMAP3_MAX_DPLL_DIV,
 588         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 589 };
 590
 591 static struct clk dpll4_ck = {
 592         .name           = "dpll4_ck",
 593         .parent         = &sys_ck,
 594         .dpll_data      = &dpll4_dd,
 595         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 596         .enable         = &omap3_noncore_dpll_enable,
 597         .disable        = &omap3_noncore_dpll_disable,
 598         .round_rate     = &omap2_dpll_round_rate,
 599         .set_rate       = &omap3_noncore_dpll_set_rate,
 600         .recalc         = &omap3_dpll_recalc,
 601 };
 602
 603 /*
 604  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 605  * DPLL isn't bypassed --
 606  * XXX does this serve any downstream clocks?
 607  */
 608 static struct clk dpll4_x2_ck = {
 609         .name           = "dpll4_x2_ck",
 610         .parent         = &dpll4_ck,
 611         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 612                                 PARENT_CONTROLS_CLOCK,
 613         .recalc         = &omap3_clkoutx2_recalc,
 614 };
 615
 616 static const struct clksel div16_dpll4_clksel[] = {
 617         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 618         { .parent = NULL }
 619 };
 620
 621 /* This virtual clock is the source for dpll4_m2x2_ck */
 622 static struct clk dpll4_m2_ck = {
 623         .name           = "dpll4_m2_ck",
 624         .parent         = &dpll4_ck,
 625         .init           = &omap2_init_clksel_parent,
 626         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 627         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 628         .clksel         = div16_dpll4_clksel,
 629         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 630                                 PARENT_CONTROLS_CLOCK,
 631         .recalc         = &omap2_clksel_recalc,
 632 };
 633
 634 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 635 static struct clk dpll4_m2x2_ck = {
 636         .name           = "dpll4_m2x2_ck",
 637         .parent         = &dpll4_m2_ck,
 638         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 639         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 640         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 641         .recalc         = &omap3_clkoutx2_recalc,
 642 };
 643
 644 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 645         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 646         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 647         { .parent = NULL }
 648 };
 649
 650 static struct clk omap_96m_alwon_fck = {
 651         .name           = "omap_96m_alwon_fck",
 652         .parent         = &dpll4_m2x2_ck,
 653         .init           = &omap2_init_clksel_parent,
 654         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 655         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 656         .clksel         = omap_96m_alwon_fck_clksel,
 657         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 658                                  PARENT_CONTROLS_CLOCK,
 659         .recalc         = &omap2_clksel_recalc,
 660 };
 661
 662 static struct clk omap_96m_fck = {
 663         .name           = "omap_96m_fck",
 664         .parent         = &omap_96m_alwon_fck,
 665         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 666                                 PARENT_CONTROLS_CLOCK,
 667         .recalc         = &followparent_recalc,
 668 };
 669
 670 static const struct clksel cm_96m_fck_clksel[] = {
 671         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 672         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 673         { .parent = NULL }
 674 };
 675
 676 static struct clk cm_96m_fck = {
 677         .name           = "cm_96m_fck",
 678         .parent         = &dpll4_m2x2_ck,
 679         .init           = &omap2_init_clksel_parent,
 680         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 681         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 682         .clksel         = cm_96m_fck_clksel,
 683         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 684                                 PARENT_CONTROLS_CLOCK,
 685         .recalc         = &omap2_clksel_recalc,
 686 };
 687
 688 /* This virtual clock is the source for dpll4_m3x2_ck */
 689 static struct clk dpll4_m3_ck = {
 690         .name           = "dpll4_m3_ck",
 691         .parent         = &dpll4_ck,
 692         .init           = &omap2_init_clksel_parent,
 693         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 694         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 695         .clksel         = div16_dpll4_clksel,
 696         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 697                                 PARENT_CONTROLS_CLOCK,
 698         .recalc         = &omap2_clksel_recalc,
 699 };
 700
 701 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 702 static struct clk dpll4_m3x2_ck = {
 703         .name           = "dpll4_m3x2_ck",
 704         .parent         = &dpll4_m3_ck,
 705         .init           = &omap2_init_clksel_parent,
 706         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 707         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 708         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 709         .recalc         = &omap3_clkoutx2_recalc,
 710 };
 711
 712 static const struct clksel virt_omap_54m_fck_clksel[] = {
 713         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 714         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 715         { .parent = NULL }
 716 };
 717
 718 static struct clk virt_omap_54m_fck = {
 719         .name           = "virt_omap_54m_fck",
 720         .parent         = &dpll4_m3x2_ck,
 721         .init           = &omap2_init_clksel_parent,
 722         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 723         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 724         .clksel         = virt_omap_54m_fck_clksel,
 725         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 726                                 PARENT_CONTROLS_CLOCK,
 727         .recalc         = &omap2_clksel_recalc,
 728 };
 729
 730 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 731         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 732         { .div = 0 }
 733 };
 734
 735 static const struct clksel_rate omap_54m_alt_rates[] = {
 736         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 737         { .div = 0 }
 738 };
 739
 740 static const struct clksel omap_54m_clksel[] = {
 741         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 742         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 743         { .parent = NULL }
 744 };
 745
 746 static struct clk omap_54m_fck = {
 747         .name           = "omap_54m_fck",
 748         .init           = &omap2_init_clksel_parent,
 749         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 750         .clksel_mask    = OMAP3430_SOURCE_54M,
 751         .clksel         = omap_54m_clksel,
 752         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 753                                 PARENT_CONTROLS_CLOCK,
 754         .recalc         = &omap2_clksel_recalc,
 755 };
 756
 757 static const struct clksel_rate omap_48m_96md2_rates[] = {
 758         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 759         { .div = 0 }
 760 };
 761
 762 static const struct clksel_rate omap_48m_alt_rates[] = {
 763         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 764         { .div = 0 }
 765 };
 766
 767 static const struct clksel omap_48m_clksel[] = {
 768         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 769         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 770         { .parent = NULL }
 771 };
 772
 773 static struct clk omap_48m_fck = {
 774         .name           = "omap_48m_fck",
 775         .init           = &omap2_init_clksel_parent,
 776         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 777         .clksel_mask    = OMAP3430_SOURCE_48M,
 778         .clksel         = omap_48m_clksel,
 779         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 780                                 PARENT_CONTROLS_CLOCK,
 781         .recalc         = &omap2_clksel_recalc,
 782 };
 783
 784 static struct clk omap_12m_fck = {
 785         .name           = "omap_12m_fck",
 786         .parent         = &omap_48m_fck,
 787         .fixed_div      = 4,
 788         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 789                                 PARENT_CONTROLS_CLOCK,
 790         .recalc         = &omap2_fixed_divisor_recalc,
 791 };
 792
 793 /* This virstual clock is the source for dpll4_m4x2_ck */
 794 static struct clk dpll4_m4_ck = {
 795         .name           = "dpll4_m4_ck",
 796         .parent         = &dpll4_ck,
 797         .init           = &omap2_init_clksel_parent,
 798         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 799         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 800         .clksel         = div16_dpll4_clksel,
 801         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 802                                 PARENT_CONTROLS_CLOCK,
 803         .recalc         = &omap2_clksel_recalc,
 804 };
 805
 806 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 807 static struct clk dpll4_m4x2_ck = {
 808         .name           = "dpll4_m4x2_ck",
 809         .parent         = &dpll4_m4_ck,
 810         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 811         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 812         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 813         .recalc         = &omap3_clkoutx2_recalc,
 814 };
 815
 816 /* This virtual clock is the source for dpll4_m5x2_ck */
 817 static struct clk dpll4_m5_ck = {
 818         .name           = "dpll4_m5_ck",
 819         .parent         = &dpll4_ck,
 820         .init           = &omap2_init_clksel_parent,
 821         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 822         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 823         .clksel         = div16_dpll4_clksel,
 824         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 825                                 PARENT_CONTROLS_CLOCK,
 826         .recalc         = &omap2_clksel_recalc,
 827 };
 828
 829 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 830 static struct clk dpll4_m5x2_ck = {
 831         .name           = "dpll4_m5x2_ck",
 832         .parent         = &dpll4_m5_ck,
 833         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 834         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 835         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 836         .recalc         = &omap3_clkoutx2_recalc,
 837 };
 838
 839 /* This virtual clock is the source for dpll4_m6x2_ck */
 840 static struct clk dpll4_m6_ck = {
 841         .name           = "dpll4_m6_ck",
 842         .parent         = &dpll4_ck,
 843         .init           = &omap2_init_clksel_parent,
 844         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 845         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 846         .clksel         = div16_dpll4_clksel,
 847         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 848                                 PARENT_CONTROLS_CLOCK,
 849         .recalc         = &omap2_clksel_recalc,
 850 };
 851
 852 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 853 static struct clk dpll4_m6x2_ck = {
 854         .name           = "dpll4_m6x2_ck",
 855         .parent         = &dpll4_m6_ck,
 856         .init           = &omap2_init_clksel_parent,
 857         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 858         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 859         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 860         .recalc         = &omap3_clkoutx2_recalc,
 861 };
 862
 863 static struct clk emu_per_alwon_ck = {
 864         .name           = "emu_per_alwon_ck",
 865         .parent         = &dpll4_m6x2_ck,
 866         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 867                                 PARENT_CONTROLS_CLOCK,
 868         .recalc         = &followparent_recalc,
 869 };
 870
 871 /* DPLL5 */
 872 /* Supplies 120MHz clock, USIM source clock */
 873 /* Type: DPLL */
 874 /* 3430ES2 only */
 875 static struct dpll_data dpll5_dd = {
 876         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 877         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 878         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 879         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 880         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 881         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 882         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 883         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 884         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 885         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 886         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 887         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 888         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 889         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 890         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 891         .max_divider    = OMAP3_MAX_DPLL_DIV,
 892         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 893 };
 894
 895 static struct clk dpll5_ck = {
 896         .name           = "dpll5_ck",
 897         .parent         = &sys_ck,
 898         .dpll_data      = &dpll5_dd,
 899         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 900         .enable         = &omap3_noncore_dpll_enable,
 901         .disable        = &omap3_noncore_dpll_disable,
 902         .round_rate     = &omap2_dpll_round_rate,
 903         .set_rate       = &omap3_noncore_dpll_set_rate,
 904         .recalc         = &omap3_dpll_recalc,
 905 };
 906
 907 static const struct clksel div16_dpll5_clksel[] = {
 908         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 909         { .parent = NULL }
 910 };
 911
 912 static struct clk dpll5_m2_ck = {
 913         .name           = "dpll5_m2_ck",
 914         .parent         = &dpll5_ck,
 915         .init           = &omap2_init_clksel_parent,
 916         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 917         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 918         .clksel         = div16_dpll5_clksel,
 919         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 920         .recalc         = &omap2_clksel_recalc,
 921 };
 922
 923 static const struct clksel omap_120m_fck_clksel[] = {
 924         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 925         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 926         { .parent = NULL }
 927 };
 928
 929 static struct clk omap_120m_fck = {
 930         .name           = "omap_120m_fck",
 931         .parent         = &dpll5_m2_ck,
 932         .init           = &omap2_init_clksel_parent,
 933         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 934         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 935         .clksel         = omap_120m_fck_clksel,
 936         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 937                                 PARENT_CONTROLS_CLOCK,
 938         .recalc         = &omap2_clksel_recalc,
 939 };
 940
 941 /* CM EXTERNAL CLOCK OUTPUTS */
 942
 943 static const struct clksel_rate clkout2_src_core_rates[] = {
 944         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 945         { .div = 0 }
 946 };
 947
 948 static const struct clksel_rate clkout2_src_sys_rates[] = {
 949         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 950         { .div = 0 }
 951 };
 952
 953 static const struct clksel_rate clkout2_src_96m_rates[] = {
 954         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 955         { .div = 0 }
 956 };
 957
 958 static const struct clksel_rate clkout2_src_54m_rates[] = {
 959         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 960         { .div = 0 }
 961 };
 962
 963 static const struct clksel clkout2_src_clksel[] = {
 964         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 965         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 966         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 967         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 968         { .parent = NULL }
 969 };
 970
 971 static struct clk clkout2_src_ck = {
 972         .name           = "clkout2_src_ck",
 973         .init           = &omap2_init_clksel_parent,
 974         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 975         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 976         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 977         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 978         .clksel         = clkout2_src_clksel,
 979         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 980         .recalc         = &omap2_clksel_recalc,
 981 };
 982
 983 static const struct clksel_rate sys_clkout2_rates[] = {
 984         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 985         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 986         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 987         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 988         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 989         { .div = 0 },
 990 };
 991
 992 static const struct clksel sys_clkout2_clksel[] = {
 993         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 994         { .parent = NULL },
 995 };
 996
 997 static struct clk sys_clkout2 = {
 998         .name           = "sys_clkout2",
 999         .init           = &omap2_init_clksel_parent,
1000         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1001         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1002         .clksel         = sys_clkout2_clksel,
1003         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1004         .recalc         = &omap2_clksel_recalc,
1005 };
1006
1007 /* CM OUTPUT CLOCKS */
1008
1009 static struct clk corex2_fck = {
1010         .name           = "corex2_fck",
1011         .parent         = &dpll3_m2x2_ck,
1012         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1013                                 PARENT_CONTROLS_CLOCK,
1014         .recalc         = &followparent_recalc,
1015 };
1016
1017 /* DPLL power domain clock controls */
1018
1019 static const struct clksel div2_core_clksel[] = {
1020         { .parent = &core_ck, .rates = div2_rates },
1021         { .parent = NULL }
1022 };
1023
1024 /*
1025  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1026  * may be inconsistent here?
1027  */
1028 static struct clk dpll1_fck = {
1029         .name           = "dpll1_fck",
1030         .parent         = &core_ck,
1031         .init           = &omap2_init_clksel_parent,
1032         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1033         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1034         .clksel         = div2_core_clksel,
1035         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1036                                 PARENT_CONTROLS_CLOCK,
1037         .recalc         = &omap2_clksel_recalc,
1038 };
1039
1040 /*
1041  * MPU clksel:
1042  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1043  * derives from the high-frequency bypass clock originating from DPLL3,
1044  * called 'dpll1_fck'
1045  */
1046 static const struct clksel mpu_clksel[] = {
1047         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1048         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1049         { .parent = NULL }
1050 };
1051
1052 static struct clk mpu_ck = {
1053         .name           = "mpu_ck",
1054         .parent         = &dpll1_x2m2_ck,
1055         .init           = &omap2_init_clksel_parent,
1056         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1057         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1058         .clksel         = mpu_clksel,
1059         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1060                                 PARENT_CONTROLS_CLOCK,
1061         .recalc         = &omap2_clksel_recalc,
1062 };
1063
1064 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1065 static const struct clksel_rate arm_fck_rates[] = {
1066         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1067         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1068         { .div = 0 },
1069 };
1070
1071 static const struct clksel arm_fck_clksel[] = {
1072         { .parent = &mpu_ck, .rates = arm_fck_rates },
1073         { .parent = NULL }
1074 };
1075
1076 static struct clk arm_fck = {
1077         .name           = "arm_fck",
1078         .parent         = &mpu_ck,
1079         .init           = &omap2_init_clksel_parent,
1080         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1081         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1082         .clksel         = arm_fck_clksel,
1083         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1084                                 PARENT_CONTROLS_CLOCK,
1085         .recalc         = &omap2_clksel_recalc,
1086 };
1087
1088 /*
1089  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1090  * although it is referenced - so this is a guess
1091  */
1092 static struct clk emu_mpu_alwon_ck = {
1093         .name           = "emu_mpu_alwon_ck",
1094         .parent         = &mpu_ck,
1095         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1096                                 PARENT_CONTROLS_CLOCK,
1097         .recalc         = &followparent_recalc,
1098 };
1099
1100 static struct clk dpll2_fck = {
1101         .name           = "dpll2_fck",
1102         .parent         = &core_ck,
1103         .init           = &omap2_init_clksel_parent,
1104         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1105         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1106         .clksel         = div2_core_clksel,
1107         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1108                                 PARENT_CONTROLS_CLOCK,
1109         .recalc         = &omap2_clksel_recalc,
1110 };
1111
1112 /*
1113  * IVA2 clksel:
1114  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1115  * derives from the high-frequency bypass clock originating from DPLL3,
1116  * called 'dpll2_fck'
1117  */
1118
1119 static const struct clksel iva2_clksel[] = {
1120         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1121         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1122         { .parent = NULL }
1123 };
1124
1125 static struct clk iva2_ck = {
1126         .name           = "iva2_ck",
1127         .parent         = &dpll2_m2_ck,
1128         .init           = &omap2_init_clksel_parent,
1129         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1130         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1131         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1132                                           OMAP3430_CM_IDLEST_PLL),
1133         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1134         .clksel         = iva2_clksel,
1135         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1136         .recalc         = &omap2_clksel_recalc,
1137 };
1138
1139 /* Common interface clocks */
1140
1141 static struct clk l3_ick = {
1142         .name           = "l3_ick",
1143         .parent         = &core_ck,
1144         .init           = &omap2_init_clksel_parent,
1145         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1146         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1147         .clksel         = div2_core_clksel,
1148         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1149                                 PARENT_CONTROLS_CLOCK,
1150         .recalc         = &omap2_clksel_recalc,
1151 };
1152
1153 static const struct clksel div2_l3_clksel[] = {
1154         { .parent = &l3_ick, .rates = div2_rates },
1155         { .parent = NULL }
1156 };
1157
1158 static struct clk l4_ick = {
1159         .name           = "l4_ick",
1160         .parent         = &l3_ick,
1161         .init           = &omap2_init_clksel_parent,
1162         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1163         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1164         .clksel         = div2_l3_clksel,
1165         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1166                                 PARENT_CONTROLS_CLOCK,
1167         .recalc         = &omap2_clksel_recalc,
1168
1169 };
1170
1171 static const struct clksel div2_l4_clksel[] = {
1172         { .parent = &l4_ick, .rates = div2_rates },
1173         { .parent = NULL }
1174 };
1175
1176 static struct clk rm_ick = {
1177         .name           = "rm_ick",
1178         .parent         = &l4_ick,
1179         .init           = &omap2_init_clksel_parent,
1180         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1181         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1182         .clksel         = div2_l4_clksel,
1183         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1184         .recalc         = &omap2_clksel_recalc,
1185 };
1186
1187 /* GFX power domain */
1188
1189 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1190
1191 static const struct clksel gfx_l3_clksel[] = {
1192         { .parent = &l3_ick, .rates = gfx_l3_rates },
1193         { .parent = NULL }
1194 };
1195
1196 static struct clk gfx_l3_fck = {
1197         .name           = "gfx_l3_fck",
1198         .parent         = &l3_ick,
1199         .init           = &omap2_init_clksel_parent,
1200         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1201         .enable_bit     = OMAP_EN_GFX_SHIFT,
1202         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1203         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1204         .clksel         = gfx_l3_clksel,
1205         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1206         .recalc         = &omap2_clksel_recalc,
1207 };
1208
1209 static struct clk gfx_l3_ick = {
1210         .name           = "gfx_l3_ick",
1211         .parent         = &l3_ick,
1212         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1213         .enable_bit     = OMAP_EN_GFX_SHIFT,
1214         .flags          = CLOCK_IN_OMAP3430ES1,
1215         .recalc         = &followparent_recalc,
1216 };
1217
1218 static struct clk gfx_cg1_ck = {
1219         .name           = "gfx_cg1_ck",
1220         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1221         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1222         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1223         .flags          = CLOCK_IN_OMAP3430ES1,
1224         .recalc         = &followparent_recalc,
1225 };
1226
1227 static struct clk gfx_cg2_ck = {
1228         .name           = "gfx_cg2_ck",
1229         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1230         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1231         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1232         .flags          = CLOCK_IN_OMAP3430ES1,
1233         .recalc         = &followparent_recalc,
1234 };
1235
1236 /* SGX power domain - 3430ES2 only */
1237
1238 static const struct clksel_rate sgx_core_rates[] = {
1239         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1240         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1241         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1242         { .div = 0 },
1243 };
1244
1245 static const struct clksel_rate sgx_96m_rates[] = {
1246         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1247         { .div = 0 },
1248 };
1249
1250 static const struct clksel sgx_clksel[] = {
1251         { .parent = &core_ck,    .rates = sgx_core_rates },
1252         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1253         { .parent = NULL },
1254 };
1255
1256 static struct clk sgx_fck = {
1257         .name           = "sgx_fck",
1258         .init           = &omap2_init_clksel_parent,
1259         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1260         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1261         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1262         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1263         .clksel         = sgx_clksel,
1264         .flags          = CLOCK_IN_OMAP3430ES2,
1265         .recalc         = &omap2_clksel_recalc,
1266 };
1267
1268 static struct clk sgx_ick = {
1269         .name           = "sgx_ick",
1270         .parent         = &l3_ick,
1271         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1272         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1273         .flags          = CLOCK_IN_OMAP3430ES2,
1274         .recalc         = &followparent_recalc,
1275 };
1276
1277 /* CORE power domain */
1278
1279 static struct clk d2d_26m_fck = {
1280         .name           = "d2d_26m_fck",
1281         .parent         = &sys_ck,
1282         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1283         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1284         .flags          = CLOCK_IN_OMAP3430ES1,
1285         .recalc         = &followparent_recalc,
1286 };
1287
1288 static const struct clksel omap343x_gpt_clksel[] = {
1289         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1290         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1291         { .parent = NULL}
1292 };
1293
1294 static struct clk gpt10_fck = {
1295         .name           = "gpt10_fck",
1296         .parent         = &sys_ck,
1297         .init           = &omap2_init_clksel_parent,
1298         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1299         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1300         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1301         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1302         .clksel         = omap343x_gpt_clksel,
1303         .flags          = CLOCK_IN_OMAP343X,
1304         .recalc         = &omap2_clksel_recalc,
1305 };
1306
1307 static struct clk gpt11_fck = {
1308         .name           = "gpt11_fck",
1309         .parent         = &sys_ck,
1310         .init           = &omap2_init_clksel_parent,
1311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1312         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1313         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1314         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1315         .clksel         = omap343x_gpt_clksel,
1316         .flags          = CLOCK_IN_OMAP343X,
1317         .recalc         = &omap2_clksel_recalc,
1318 };
1319
1320 static struct clk cpefuse_fck = {
1321         .name           = "cpefuse_fck",
1322         .parent         = &sys_ck,
1323         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1324         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1325         .flags          = CLOCK_IN_OMAP3430ES2,
1326         .recalc         = &followparent_recalc,
1327 };
1328
1329 static struct clk ts_fck = {
1330         .name           = "ts_fck",
1331         .parent         = &omap_32k_fck,
1332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1333         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1334         .flags          = CLOCK_IN_OMAP3430ES2,
1335         .recalc         = &followparent_recalc,
1336 };
1337
1338 static struct clk usbtll_fck = {
1339         .name           = "usbtll_fck",
1340         .parent         = &omap_120m_fck,
1341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1342         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1343         .flags          = CLOCK_IN_OMAP3430ES2,
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 /* CORE 96M FCLK-derived clocks */
1348
1349 static struct clk core_96m_fck = {
1350         .name           = "core_96m_fck",
1351         .parent         = &omap_96m_fck,
1352         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1353                                 PARENT_CONTROLS_CLOCK,
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static struct clk mmchs3_fck = {
1358         .name           = "mmchs_fck",
1359         .id             = 3,
1360         .parent         = &core_96m_fck,
1361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1362         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1363         .flags          = CLOCK_IN_OMAP3430ES2,
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 static struct clk mmchs2_fck = {
1368         .name           = "mmchs_fck",
1369         .id             = 2,
1370         .parent         = &core_96m_fck,
1371         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1372         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1373         .flags          = CLOCK_IN_OMAP343X,
1374         .recalc         = &followparent_recalc,
1375 };
1376
1377 static struct clk mspro_fck = {
1378         .name           = "mspro_fck",
1379         .parent         = &core_96m_fck,
1380         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1381         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1382         .flags          = CLOCK_IN_OMAP343X,
1383         .recalc         = &followparent_recalc,
1384 };
1385
1386 static struct clk mmchs1_fck = {
1387         .name           = "mmchs_fck",
1388         .id             = 1,
1389         .parent         = &core_96m_fck,
1390         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1392         .flags          = CLOCK_IN_OMAP343X,
1393         .recalc         = &followparent_recalc,
1394 };
1395
1396 static struct clk i2c3_fck = {
1397         .name           = "i2c_fck",
1398         .id             = 3,
1399         .parent         = &core_96m_fck,
1400         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1402         .flags          = CLOCK_IN_OMAP343X,
1403         .recalc         = &followparent_recalc,
1404 };
1405
1406 static struct clk i2c2_fck = {
1407         .name           = "i2c_fck",
1408         .id             = 2,
1409         .parent         = &core_96m_fck,
1410         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1412         .flags          = CLOCK_IN_OMAP343X,
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 static struct clk i2c1_fck = {
1417         .name           = "i2c_fck",
1418         .id             = 1,
1419         .parent         = &core_96m_fck,
1420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1421         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1422         .flags          = CLOCK_IN_OMAP343X,
1423         .recalc         = &followparent_recalc,
1424 };
1425
1426 /*
1427  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1428  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1429  */
1430 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1431         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1432         { .div = 0 }
1433 };
1434
1435 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1436         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1437         { .div = 0 }
1438 };
1439
1440 static const struct clksel mcbsp_15_clksel[] = {
1441         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1442         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1443         { .parent = NULL }
1444 };
1445
1446 static struct clk mcbsp5_fck = {
1447         .name           = "mcbsp5_fck",
1448         .init           = &omap2_init_clksel_parent,
1449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1451         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1452         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1453         .clksel         = mcbsp_15_clksel,
1454         .flags          = CLOCK_IN_OMAP343X,
1455         .recalc         = &omap2_clksel_recalc,
1456 };
1457
1458 static struct clk mcbsp1_fck = {
1459         .name           = "mcbsp1_fck",
1460         .init           = &omap2_init_clksel_parent,
1461         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1463         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1464         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1465         .clksel         = mcbsp_15_clksel,
1466         .flags          = CLOCK_IN_OMAP343X,
1467         .recalc         = &omap2_clksel_recalc,
1468 };
1469
1470 /* CORE_48M_FCK-derived clocks */
1471
1472 static struct clk core_48m_fck = {
1473         .name           = "core_48m_fck",
1474         .parent         = &omap_48m_fck,
1475         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1476                                 PARENT_CONTROLS_CLOCK,
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 static struct clk mcspi4_fck = {
1481         .name           = "mcspi_fck",
1482         .id             = 4,
1483         .parent         = &core_48m_fck,
1484         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1485         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1486         .flags          = CLOCK_IN_OMAP343X,
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 static struct clk mcspi3_fck = {
1491         .name           = "mcspi_fck",
1492         .id             = 3,
1493         .parent         = &core_48m_fck,
1494         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1495         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1496         .flags          = CLOCK_IN_OMAP343X,
1497         .recalc         = &followparent_recalc,
1498 };
1499
1500 static struct clk mcspi2_fck = {
1501         .name           = "mcspi_fck",
1502         .id             = 2,
1503         .parent         = &core_48m_fck,
1504         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1505         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1506         .flags          = CLOCK_IN_OMAP343X,
1507         .recalc         = &followparent_recalc,
1508 };
1509
1510 static struct clk mcspi1_fck = {
1511         .name           = "mcspi_fck",
1512         .id             = 1,
1513         .parent         = &core_48m_fck,
1514         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1515         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1516         .flags          = CLOCK_IN_OMAP343X,
1517         .recalc         = &followparent_recalc,
1518 };
1519
1520 static struct clk uart2_fck = {
1521         .name           = "uart2_fck",
1522         .parent         = &core_48m_fck,
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1525         .flags          = CLOCK_IN_OMAP343X,
1526         .recalc         = &followparent_recalc,
1527 };
1528
1529 static struct clk uart1_fck = {
1530         .name           = "uart1_fck",
1531         .parent         = &core_48m_fck,
1532         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1533         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1534         .flags          = CLOCK_IN_OMAP343X,
1535         .recalc         = &followparent_recalc,
1536 };
1537
1538 static struct clk fshostusb_fck = {
1539         .name           = "fshostusb_fck",
1540         .parent         = &core_48m_fck,
1541         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1542         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1543         .flags          = CLOCK_IN_OMAP3430ES1,
1544         .recalc         = &followparent_recalc,
1545 };
1546
1547 /* CORE_12M_FCK based clocks */
1548
1549 static struct clk core_12m_fck = {
1550         .name           = "core_12m_fck",
1551         .parent         = &omap_12m_fck,
1552         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1553                                 PARENT_CONTROLS_CLOCK,
1554         .recalc         = &followparent_recalc,
1555 };
1556
1557 static struct clk hdq_fck = {
1558         .name           = "hdq_fck",
1559         .parent         = &core_12m_fck,
1560         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1562         .flags          = CLOCK_IN_OMAP343X,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 /* DPLL3-derived clock */
1567
1568 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1569         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1570         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1571         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1572         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1573         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1574         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1575         { .div = 0 }
1576 };
1577
1578 static const struct clksel ssi_ssr_clksel[] = {
1579         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1580         { .parent = NULL }
1581 };
1582
1583 static struct clk ssi_ssr_fck = {
1584         .name           = "ssi_ssr_fck",
1585         .init           = &omap2_init_clksel_parent,
1586         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1587         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1588         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1589         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1590         .clksel         = ssi_ssr_clksel,
1591         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1592         .recalc         = &omap2_clksel_recalc,
1593 };
1594
1595 static struct clk ssi_sst_fck = {
1596         .name           = "ssi_sst_fck",
1597         .parent         = &ssi_ssr_fck,
1598         .fixed_div      = 2,
1599         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1600         .recalc         = &omap2_fixed_divisor_recalc,
1601 };
1602
1603
1604
1605 /* CORE_L3_ICK based clocks */
1606
1607 static struct clk core_l3_ick = {
1608         .name           = "core_l3_ick",
1609         .parent         = &l3_ick,
1610         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1611                                 PARENT_CONTROLS_CLOCK,
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk hsotgusb_ick = {
1616         .name           = "hsotgusb_ick",
1617         .parent         = &core_l3_ick,
1618         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1619         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1620         .flags          = CLOCK_IN_OMAP343X,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 static struct clk sdrc_ick = {
1625         .name           = "sdrc_ick",
1626         .parent         = &core_l3_ick,
1627         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1628         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1629         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 static struct clk gpmc_fck = {
1634         .name           = "gpmc_fck",
1635         .parent         = &core_l3_ick,
1636         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1637                                 ENABLE_ON_INIT,
1638         .recalc         = &followparent_recalc,
1639 };
1640
1641 /* SECURITY_L3_ICK based clocks */
1642
1643 static struct clk security_l3_ick = {
1644         .name           = "security_l3_ick",
1645         .parent         = &l3_ick,
1646         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1647                                 PARENT_CONTROLS_CLOCK,
1648         .recalc         = &followparent_recalc,
1649 };
1650
1651 static struct clk pka_ick = {
1652         .name           = "pka_ick",
1653         .parent         = &security_l3_ick,
1654         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1655         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1656         .flags          = CLOCK_IN_OMAP343X,
1657         .recalc         = &followparent_recalc,
1658 };
1659
1660 /* CORE_L4_ICK based clocks */
1661
1662 static struct clk core_l4_ick = {
1663         .name           = "core_l4_ick",
1664         .parent         = &l4_ick,
1665         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1666                                 PARENT_CONTROLS_CLOCK,
1667         .recalc         = &followparent_recalc,
1668 };
1669
1670 static struct clk usbtll_ick = {
1671         .name           = "usbtll_ick",
1672         .parent         = &core_l4_ick,
1673         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1674         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1675         .flags          = CLOCK_IN_OMAP3430ES2,
1676         .recalc         = &followparent_recalc,
1677 };
1678
1679 static struct clk mmchs3_ick = {
1680         .name           = "mmchs_ick",
1681         .id             = 3,
1682         .parent         = &core_l4_ick,
1683         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1684         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1685         .flags          = CLOCK_IN_OMAP3430ES2,
1686         .recalc         = &followparent_recalc,
1687 };
1688
1689 /* Intersystem Communication Registers - chassis mode only */
1690 static struct clk icr_ick = {
1691         .name           = "icr_ick",
1692         .parent         = &core_l4_ick,
1693         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1694         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1695         .flags          = CLOCK_IN_OMAP343X,
1696         .recalc         = &followparent_recalc,
1697 };
1698
1699 static struct clk aes2_ick = {
1700         .name           = "aes2_ick",
1701         .parent         = &core_l4_ick,
1702         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1703         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1704         .flags          = CLOCK_IN_OMAP343X,
1705         .recalc         = &followparent_recalc,
1706 };
1707
1708 static struct clk sha12_ick = {
1709         .name           = "sha12_ick",
1710         .parent         = &core_l4_ick,
1711         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1712         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1713         .flags          = CLOCK_IN_OMAP343X,
1714         .recalc         = &followparent_recalc,
1715 };
1716
1717 static struct clk des2_ick = {
1718         .name           = "des2_ick",
1719         .parent         = &core_l4_ick,
1720         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1721         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1722         .flags          = CLOCK_IN_OMAP343X,
1723         .recalc         = &followparent_recalc,
1724 };
1725
1726 static struct clk mmchs2_ick = {
1727         .name           = "mmchs_ick",
1728         .id             = 2,
1729         .parent         = &core_l4_ick,
1730         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1731         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1732         .flags          = CLOCK_IN_OMAP343X,
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static struct clk mmchs1_ick = {
1737         .name           = "mmchs_ick",
1738         .id             = 1,
1739         .parent         = &core_l4_ick,
1740         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1741         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1742         .flags          = CLOCK_IN_OMAP343X,
1743         .recalc         = &followparent_recalc,
1744 };
1745
1746 static struct clk mspro_ick = {
1747         .name           = "mspro_ick",
1748         .parent         = &core_l4_ick,
1749         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1750         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1751         .flags          = CLOCK_IN_OMAP343X,
1752         .recalc         = &followparent_recalc,
1753 };
1754
1755 static struct clk hdq_ick = {
1756         .name           = "hdq_ick",
1757         .parent         = &core_l4_ick,
1758         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1759         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1760         .flags          = CLOCK_IN_OMAP343X,
1761         .recalc         = &followparent_recalc,
1762 };
1763
1764 static struct clk mcspi4_ick = {
1765         .name           = "mcspi_ick",
1766         .id             = 4,
1767         .parent         = &core_l4_ick,
1768         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1769         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1770         .flags          = CLOCK_IN_OMAP343X,
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk mcspi3_ick = {
1775         .name           = "mcspi_ick",
1776         .id             = 3,
1777         .parent         = &core_l4_ick,
1778         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1780         .flags          = CLOCK_IN_OMAP343X,
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 static struct clk mcspi2_ick = {
1785         .name           = "mcspi_ick",
1786         .id             = 2,
1787         .parent         = &core_l4_ick,
1788         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1790         .flags          = CLOCK_IN_OMAP343X,
1791         .recalc         = &followparent_recalc,
1792 };
1793
1794 static struct clk mcspi1_ick = {
1795         .name           = "mcspi_ick",
1796         .id             = 1,
1797         .parent         = &core_l4_ick,
1798         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1800         .flags          = CLOCK_IN_OMAP343X,
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk i2c3_ick = {
1805         .name           = "i2c_ick",
1806         .id             = 3,
1807         .parent         = &core_l4_ick,
1808         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1809         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1810         .flags          = CLOCK_IN_OMAP343X,
1811         .recalc         = &followparent_recalc,
1812 };
1813
1814 static struct clk i2c2_ick = {
1815         .name           = "i2c_ick",
1816         .id             = 2,
1817         .parent         = &core_l4_ick,
1818         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1819         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1820         .flags          = CLOCK_IN_OMAP343X,
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk i2c1_ick = {
1825         .name           = "i2c_ick",
1826         .id             = 1,
1827         .parent         = &core_l4_ick,
1828         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1830         .flags          = CLOCK_IN_OMAP343X,
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 static struct clk uart2_ick = {
1835         .name           = "uart2_ick",
1836         .parent         = &core_l4_ick,
1837         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1838         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1839         .flags          = CLOCK_IN_OMAP343X,
1840         .recalc         = &followparent_recalc,
1841 };
1842
1843 static struct clk uart1_ick = {
1844         .name           = "uart1_ick",
1845         .parent         = &core_l4_ick,
1846         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1848         .flags          = CLOCK_IN_OMAP343X,
1849         .recalc         = &followparent_recalc,
1850 };
1851
1852 static struct clk gpt11_ick = {
1853         .name           = "gpt11_ick",
1854         .parent         = &core_l4_ick,
1855         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1856         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1857         .flags          = CLOCK_IN_OMAP343X,
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 static struct clk gpt10_ick = {
1862         .name           = "gpt10_ick",
1863         .parent         = &core_l4_ick,
1864         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1866         .flags          = CLOCK_IN_OMAP343X,
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk mcbsp5_ick = {
1871         .name           = "mcbsp5_ick",
1872         .parent         = &core_l4_ick,
1873         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1874         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1875         .flags          = CLOCK_IN_OMAP343X,
1876         .recalc         = &followparent_recalc,
1877 };
1878
1879 static struct clk mcbsp1_ick = {
1880         .name           = "mcbsp1_ick",
1881         .parent         = &core_l4_ick,
1882         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1883         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1884         .flags          = CLOCK_IN_OMAP343X,
1885         .recalc         = &followparent_recalc,
1886 };
1887
1888 static struct clk fac_ick = {
1889         .name           = "fac_ick",
1890         .parent         = &core_l4_ick,
1891         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1893         .flags          = CLOCK_IN_OMAP3430ES1,
1894         .recalc         = &followparent_recalc,
1895 };
1896
1897 static struct clk mailboxes_ick = {
1898         .name           = "mailboxes_ick",
1899         .parent         = &core_l4_ick,
1900         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1902         .flags          = CLOCK_IN_OMAP343X,
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk omapctrl_ick = {
1907         .name           = "omapctrl_ick",
1908         .parent         = &core_l4_ick,
1909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1910         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1911         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1912         .recalc         = &followparent_recalc,
1913 };
1914
1915 /* SSI_L4_ICK based clocks */
1916
1917 static struct clk ssi_l4_ick = {
1918         .name           = "ssi_l4_ick",
1919         .parent         = &l4_ick,
1920         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1921         .recalc         = &followparent_recalc,
1922 };
1923
1924 static struct clk ssi_ick = {
1925         .name           = "ssi_ick",
1926         .parent         = &ssi_l4_ick,
1927         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1928         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1929         .flags          = CLOCK_IN_OMAP343X,
1930         .recalc         = &followparent_recalc,
1931 };
1932
1933 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1934  * but l4_ick makes more sense to me */
1935
1936 static const struct clksel usb_l4_clksel[] = {
1937         { .parent = &l4_ick, .rates = div2_rates },
1938         { .parent = NULL },
1939 };
1940
1941 static struct clk usb_l4_ick = {
1942         .name           = "usb_l4_ick",
1943         .parent         = &l4_ick,
1944         .init           = &omap2_init_clksel_parent,
1945         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1946         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1947         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1948         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1949         .clksel         = usb_l4_clksel,
1950         .flags          = CLOCK_IN_OMAP3430ES1,
1951         .recalc         = &omap2_clksel_recalc,
1952 };
1953
1954 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1955
1956 /* SECURITY_L4_ICK2 based clocks */
1957
1958 static struct clk security_l4_ick2 = {
1959         .name           = "security_l4_ick2",
1960         .parent         = &l4_ick,
1961         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1962                                 PARENT_CONTROLS_CLOCK,
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk aes1_ick = {
1967         .name           = "aes1_ick",
1968         .parent         = &security_l4_ick2,
1969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1970         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1971         .flags          = CLOCK_IN_OMAP343X,
1972         .recalc         = &followparent_recalc,
1973 };
1974
1975 static struct clk rng_ick = {
1976         .name           = "rng_ick",
1977         .parent         = &security_l4_ick2,
1978         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1979         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1980         .flags          = CLOCK_IN_OMAP343X,
1981         .recalc         = &followparent_recalc,
1982 };
1983
1984 static struct clk sha11_ick = {
1985         .name           = "sha11_ick",
1986         .parent         = &security_l4_ick2,
1987         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1988         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1989         .flags          = CLOCK_IN_OMAP343X,
1990         .recalc         = &followparent_recalc,
1991 };
1992
1993 static struct clk des1_ick = {
1994         .name           = "des1_ick",
1995         .parent         = &security_l4_ick2,
1996         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1997         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1998         .flags          = CLOCK_IN_OMAP343X,
1999         .recalc         = &followparent_recalc,
2000 };
2001
2002 /* DSS */
2003 static const struct clksel dss1_alwon_fck_clksel[] = {
2004         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2005         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2006         { .parent = NULL }
2007 };
2008
2009 static struct clk dss1_alwon_fck = {
2010         .name           = "dss1_alwon_fck",
2011         .parent         = &dpll4_m4x2_ck,
2012         .init           = &omap2_init_clksel_parent,
2013         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2014         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2015         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2016         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2017         .clksel         = dss1_alwon_fck_clksel,
2018         .flags          = CLOCK_IN_OMAP343X,
2019         .recalc         = &omap2_clksel_recalc,
2020 };
2021
2022 static struct clk dss_tv_fck = {
2023         .name           = "dss_tv_fck",
2024         .parent         = &omap_54m_fck,
2025         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2026         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2027         .flags          = CLOCK_IN_OMAP343X,
2028         .recalc         = &followparent_recalc,
2029 };
2030
2031 static struct clk dss_96m_fck = {
2032         .name           = "dss_96m_fck",
2033         .parent         = &omap_96m_fck,
2034         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2035         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2036         .flags          = CLOCK_IN_OMAP343X,
2037         .recalc         = &followparent_recalc,
2038 };
2039
2040 static struct clk dss2_alwon_fck = {
2041         .name           = "dss2_alwon_fck",
2042         .parent         = &sys_ck,
2043         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2044         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2045         .flags          = CLOCK_IN_OMAP343X,
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 static struct clk dss_ick = {
2050         /* Handles both L3 and L4 clocks */
2051         .name           = "dss_ick",
2052         .parent         = &l4_ick,
2053         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2054         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2055         .flags          = CLOCK_IN_OMAP343X,
2056         .recalc         = &followparent_recalc,
2057 };
2058
2059 /* CAM */
2060
2061 static const struct clksel cam_mclk_clksel[] = {
2062         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2063         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2064         { .parent = NULL }
2065 };
2066
2067 static struct clk cam_mclk = {
2068         .name           = "cam_mclk",
2069         .parent         = &dpll4_m5x2_ck,
2070         .init           = &omap2_init_clksel_parent,
2071         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2072         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2073         .clksel         = cam_mclk_clksel,
2074         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2075         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2076         .flags          = CLOCK_IN_OMAP343X,
2077         .recalc         = &omap2_clksel_recalc,
2078 };
2079
2080 static struct clk cam_l3_ick = {
2081         .name           = "cam_l3_ick",
2082         .parent         = &l3_ick,
2083         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2084         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2085         .flags          = CLOCK_IN_OMAP343X,
2086         .recalc         = &followparent_recalc,
2087 };
2088
2089 static struct clk cam_l4_ick = {
2090         .name           = "cam_l4_ick",
2091         .parent         = &l4_ick,
2092         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2093         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2094         .flags          = CLOCK_IN_OMAP343X,
2095         .recalc         = &followparent_recalc,
2096 };
2097
2098 /* USBHOST - 3430ES2 only */
2099
2100 static struct clk usbhost_120m_fck = {
2101         .name           = "usbhost_120m_fck",
2102         .parent         = &omap_120m_fck,
2103         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2104         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2105         .flags          = CLOCK_IN_OMAP3430ES2,
2106         .recalc         = &followparent_recalc,
2107 };
2108
2109 static struct clk usbhost_48m_fck = {
2110         .name           = "usbhost_48m_fck",
2111         .parent         = &omap_48m_fck,
2112         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2113         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2114         .flags          = CLOCK_IN_OMAP3430ES2,
2115         .recalc         = &followparent_recalc,
2116 };
2117
2118 static struct clk usbhost_l3_ick = {
2119         .name           = "usbhost_l3_ick",
2120         .parent         = &l3_ick,
2121         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2122         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2123         .flags          = CLOCK_IN_OMAP3430ES2,
2124         .recalc         = &followparent_recalc,
2125 };
2126
2127 static struct clk usbhost_l4_ick = {
2128         .name           = "usbhost_l4_ick",
2129         .parent         = &l4_ick,
2130         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2131         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2132         .flags          = CLOCK_IN_OMAP3430ES2,
2133         .recalc         = &followparent_recalc,
2134 };
2135
2136 static struct clk usbhost_sar_fck = {
2137         .name           = "usbhost_sar_fck",
2138         .parent         = &osc_sys_ck,
2139         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2140         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2141         .flags          = CLOCK_IN_OMAP3430ES2,
2142         .recalc         = &followparent_recalc,
2143 };
2144
2145 /* WKUP */
2146
2147 static const struct clksel_rate usim_96m_rates[] = {
2148         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2149         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2150         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2151         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2152         { .div = 0 },
2153 };
2154
2155 static const struct clksel_rate usim_120m_rates[] = {
2156         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2157         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2158         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2159         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2160         { .div = 0 },
2161 };
2162
2163 static const struct clksel usim_clksel[] = {
2164         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2165         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2166         { .parent = &sys_ck,            .rates = div2_rates },
2167         { .parent = NULL },
2168 };
2169
2170 /* 3430ES2 only */
2171 static struct clk usim_fck = {
2172         .name           = "usim_fck",
2173         .init           = &omap2_init_clksel_parent,
2174         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2175         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2176         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2177         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2178         .clksel         = usim_clksel,
2179         .flags          = CLOCK_IN_OMAP3430ES2,
2180         .recalc         = &omap2_clksel_recalc,
2181 };
2182
2183 static struct clk gpt1_fck = {
2184         .name           = "gpt1_fck",
2185         .init           = &omap2_init_clksel_parent,
2186         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2187         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2188         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2189         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2190         .clksel         = omap343x_gpt_clksel,
2191         .flags          = CLOCK_IN_OMAP343X,
2192         .recalc         = &omap2_clksel_recalc,
2193 };
2194
2195 static struct clk wkup_32k_fck = {
2196         .name           = "wkup_32k_fck",
2197         .parent         = &omap_32k_fck,
2198         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk gpio1_fck = {
2203         .name           = "gpio1_fck",
2204         .parent         = &wkup_32k_fck,
2205         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2206         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2207         .flags          = CLOCK_IN_OMAP343X,
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk wdt2_fck = {
2212         .name           = "wdt2_fck",
2213         .parent         = &wkup_32k_fck,
2214         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2215         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2216         .flags          = CLOCK_IN_OMAP343X,
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 static struct clk wkup_l4_ick = {
2221         .name           = "wkup_l4_ick",
2222         .parent         = &sys_ck,
2223         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2224         .recalc         = &followparent_recalc,
2225 };
2226
2227 /* 3430ES2 only */
2228 /* Never specifically named in the TRM, so we have to infer a likely name */
2229 static struct clk usim_ick = {
2230         .name           = "usim_ick",
2231         .parent         = &wkup_l4_ick,
2232         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2233         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2234         .flags          = CLOCK_IN_OMAP3430ES2,
2235         .recalc         = &followparent_recalc,
2236 };
2237
2238 static struct clk wdt2_ick = {
2239         .name           = "wdt2_ick",
2240         .parent         = &wkup_l4_ick,
2241         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2242         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2243         .flags          = CLOCK_IN_OMAP343X,
2244         .recalc         = &followparent_recalc,
2245 };
2246
2247 static struct clk wdt1_ick = {
2248         .name           = "wdt1_ick",
2249         .parent         = &wkup_l4_ick,
2250         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2251         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2252         .flags          = CLOCK_IN_OMAP343X,
2253         .recalc         = &followparent_recalc,
2254 };
2255
2256 static struct clk gpio1_ick = {
2257         .name           = "gpio1_ick",
2258         .parent         = &wkup_l4_ick,
2259         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2260         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2261         .flags          = CLOCK_IN_OMAP343X,
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 static struct clk omap_32ksync_ick = {
2266         .name           = "omap_32ksync_ick",
2267         .parent         = &wkup_l4_ick,
2268         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2269         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2270         .flags          = CLOCK_IN_OMAP343X,
2271         .recalc         = &followparent_recalc,
2272 };
2273
2274 static struct clk gpt12_ick = {
2275         .name           = "gpt12_ick",
2276         .parent         = &wkup_l4_ick,
2277         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2278         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2279         .flags          = CLOCK_IN_OMAP343X,
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk gpt1_ick = {
2284         .name           = "gpt1_ick",
2285         .parent         = &wkup_l4_ick,
2286         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2287         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2288         .flags          = CLOCK_IN_OMAP343X,
2289         .recalc         = &followparent_recalc,
2290 };
2291
2292
2293
2294 /* PER clock domain */
2295
2296 static struct clk per_96m_fck = {
2297         .name           = "per_96m_fck",
2298         .parent         = &omap_96m_alwon_fck,
2299         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2300                                 PARENT_CONTROLS_CLOCK,
2301         .recalc         = &followparent_recalc,
2302 };
2303
2304 static struct clk per_48m_fck = {
2305         .name           = "per_48m_fck",
2306         .parent         = &omap_48m_fck,
2307         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2308                                 PARENT_CONTROLS_CLOCK,
2309         .recalc         = &followparent_recalc,
2310 };
2311
2312 static struct clk uart3_fck = {
2313         .name           = "uart3_fck",
2314         .parent         = &per_48m_fck,
2315         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2316         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2317         .flags          = CLOCK_IN_OMAP343X,
2318         .recalc         = &followparent_recalc,
2319 };
2320
2321 static struct clk gpt2_fck = {
2322         .name           = "gpt2_fck",
2323         .init           = &omap2_init_clksel_parent,
2324         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2325         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2326         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2327         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2328         .clksel         = omap343x_gpt_clksel,
2329         .flags          = CLOCK_IN_OMAP343X,
2330         .recalc         = &omap2_clksel_recalc,
2331 };
2332
2333 static struct clk gpt3_fck = {
2334         .name           = "gpt3_fck",
2335         .init           = &omap2_init_clksel_parent,
2336         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2337         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2338         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2339         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2340         .clksel         = omap343x_gpt_clksel,
2341         .flags          = CLOCK_IN_OMAP343X,
2342         .recalc         = &omap2_clksel_recalc,
2343 };
2344
2345 static struct clk gpt4_fck = {
2346         .name           = "gpt4_fck",
2347         .init           = &omap2_init_clksel_parent,
2348         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2349         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2350         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2351         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2352         .clksel         = omap343x_gpt_clksel,
2353         .flags          = CLOCK_IN_OMAP343X,
2354         .recalc         = &omap2_clksel_recalc,
2355 };
2356
2357 static struct clk gpt5_fck = {
2358         .name           = "gpt5_fck",
2359         .init           = &omap2_init_clksel_parent,
2360         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2361         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2362         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2363         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2364         .clksel         = omap343x_gpt_clksel,
2365         .flags          = CLOCK_IN_OMAP343X,
2366         .recalc         = &omap2_clksel_recalc,
2367 };
2368
2369 static struct clk gpt6_fck = {
2370         .name           = "gpt6_fck",
2371         .init           = &omap2_init_clksel_parent,
2372         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2373         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2374         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2375         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2376         .clksel         = omap343x_gpt_clksel,
2377         .flags          = CLOCK_IN_OMAP343X,
2378         .recalc         = &omap2_clksel_recalc,
2379 };
2380
2381 static struct clk gpt7_fck = {
2382         .name           = "gpt7_fck",
2383         .init           = &omap2_init_clksel_parent,
2384         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2385         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2386         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2387         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2388         .clksel         = omap343x_gpt_clksel,
2389         .flags          = CLOCK_IN_OMAP343X,
2390         .recalc         = &omap2_clksel_recalc,
2391 };
2392
2393 static struct clk gpt8_fck = {
2394         .name           = "gpt8_fck",
2395         .init           = &omap2_init_clksel_parent,
2396         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2397         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2398         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2399         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2400         .clksel         = omap343x_gpt_clksel,
2401         .flags          = CLOCK_IN_OMAP343X,
2402         .recalc         = &omap2_clksel_recalc,
2403 };
2404
2405 static struct clk gpt9_fck = {
2406         .name           = "gpt9_fck",
2407         .init           = &omap2_init_clksel_parent,
2408         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2409         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2410         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2411         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2412         .clksel         = omap343x_gpt_clksel,
2413         .flags          = CLOCK_IN_OMAP343X,
2414         .recalc         = &omap2_clksel_recalc,
2415 };
2416
2417 static struct clk per_32k_alwon_fck = {
2418         .name           = "per_32k_alwon_fck",
2419         .parent         = &omap_32k_fck,
2420         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2421         .recalc         = &followparent_recalc,
2422 };
2423
2424 static struct clk gpio6_fck = {
2425         .name           = "gpio6_fck",
2426         .parent         = &per_32k_alwon_fck,
2427         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2428         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2429         .flags          = CLOCK_IN_OMAP343X,
2430         .recalc         = &followparent_recalc,
2431 };
2432
2433 static struct clk gpio5_fck = {
2434         .name           = "gpio5_fck",
2435         .parent         = &per_32k_alwon_fck,
2436         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2437         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2438         .flags          = CLOCK_IN_OMAP343X,
2439         .recalc         = &followparent_recalc,
2440 };
2441
2442 static struct clk gpio4_fck = {
2443         .name           = "gpio4_fck",
2444         .parent         = &per_32k_alwon_fck,
2445         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2446         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2447         .flags          = CLOCK_IN_OMAP343X,
2448         .recalc         = &followparent_recalc,
2449 };
2450
2451 static struct clk gpio3_fck = {
2452         .name           = "gpio3_fck",
2453         .parent         = &per_32k_alwon_fck,
2454         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2455         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2456         .flags          = CLOCK_IN_OMAP343X,
2457         .recalc         = &followparent_recalc,
2458 };
2459
2460 static struct clk gpio2_fck = {
2461         .name           = "gpio2_fck",
2462         .parent         = &per_32k_alwon_fck,
2463         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2464         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2465         .flags          = CLOCK_IN_OMAP343X,
2466         .recalc         = &followparent_recalc,
2467 };
2468
2469 static struct clk wdt3_fck = {
2470         .name           = "wdt3_fck",
2471         .parent         = &per_32k_alwon_fck,
2472         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2473         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2474         .flags          = CLOCK_IN_OMAP343X,
2475         .recalc         = &followparent_recalc,
2476 };
2477
2478 static struct clk per_l4_ick = {
2479         .name           = "per_l4_ick",
2480         .parent         = &l4_ick,
2481         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2482                                 PARENT_CONTROLS_CLOCK,
2483         .recalc         = &followparent_recalc,
2484 };
2485
2486 static struct clk gpio6_ick = {
2487         .name           = "gpio6_ick",
2488         .parent         = &per_l4_ick,
2489         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2490         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2491         .flags          = CLOCK_IN_OMAP343X,
2492         .recalc         = &followparent_recalc,
2493 };
2494
2495 static struct clk gpio5_ick = {
2496         .name           = "gpio5_ick",
2497         .parent         = &per_l4_ick,
2498         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2499         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2500         .flags          = CLOCK_IN_OMAP343X,
2501         .recalc         = &followparent_recalc,
2502 };
2503
2504 static struct clk gpio4_ick = {
2505         .name           = "gpio4_ick",
2506         .parent         = &per_l4_ick,
2507         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2508         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2509         .flags          = CLOCK_IN_OMAP343X,
2510         .recalc         = &followparent_recalc,
2511 };
2512
2513 static struct clk gpio3_ick = {
2514         .name           = "gpio3_ick",
2515         .parent         = &per_l4_ick,
2516         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2517         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2518         .flags          = CLOCK_IN_OMAP343X,
2519         .recalc         = &followparent_recalc,
2520 };
2521
2522 static struct clk gpio2_ick = {
2523         .name           = "gpio2_ick",
2524         .parent         = &per_l4_ick,
2525         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2526         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2527         .flags          = CLOCK_IN_OMAP343X,
2528         .recalc         = &followparent_recalc,
2529 };
2530
2531 static struct clk wdt3_ick = {
2532         .name           = "wdt3_ick",
2533         .parent         = &per_l4_ick,
2534         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2535         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2536         .flags          = CLOCK_IN_OMAP343X,
2537         .recalc         = &followparent_recalc,
2538 };
2539
2540 static struct clk uart3_ick = {
2541         .name           = "uart3_ick",
2542         .parent         = &per_l4_ick,
2543         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2544         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2545         .flags          = CLOCK_IN_OMAP343X,
2546         .recalc         = &followparent_recalc,
2547 };
2548
2549 static struct clk gpt9_ick = {
2550         .name           = "gpt9_ick",
2551         .parent         = &per_l4_ick,
2552         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2553         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2554         .flags          = CLOCK_IN_OMAP343X,
2555         .recalc         = &followparent_recalc,
2556 };
2557
2558 static struct clk gpt8_ick = {
2559         .name           = "gpt8_ick",
2560         .parent         = &per_l4_ick,
2561         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2562         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2563         .flags          = CLOCK_IN_OMAP343X,
2564         .recalc         = &followparent_recalc,
2565 };
2566
2567 static struct clk gpt7_ick = {
2568         .name           = "gpt7_ick",
2569         .parent         = &per_l4_ick,
2570         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2571         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2572         .flags          = CLOCK_IN_OMAP343X,
2573         .recalc         = &followparent_recalc,
2574 };
2575
2576 static struct clk gpt6_ick = {
2577         .name           = "gpt6_ick",
2578         .parent         = &per_l4_ick,
2579         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2580         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2581         .flags          = CLOCK_IN_OMAP343X,
2582         .recalc         = &followparent_recalc,
2583 };
2584
2585 static struct clk gpt5_ick = {
2586         .name           = "gpt5_ick",
2587         .parent         = &per_l4_ick,
2588         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2589         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2590         .flags          = CLOCK_IN_OMAP343X,
2591         .recalc         = &followparent_recalc,
2592 };
2593
2594 static struct clk gpt4_ick = {
2595         .name           = "gpt4_ick",
2596         .parent         = &per_l4_ick,
2597         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2598         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2599         .flags          = CLOCK_IN_OMAP343X,
2600         .recalc         = &followparent_recalc,
2601 };
2602
2603 static struct clk gpt3_ick = {
2604         .name           = "gpt3_ick",
2605         .parent         = &per_l4_ick,
2606         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2607         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2608         .flags          = CLOCK_IN_OMAP343X,
2609         .recalc         = &followparent_recalc,
2610 };
2611
2612 static struct clk gpt2_ick = {
2613         .name           = "gpt2_ick",
2614         .parent         = &per_l4_ick,
2615         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2616         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2617         .flags          = CLOCK_IN_OMAP343X,
2618         .recalc         = &followparent_recalc,
2619 };
2620
2621 static struct clk mcbsp2_ick = {
2622         .name           = "mcbsp2_ick",
2623         .parent         = &per_l4_ick,
2624         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2625         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2626         .flags          = CLOCK_IN_OMAP343X,
2627         .recalc         = &followparent_recalc,
2628 };
2629
2630 static struct clk mcbsp3_ick = {
2631         .name           = "mcbsp3_ick",
2632         .parent         = &per_l4_ick,
2633         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2634         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2635         .flags          = CLOCK_IN_OMAP343X,
2636         .recalc         = &followparent_recalc,
2637 };
2638
2639 static struct clk mcbsp4_ick = {
2640         .name           = "mcbsp4_ick",
2641         .parent         = &per_l4_ick,
2642         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2643         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2644         .flags          = CLOCK_IN_OMAP343X,
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static const struct clksel mcbsp_234_clksel[] = {
2649         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2650         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2651         { .parent = NULL }
2652 };
2653
2654 static struct clk mcbsp2_fck = {
2655         .name           = "mcbsp2_fck",
2656         .init           = &omap2_init_clksel_parent,
2657         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2658         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2659         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2660         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2661         .clksel         = mcbsp_234_clksel,
2662         .flags          = CLOCK_IN_OMAP343X,
2663         .recalc         = &omap2_clksel_recalc,
2664 };
2665
2666 static struct clk mcbsp3_fck = {
2667         .name           = "mcbsp3_fck",
2668         .init           = &omap2_init_clksel_parent,
2669         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2670         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2671         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2672         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2673         .clksel         = mcbsp_234_clksel,
2674         .flags          = CLOCK_IN_OMAP343X,
2675         .recalc         = &omap2_clksel_recalc,
2676 };
2677
2678 static struct clk mcbsp4_fck = {
2679         .name           = "mcbsp4_fck",
2680         .init           = &omap2_init_clksel_parent,
2681         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2682         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2683         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2684         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2685         .clksel         = mcbsp_234_clksel,
2686         .flags          = CLOCK_IN_OMAP343X,
2687         .recalc         = &omap2_clksel_recalc,
2688 };
2689
2690 /* EMU clocks */
2691
2692 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2693
2694 static const struct clksel_rate emu_src_sys_rates[] = {
2695         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2696         { .div = 0 },
2697 };
2698
2699 static const struct clksel_rate emu_src_core_rates[] = {
2700         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2701         { .div = 0 },
2702 };
2703
2704 static const struct clksel_rate emu_src_per_rates[] = {
2705         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2706         { .div = 0 },
2707 };
2708
2709 static const struct clksel_rate emu_src_mpu_rates[] = {
2710         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2711         { .div = 0 },
2712 };
2713
2714 static const struct clksel emu_src_clksel[] = {
2715         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2716         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2717         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2718         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2719         { .parent = NULL },
2720 };
2721
2722 /*
2723  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2724  * to switch the source of some of the EMU clocks.
2725  * XXX Are there CLKEN bits for these EMU clks?
2726  */
2727 static struct clk emu_src_ck = {
2728         .name           = "emu_src_ck",
2729         .init           = &omap2_init_clksel_parent,
2730         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2731         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2732         .clksel         = emu_src_clksel,
2733         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2734         .recalc         = &omap2_clksel_recalc,
2735 };
2736
2737 static const struct clksel_rate pclk_emu_rates[] = {
2738         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2739         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2740         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2741         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2742         { .div = 0 },
2743 };
2744
2745 static const struct clksel pclk_emu_clksel[] = {
2746         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2747         { .parent = NULL },
2748 };
2749
2750 static struct clk pclk_fck = {
2751         .name           = "pclk_fck",
2752         .init           = &omap2_init_clksel_parent,
2753         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2754         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2755         .clksel         = pclk_emu_clksel,
2756         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2757         .recalc         = &omap2_clksel_recalc,
2758 };
2759
2760 static const struct clksel_rate pclkx2_emu_rates[] = {
2761         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2762         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2763         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2764         { .div = 0 },
2765 };
2766
2767 static const struct clksel pclkx2_emu_clksel[] = {
2768         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2769         { .parent = NULL },
2770 };
2771
2772 static struct clk pclkx2_fck = {
2773         .name           = "pclkx2_fck",
2774         .init           = &omap2_init_clksel_parent,
2775         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2776         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2777         .clksel         = pclkx2_emu_clksel,
2778         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2779         .recalc         = &omap2_clksel_recalc,
2780 };
2781
2782 static const struct clksel atclk_emu_clksel[] = {
2783         { .parent = &emu_src_ck, .rates = div2_rates },
2784         { .parent = NULL },
2785 };
2786
2787 static struct clk atclk_fck = {
2788         .name           = "atclk_fck",
2789         .init           = &omap2_init_clksel_parent,
2790         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2791         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2792         .clksel         = atclk_emu_clksel,
2793         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2794         .recalc         = &omap2_clksel_recalc,
2795 };
2796
2797 static struct clk traceclk_src_fck = {
2798         .name           = "traceclk_src_fck",
2799         .init           = &omap2_init_clksel_parent,
2800         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2801         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2802         .clksel         = emu_src_clksel,
2803         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2804         .recalc         = &omap2_clksel_recalc,
2805 };
2806
2807 static const struct clksel_rate traceclk_rates[] = {
2808         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2809         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2810         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2811         { .div = 0 },
2812 };
2813
2814 static const struct clksel traceclk_clksel[] = {
2815         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2816         { .parent = NULL },
2817 };
2818
2819 static struct clk traceclk_fck = {
2820         .name           = "traceclk_fck",
2821         .init           = &omap2_init_clksel_parent,
2822         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2823         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2824         .clksel         = traceclk_clksel,
2825         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2826         .recalc         = &omap2_clksel_recalc,
2827 };
2828
2829 /* SR clocks */
2830
2831 /* SmartReflex fclk (VDD1) */
2832 static struct clk sr1_fck = {
2833         .name           = "sr1_fck",
2834         .parent         = &sys_ck,
2835         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2836         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2837         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2838         .recalc         = &followparent_recalc,
2839 };
2840
2841 /* SmartReflex fclk (VDD2) */
2842 static struct clk sr2_fck = {
2843         .name           = "sr2_fck",
2844         .parent         = &sys_ck,
2845         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2846         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2847         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2848         .recalc         = &followparent_recalc,
2849 };
2850
2851 static struct clk sr_l4_ick = {
2852         .name           = "sr_l4_ick",
2853         .parent         = &l4_ick,
2854         .flags          = CLOCK_IN_OMAP343X,
2855         .recalc         = &followparent_recalc,
2856 };
2857
2858 /* SECURE_32K_FCK clocks */
2859
2860 static struct clk gpt12_fck = {
2861         .name           = "gpt12_fck",
2862         .parent         = &secure_32k_fck,
2863         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2864         .recalc         = &followparent_recalc,
2865 };
2866
2867 static struct clk wdt1_fck = {
2868         .name           = "wdt1_fck",
2869         .parent         = &secure_32k_fck,
2870         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2871         .recalc         = &followparent_recalc,
2872 };
2873
2874 static struct clk *onchip_34xx_clks[] __initdata = {
2875         &omap_32k_fck,
2876         &virt_12m_ck,
2877         &virt_13m_ck,
2878         &virt_16_8m_ck,
2879         &virt_19_2m_ck,
2880         &virt_26m_ck,
2881         &virt_38_4m_ck,
2882         &osc_sys_ck,
2883         &sys_ck,
2884         &sys_altclk,
2885         &mcbsp_clks,
2886         &sys_clkout1,
2887         &dpll1_ck,
2888         &dpll1_x2_ck,
2889         &dpll1_x2m2_ck,
2890         &dpll2_ck,
2891         &dpll2_m2_ck,
2892         &dpll3_ck,
2893         &core_ck,
2894         &dpll3_x2_ck,
2895         &dpll3_m2_ck,
2896         &dpll3_m2x2_ck,
2897         &dpll3_m3_ck,
2898         &dpll3_m3x2_ck,
2899         &emu_core_alwon_ck,
2900         &dpll4_ck,
2901         &dpll4_x2_ck,
2902         &omap_96m_alwon_fck,
2903         &omap_96m_fck,
2904         &cm_96m_fck,
2905         &virt_omap_54m_fck,
2906         &omap_54m_fck,
2907         &omap_48m_fck,
2908         &omap_12m_fck,
2909         &dpll4_m2_ck,
2910         &dpll4_m2x2_ck,
2911         &dpll4_m3_ck,
2912         &dpll4_m3x2_ck,
2913         &dpll4_m4_ck,
2914         &dpll4_m4x2_ck,
2915         &dpll4_m5_ck,
2916         &dpll4_m5x2_ck,
2917         &dpll4_m6_ck,
2918         &dpll4_m6x2_ck,
2919         &emu_per_alwon_ck,
2920         &dpll5_ck,
2921         &dpll5_m2_ck,
2922         &omap_120m_fck,
2923         &clkout2_src_ck,
2924         &sys_clkout2,
2925         &corex2_fck,
2926         &dpll1_fck,
2927         &mpu_ck,
2928         &arm_fck,
2929         &emu_mpu_alwon_ck,
2930         &dpll2_fck,
2931         &iva2_ck,
2932         &l3_ick,
2933         &l4_ick,
2934         &rm_ick,
2935         &gfx_l3_fck,
2936         &gfx_l3_ick,
2937         &gfx_cg1_ck,
2938         &gfx_cg2_ck,
2939         &sgx_fck,
2940         &sgx_ick,
2941         &d2d_26m_fck,
2942         &gpt10_fck,
2943         &gpt11_fck,
2944         &cpefuse_fck,
2945         &ts_fck,
2946         &usbtll_fck,
2947         &core_96m_fck,
2948         &mmchs3_fck,
2949         &mmchs2_fck,
2950         &mspro_fck,
2951         &mmchs1_fck,
2952         &i2c3_fck,
2953         &i2c2_fck,
2954         &i2c1_fck,
2955         &mcbsp5_fck,
2956         &mcbsp1_fck,
2957         &core_48m_fck,
2958         &mcspi4_fck,
2959         &mcspi3_fck,
2960         &mcspi2_fck,
2961         &mcspi1_fck,
2962         &uart2_fck,
2963         &uart1_fck,
2964         &fshostusb_fck,
2965         &core_12m_fck,
2966         &hdq_fck,
2967         &ssi_ssr_fck,
2968         &ssi_sst_fck,
2969         &core_l3_ick,
2970         &hsotgusb_ick,
2971         &sdrc_ick,
2972         &gpmc_fck,
2973         &security_l3_ick,
2974         &pka_ick,
2975         &core_l4_ick,
2976         &usbtll_ick,
2977         &mmchs3_ick,
2978         &icr_ick,
2979         &aes2_ick,
2980         &sha12_ick,
2981         &des2_ick,
2982         &mmchs2_ick,
2983         &mmchs1_ick,
2984         &mspro_ick,
2985         &hdq_ick,
2986         &mcspi4_ick,
2987         &mcspi3_ick,
2988         &mcspi2_ick,
2989         &mcspi1_ick,
2990         &i2c3_ick,
2991         &i2c2_ick,
2992         &i2c1_ick,
2993         &uart2_ick,
2994         &uart1_ick,
2995         &gpt11_ick,
2996         &gpt10_ick,
2997         &mcbsp5_ick,
2998         &mcbsp1_ick,
2999         &fac_ick,
3000         &mailboxes_ick,
3001         &omapctrl_ick,
3002         &ssi_l4_ick,
3003         &ssi_ick,
3004         &usb_l4_ick,
3005         &security_l4_ick2,
3006         &aes1_ick,
3007         &rng_ick,
3008         &sha11_ick,
3009         &des1_ick,
3010         &dss1_alwon_fck,
3011         &dss_tv_fck,
3012         &dss_96m_fck,
3013         &dss2_alwon_fck,
3014         &dss_ick,
3015         &cam_mclk,
3016         &cam_l3_ick,
3017         &cam_l4_ick,
3018         &usbhost_120m_fck,
3019         &usbhost_48m_fck,
3020         &usbhost_l3_ick,
3021         &usbhost_l4_ick,
3022         &usbhost_sar_fck,
3023         &usim_fck,
3024         &gpt1_fck,
3025         &wkup_32k_fck,
3026         &gpio1_fck,
3027         &wdt2_fck,
3028         &wkup_l4_ick,
3029         &usim_ick,
3030         &wdt2_ick,
3031         &wdt1_ick,
3032         &gpio1_ick,
3033         &omap_32ksync_ick,
3034         &gpt12_ick,
3035         &gpt1_ick,
3036         &per_96m_fck,
3037         &per_48m_fck,
3038         &uart3_fck,
3039         &gpt2_fck,
3040         &gpt3_fck,
3041         &gpt4_fck,
3042         &gpt5_fck,
3043         &gpt6_fck,
3044         &gpt7_fck,
3045         &gpt8_fck,
3046         &gpt9_fck,
3047         &per_32k_alwon_fck,
3048         &gpio6_fck,
3049         &gpio5_fck,
3050         &gpio4_fck,
3051         &gpio3_fck,
3052         &gpio2_fck,
3053         &wdt3_fck,
3054         &per_l4_ick,
3055         &gpio6_ick,
3056         &gpio5_ick,
3057         &gpio4_ick,
3058         &gpio3_ick,
3059         &gpio2_ick,
3060         &wdt3_ick,
3061         &uart3_ick,
3062         &gpt9_ick,
3063         &gpt8_ick,
3064         &gpt7_ick,
3065         &gpt6_ick,
3066         &gpt5_ick,
3067         &gpt4_ick,
3068         &gpt3_ick,
3069         &gpt2_ick,
3070         &mcbsp2_ick,
3071         &mcbsp3_ick,
3072         &mcbsp4_ick,
3073         &mcbsp2_fck,
3074         &mcbsp3_fck,
3075         &mcbsp4_fck,
3076         &emu_src_ck,
3077         &pclk_fck,
3078         &pclkx2_fck,
3079         &atclk_fck,
3080         &traceclk_src_fck,
3081         &traceclk_fck,
3082         &sr1_fck,
3083         &sr2_fck,
3084         &sr_l4_ick,
3085         &secure_32k_fck,
3086         &gpt12_fck,
3087         &wdt1_fck,
3088 };
3089
3090 #endif