arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  53 #define DPLL_LOW_POWER_STOP             0x1
  54 #define DPLL_LOW_POWER_BYPASS           0x5
  55 #define DPLL_LOCKED                     0x7
  56
  57 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  58         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  59
  60 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  61         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  62
  63 #define OMAP3430_PRM_CLKSEL                                             \
  64         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  65
  66 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  67         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  68
  69 /* PRM CLOCKS */
  70
  71 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  72 static struct clk omap_32k_fck = {
  73         .name           = "omap_32k_fck",
  74         .rate           = 32768,
  75         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .clkdm          = { .name = "prm_clkdm" },
  78         .recalc         = &propagate_rate,
  79 };
  80
  81 static struct clk secure_32k_fck = {
  82         .name           = "secure_32k_fck",
  83         .rate           = 32768,
  84         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  85                                 ALWAYS_ENABLED,
  86         .clkdm          = { .name = "prm_clkdm" },
  87         .recalc         = &propagate_rate,
  88 };
  89
  90 /* Virtual source clocks for osc_sys_ck */
  91 static struct clk virt_12m_ck = {
  92         .name           = "virt_12m_ck",
  93         .rate           = 12000000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .clkdm          = { .name = "prm_clkdm" },
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_13m_ck = {
 101         .name           = "virt_13m_ck",
 102         .rate           = 13000000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .clkdm          = { .name = "prm_clkdm" },
 106         .recalc         = &propagate_rate,
 107 };
 108
 109 static struct clk virt_16_8m_ck = {
 110         .name           = "virt_16_8m_ck",
 111         .rate           = 16800000,
 112         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 113                                 ALWAYS_ENABLED,
 114         .clkdm          = { .name = "prm_clkdm" },
 115         .recalc         = &propagate_rate,
 116 };
 117
 118 static struct clk virt_19_2m_ck = {
 119         .name           = "virt_19_2m_ck",
 120         .rate           = 19200000,
 121         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 122                                 ALWAYS_ENABLED,
 123         .clkdm          = { .name = "prm_clkdm" },
 124         .recalc         = &propagate_rate,
 125 };
 126
 127 static struct clk virt_26m_ck = {
 128         .name           = "virt_26m_ck",
 129         .rate           = 26000000,
 130         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 131                                 ALWAYS_ENABLED,
 132         .clkdm          = { .name = "prm_clkdm" },
 133         .recalc         = &propagate_rate,
 134 };
 135
 136 static struct clk virt_38_4m_ck = {
 137         .name           = "virt_38_4m_ck",
 138         .rate           = 38400000,
 139         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 140                                 ALWAYS_ENABLED,
 141         .clkdm          = { .name = "prm_clkdm" },
 142         .recalc         = &propagate_rate,
 143 };
 144
 145 static const struct clksel_rate osc_sys_12m_rates[] = {
 146         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 147         { .div = 0 }
 148 };
 149
 150 static const struct clksel_rate osc_sys_13m_rates[] = {
 151         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 152         { .div = 0 }
 153 };
 154
 155 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 156         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 161         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 162         { .div = 0 }
 163 };
 164
 165 static const struct clksel_rate osc_sys_26m_rates[] = {
 166         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 167         { .div = 0 }
 168 };
 169
 170 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 171         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel osc_sys_clksel[] = {
 176         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 177         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 178         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 179         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 180         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 181         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 182         { .parent = NULL },
 183 };
 184
 185 /* Oscillator clock */
 186 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 187 static struct clk osc_sys_ck = {
 188         .name           = "osc_sys_ck",
 189         .init           = &omap2_init_clksel_parent,
 190         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 191         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 192         .clksel         = osc_sys_clksel,
 193         /* REVISIT: deal with autoextclkmode? */
 194         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 195                                 ALWAYS_ENABLED,
 196         .clkdm          = { .name = "prm_clkdm" },
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static const struct clksel_rate div2_rates[] = {
 201         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 202         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 203         { .div = 0 }
 204 };
 205
 206 static const struct clksel sys_clksel[] = {
 207         { .parent = &osc_sys_ck, .rates = div2_rates },
 208         { .parent = NULL }
 209 };
 210
 211 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 212 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 213 static struct clk sys_ck = {
 214         .name           = "sys_ck",
 215         .parent         = &osc_sys_ck,
 216         .init           = &omap2_init_clksel_parent,
 217         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 218         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 219         .clksel         = sys_clksel,
 220         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 221         .clkdm          = { .name = "prm_clkdm" },
 222         .recalc         = &omap2_clksel_recalc,
 223 };
 224
 225 static struct clk sys_altclk = {
 226         .name           = "sys_altclk",
 227         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 228         .clkdm          = { .name = "cm_clkdm" },
 229         .recalc         = &propagate_rate,
 230 };
 231
 232 /*
 233  * Optional external clock input for some McBSPs
 234  * Apparently this is not really in prm_clkdm, but rather is fed into
 235  * both CORE and PER separately.
 236  */
 237 static struct clk mcbsp_clks = {
 238         .name           = "mcbsp_clks",
 239         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 240         .clkdm          = { .name = "prm_clkdm" },
 241         .recalc         = &propagate_rate,
 242 };
 243
 244 /* PRM EXTERNAL CLOCK OUTPUT */
 245
 246 static struct clk sys_clkout1 = {
 247         .name           = "sys_clkout1",
 248         .parent         = &osc_sys_ck,
 249         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 250         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 251         .flags          = CLOCK_IN_OMAP343X,
 252         .clkdm          = { .name = "prm_clkdm" },
 253         .recalc         = &followparent_recalc,
 254 };
 255
 256 /* DPLLS */
 257
 258 /* CM CLOCKS */
 259
 260 static const struct clksel_rate dpll_bypass_rates[] = {
 261         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 262         { .div = 0 }
 263 };
 264
 265 static const struct clksel_rate dpll_locked_rates[] = {
 266         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 267         { .div = 0 }
 268 };
 269
 270 static const struct clksel_rate div16_dpll_rates[] = {
 271         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 272         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 273         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 274         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 275         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 276         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 277         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 278         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 279         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 280         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 281         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 282         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 283         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 284         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 285         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 286         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 287         { .div = 0 }
 288 };
 289
 290 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 291         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 292
 293 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 294         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 295
 296 /* DPLL1 */
 297 /* MPU clock source */
 298 /* Type: DPLL */
 299 static struct dpll_data dpll1_dd = {
 300         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 301         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 302         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 303         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 304         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 305         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 306         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 307         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 308         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 309         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 310         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 311         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 312         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 313         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 314         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 315         .max_divider    = OMAP3_MAX_DPLL_DIV,
 316         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 317 };
 318
 319 static struct clk dpll1_ck = {
 320         .name           = "dpll1_ck",
 321         .parent         = &sys_ck,
 322         .dpll_data      = &dpll1_dd,
 323         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 324         .round_rate     = &omap2_dpll_round_rate,
 325         .set_rate       = &omap3_noncore_dpll_set_rate,
 326         .clkdm          = { .name = "dpll1_clkdm" },
 327         .recalc         = &omap3_dpll_recalc,
 328 };
 329
 330 /*
 331  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 332  * DPLL isn't bypassed.
 333  */
 334 static struct clk dpll1_x2_ck = {
 335         .name           = "dpll1_x2_ck",
 336         .parent         = &dpll1_ck,
 337         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 338                                 PARENT_CONTROLS_CLOCK,
 339         .clkdm          = { .name = "dpll1_clkdm" },
 340         .recalc         = &omap3_clkoutx2_recalc,
 341 };
 342
 343 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 344 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 345         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 346         { .parent = NULL }
 347 };
 348
 349 /*
 350  * Does not exist in the TRM - needed to separate the M2 divider from
 351  * bypass selection in mpu_ck
 352  */
 353 static struct clk dpll1_x2m2_ck = {
 354         .name           = "dpll1_x2m2_ck",
 355         .parent         = &dpll1_x2_ck,
 356         .init           = &omap2_init_clksel_parent,
 357         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 358         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 359         .clksel         = div16_dpll1_x2m2_clksel,
 360         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 361                                 PARENT_CONTROLS_CLOCK,
 362         .clkdm          = { .name = "dpll1_clkdm" },
 363         .recalc         = &omap2_clksel_recalc,
 364 };
 365
 366 /* DPLL2 */
 367 /* IVA2 clock source */
 368 /* Type: DPLL */
 369
 370 static struct dpll_data dpll2_dd = {
 371         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 372         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 373         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 374         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 375         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 376         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 377         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 378                                 (1 << DPLL_LOW_POWER_BYPASS),
 379         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 380         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 381         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 382         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 383         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 384         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 385         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 386         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 387         .max_divider    = OMAP3_MAX_DPLL_DIV,
 388         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 389 };
 390
 391 static struct clk dpll2_ck = {
 392         .name           = "dpll2_ck",
 393         .parent         = &sys_ck,
 394         .dpll_data      = &dpll2_dd,
 395         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 396         .enable         = &omap3_noncore_dpll_enable,
 397         .disable        = &omap3_noncore_dpll_disable,
 398         .round_rate     = &omap2_dpll_round_rate,
 399         .set_rate       = &omap3_noncore_dpll_set_rate,
 400         .clkdm          = { .name = "dpll2_clkdm" },
 401         .recalc         = &omap3_dpll_recalc,
 402 };
 403
 404 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 405         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 406         { .parent = NULL }
 407 };
 408
 409 /*
 410  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 411  * or CLKOUTX2. CLKOUT seems most plausible.
 412  */
 413 static struct clk dpll2_m2_ck = {
 414         .name           = "dpll2_m2_ck",
 415         .parent         = &dpll2_ck,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 418                                           OMAP3430_CM_CLKSEL2_PLL),
 419         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 420         .clksel         = div16_dpll2_m2x2_clksel,
 421         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 422                                 PARENT_CONTROLS_CLOCK,
 423         .clkdm          = { .name = "dpll2_clkdm" },
 424         .recalc         = &omap2_clksel_recalc,
 425 };
 426
 427 /*
 428  * DPLL3
 429  * Source clock for all interfaces and for some device fclks
 430  * REVISIT: Also supports fast relock bypass - not included below
 431  */
 432 static struct dpll_data dpll3_dd = {
 433         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 434         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 435         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 436         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 437         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 438         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 439         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 440         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 441         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 442         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 443         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 444         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 445         .max_divider    = OMAP3_MAX_DPLL_DIV,
 446         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 447 };
 448
 449 static struct clk dpll3_ck = {
 450         .name           = "dpll3_ck",
 451         .parent         = &sys_ck,
 452         .dpll_data      = &dpll3_dd,
 453         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 454         .round_rate     = &omap2_dpll_round_rate,
 455         .clkdm          = { .name = "dpll3_clkdm" },
 456         .recalc         = &omap3_dpll_recalc,
 457 };
 458
 459 /*
 460  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 461  * DPLL isn't bypassed
 462  */
 463 static struct clk dpll3_x2_ck = {
 464         .name           = "dpll3_x2_ck",
 465         .parent         = &dpll3_ck,
 466         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 467                                 PARENT_CONTROLS_CLOCK,
 468         .clkdm          = { .name = "dpll3_clkdm" },
 469         .recalc         = &omap3_clkoutx2_recalc,
 470 };
 471
 472 static const struct clksel_rate div31_dpll3_rates[] = {
 473         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 474         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 475         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 476         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 477         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 478         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 479         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 480         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 481         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 482         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 483         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 484         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 485         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 486         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 487         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 488         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 489         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 490         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 491         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 492         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 493         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 494         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 495         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 496         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 497         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 498         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 499         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 500         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 501         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 502         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 503         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 504         { .div = 0 },
 505 };
 506
 507 static const struct clksel div31_dpll3m2_clksel[] = {
 508         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 509         { .parent = NULL }
 510 };
 511
 512 /* DPLL3 output M2 - primary control point for CORE speed */
 513 static struct clk dpll3_m2_ck = {
 514         .name           = "dpll3_m2_ck",
 515         .parent         = &dpll3_ck,
 516         .init           = &omap2_init_clksel_parent,
 517         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 518         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 519         .clksel         = div31_dpll3m2_clksel,
 520         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 521                                 PARENT_CONTROLS_CLOCK,
 522         .clkdm          = { .name = "dpll3_clkdm" },
 523         .round_rate     = &omap2_clksel_round_rate,
 524         .set_rate       = &omap3_core_dpll_m2_set_rate,
 525         .recalc         = &omap2_clksel_recalc,
 526 };
 527
 528 static const struct clksel core_ck_clksel[] = {
 529         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 530         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 531         { .parent = NULL }
 532 };
 533
 534 static struct clk core_ck = {
 535         .name           = "core_ck",
 536         .init           = &omap2_init_clksel_parent,
 537         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 538         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 539         .clksel         = core_ck_clksel,
 540         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 541                                 PARENT_CONTROLS_CLOCK,
 542         .clkdm          = { .name = "cm_clkdm" },
 543         .recalc         = &omap2_clksel_recalc,
 544 };
 545
 546 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 547         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 548         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 549         { .parent = NULL }
 550 };
 551
 552 static struct clk dpll3_m2x2_ck = {
 553         .name           = "dpll3_m2x2_ck",
 554         .init           = &omap2_init_clksel_parent,
 555         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 556         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 557         .clksel         = dpll3_m2x2_ck_clksel,
 558         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 559                                 PARENT_CONTROLS_CLOCK,
 560         .clkdm          = { .name = "dpll3_clkdm" },
 561         .recalc         = &omap2_clksel_recalc,
 562 };
 563
 564 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 565 static const struct clksel div16_dpll3_clksel[] = {
 566         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 567         { .parent = NULL }
 568 };
 569
 570 /* This virtual clock is the source for dpll3_m3x2_ck */
 571 static struct clk dpll3_m3_ck = {
 572         .name           = "dpll3_m3_ck",
 573         .parent         = &dpll3_ck,
 574         .init           = &omap2_init_clksel_parent,
 575         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 576         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 577         .clksel         = div16_dpll3_clksel,
 578         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 579                                 PARENT_CONTROLS_CLOCK,
 580         .clkdm          = { .name = "dpll3_clkdm" },
 581         .recalc         = &omap2_clksel_recalc,
 582 };
 583
 584 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 585 static struct clk dpll3_m3x2_ck = {
 586         .name           = "dpll3_m3x2_ck",
 587         .parent         = &dpll3_m3_ck,
 588         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 589         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 590         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 591         .clkdm          = { .name = "dpll3_clkdm" },
 592         .recalc         = &omap3_clkoutx2_recalc,
 593 };
 594
 595 static const struct clksel emu_core_alwon_ck_clksel[] = {
 596         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 597         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 598         { .parent = NULL }
 599 };
 600
 601 static struct clk emu_core_alwon_ck = {
 602         .name           = "emu_core_alwon_ck",
 603         .parent         = &dpll3_m3x2_ck,
 604         .init           = &omap2_init_clksel_parent,
 605         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 606         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 607         .clksel         = emu_core_alwon_ck_clksel,
 608         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 609                                 PARENT_CONTROLS_CLOCK,
 610         .clkdm          = { .name = "dpll3_clkdm" },
 611         .recalc         = &omap2_clksel_recalc,
 612 };
 613
 614 /* DPLL4 */
 615 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 616 /* Type: DPLL */
 617 static struct dpll_data dpll4_dd = {
 618         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 619         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 620         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 621         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 622         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 623         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 624         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 625         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 626         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 627         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 628         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 629         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 630         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 631         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 632         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 633         .max_divider    = OMAP3_MAX_DPLL_DIV,
 634         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 635 };
 636
 637 static struct clk dpll4_ck = {
 638         .name           = "dpll4_ck",
 639         .parent         = &sys_ck,
 640         .dpll_data      = &dpll4_dd,
 641         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 642         .enable         = &omap3_noncore_dpll_enable,
 643         .disable        = &omap3_noncore_dpll_disable,
 644         .round_rate     = &omap2_dpll_round_rate,
 645         .set_rate       = &omap3_noncore_dpll_set_rate,
 646         .clkdm          = { .name = "dpll4_clkdm" },
 647         .recalc         = &omap3_dpll_recalc,
 648 };
 649
 650 /*
 651  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 652  * DPLL isn't bypassed --
 653  * XXX does this serve any downstream clocks?
 654  */
 655 static struct clk dpll4_x2_ck = {
 656         .name           = "dpll4_x2_ck",
 657         .parent         = &dpll4_ck,
 658         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 659                                 PARENT_CONTROLS_CLOCK,
 660         .clkdm          = { .name = "dpll4_clkdm" },
 661         .recalc         = &omap3_clkoutx2_recalc,
 662 };
 663
 664 static const struct clksel div16_dpll4_clksel[] = {
 665         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 666         { .parent = NULL }
 667 };
 668
 669 /* This virtual clock is the source for dpll4_m2x2_ck */
 670 static struct clk dpll4_m2_ck = {
 671         .name           = "dpll4_m2_ck",
 672         .parent         = &dpll4_ck,
 673         .init           = &omap2_init_clksel_parent,
 674         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 675         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 676         .clksel         = div16_dpll4_clksel,
 677         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 678                                 PARENT_CONTROLS_CLOCK,
 679         .clkdm          = { .name = "dpll4_clkdm" },
 680         .recalc         = &omap2_clksel_recalc,
 681 };
 682
 683 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 684 static struct clk dpll4_m2x2_ck = {
 685         .name           = "dpll4_m2x2_ck",
 686         .parent         = &dpll4_m2_ck,
 687         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 688         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 689         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 690         .clkdm          = { .name = "dpll4_clkdm" },
 691         .recalc         = &omap3_clkoutx2_recalc,
 692 };
 693
 694 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 695         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 696         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 697         { .parent = NULL }
 698 };
 699
 700 /*
 701  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 702  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 703  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 704  * CM_96K_(F)CLK.
 705  */
 706 static struct clk omap_96m_alwon_fck = {
 707         .name           = "omap_96m_alwon_fck",
 708         .parent         = &dpll4_m2x2_ck,
 709         .init           = &omap2_init_clksel_parent,
 710         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 711         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 712         .clksel         = omap_96m_alwon_fck_clksel,
 713         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 714                                 PARENT_CONTROLS_CLOCK,
 715         .clkdm          = { .name = "prm_clkdm" },
 716         .recalc         = &omap2_clksel_recalc,
 717 };
 718
 719 static struct clk cm_96m_fck = {
 720         .name           = "cm_96m_fck",
 721         .parent         = &omap_96m_alwon_fck,
 722         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 723                                 PARENT_CONTROLS_CLOCK,
 724         .clkdm          = { .name = "cm_clkdm" },
 725         .recalc         = &followparent_recalc,
 726 };
 727
 728 static const struct clksel_rate omap_96m_dpll_rates[] = {
 729         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 730         { .div = 0 }
 731 };
 732
 733 static const struct clksel_rate omap_96m_sys_rates[] = {
 734         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 735         { .div = 0 }
 736 };
 737
 738 static const struct clksel omap_96m_fck_clksel[] = {
 739         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 740         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 741         { .parent = NULL }
 742 };
 743
 744 static struct clk omap_96m_fck = {
 745         .name           = "omap_96m_fck",
 746         .parent         = &sys_ck,
 747         .init           = &omap2_init_clksel_parent,
 748         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 749         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 750         .clksel         = omap_96m_fck_clksel,
 751         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 752                                 PARENT_CONTROLS_CLOCK,
 753         .clkdm          = { .name = "cm_clkdm" },
 754         .recalc         = &omap2_clksel_recalc,
 755 };
 756
 757 /* This virtual clock is the source for dpll4_m3x2_ck */
 758 static struct clk dpll4_m3_ck = {
 759         .name           = "dpll4_m3_ck",
 760         .parent         = &dpll4_ck,
 761         .init           = &omap2_init_clksel_parent,
 762         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 763         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 764         .clksel         = div16_dpll4_clksel,
 765         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 766                                 PARENT_CONTROLS_CLOCK,
 767         .clkdm          = { .name = "dpll4_clkdm" },
 768         .recalc         = &omap2_clksel_recalc,
 769 };
 770
 771 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 772 static struct clk dpll4_m3x2_ck = {
 773         .name           = "dpll4_m3x2_ck",
 774         .parent         = &dpll4_m3_ck,
 775         .init           = &omap2_init_clksel_parent,
 776         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 777         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 778         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 779         .clkdm          = { .name = "dpll4_clkdm" },
 780         .recalc         = &omap3_clkoutx2_recalc,
 781 };
 782
 783 static const struct clksel virt_omap_54m_fck_clksel[] = {
 784         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 785         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 786         { .parent = NULL }
 787 };
 788
 789 static struct clk virt_omap_54m_fck = {
 790         .name           = "virt_omap_54m_fck",
 791         .parent         = &dpll4_m3x2_ck,
 792         .init           = &omap2_init_clksel_parent,
 793         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 794         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 795         .clksel         = virt_omap_54m_fck_clksel,
 796         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 797                                 PARENT_CONTROLS_CLOCK,
 798         .clkdm          = { .name = "cm_clkdm" },
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 803         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 804         { .div = 0 }
 805 };
 806
 807 static const struct clksel_rate omap_54m_alt_rates[] = {
 808         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 809         { .div = 0 }
 810 };
 811
 812 static const struct clksel omap_54m_clksel[] = {
 813         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 814         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 815         { .parent = NULL }
 816 };
 817
 818 static struct clk omap_54m_fck = {
 819         .name           = "omap_54m_fck",
 820         .init           = &omap2_init_clksel_parent,
 821         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 822         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 823         .clksel         = omap_54m_clksel,
 824         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 825                                 PARENT_CONTROLS_CLOCK,
 826         .clkdm          = { .name = "cm_clkdm" },
 827         .recalc         = &omap2_clksel_recalc,
 828 };
 829
 830 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 831         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 832         { .div = 0 }
 833 };
 834
 835 static const struct clksel_rate omap_48m_alt_rates[] = {
 836         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 837         { .div = 0 }
 838 };
 839
 840 static const struct clksel omap_48m_clksel[] = {
 841         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 842         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 843         { .parent = NULL }
 844 };
 845
 846 static struct clk omap_48m_fck = {
 847         .name           = "omap_48m_fck",
 848         .init           = &omap2_init_clksel_parent,
 849         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 850         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 851         .clksel         = omap_48m_clksel,
 852         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 853                                 PARENT_CONTROLS_CLOCK,
 854         .clkdm          = { .name = "cm_clkdm" },
 855         .recalc         = &omap2_clksel_recalc,
 856 };
 857
 858 static struct clk omap_12m_fck = {
 859         .name           = "omap_12m_fck",
 860         .parent         = &omap_48m_fck,
 861         .fixed_div      = 4,
 862         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 863                                 PARENT_CONTROLS_CLOCK,
 864         .clkdm          = { .name = "cm_clkdm" },
 865         .recalc         = &omap2_fixed_divisor_recalc,
 866 };
 867
 868 /* This virstual clock is the source for dpll4_m4x2_ck */
 869 static struct clk dpll4_m4_ck = {
 870         .name           = "dpll4_m4_ck",
 871         .parent         = &dpll4_ck,
 872         .init           = &omap2_init_clksel_parent,
 873         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 874         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 875         .clksel         = div16_dpll4_clksel,
 876         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 877                                 PARENT_CONTROLS_CLOCK,
 878         .clkdm          = { .name = "dpll4_clkdm" },
 879         .recalc         = &omap2_clksel_recalc,
 880 };
 881
 882 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 883 static struct clk dpll4_m4x2_ck = {
 884         .name           = "dpll4_m4x2_ck",
 885         .parent         = &dpll4_m4_ck,
 886         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 887         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 888         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 889         .clkdm          = { .name = "dpll4_clkdm" },
 890         .recalc         = &omap3_clkoutx2_recalc,
 891 };
 892
 893 /* This virtual clock is the source for dpll4_m5x2_ck */
 894 static struct clk dpll4_m5_ck = {
 895         .name           = "dpll4_m5_ck",
 896         .parent         = &dpll4_ck,
 897         .init           = &omap2_init_clksel_parent,
 898         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 899         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 900         .clksel         = div16_dpll4_clksel,
 901         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 902                                 PARENT_CONTROLS_CLOCK,
 903         .clkdm          = { .name = "dpll4_clkdm" },
 904         .recalc         = &omap2_clksel_recalc,
 905 };
 906
 907 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 908 static struct clk dpll4_m5x2_ck = {
 909         .name           = "dpll4_m5x2_ck",
 910         .parent         = &dpll4_m5_ck,
 911         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 912         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 913         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 914         .clkdm          = { .name = "dpll4_clkdm" },
 915         .recalc         = &omap3_clkoutx2_recalc,
 916 };
 917
 918 /* This virtual clock is the source for dpll4_m6x2_ck */
 919 static struct clk dpll4_m6_ck = {
 920         .name           = "dpll4_m6_ck",
 921         .parent         = &dpll4_ck,
 922         .init           = &omap2_init_clksel_parent,
 923         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 924         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 925         .clksel         = div16_dpll4_clksel,
 926         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 927                                 PARENT_CONTROLS_CLOCK,
 928         .clkdm          = { .name = "dpll4_clkdm" },
 929         .recalc         = &omap2_clksel_recalc,
 930 };
 931
 932 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 933 static struct clk dpll4_m6x2_ck = {
 934         .name           = "dpll4_m6x2_ck",
 935         .parent         = &dpll4_m6_ck,
 936         .init           = &omap2_init_clksel_parent,
 937         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 938         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 939         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 940         .clkdm          = { .name = "dpll4_clkdm" },
 941         .recalc         = &omap3_clkoutx2_recalc,
 942 };
 943
 944 static struct clk emu_per_alwon_ck = {
 945         .name           = "emu_per_alwon_ck",
 946         .parent         = &dpll4_m6x2_ck,
 947         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 948                                 PARENT_CONTROLS_CLOCK,
 949         .clkdm          = { .name = "dpll4_clkdm" },
 950         .recalc         = &followparent_recalc,
 951 };
 952
 953 /* DPLL5 */
 954 /* Supplies 120MHz clock, USIM source clock */
 955 /* Type: DPLL */
 956 /* 3430ES2 only */
 957 static struct dpll_data dpll5_dd = {
 958         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 959         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 960         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 961         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 962         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 963         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 964         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 965         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 966         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 967         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 968         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 969         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 970         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 971         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 972         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 973         .max_divider    = OMAP3_MAX_DPLL_DIV,
 974         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 975 };
 976
 977 static struct clk dpll5_ck = {
 978         .name           = "dpll5_ck",
 979         .parent         = &sys_ck,
 980         .dpll_data      = &dpll5_dd,
 981         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 982         .enable         = &omap3_noncore_dpll_enable,
 983         .disable        = &omap3_noncore_dpll_disable,
 984         .round_rate     = &omap2_dpll_round_rate,
 985         .set_rate       = &omap3_noncore_dpll_set_rate,
 986         .clkdm          = { .name = "dpll5_clkdm" },
 987         .recalc         = &omap3_dpll_recalc,
 988 };
 989
 990 static const struct clksel div16_dpll5_clksel[] = {
 991         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 992         { .parent = NULL }
 993 };
 994
 995 static struct clk dpll5_m2_ck = {
 996         .name           = "dpll5_m2_ck",
 997         .parent         = &dpll5_ck,
 998         .init           = &omap2_init_clksel_parent,
 999         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1000         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
1001         .clksel         = div16_dpll5_clksel,
1002         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1003                                 PARENT_CONTROLS_CLOCK,
1004         .clkdm          = { .name = "dpll5_clkdm" },
1005         .recalc         = &omap2_clksel_recalc,
1006 };
1007
1008 static const struct clksel omap_120m_fck_clksel[] = {
1009         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
1010         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
1011         { .parent = NULL }
1012 };
1013
1014 static struct clk omap_120m_fck = {
1015         .name           = "omap_120m_fck",
1016         .parent         = &dpll5_m2_ck,
1017         .init           = &omap2_init_clksel_parent,
1018         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1019         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1020         .clksel         = omap_120m_fck_clksel,
1021         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
1022                                 PARENT_CONTROLS_CLOCK,
1023         .recalc         = &omap2_clksel_recalc,
1024 };
1025
1026 /* CM EXTERNAL CLOCK OUTPUTS */
1027
1028 static const struct clksel_rate clkout2_src_core_rates[] = {
1029         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1030         { .div = 0 }
1031 };
1032
1033 static const struct clksel_rate clkout2_src_sys_rates[] = {
1034         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1035         { .div = 0 }
1036 };
1037
1038 static const struct clksel_rate clkout2_src_96m_rates[] = {
1039         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1040         { .div = 0 }
1041 };
1042
1043 static const struct clksel_rate clkout2_src_54m_rates[] = {
1044         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1045         { .div = 0 }
1046 };
1047
1048 static const struct clksel clkout2_src_clksel[] = {
1049         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1050         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1051         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1052         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1053         { .parent = NULL }
1054 };
1055
1056 static struct clk clkout2_src_ck = {
1057         .name           = "clkout2_src_ck",
1058         .init           = &omap2_init_clksel_parent,
1059         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1060         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1061         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1062         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1063         .clksel         = clkout2_src_clksel,
1064         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1065         .clkdm          = { .name = "cm_clkdm" },
1066         .recalc         = &omap2_clksel_recalc,
1067 };
1068
1069 static const struct clksel_rate sys_clkout2_rates[] = {
1070         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1071         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1072         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1073         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1074         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1075         { .div = 0 },
1076 };
1077
1078 static const struct clksel sys_clkout2_clksel[] = {
1079         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1080         { .parent = NULL },
1081 };
1082
1083 static struct clk sys_clkout2 = {
1084         .name           = "sys_clkout2",
1085         .init           = &omap2_init_clksel_parent,
1086         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1087         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1088         .clksel         = sys_clkout2_clksel,
1089         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1090         .clkdm          = { .name = "cm_clkdm" },
1091         .recalc         = &omap2_clksel_recalc,
1092 };
1093
1094 /* CM OUTPUT CLOCKS */
1095
1096 static struct clk corex2_fck = {
1097         .name           = "corex2_fck",
1098         .parent         = &dpll3_m2x2_ck,
1099         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1100                                 PARENT_CONTROLS_CLOCK,
1101         .clkdm          = { .name = "cm_clkdm" },
1102         .recalc         = &followparent_recalc,
1103 };
1104
1105 /* DPLL power domain clock controls */
1106
1107 static const struct clksel_rate div4_rates[] = {
1108         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1109         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1110         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1111         { .div = 0 }
1112 };
1113
1114 static const struct clksel div4_core_clksel[] = {
1115         { .parent = &core_ck, .rates = div4_rates },
1116         { .parent = NULL }
1117 };
1118
1119 static struct clk dpll1_fck = {
1120         .name           = "dpll1_fck",
1121         .parent         = &core_ck,
1122         .init           = &omap2_init_clksel_parent,
1123         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1124         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1125         .clksel         = div4_core_clksel,
1126         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1127                                 PARENT_CONTROLS_CLOCK,
1128         .clkdm          = { .name = "cm_clkdm" },
1129         .recalc         = &omap2_clksel_recalc,
1130 };
1131
1132 /*
1133  * MPU clksel:
1134  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1135  * derives from the high-frequency bypass clock originating from DPLL3,
1136  * called 'dpll1_fck'
1137  */
1138 static const struct clksel mpu_clksel[] = {
1139         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1140         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1141         { .parent = NULL }
1142 };
1143
1144 static struct clk mpu_ck = {
1145         .name           = "mpu_ck",
1146         .parent         = &dpll1_x2m2_ck,
1147         .init           = &omap2_init_clksel_parent,
1148         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1149         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1150         .clksel         = mpu_clksel,
1151         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1152                                 PARENT_CONTROLS_CLOCK,
1153         .clkdm          = { .name = "mpu_clkdm" },
1154         .recalc         = &omap2_clksel_recalc,
1155 };
1156
1157 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1158 static const struct clksel_rate arm_fck_rates[] = {
1159         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1160         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1161         { .div = 0 },
1162 };
1163
1164 static const struct clksel arm_fck_clksel[] = {
1165         { .parent = &mpu_ck, .rates = arm_fck_rates },
1166         { .parent = NULL }
1167 };
1168
1169 static struct clk arm_fck = {
1170         .name           = "arm_fck",
1171         .parent         = &mpu_ck,
1172         .init           = &omap2_init_clksel_parent,
1173         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1174         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1175         .clksel         = arm_fck_clksel,
1176         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1177                                 PARENT_CONTROLS_CLOCK,
1178         .recalc         = &omap2_clksel_recalc,
1179 };
1180
1181 /* XXX What about neon_clkdm ? */
1182
1183 /*
1184  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1185  * although it is referenced - so this is a guess
1186  */
1187 static struct clk emu_mpu_alwon_ck = {
1188         .name           = "emu_mpu_alwon_ck",
1189         .parent         = &mpu_ck,
1190         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1191                                 PARENT_CONTROLS_CLOCK,
1192         .recalc         = &followparent_recalc,
1193 };
1194
1195 static struct clk dpll2_fck = {
1196         .name           = "dpll2_fck",
1197         .parent         = &core_ck,
1198         .init           = &omap2_init_clksel_parent,
1199         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1200         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1201         .clksel         = div4_core_clksel,
1202         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1203                                 PARENT_CONTROLS_CLOCK,
1204         .clkdm          = { .name = "cm_clkdm" },
1205         .recalc         = &omap2_clksel_recalc,
1206 };
1207
1208 /*
1209  * IVA2 clksel:
1210  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1211  * derives from the high-frequency bypass clock originating from DPLL3,
1212  * called 'dpll2_fck'
1213  */
1214
1215 static const struct clksel iva2_clksel[] = {
1216         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1217         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1218         { .parent = NULL }
1219 };
1220
1221 static struct clk iva2_ck = {
1222         .name           = "iva2_ck",
1223         .parent         = &dpll2_m2_ck,
1224         .init           = &omap2_init_clksel_parent,
1225         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1226         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1227         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1228                                           OMAP3430_CM_IDLEST_PLL),
1229         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1230         .clksel         = iva2_clksel,
1231         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1232         .clkdm          = { .name = "iva2_clkdm" },
1233         .recalc         = &omap2_clksel_recalc,
1234 };
1235
1236 /* Common interface clocks */
1237
1238 static const struct clksel div2_core_clksel[] = {
1239         { .parent = &core_ck, .rates = div2_rates },
1240         { .parent = NULL }
1241 };
1242
1243 static struct clk l3_ick = {
1244         .name           = "l3_ick",
1245         .parent         = &core_ck,
1246         .init           = &omap2_init_clksel_parent,
1247         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1248         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1249         .clksel         = div2_core_clksel,
1250         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1251                                 PARENT_CONTROLS_CLOCK,
1252         .clkdm          = { .name = "core_l3_clkdm" },
1253         .recalc         = &omap2_clksel_recalc,
1254 };
1255
1256 static const struct clksel div2_l3_clksel[] = {
1257         { .parent = &l3_ick, .rates = div2_rates },
1258         { .parent = NULL }
1259 };
1260
1261 static struct clk l4_ick = {
1262         .name           = "l4_ick",
1263         .parent         = &l3_ick,
1264         .init           = &omap2_init_clksel_parent,
1265         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1266         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1267         .clksel         = div2_l3_clksel,
1268         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1269                                 PARENT_CONTROLS_CLOCK,
1270         .clkdm          = { .name = "core_l4_clkdm" },
1271         .recalc         = &omap2_clksel_recalc,
1272
1273 };
1274
1275 static const struct clksel div2_l4_clksel[] = {
1276         { .parent = &l4_ick, .rates = div2_rates },
1277         { .parent = NULL }
1278 };
1279
1280 static struct clk rm_ick = {
1281         .name           = "rm_ick",
1282         .parent         = &l4_ick,
1283         .init           = &omap2_init_clksel_parent,
1284         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1285         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1286         .clksel         = div2_l4_clksel,
1287         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1288         .clkdm          = { .name = "cm_clkdm" },
1289         .recalc         = &omap2_clksel_recalc,
1290 };
1291
1292 /* GFX power domain */
1293
1294 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1295
1296 static const struct clksel gfx_l3_clksel[] = {
1297         { .parent = &l3_ick, .rates = gfx_l3_rates },
1298         { .parent = NULL }
1299 };
1300
1301 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1302 static struct clk gfx_l3_ck = {
1303         .name           = "gfx_l3_ck",
1304         .parent         = &l3_ick,
1305         .init           = &omap2_init_clksel_parent,
1306         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1307         .enable_bit     = OMAP_EN_GFX_SHIFT,
1308         .flags          = CLOCK_IN_OMAP3430ES1,
1309         .recalc         = &followparent_recalc,
1310 };
1311
1312 static struct clk gfx_l3_fck = {
1313         .name           = "gfx_l3_fck",
1314         .parent         = &gfx_l3_ck,
1315         .init           = &omap2_init_clksel_parent,
1316         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1317         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1318         .clksel         = gfx_l3_clksel,
1319         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1320                                 PARENT_CONTROLS_CLOCK,
1321         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1322         .recalc         = &omap2_clksel_recalc,
1323 };
1324
1325 static struct clk gfx_l3_ick = {
1326         .name           = "gfx_l3_ick",
1327         .parent         = &gfx_l3_ck,
1328         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1329         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1330         .recalc         = &followparent_recalc,
1331 };
1332
1333 static struct clk gfx_cg1_ck = {
1334         .name           = "gfx_cg1_ck",
1335         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1336         .init           = &omap2_init_clk_clkdm,
1337         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1338         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1339         .flags          = CLOCK_IN_OMAP3430ES1,
1340         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1341         .recalc         = &followparent_recalc,
1342 };
1343
1344 static struct clk gfx_cg2_ck = {
1345         .name           = "gfx_cg2_ck",
1346         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1347         .init           = &omap2_init_clk_clkdm,
1348         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1349         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1350         .flags          = CLOCK_IN_OMAP3430ES1,
1351         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1352         .recalc         = &followparent_recalc,
1353 };
1354
1355 /* SGX power domain - 3430ES2 only */
1356
1357 static const struct clksel_rate sgx_core_rates[] = {
1358         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1359         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1360         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1361         { .div = 0 },
1362 };
1363
1364 static const struct clksel_rate sgx_96m_rates[] = {
1365         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1366         { .div = 0 },
1367 };
1368
1369 static const struct clksel sgx_clksel[] = {
1370         { .parent = &core_ck,    .rates = sgx_core_rates },
1371         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1372         { .parent = NULL },
1373 };
1374
1375 static struct clk sgx_fck = {
1376         .name           = "sgx_fck",
1377         .init           = &omap2_init_clksel_parent,
1378         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1379         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1380         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1381         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1382         .clksel         = sgx_clksel,
1383         .flags          = CLOCK_IN_OMAP3430ES2,
1384         .clkdm          = { .name = "sgx_clkdm" },
1385         .recalc         = &omap2_clksel_recalc,
1386 };
1387
1388 static struct clk sgx_ick = {
1389         .name           = "sgx_ick",
1390         .parent         = &l3_ick,
1391         .init           = &omap2_init_clk_clkdm,
1392         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1393         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1394         .flags          = CLOCK_IN_OMAP3430ES2,
1395         .clkdm          = { .name = "sgx_clkdm" },
1396         .recalc         = &followparent_recalc,
1397 };
1398
1399 /* CORE power domain */
1400
1401 static struct clk d2d_26m_fck = {
1402         .name           = "d2d_26m_fck",
1403         .parent         = &sys_ck,
1404         .init           = &omap2_init_clk_clkdm,
1405         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1407         .flags          = CLOCK_IN_OMAP3430ES1,
1408         .clkdm          = { .name = "d2d_clkdm" },
1409         .recalc         = &followparent_recalc,
1410 };
1411
1412 static const struct clksel omap343x_gpt_clksel[] = {
1413         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1414         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1415         { .parent = NULL}
1416 };
1417
1418 static struct clk gpt10_fck = {
1419         .name           = "gpt10_fck",
1420         .parent         = &sys_ck,
1421         .init           = &omap2_init_clksel_parent,
1422         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1423         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1424         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1425         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1426         .clksel         = omap343x_gpt_clksel,
1427         .flags          = CLOCK_IN_OMAP343X,
1428         .clkdm          = { .name = "core_l4_clkdm" },
1429         .recalc         = &omap2_clksel_recalc,
1430 };
1431
1432 static struct clk gpt11_fck = {
1433         .name           = "gpt11_fck",
1434         .parent         = &sys_ck,
1435         .init           = &omap2_init_clksel_parent,
1436         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1438         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1439         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1440         .clksel         = omap343x_gpt_clksel,
1441         .flags          = CLOCK_IN_OMAP343X,
1442         .clkdm          = { .name = "core_l4_clkdm" },
1443         .recalc         = &omap2_clksel_recalc,
1444 };
1445
1446 static struct clk cpefuse_fck = {
1447         .name           = "cpefuse_fck",
1448         .parent         = &sys_ck,
1449         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1450         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1451         .flags          = CLOCK_IN_OMAP3430ES2,
1452         .clkdm          = { .name = "cm_clkdm" },
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 static struct clk ts_fck = {
1457         .name           = "ts_fck",
1458         .parent         = &omap_32k_fck,
1459         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1460         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1461         .flags          = CLOCK_IN_OMAP3430ES2,
1462         .recalc         = &followparent_recalc,
1463 };
1464
1465 static struct clk usbtll_fck = {
1466         .name           = "usbtll_fck",
1467         .parent         = &omap_120m_fck,
1468         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1469         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1470         .flags          = CLOCK_IN_OMAP3430ES2,
1471         .recalc         = &followparent_recalc,
1472 };
1473
1474 /* CORE 96M FCLK-derived clocks */
1475
1476 static struct clk core_96m_fck = {
1477         .name           = "core_96m_fck",
1478         .parent         = &omap_96m_fck,
1479         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1480                                 PARENT_CONTROLS_CLOCK,
1481         .clkdm          = { .name = "core_l4_clkdm" },
1482         .recalc         = &followparent_recalc,
1483 };
1484
1485 static struct clk mmchs3_fck = {
1486         .name           = "mmchs_fck",
1487         .id             = 3,
1488         .parent         = &core_96m_fck,
1489         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1490         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1491         .flags          = CLOCK_IN_OMAP3430ES2,
1492         .clkdm          = { .name = "core_l4_clkdm" },
1493         .recalc         = &followparent_recalc,
1494 };
1495
1496 static struct clk mmchs2_fck = {
1497         .name           = "mmchs_fck",
1498         .id             = 2,
1499         .parent         = &core_96m_fck,
1500         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1501         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1502         .flags          = CLOCK_IN_OMAP343X,
1503         .clkdm          = { .name = "core_l4_clkdm" },
1504         .recalc         = &followparent_recalc,
1505 };
1506
1507 static struct clk mspro_fck = {
1508         .name           = "mspro_fck",
1509         .parent         = &core_96m_fck,
1510         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1511         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1512         .flags          = CLOCK_IN_OMAP343X,
1513         .clkdm          = { .name = "core_l4_clkdm" },
1514         .recalc         = &followparent_recalc,
1515 };
1516
1517 static struct clk mmchs1_fck = {
1518         .name           = "mmchs_fck",
1519         .id             = 1,
1520         .parent         = &core_96m_fck,
1521         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1522         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1523         .flags          = CLOCK_IN_OMAP343X,
1524         .clkdm          = { .name = "core_l4_clkdm" },
1525         .recalc         = &followparent_recalc,
1526 };
1527
1528 static struct clk i2c3_fck = {
1529         .name           = "i2c_fck",
1530         .id             = 3,
1531         .parent         = &core_96m_fck,
1532         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1533         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1534         .flags          = CLOCK_IN_OMAP343X,
1535         .clkdm          = { .name = "core_l4_clkdm" },
1536         .recalc         = &followparent_recalc,
1537 };
1538
1539 static struct clk i2c2_fck = {
1540         .name           = "i2c_fck",
1541         .id             = 2,
1542         .parent         = &core_96m_fck,
1543         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1545         .flags          = CLOCK_IN_OMAP343X,
1546         .clkdm          = { .name = "core_l4_clkdm" },
1547         .recalc         = &followparent_recalc,
1548 };
1549
1550 static struct clk i2c1_fck = {
1551         .name           = "i2c_fck",
1552         .id             = 1,
1553         .parent         = &core_96m_fck,
1554         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1555         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1556         .flags          = CLOCK_IN_OMAP343X,
1557         .clkdm          = { .name = "core_l4_clkdm" },
1558         .recalc         = &followparent_recalc,
1559 };
1560
1561 /*
1562  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1563  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1564  */
1565 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1566         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1567         { .div = 0 }
1568 };
1569
1570 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1571         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1572         { .div = 0 }
1573 };
1574
1575 static const struct clksel mcbsp_15_clksel[] = {
1576         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1577         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1578         { .parent = NULL }
1579 };
1580
1581 static struct clk mcbsp5_fck = {
1582         .name           = "mcbsp_fck",
1583         .id             = 5,
1584         .init           = &omap2_init_clksel_parent,
1585         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1587         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1588         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1589         .clksel         = mcbsp_15_clksel,
1590         .flags          = CLOCK_IN_OMAP343X,
1591         .clkdm          = { .name = "core_l4_clkdm" },
1592         .recalc         = &omap2_clksel_recalc,
1593 };
1594
1595 static struct clk mcbsp1_fck = {
1596         .name           = "mcbsp_fck",
1597         .id             = 1,
1598         .init           = &omap2_init_clksel_parent,
1599         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1601         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1602         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1603         .clksel         = mcbsp_15_clksel,
1604         .flags          = CLOCK_IN_OMAP343X,
1605         .clkdm          = { .name = "core_l4_clkdm" },
1606         .recalc         = &omap2_clksel_recalc,
1607 };
1608
1609 /* CORE_48M_FCK-derived clocks */
1610
1611 static struct clk core_48m_fck = {
1612         .name           = "core_48m_fck",
1613         .parent         = &omap_48m_fck,
1614         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1615                                 PARENT_CONTROLS_CLOCK,
1616         .clkdm          = { .name = "core_l4_clkdm" },
1617         .recalc         = &followparent_recalc,
1618 };
1619
1620 static struct clk mcspi4_fck = {
1621         .name           = "mcspi_fck",
1622         .id             = 4,
1623         .parent         = &core_48m_fck,
1624         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1625         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1626         .flags          = CLOCK_IN_OMAP343X,
1627         .recalc         = &followparent_recalc,
1628 };
1629
1630 static struct clk mcspi3_fck = {
1631         .name           = "mcspi_fck",
1632         .id             = 3,
1633         .parent         = &core_48m_fck,
1634         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1635         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1636         .flags          = CLOCK_IN_OMAP343X,
1637         .recalc         = &followparent_recalc,
1638 };
1639
1640 static struct clk mcspi2_fck = {
1641         .name           = "mcspi_fck",
1642         .id             = 2,
1643         .parent         = &core_48m_fck,
1644         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1645         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1646         .flags          = CLOCK_IN_OMAP343X,
1647         .recalc         = &followparent_recalc,
1648 };
1649
1650 static struct clk mcspi1_fck = {
1651         .name           = "mcspi_fck",
1652         .id             = 1,
1653         .parent         = &core_48m_fck,
1654         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1655         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1656         .flags          = CLOCK_IN_OMAP343X,
1657         .recalc         = &followparent_recalc,
1658 };
1659
1660 static struct clk uart2_fck = {
1661         .name           = "uart2_fck",
1662         .parent         = &core_48m_fck,
1663         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1664         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1665         .flags          = CLOCK_IN_OMAP343X,
1666         .recalc         = &followparent_recalc,
1667 };
1668
1669 static struct clk uart1_fck = {
1670         .name           = "uart1_fck",
1671         .parent         = &core_48m_fck,
1672         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1673         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1674         .flags          = CLOCK_IN_OMAP343X,
1675         .recalc         = &followparent_recalc,
1676 };
1677
1678 static struct clk fshostusb_fck = {
1679         .name           = "fshostusb_fck",
1680         .parent         = &core_48m_fck,
1681         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1682         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1683         .flags          = CLOCK_IN_OMAP3430ES1,
1684         .recalc         = &followparent_recalc,
1685 };
1686
1687 /* CORE_12M_FCK based clocks */
1688
1689 static struct clk core_12m_fck = {
1690         .name           = "core_12m_fck",
1691         .parent         = &omap_12m_fck,
1692         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1693                                 PARENT_CONTROLS_CLOCK,
1694         .clkdm          = { .name = "core_l4_clkdm" },
1695         .recalc         = &followparent_recalc,
1696 };
1697
1698 static struct clk hdq_fck = {
1699         .name           = "hdq_fck",
1700         .parent         = &core_12m_fck,
1701         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1702         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1703         .flags          = CLOCK_IN_OMAP343X,
1704         .recalc         = &followparent_recalc,
1705 };
1706
1707 /* DPLL3-derived clock */
1708
1709 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1710         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1711         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1712         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1713         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1714         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1715         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1716         { .div = 0 }
1717 };
1718
1719 static const struct clksel ssi_ssr_clksel[] = {
1720         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1721         { .parent = NULL }
1722 };
1723
1724 static struct clk ssi_ssr_fck = {
1725         .name           = "ssi_ssr_fck",
1726         .init           = &omap2_init_clksel_parent,
1727         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1728         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1729         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1730         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1731         .clksel         = ssi_ssr_clksel,
1732         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1733         .clkdm          = { .name = "core_l4_clkdm" },
1734         .recalc         = &omap2_clksel_recalc,
1735 };
1736
1737 static struct clk ssi_sst_fck = {
1738         .name           = "ssi_sst_fck",
1739         .parent         = &ssi_ssr_fck,
1740         .fixed_div      = 2,
1741         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1742         .recalc         = &omap2_fixed_divisor_recalc,
1743 };
1744
1745
1746
1747 /* CORE_L3_ICK based clocks */
1748
1749 /*
1750  * XXX must add clk_enable/clk_disable for these if standard code won't
1751  * handle it
1752  */
1753 static struct clk core_l3_ick = {
1754         .name           = "core_l3_ick",
1755         .parent         = &l3_ick,
1756         .init           = &omap2_init_clk_clkdm,
1757         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1758                                 PARENT_CONTROLS_CLOCK,
1759         .clkdm          = { .name = "core_l3_clkdm" },
1760         .recalc         = &followparent_recalc,
1761 };
1762
1763 static struct clk hsotgusb_ick = {
1764         .name           = "hsotgusb_ick",
1765         .parent         = &core_l3_ick,
1766         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1767         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1768         .flags          = CLOCK_IN_OMAP343X,
1769         .clkdm          = { .name = "core_l3_clkdm" },
1770         .recalc         = &followparent_recalc,
1771 };
1772
1773 static struct clk sdrc_ick = {
1774         .name           = "sdrc_ick",
1775         .parent         = &core_l3_ick,
1776         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1778         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1779         .clkdm          = { .name = "core_l3_clkdm" },
1780         .recalc         = &followparent_recalc,
1781 };
1782
1783 static struct clk gpmc_fck = {
1784         .name           = "gpmc_fck",
1785         .parent         = &core_l3_ick,
1786         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1787                                 ENABLE_ON_INIT,
1788         .clkdm          = { .name = "core_l3_clkdm" },
1789         .recalc         = &followparent_recalc,
1790 };
1791
1792 /* SECURITY_L3_ICK based clocks */
1793
1794 static struct clk security_l3_ick = {
1795         .name           = "security_l3_ick",
1796         .parent         = &l3_ick,
1797         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1798                                 PARENT_CONTROLS_CLOCK,
1799         .recalc         = &followparent_recalc,
1800 };
1801
1802 static struct clk pka_ick = {
1803         .name           = "pka_ick",
1804         .parent         = &security_l3_ick,
1805         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1806         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1807         .flags          = CLOCK_IN_OMAP343X,
1808         .recalc         = &followparent_recalc,
1809 };
1810
1811 /* CORE_L4_ICK based clocks */
1812
1813 static struct clk core_l4_ick = {
1814         .name           = "core_l4_ick",
1815         .parent         = &l4_ick,
1816         .init           = &omap2_init_clk_clkdm,
1817         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1818                                 PARENT_CONTROLS_CLOCK,
1819         .clkdm          = { .name = "core_l4_clkdm" },
1820         .recalc         = &followparent_recalc,
1821 };
1822
1823 static struct clk usbtll_ick = {
1824         .name           = "usbtll_ick",
1825         .parent         = &core_l4_ick,
1826         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1827         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1828         .flags          = CLOCK_IN_OMAP3430ES2,
1829         .clkdm          = { .name = "core_l4_clkdm" },
1830         .recalc         = &followparent_recalc,
1831 };
1832
1833 static struct clk mmchs3_ick = {
1834         .name           = "mmchs_ick",
1835         .id             = 3,
1836         .parent         = &core_l4_ick,
1837         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1838         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1839         .flags          = CLOCK_IN_OMAP3430ES2,
1840         .clkdm          = { .name = "core_l4_clkdm" },
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 /* Intersystem Communication Registers - chassis mode only */
1845 static struct clk icr_ick = {
1846         .name           = "icr_ick",
1847         .parent         = &core_l4_ick,
1848         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1849         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1850         .flags          = CLOCK_IN_OMAP343X,
1851         .clkdm          = { .name = "core_l4_clkdm" },
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk aes2_ick = {
1856         .name           = "aes2_ick",
1857         .parent         = &core_l4_ick,
1858         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1859         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1860         .flags          = CLOCK_IN_OMAP343X,
1861         .clkdm          = { .name = "core_l4_clkdm" },
1862         .recalc         = &followparent_recalc,
1863 };
1864
1865 static struct clk sha12_ick = {
1866         .name           = "sha12_ick",
1867         .parent         = &core_l4_ick,
1868         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1869         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1870         .flags          = CLOCK_IN_OMAP343X,
1871         .clkdm          = { .name = "core_l4_clkdm" },
1872         .recalc         = &followparent_recalc,
1873 };
1874
1875 static struct clk des2_ick = {
1876         .name           = "des2_ick",
1877         .parent         = &core_l4_ick,
1878         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1879         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1880         .flags          = CLOCK_IN_OMAP343X,
1881         .clkdm          = { .name = "core_l4_clkdm" },
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk mmchs2_ick = {
1886         .name           = "mmchs_ick",
1887         .id             = 2,
1888         .parent         = &core_l4_ick,
1889         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1891         .flags          = CLOCK_IN_OMAP343X,
1892         .clkdm          = { .name = "core_l4_clkdm" },
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mmchs1_ick = {
1897         .name           = "mmchs_ick",
1898         .id             = 1,
1899         .parent         = &core_l4_ick,
1900         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1902         .flags          = CLOCK_IN_OMAP343X,
1903         .clkdm          = { .name = "core_l4_clkdm" },
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mspro_ick = {
1908         .name           = "mspro_ick",
1909         .parent         = &core_l4_ick,
1910         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1911         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1912         .flags          = CLOCK_IN_OMAP343X,
1913         .clkdm          = { .name = "core_l4_clkdm" },
1914         .recalc         = &followparent_recalc,
1915 };
1916
1917 static struct clk hdq_ick = {
1918         .name           = "hdq_ick",
1919         .parent         = &core_l4_ick,
1920         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1922         .flags          = CLOCK_IN_OMAP343X,
1923         .clkdm          = { .name = "core_l4_clkdm" },
1924         .recalc         = &followparent_recalc,
1925 };
1926
1927 static struct clk mcspi4_ick = {
1928         .name           = "mcspi_ick",
1929         .id             = 4,
1930         .parent         = &core_l4_ick,
1931         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1932         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1933         .flags          = CLOCK_IN_OMAP343X,
1934         .clkdm          = { .name = "core_l4_clkdm" },
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk mcspi3_ick = {
1939         .name           = "mcspi_ick",
1940         .id             = 3,
1941         .parent         = &core_l4_ick,
1942         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1944         .flags          = CLOCK_IN_OMAP343X,
1945         .clkdm          = { .name = "core_l4_clkdm" },
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk mcspi2_ick = {
1950         .name           = "mcspi_ick",
1951         .id             = 2,
1952         .parent         = &core_l4_ick,
1953         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1954         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1955         .flags          = CLOCK_IN_OMAP343X,
1956         .clkdm          = { .name = "core_l4_clkdm" },
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk mcspi1_ick = {
1961         .name           = "mcspi_ick",
1962         .id             = 1,
1963         .parent         = &core_l4_ick,
1964         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1966         .flags          = CLOCK_IN_OMAP343X,
1967         .clkdm          = { .name = "core_l4_clkdm" },
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk i2c3_ick = {
1972         .name           = "i2c_ick",
1973         .id             = 3,
1974         .parent         = &core_l4_ick,
1975         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1976         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1977         .flags          = CLOCK_IN_OMAP343X,
1978         .clkdm          = { .name = "core_l4_clkdm" },
1979         .recalc         = &followparent_recalc,
1980 };
1981
1982 static struct clk i2c2_ick = {
1983         .name           = "i2c_ick",
1984         .id             = 2,
1985         .parent         = &core_l4_ick,
1986         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1988         .flags          = CLOCK_IN_OMAP343X,
1989         .clkdm          = { .name = "core_l4_clkdm" },
1990         .recalc         = &followparent_recalc,
1991 };
1992
1993 static struct clk i2c1_ick = {
1994         .name           = "i2c_ick",
1995         .id             = 1,
1996         .parent         = &core_l4_ick,
1997         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1999         .flags          = CLOCK_IN_OMAP343X,
2000         .clkdm          = { .name = "core_l4_clkdm" },
2001         .recalc         = &followparent_recalc,
2002 };
2003
2004 static struct clk uart2_ick = {
2005         .name           = "uart2_ick",
2006         .parent         = &core_l4_ick,
2007         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2008         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2009         .flags          = CLOCK_IN_OMAP343X,
2010         .clkdm          = { .name = "core_l4_clkdm" },
2011         .recalc         = &followparent_recalc,
2012 };
2013
2014 static struct clk uart1_ick = {
2015         .name           = "uart1_ick",
2016         .parent         = &core_l4_ick,
2017         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2018         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2019         .flags          = CLOCK_IN_OMAP343X,
2020         .clkdm          = { .name = "core_l4_clkdm" },
2021         .recalc         = &followparent_recalc,
2022 };
2023
2024 static struct clk gpt11_ick = {
2025         .name           = "gpt11_ick",
2026         .parent         = &core_l4_ick,
2027         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2028         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2029         .flags          = CLOCK_IN_OMAP343X,
2030         .clkdm          = { .name = "core_l4_clkdm" },
2031         .recalc         = &followparent_recalc,
2032 };
2033
2034 static struct clk gpt10_ick = {
2035         .name           = "gpt10_ick",
2036         .parent         = &core_l4_ick,
2037         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2038         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2039         .flags          = CLOCK_IN_OMAP343X,
2040         .clkdm          = { .name = "core_l4_clkdm" },
2041         .recalc         = &followparent_recalc,
2042 };
2043
2044 static struct clk mcbsp5_ick = {
2045         .name           = "mcbsp_ick",
2046         .id             = 5,
2047         .parent         = &core_l4_ick,
2048         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2050         .flags          = CLOCK_IN_OMAP343X,
2051         .clkdm          = { .name = "core_l4_clkdm" },
2052         .recalc         = &followparent_recalc,
2053 };
2054
2055 static struct clk mcbsp1_ick = {
2056         .name           = "mcbsp_ick",
2057         .id             = 1,
2058         .parent         = &core_l4_ick,
2059         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2060         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2061         .flags          = CLOCK_IN_OMAP343X,
2062         .clkdm          = { .name = "core_l4_clkdm" },
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk fac_ick = {
2067         .name           = "fac_ick",
2068         .parent         = &core_l4_ick,
2069         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2070         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2071         .flags          = CLOCK_IN_OMAP3430ES1,
2072         .clkdm          = { .name = "core_l4_clkdm" },
2073         .recalc         = &followparent_recalc,
2074 };
2075
2076 static struct clk mailboxes_ick = {
2077         .name           = "mailboxes_ick",
2078         .parent         = &core_l4_ick,
2079         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2080         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2081         .flags          = CLOCK_IN_OMAP343X,
2082         .clkdm          = { .name = "core_l4_clkdm" },
2083         .recalc         = &followparent_recalc,
2084 };
2085
2086 static struct clk omapctrl_ick = {
2087         .name           = "omapctrl_ick",
2088         .parent         = &core_l4_ick,
2089         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2090         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2091         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2092         .recalc         = &followparent_recalc,
2093 };
2094
2095 /* SSI_L4_ICK based clocks */
2096
2097 static struct clk ssi_l4_ick = {
2098         .name           = "ssi_l4_ick",
2099         .parent         = &l4_ick,
2100         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2101                                 PARENT_CONTROLS_CLOCK,
2102         .clkdm          = { .name = "core_l4_clkdm" },
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk ssi_ick = {
2107         .name           = "ssi_ick",
2108         .parent         = &ssi_l4_ick,
2109         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2110         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2111         .flags          = CLOCK_IN_OMAP343X,
2112         .clkdm          = { .name = "core_l4_clkdm" },
2113         .recalc         = &followparent_recalc,
2114 };
2115
2116 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2117  * but l4_ick makes more sense to me */
2118
2119 static const struct clksel usb_l4_clksel[] = {
2120         { .parent = &l4_ick, .rates = div2_rates },
2121         { .parent = NULL },
2122 };
2123
2124 static struct clk usb_l4_ick = {
2125         .name           = "usb_l4_ick",
2126         .parent         = &l4_ick,
2127         .init           = &omap2_init_clksel_parent,
2128         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2129         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2130         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2131         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2132         .clksel         = usb_l4_clksel,
2133         .flags          = CLOCK_IN_OMAP3430ES1,
2134         .recalc         = &omap2_clksel_recalc,
2135 };
2136
2137 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2138
2139 /* SECURITY_L4_ICK2 based clocks */
2140
2141 static struct clk security_l4_ick2 = {
2142         .name           = "security_l4_ick2",
2143         .parent         = &l4_ick,
2144         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2145                                 PARENT_CONTROLS_CLOCK,
2146         .recalc         = &followparent_recalc,
2147 };
2148
2149 static struct clk aes1_ick = {
2150         .name           = "aes1_ick",
2151         .parent         = &security_l4_ick2,
2152         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2153         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2154         .flags          = CLOCK_IN_OMAP343X,
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 static struct clk rng_ick = {
2159         .name           = "rng_ick",
2160         .parent         = &security_l4_ick2,
2161         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2162         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2163         .flags          = CLOCK_IN_OMAP343X,
2164         .recalc         = &followparent_recalc,
2165 };
2166
2167 static struct clk sha11_ick = {
2168         .name           = "sha11_ick",
2169         .parent         = &security_l4_ick2,
2170         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2171         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2172         .flags          = CLOCK_IN_OMAP343X,
2173         .recalc         = &followparent_recalc,
2174 };
2175
2176 static struct clk des1_ick = {
2177         .name           = "des1_ick",
2178         .parent         = &security_l4_ick2,
2179         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2180         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2181         .flags          = CLOCK_IN_OMAP343X,
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 /* DSS */
2186 static const struct clksel dss1_alwon_fck_clksel[] = {
2187         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2188         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2189         { .parent = NULL }
2190 };
2191
2192 static struct clk dss1_alwon_fck = {
2193         .name           = "dss1_alwon_fck",
2194         .parent         = &dpll4_m4x2_ck,
2195         .init           = &omap2_init_clksel_parent,
2196         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2197         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2198         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2199         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2200         .clksel         = dss1_alwon_fck_clksel,
2201         .flags          = CLOCK_IN_OMAP343X,
2202         .clkdm          = { .name = "dss_clkdm" },
2203         .recalc         = &omap2_clksel_recalc,
2204 };
2205
2206 static struct clk dss_tv_fck = {
2207         .name           = "dss_tv_fck",
2208         .parent         = &omap_54m_fck,
2209         .init           = &omap2_init_clk_clkdm,
2210         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2211         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2212         .flags          = CLOCK_IN_OMAP343X,
2213         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2214         .recalc         = &followparent_recalc,
2215 };
2216
2217 static struct clk dss_96m_fck = {
2218         .name           = "dss_96m_fck",
2219         .parent         = &omap_96m_fck,
2220         .init           = &omap2_init_clk_clkdm,
2221         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2222         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2223         .flags          = CLOCK_IN_OMAP343X,
2224         .clkdm          = { .name = "dss_clkdm" },
2225         .recalc         = &followparent_recalc,
2226 };
2227
2228 static struct clk dss2_alwon_fck = {
2229         .name           = "dss2_alwon_fck",
2230         .parent         = &sys_ck,
2231         .init           = &omap2_init_clk_clkdm,
2232         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2233         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2234         .flags          = CLOCK_IN_OMAP343X,
2235         .clkdm          = { .name = "dss_clkdm" },
2236         .recalc         = &followparent_recalc,
2237 };
2238
2239 static struct clk dss_ick = {
2240         /* Handles both L3 and L4 clocks */
2241         .name           = "dss_ick",
2242         .parent         = &l4_ick,
2243         .init           = &omap2_init_clk_clkdm,
2244         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2245         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2246         .flags          = CLOCK_IN_OMAP343X,
2247         .clkdm          = { .name = "dss_clkdm" },
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 /* CAM */
2252
2253 static const struct clksel cam_mclk_clksel[] = {
2254         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2255         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2256         { .parent = NULL }
2257 };
2258
2259 static struct clk cam_mclk = {
2260         .name           = "cam_mclk",
2261         .parent         = &dpll4_m5x2_ck,
2262         .init           = &omap2_init_clksel_parent,
2263         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2264         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2265         .clksel         = cam_mclk_clksel,
2266         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2267         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2268         .flags          = CLOCK_IN_OMAP343X,
2269         .clkdm          = { .name = "cam_clkdm" },
2270         .recalc         = &omap2_clksel_recalc,
2271 };
2272
2273 static struct clk cam_ick = {
2274         /* Handles both L3 and L4 clocks */
2275         .name           = "cam_ick",
2276         .parent         = &l4_ick,
2277         .init           = &omap2_init_clk_clkdm,
2278         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2279         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2280         .flags          = CLOCK_IN_OMAP343X,
2281         .clkdm          = { .name = "cam_clkdm" },
2282         .recalc         = &followparent_recalc,
2283 };
2284
2285 static struct clk csi2_96m_fck = {
2286         .name           = "csi2_96m_fck",
2287         .parent         = &core_96m_fck,
2288         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2289         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2290         .flags          = CLOCK_IN_OMAP343X,
2291         .clkdm          = { .name = "cam_clkdm" },
2292         .recalc         = &followparent_recalc,
2293 };
2294
2295 /* USBHOST - 3430ES2 only */
2296
2297 static struct clk usbhost_120m_fck = {
2298         .name           = "usbhost_120m_fck",
2299         .parent         = &omap_120m_fck,
2300         .init           = &omap2_init_clk_clkdm,
2301         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2302         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2303         .flags          = CLOCK_IN_OMAP3430ES2,
2304         .clkdm          = { .name = "usbhost_clkdm" },
2305         .recalc         = &followparent_recalc,
2306 };
2307
2308 static struct clk usbhost_48m_fck = {
2309         .name           = "usbhost_48m_fck",
2310         .parent         = &omap_48m_fck,
2311         .init           = &omap2_init_clk_clkdm,
2312         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2313         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2314         .flags          = CLOCK_IN_OMAP3430ES2,
2315         .clkdm          = { .name = "usbhost_clkdm" },
2316         .recalc         = &followparent_recalc,
2317 };
2318
2319 static struct clk usbhost_ick = {
2320         /* Handles both L3 and L4 clocks */
2321         .name           = "usbhost_ick",
2322         .parent         = &l4_ick,
2323         .init           = &omap2_init_clk_clkdm,
2324         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2325         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2326         .flags          = CLOCK_IN_OMAP3430ES2,
2327         .clkdm          = { .name = "usbhost_clkdm" },
2328         .recalc         = &followparent_recalc,
2329 };
2330
2331 /* WKUP */
2332
2333 static const struct clksel_rate usim_96m_rates[] = {
2334         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2335         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2336         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2337         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2338         { .div = 0 },
2339 };
2340
2341 static const struct clksel_rate usim_120m_rates[] = {
2342         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2343         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2344         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2345         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2346         { .div = 0 },
2347 };
2348
2349 static const struct clksel usim_clksel[] = {
2350         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2351         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2352         { .parent = &sys_ck,            .rates = div2_rates },
2353         { .parent = NULL },
2354 };
2355
2356 /* 3430ES2 only */
2357 static struct clk usim_fck = {
2358         .name           = "usim_fck",
2359         .init           = &omap2_init_clksel_parent,
2360         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2361         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2362         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2363         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2364         .clksel         = usim_clksel,
2365         .flags          = CLOCK_IN_OMAP3430ES2,
2366         .clkdm          = { .name = "prm_clkdm" },
2367         .recalc         = &omap2_clksel_recalc,
2368 };
2369
2370 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2371 static struct clk gpt1_fck = {
2372         .name           = "gpt1_fck",
2373         .init           = &omap2_init_clksel_parent,
2374         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2375         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2376         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2377         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2378         .clksel         = omap343x_gpt_clksel,
2379         .flags          = CLOCK_IN_OMAP343X,
2380         .clkdm          = { .name = "prm_clkdm" },
2381         .recalc         = &omap2_clksel_recalc,
2382 };
2383
2384 static struct clk wkup_32k_fck = {
2385         .name           = "wkup_32k_fck",
2386         .init           = &omap2_init_clk_clkdm,
2387         .parent         = &omap_32k_fck,
2388         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2389         .clkdm          = { .name = "prm_clkdm" },
2390         .recalc         = &followparent_recalc,
2391 };
2392
2393 static struct clk gpio1_fck = {
2394         .name           = "gpio1_fck",
2395         .parent         = &wkup_32k_fck,
2396         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2397         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2398         .flags          = CLOCK_IN_OMAP343X,
2399         .clkdm          = { .name = "prm_clkdm" },
2400         .recalc         = &followparent_recalc,
2401 };
2402
2403 static struct clk wdt2_fck = {
2404         .name           = "wdt2_fck",
2405         .parent         = &wkup_32k_fck,
2406         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2407         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2408         .flags          = CLOCK_IN_OMAP343X,
2409         .clkdm          = { .name = "prm_clkdm" },
2410         .recalc         = &followparent_recalc,
2411 };
2412
2413 static struct clk wkup_l4_ick = {
2414         .name           = "wkup_l4_ick",
2415         .parent         = &sys_ck,
2416         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2417         .clkdm          = { .name = "prm_clkdm" },
2418         .recalc         = &followparent_recalc,
2419 };
2420
2421 /* 3430ES2 only */
2422 /* Never specifically named in the TRM, so we have to infer a likely name */
2423 static struct clk usim_ick = {
2424         .name           = "usim_ick",
2425         .parent         = &wkup_l4_ick,
2426         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2427         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2428         .flags          = CLOCK_IN_OMAP3430ES2,
2429         .clkdm          = { .name = "prm_clkdm" },
2430         .recalc         = &followparent_recalc,
2431 };
2432
2433 static struct clk wdt2_ick = {
2434         .name           = "wdt2_ick",
2435         .parent         = &wkup_l4_ick,
2436         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2437         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2438         .flags          = CLOCK_IN_OMAP343X,
2439         .clkdm          = { .name = "prm_clkdm" },
2440         .recalc         = &followparent_recalc,
2441 };
2442
2443 static struct clk wdt1_ick = {
2444         .name           = "wdt1_ick",
2445         .parent         = &wkup_l4_ick,
2446         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2447         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2448         .flags          = CLOCK_IN_OMAP343X,
2449         .clkdm          = { .name = "prm_clkdm" },
2450         .recalc         = &followparent_recalc,
2451 };
2452
2453 static struct clk gpio1_ick = {
2454         .name           = "gpio1_ick",
2455         .parent         = &wkup_l4_ick,
2456         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2457         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2458         .flags          = CLOCK_IN_OMAP343X,
2459         .clkdm          = { .name = "prm_clkdm" },
2460         .recalc         = &followparent_recalc,
2461 };
2462
2463 static struct clk omap_32ksync_ick = {
2464         .name           = "omap_32ksync_ick",
2465         .parent         = &wkup_l4_ick,
2466         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2467         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2468         .flags          = CLOCK_IN_OMAP343X,
2469         .clkdm          = { .name = "prm_clkdm" },
2470         .recalc         = &followparent_recalc,
2471 };
2472
2473 static struct clk gpt12_ick = {
2474         .name           = "gpt12_ick",
2475         .parent         = &wkup_l4_ick,
2476         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2477         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2478         .flags          = CLOCK_IN_OMAP343X,
2479         .clkdm          = { .name = "prm_clkdm" },
2480         .recalc         = &followparent_recalc,
2481 };
2482
2483 static struct clk gpt1_ick = {
2484         .name           = "gpt1_ick",
2485         .parent         = &wkup_l4_ick,
2486         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2487         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2488         .flags          = CLOCK_IN_OMAP343X,
2489         .clkdm          = { .name = "prm_clkdm" },
2490         .recalc         = &followparent_recalc,
2491 };
2492
2493
2494
2495 /* PER clock domain */
2496
2497 static struct clk per_96m_fck = {
2498         .name           = "per_96m_fck",
2499         .parent         = &omap_96m_alwon_fck,
2500         .init           = &omap2_init_clk_clkdm,
2501         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2502                                 PARENT_CONTROLS_CLOCK,
2503         .clkdm          = { .name = "per_clkdm" },
2504         .recalc         = &followparent_recalc,
2505 };
2506
2507 static struct clk per_48m_fck = {
2508         .name           = "per_48m_fck",
2509         .parent         = &omap_48m_fck,
2510         .init           = &omap2_init_clk_clkdm,
2511         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2512                                 PARENT_CONTROLS_CLOCK,
2513         .clkdm          = { .name = "per_clkdm" },
2514         .recalc         = &followparent_recalc,
2515 };
2516
2517 static struct clk uart3_fck = {
2518         .name           = "uart3_fck",
2519         .parent         = &per_48m_fck,
2520         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2521         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2522         .flags          = CLOCK_IN_OMAP343X,
2523         .clkdm          = { .name = "per_clkdm" },
2524         .recalc         = &followparent_recalc,
2525 };
2526
2527 static struct clk gpt2_fck = {
2528         .name           = "gpt2_fck",
2529         .init           = &omap2_init_clksel_parent,
2530         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2531         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2532         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2533         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2534         .clksel         = omap343x_gpt_clksel,
2535         .flags          = CLOCK_IN_OMAP343X,
2536         .clkdm          = { .name = "per_clkdm" },
2537         .recalc         = &omap2_clksel_recalc,
2538 };
2539
2540 static struct clk gpt3_fck = {
2541         .name           = "gpt3_fck",
2542         .init           = &omap2_init_clksel_parent,
2543         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2544         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2545         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2546         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2547         .clksel         = omap343x_gpt_clksel,
2548         .flags          = CLOCK_IN_OMAP343X,
2549         .clkdm          = { .name = "per_clkdm" },
2550         .recalc         = &omap2_clksel_recalc,
2551 };
2552
2553 static struct clk gpt4_fck = {
2554         .name           = "gpt4_fck",
2555         .init           = &omap2_init_clksel_parent,
2556         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2557         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2558         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2559         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2560         .clksel         = omap343x_gpt_clksel,
2561         .flags          = CLOCK_IN_OMAP343X,
2562         .clkdm          = { .name = "per_clkdm" },
2563         .recalc         = &omap2_clksel_recalc,
2564 };
2565
2566 static struct clk gpt5_fck = {
2567         .name           = "gpt5_fck",
2568         .init           = &omap2_init_clksel_parent,
2569         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2570         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2571         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2572         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2573         .clksel         = omap343x_gpt_clksel,
2574         .flags          = CLOCK_IN_OMAP343X,
2575         .clkdm          = { .name = "per_clkdm" },
2576         .recalc         = &omap2_clksel_recalc,
2577 };
2578
2579 static struct clk gpt6_fck = {
2580         .name           = "gpt6_fck",
2581         .init           = &omap2_init_clksel_parent,
2582         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2583         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2584         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2585         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2586         .clksel         = omap343x_gpt_clksel,
2587         .flags          = CLOCK_IN_OMAP343X,
2588         .clkdm          = { .name = "per_clkdm" },
2589         .recalc         = &omap2_clksel_recalc,
2590 };
2591
2592 static struct clk gpt7_fck = {
2593         .name           = "gpt7_fck",
2594         .init           = &omap2_init_clksel_parent,
2595         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2596         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2597         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2598         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2599         .clksel         = omap343x_gpt_clksel,
2600         .flags          = CLOCK_IN_OMAP343X,
2601         .clkdm          = { .name = "per_clkdm" },
2602         .recalc         = &omap2_clksel_recalc,
2603 };
2604
2605 static struct clk gpt8_fck = {
2606         .name           = "gpt8_fck",
2607         .init           = &omap2_init_clksel_parent,
2608         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2609         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2610         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2611         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2612         .clksel         = omap343x_gpt_clksel,
2613         .flags          = CLOCK_IN_OMAP343X,
2614         .clkdm          = { .name = "per_clkdm" },
2615         .recalc         = &omap2_clksel_recalc,
2616 };
2617
2618 static struct clk gpt9_fck = {
2619         .name           = "gpt9_fck",
2620         .init           = &omap2_init_clksel_parent,
2621         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2622         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2623         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2624         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2625         .clksel         = omap343x_gpt_clksel,
2626         .flags          = CLOCK_IN_OMAP343X,
2627         .clkdm          = { .name = "per_clkdm" },
2628         .recalc         = &omap2_clksel_recalc,
2629 };
2630
2631 static struct clk per_32k_alwon_fck = {
2632         .name           = "per_32k_alwon_fck",
2633         .parent         = &omap_32k_fck,
2634         .clkdm          = { .name = "per_clkdm" },
2635         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2636         .recalc         = &followparent_recalc,
2637 };
2638
2639 static struct clk gpio6_fck = {
2640         .name           = "gpio6_fck",
2641         .parent         = &per_32k_alwon_fck,
2642         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2643         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2644         .flags          = CLOCK_IN_OMAP343X,
2645         .clkdm          = { .name = "per_clkdm" },
2646         .recalc         = &followparent_recalc,
2647 };
2648
2649 static struct clk gpio5_fck = {
2650         .name           = "gpio5_fck",
2651         .parent         = &per_32k_alwon_fck,
2652         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2653         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2654         .flags          = CLOCK_IN_OMAP343X,
2655         .clkdm          = { .name = "per_clkdm" },
2656         .recalc         = &followparent_recalc,
2657 };
2658
2659 static struct clk gpio4_fck = {
2660         .name           = "gpio4_fck",
2661         .parent         = &per_32k_alwon_fck,
2662         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2663         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2664         .flags          = CLOCK_IN_OMAP343X,
2665         .clkdm          = { .name = "per_clkdm" },
2666         .recalc         = &followparent_recalc,
2667 };
2668
2669 static struct clk gpio3_fck = {
2670         .name           = "gpio3_fck",
2671         .parent         = &per_32k_alwon_fck,
2672         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2673         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2674         .flags          = CLOCK_IN_OMAP343X,
2675         .clkdm          = { .name = "per_clkdm" },
2676         .recalc         = &followparent_recalc,
2677 };
2678
2679 static struct clk gpio2_fck = {
2680         .name           = "gpio2_fck",
2681         .parent         = &per_32k_alwon_fck,
2682         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2683         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2684         .flags          = CLOCK_IN_OMAP343X,
2685         .clkdm          = { .name = "per_clkdm" },
2686         .recalc         = &followparent_recalc,
2687 };
2688
2689 static struct clk wdt3_fck = {
2690         .name           = "wdt3_fck",
2691         .parent         = &per_32k_alwon_fck,
2692         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2693         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2694         .flags          = CLOCK_IN_OMAP343X,
2695         .clkdm          = { .name = "per_clkdm" },
2696         .recalc         = &followparent_recalc,
2697 };
2698
2699 static struct clk per_l4_ick = {
2700         .name           = "per_l4_ick",
2701         .parent         = &l4_ick,
2702         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2703                                 PARENT_CONTROLS_CLOCK,
2704         .clkdm          = { .name = "per_clkdm" },
2705         .recalc         = &followparent_recalc,
2706 };
2707
2708 static struct clk gpio6_ick = {
2709         .name           = "gpio6_ick",
2710         .parent         = &per_l4_ick,
2711         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2712         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2713         .flags          = CLOCK_IN_OMAP343X,
2714         .clkdm          = { .name = "per_clkdm" },
2715         .recalc         = &followparent_recalc,
2716 };
2717
2718 static struct clk gpio5_ick = {
2719         .name           = "gpio5_ick",
2720         .parent         = &per_l4_ick,
2721         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2722         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2723         .flags          = CLOCK_IN_OMAP343X,
2724         .clkdm          = { .name = "per_clkdm" },
2725         .recalc         = &followparent_recalc,
2726 };
2727
2728 static struct clk gpio4_ick = {
2729         .name           = "gpio4_ick",
2730         .parent         = &per_l4_ick,
2731         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2732         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2733         .flags          = CLOCK_IN_OMAP343X,
2734         .clkdm          = { .name = "per_clkdm" },
2735         .recalc         = &followparent_recalc,
2736 };
2737
2738 static struct clk gpio3_ick = {
2739         .name           = "gpio3_ick",
2740         .parent         = &per_l4_ick,
2741         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2742         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2743         .flags          = CLOCK_IN_OMAP343X,
2744         .clkdm          = { .name = "per_clkdm" },
2745         .recalc         = &followparent_recalc,
2746 };
2747
2748 static struct clk gpio2_ick = {
2749         .name           = "gpio2_ick",
2750         .parent         = &per_l4_ick,
2751         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2752         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2753         .flags          = CLOCK_IN_OMAP343X,
2754         .clkdm          = { .name = "per_clkdm" },
2755         .recalc         = &followparent_recalc,
2756 };
2757
2758 static struct clk wdt3_ick = {
2759         .name           = "wdt3_ick",
2760         .parent         = &per_l4_ick,
2761         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2762         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2763         .flags          = CLOCK_IN_OMAP343X,
2764         .clkdm          = { .name = "per_clkdm" },
2765         .recalc         = &followparent_recalc,
2766 };
2767
2768 static struct clk uart3_ick = {
2769         .name           = "uart3_ick",
2770         .parent         = &per_l4_ick,
2771         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2772         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2773         .flags          = CLOCK_IN_OMAP343X,
2774         .clkdm          = { .name = "per_clkdm" },
2775         .recalc         = &followparent_recalc,
2776 };
2777
2778 static struct clk gpt9_ick = {
2779         .name           = "gpt9_ick",
2780         .parent         = &per_l4_ick,
2781         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2782         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2783         .flags          = CLOCK_IN_OMAP343X,
2784         .clkdm          = { .name = "per_clkdm" },
2785         .recalc         = &followparent_recalc,
2786 };
2787
2788 static struct clk gpt8_ick = {
2789         .name           = "gpt8_ick",
2790         .parent         = &per_l4_ick,
2791         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2792         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2793         .flags          = CLOCK_IN_OMAP343X,
2794         .clkdm          = { .name = "per_clkdm" },
2795         .recalc         = &followparent_recalc,
2796 };
2797
2798 static struct clk gpt7_ick = {
2799         .name           = "gpt7_ick",
2800         .parent         = &per_l4_ick,
2801         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2802         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2803         .flags          = CLOCK_IN_OMAP343X,
2804         .clkdm          = { .name = "per_clkdm" },
2805         .recalc         = &followparent_recalc,
2806 };
2807
2808 static struct clk gpt6_ick = {
2809         .name           = "gpt6_ick",
2810         .parent         = &per_l4_ick,
2811         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2812         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2813         .flags          = CLOCK_IN_OMAP343X,
2814         .clkdm          = { .name = "per_clkdm" },
2815         .recalc         = &followparent_recalc,
2816 };
2817
2818 static struct clk gpt5_ick = {
2819         .name           = "gpt5_ick",
2820         .parent         = &per_l4_ick,
2821         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2822         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2823         .flags          = CLOCK_IN_OMAP343X,
2824         .clkdm          = { .name = "per_clkdm" },
2825         .recalc         = &followparent_recalc,
2826 };
2827
2828 static struct clk gpt4_ick = {
2829         .name           = "gpt4_ick",
2830         .parent         = &per_l4_ick,
2831         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2832         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2833         .flags          = CLOCK_IN_OMAP343X,
2834         .clkdm          = { .name = "per_clkdm" },
2835         .recalc         = &followparent_recalc,
2836 };
2837
2838 static struct clk gpt3_ick = {
2839         .name           = "gpt3_ick",
2840         .parent         = &per_l4_ick,
2841         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2842         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2843         .flags          = CLOCK_IN_OMAP343X,
2844         .clkdm          = { .name = "per_clkdm" },
2845         .recalc         = &followparent_recalc,
2846 };
2847
2848 static struct clk gpt2_ick = {
2849         .name           = "gpt2_ick",
2850         .parent         = &per_l4_ick,
2851         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2852         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2853         .flags          = CLOCK_IN_OMAP343X,
2854         .clkdm          = { .name = "per_clkdm" },
2855         .recalc         = &followparent_recalc,
2856 };
2857
2858 static struct clk mcbsp2_ick = {
2859         .name           = "mcbsp_ick",
2860         .id             = 2,
2861         .parent         = &per_l4_ick,
2862         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2863         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2864         .flags          = CLOCK_IN_OMAP343X,
2865         .clkdm          = { .name = "per_clkdm" },
2866         .recalc         = &followparent_recalc,
2867 };
2868
2869 static struct clk mcbsp3_ick = {
2870         .name           = "mcbsp_ick",
2871         .id             = 3,
2872         .parent         = &per_l4_ick,
2873         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2874         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2875         .flags          = CLOCK_IN_OMAP343X,
2876         .clkdm          = { .name = "per_clkdm" },
2877         .recalc         = &followparent_recalc,
2878 };
2879
2880 static struct clk mcbsp4_ick = {
2881         .name           = "mcbsp_ick",
2882         .id             = 4,
2883         .parent         = &per_l4_ick,
2884         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2885         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2886         .flags          = CLOCK_IN_OMAP343X,
2887         .clkdm          = { .name = "per_clkdm" },
2888         .recalc         = &followparent_recalc,
2889 };
2890
2891 static const struct clksel mcbsp_234_clksel[] = {
2892         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2893         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2894         { .parent = NULL }
2895 };
2896
2897 static struct clk mcbsp2_fck = {
2898         .name           = "mcbsp_fck",
2899         .id             = 2,
2900         .init           = &omap2_init_clksel_parent,
2901         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2902         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2903         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2904         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2905         .clksel         = mcbsp_234_clksel,
2906         .flags          = CLOCK_IN_OMAP343X,
2907         .clkdm          = { .name = "per_clkdm" },
2908         .recalc         = &omap2_clksel_recalc,
2909 };
2910
2911 static struct clk mcbsp3_fck = {
2912         .name           = "mcbsp_fck",
2913         .id             = 3,
2914         .init           = &omap2_init_clksel_parent,
2915         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2916         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2917         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2918         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2919         .clksel         = mcbsp_234_clksel,
2920         .flags          = CLOCK_IN_OMAP343X,
2921         .clkdm          = { .name = "per_clkdm" },
2922         .recalc         = &omap2_clksel_recalc,
2923 };
2924
2925 static struct clk mcbsp4_fck = {
2926         .name           = "mcbsp_fck",
2927         .id             = 4,
2928         .init           = &omap2_init_clksel_parent,
2929         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2930         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2931         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2932         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2933         .clksel         = mcbsp_234_clksel,
2934         .flags          = CLOCK_IN_OMAP343X,
2935         .clkdm          = { .name = "per_clkdm" },
2936         .recalc         = &omap2_clksel_recalc,
2937 };
2938
2939 /* EMU clocks */
2940
2941 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2942
2943 static const struct clksel_rate emu_src_sys_rates[] = {
2944         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2945         { .div = 0 },
2946 };
2947
2948 static const struct clksel_rate emu_src_core_rates[] = {
2949         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2950         { .div = 0 },
2951 };
2952
2953 static const struct clksel_rate emu_src_per_rates[] = {
2954         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2955         { .div = 0 },
2956 };
2957
2958 static const struct clksel_rate emu_src_mpu_rates[] = {
2959         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2960         { .div = 0 },
2961 };
2962
2963 static const struct clksel emu_src_clksel[] = {
2964         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2965         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2966         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2967         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2968         { .parent = NULL },
2969 };
2970
2971 /*
2972  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2973  * to switch the source of some of the EMU clocks.
2974  * XXX Are there CLKEN bits for these EMU clks?
2975  */
2976 static struct clk emu_src_ck = {
2977         .name           = "emu_src_ck",
2978         .init           = &omap2_init_clksel_parent,
2979         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2980         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2981         .clksel         = emu_src_clksel,
2982         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2983         .clkdm          = { .name = "emu_clkdm" },
2984         .recalc         = &omap2_clksel_recalc,
2985 };
2986
2987 static const struct clksel_rate pclk_emu_rates[] = {
2988         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2989         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2990         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2991         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2992         { .div = 0 },
2993 };
2994
2995 static const struct clksel pclk_emu_clksel[] = {
2996         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2997         { .parent = NULL },
2998 };
2999
3000 static struct clk pclk_fck = {
3001         .name           = "pclk_fck",
3002         .init           = &omap2_init_clksel_parent,
3003         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3004         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3005         .clksel         = pclk_emu_clksel,
3006         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3007         .clkdm          = { .name = "emu_clkdm" },
3008         .recalc         = &omap2_clksel_recalc,
3009 };
3010
3011 static const struct clksel_rate pclkx2_emu_rates[] = {
3012         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3013         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3014         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3015         { .div = 0 },
3016 };
3017
3018 static const struct clksel pclkx2_emu_clksel[] = {
3019         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3020         { .parent = NULL },
3021 };
3022
3023 static struct clk pclkx2_fck = {
3024         .name           = "pclkx2_fck",
3025         .init           = &omap2_init_clksel_parent,
3026         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3027         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3028         .clksel         = pclkx2_emu_clksel,
3029         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3030         .clkdm          = { .name = "emu_clkdm" },
3031         .recalc         = &omap2_clksel_recalc,
3032 };
3033
3034 static const struct clksel atclk_emu_clksel[] = {
3035         { .parent = &emu_src_ck, .rates = div2_rates },
3036         { .parent = NULL },
3037 };
3038
3039 static struct clk atclk_fck = {
3040         .name           = "atclk_fck",
3041         .init           = &omap2_init_clksel_parent,
3042         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3043         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3044         .clksel         = atclk_emu_clksel,
3045         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3046         .clkdm          = { .name = "emu_clkdm" },
3047         .recalc         = &omap2_clksel_recalc,
3048 };
3049
3050 static struct clk traceclk_src_fck = {
3051         .name           = "traceclk_src_fck",
3052         .init           = &omap2_init_clksel_parent,
3053         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3054         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3055         .clksel         = emu_src_clksel,
3056         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3057         .clkdm          = { .name = "emu_clkdm" },
3058         .recalc         = &omap2_clksel_recalc,
3059 };
3060
3061 static const struct clksel_rate traceclk_rates[] = {
3062         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3063         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3064         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3065         { .div = 0 },
3066 };
3067
3068 static const struct clksel traceclk_clksel[] = {
3069         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3070         { .parent = NULL },
3071 };
3072
3073 static struct clk traceclk_fck = {
3074         .name           = "traceclk_fck",
3075         .init           = &omap2_init_clksel_parent,
3076         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3077         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3078         .clksel         = traceclk_clksel,
3079         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3080         .clkdm          = { .name = "emu_clkdm" },
3081         .recalc         = &omap2_clksel_recalc,
3082 };
3083
3084 /* SR clocks */
3085
3086 /* SmartReflex fclk (VDD1) */
3087 static struct clk sr1_fck = {
3088         .name           = "sr1_fck",
3089         .parent         = &sys_ck,
3090         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3091         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3092         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3093         .clkdm          = { .name = "prm_clkdm" },
3094         .recalc         = &followparent_recalc,
3095 };
3096
3097 /* SmartReflex fclk (VDD2) */
3098 static struct clk sr2_fck = {
3099         .name           = "sr2_fck",
3100         .parent         = &sys_ck,
3101         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3102         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3103         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3104         .clkdm          = { .name = "prm_clkdm" },
3105         .recalc         = &followparent_recalc,
3106 };
3107
3108 static struct clk sr_l4_ick = {
3109         .name           = "sr_l4_ick",
3110         .parent         = &l4_ick,
3111         .flags          = CLOCK_IN_OMAP343X,
3112         .clkdm          = { .name = "core_l4_clkdm" },
3113         .recalc         = &followparent_recalc,
3114 };
3115
3116 /* SECURE_32K_FCK clocks */
3117
3118 /* XXX This clock no longer exists in 3430 TRM rev F */
3119 static struct clk gpt12_fck = {
3120         .name           = "gpt12_fck",
3121         .parent         = &secure_32k_fck,
3122         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3123         .clkdm          = { .name = "prm_clkdm" },
3124         .recalc         = &followparent_recalc,
3125 };
3126
3127 static struct clk wdt1_fck = {
3128         .name           = "wdt1_fck",
3129         .parent         = &secure_32k_fck,
3130         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3131         .clkdm          = { .name = "prm_clkdm" },
3132         .recalc         = &followparent_recalc,
3133 };
3134
3135 static struct clk *onchip_34xx_clks[] __initdata = {
3136         &omap_32k_fck,
3137         &virt_12m_ck,
3138         &virt_13m_ck,
3139         &virt_16_8m_ck,
3140         &virt_19_2m_ck,
3141         &virt_26m_ck,
3142         &virt_38_4m_ck,
3143         &osc_sys_ck,
3144         &sys_ck,
3145         &sys_altclk,
3146         &mcbsp_clks,
3147         &sys_clkout1,
3148         &dpll1_ck,
3149         &dpll1_x2_ck,
3150         &dpll1_x2m2_ck,
3151         &dpll2_ck,
3152         &dpll2_m2_ck,
3153         &dpll3_ck,
3154         &core_ck,
3155         &dpll3_x2_ck,
3156         &dpll3_m2_ck,
3157         &dpll3_m2x2_ck,
3158         &dpll3_m3_ck,
3159         &dpll3_m3x2_ck,
3160         &emu_core_alwon_ck,
3161         &dpll4_ck,
3162         &dpll4_x2_ck,
3163         &omap_96m_alwon_fck,
3164         &omap_96m_fck,
3165         &cm_96m_fck,
3166         &virt_omap_54m_fck,
3167         &omap_54m_fck,
3168         &omap_48m_fck,
3169         &omap_12m_fck,
3170         &dpll4_m2_ck,
3171         &dpll4_m2x2_ck,
3172         &dpll4_m3_ck,
3173         &dpll4_m3x2_ck,
3174         &dpll4_m4_ck,
3175         &dpll4_m4x2_ck,
3176         &dpll4_m5_ck,
3177         &dpll4_m5x2_ck,
3178         &dpll4_m6_ck,
3179         &dpll4_m6x2_ck,
3180         &emu_per_alwon_ck,
3181         &dpll5_ck,
3182         &dpll5_m2_ck,
3183         &omap_120m_fck,
3184         &clkout2_src_ck,
3185         &sys_clkout2,
3186         &corex2_fck,
3187         &dpll1_fck,
3188         &mpu_ck,
3189         &arm_fck,
3190         &emu_mpu_alwon_ck,
3191         &dpll2_fck,
3192         &iva2_ck,
3193         &l3_ick,
3194         &l4_ick,
3195         &rm_ick,
3196         &gfx_l3_ck,
3197         &gfx_l3_fck,
3198         &gfx_l3_ick,
3199         &gfx_cg1_ck,
3200         &gfx_cg2_ck,
3201         &sgx_fck,
3202         &sgx_ick,
3203         &d2d_26m_fck,
3204         &gpt10_fck,
3205         &gpt11_fck,
3206         &cpefuse_fck,
3207         &ts_fck,
3208         &usbtll_fck,
3209         &core_96m_fck,
3210         &mmchs3_fck,
3211         &mmchs2_fck,
3212         &mspro_fck,
3213         &mmchs1_fck,
3214         &i2c3_fck,
3215         &i2c2_fck,
3216         &i2c1_fck,
3217         &mcbsp5_fck,
3218         &mcbsp1_fck,
3219         &core_48m_fck,
3220         &mcspi4_fck,
3221         &mcspi3_fck,
3222         &mcspi2_fck,
3223         &mcspi1_fck,
3224         &uart2_fck,
3225         &uart1_fck,
3226         &fshostusb_fck,
3227         &core_12m_fck,
3228         &hdq_fck,
3229         &ssi_ssr_fck,
3230         &ssi_sst_fck,
3231         &core_l3_ick,
3232         &hsotgusb_ick,
3233         &sdrc_ick,
3234         &gpmc_fck,
3235         &security_l3_ick,
3236         &pka_ick,
3237         &core_l4_ick,
3238         &usbtll_ick,
3239         &mmchs3_ick,
3240         &icr_ick,
3241         &aes2_ick,
3242         &sha12_ick,
3243         &des2_ick,
3244         &mmchs2_ick,
3245         &mmchs1_ick,
3246         &mspro_ick,
3247         &hdq_ick,
3248         &mcspi4_ick,
3249         &mcspi3_ick,
3250         &mcspi2_ick,
3251         &mcspi1_ick,
3252         &i2c3_ick,
3253         &i2c2_ick,
3254         &i2c1_ick,
3255         &uart2_ick,
3256         &uart1_ick,
3257         &gpt11_ick,
3258         &gpt10_ick,
3259         &mcbsp5_ick,
3260         &mcbsp1_ick,
3261         &fac_ick,
3262         &mailboxes_ick,
3263         &omapctrl_ick,
3264         &ssi_l4_ick,
3265         &ssi_ick,
3266         &usb_l4_ick,
3267         &security_l4_ick2,
3268         &aes1_ick,
3269         &rng_ick,
3270         &sha11_ick,
3271         &des1_ick,
3272         &dss1_alwon_fck,
3273         &dss_tv_fck,
3274         &dss_96m_fck,
3275         &dss2_alwon_fck,
3276         &dss_ick,
3277         &cam_mclk,
3278         &cam_ick,
3279         &csi2_96m_fck,
3280         &usbhost_120m_fck,
3281         &usbhost_48m_fck,
3282         &usbhost_ick,
3283         &usim_fck,
3284         &gpt1_fck,
3285         &wkup_32k_fck,
3286         &gpio1_fck,
3287         &wdt2_fck,
3288         &wkup_l4_ick,
3289         &usim_ick,
3290         &wdt2_ick,
3291         &wdt1_ick,
3292         &gpio1_ick,
3293         &omap_32ksync_ick,
3294         &gpt12_ick,
3295         &gpt1_ick,
3296         &per_96m_fck,
3297         &per_48m_fck,
3298         &uart3_fck,
3299         &gpt2_fck,
3300         &gpt3_fck,
3301         &gpt4_fck,
3302         &gpt5_fck,
3303         &gpt6_fck,
3304         &gpt7_fck,
3305         &gpt8_fck,
3306         &gpt9_fck,
3307         &per_32k_alwon_fck,
3308         &gpio6_fck,
3309         &gpio5_fck,
3310         &gpio4_fck,
3311         &gpio3_fck,
3312         &gpio2_fck,
3313         &wdt3_fck,
3314         &per_l4_ick,
3315         &gpio6_ick,
3316         &gpio5_ick,
3317         &gpio4_ick,
3318         &gpio3_ick,
3319         &gpio2_ick,
3320         &wdt3_ick,
3321         &uart3_ick,
3322         &gpt9_ick,
3323         &gpt8_ick,
3324         &gpt7_ick,
3325         &gpt6_ick,
3326         &gpt5_ick,
3327         &gpt4_ick,
3328         &gpt3_ick,
3329         &gpt2_ick,
3330         &mcbsp2_ick,
3331         &mcbsp3_ick,
3332         &mcbsp4_ick,
3333         &mcbsp2_fck,
3334         &mcbsp3_fck,
3335         &mcbsp4_fck,
3336         &emu_src_ck,
3337         &pclk_fck,
3338         &pclkx2_fck,
3339         &atclk_fck,
3340         &traceclk_src_fck,
3341         &traceclk_fck,
3342         &sr1_fck,
3343         &sr2_fck,
3344         &sr_l4_ick,
3345         &secure_32k_fck,
3346         &gpt12_fck,
3347         &wdt1_fck,
3348 };
3349
3350 #endif