arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* Forward declarations for DPLL bypass clocks */
  53 static struct clk dpll1_fck;
  54 static struct clk dpll2_fck;
  55
  56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  57 #define DPLL_LOW_POWER_STOP             0x1
  58 #define DPLL_LOW_POWER_BYPASS           0x5
  59 #define DPLL_LOCKED                     0x7
  60
  61 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  62         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  63
  64 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  65         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  66
  67 #define OMAP3430_PRM_CLKSEL                                             \
  68         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  69
  70 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  71         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  72
  73 /* PRM CLOCKS */
  74
  75 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  76 static struct clk omap_32k_fck = {
  77         .name           = "omap_32k_fck",
  78         .rate           = 32768,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .clkdm          = { .name = "prm_clkdm" },
  82         .recalc         = &propagate_rate,
  83 };
  84
  85 static struct clk secure_32k_fck = {
  86         .name           = "secure_32k_fck",
  87         .rate           = 32768,
  88         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  89                                 ALWAYS_ENABLED,
  90         .clkdm          = { .name = "prm_clkdm" },
  91         .recalc         = &propagate_rate,
  92 };
  93
  94 /* Virtual source clocks for osc_sys_ck */
  95 static struct clk virt_12m_ck = {
  96         .name           = "virt_12m_ck",
  97         .rate           = 12000000,
  98         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  99                                 ALWAYS_ENABLED,
 100         .clkdm          = { .name = "prm_clkdm" },
 101         .recalc         = &propagate_rate,
 102 };
 103
 104 static struct clk virt_13m_ck = {
 105         .name           = "virt_13m_ck",
 106         .rate           = 13000000,
 107         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 108                                 ALWAYS_ENABLED,
 109         .clkdm          = { .name = "prm_clkdm" },
 110         .recalc         = &propagate_rate,
 111 };
 112
 113 static struct clk virt_16_8m_ck = {
 114         .name           = "virt_16_8m_ck",
 115         .rate           = 16800000,
 116         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 117                                 ALWAYS_ENABLED,
 118         .clkdm          = { .name = "prm_clkdm" },
 119         .recalc         = &propagate_rate,
 120 };
 121
 122 static struct clk virt_19_2m_ck = {
 123         .name           = "virt_19_2m_ck",
 124         .rate           = 19200000,
 125         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 126                                 ALWAYS_ENABLED,
 127         .clkdm          = { .name = "prm_clkdm" },
 128         .recalc         = &propagate_rate,
 129 };
 130
 131 static struct clk virt_26m_ck = {
 132         .name           = "virt_26m_ck",
 133         .rate           = 26000000,
 134         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 135                                 ALWAYS_ENABLED,
 136         .clkdm          = { .name = "prm_clkdm" },
 137         .recalc         = &propagate_rate,
 138 };
 139
 140 static struct clk virt_38_4m_ck = {
 141         .name           = "virt_38_4m_ck",
 142         .rate           = 38400000,
 143         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 144                                 ALWAYS_ENABLED,
 145         .clkdm          = { .name = "prm_clkdm" },
 146         .recalc         = &propagate_rate,
 147 };
 148
 149 static const struct clksel_rate osc_sys_12m_rates[] = {
 150         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 151         { .div = 0 }
 152 };
 153
 154 static const struct clksel_rate osc_sys_13m_rates[] = {
 155         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 156         { .div = 0 }
 157 };
 158
 159 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 160         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 161         { .div = 0 }
 162 };
 163
 164 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 165         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 166         { .div = 0 }
 167 };
 168
 169 static const struct clksel_rate osc_sys_26m_rates[] = {
 170         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 171         { .div = 0 }
 172 };
 173
 174 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 175         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 176         { .div = 0 }
 177 };
 178
 179 static const struct clksel osc_sys_clksel[] = {
 180         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 181         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 182         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 183         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 184         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 185         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 186         { .parent = NULL },
 187 };
 188
 189 /* Oscillator clock */
 190 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 191 static struct clk osc_sys_ck = {
 192         .name           = "osc_sys_ck",
 193         .init           = &omap2_init_clksel_parent,
 194         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 195         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 196         .clksel         = osc_sys_clksel,
 197         /* REVISIT: deal with autoextclkmode? */
 198         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 199                                 ALWAYS_ENABLED,
 200         .clkdm          = { .name = "prm_clkdm" },
 201         .recalc         = &omap2_clksel_recalc,
 202 };
 203
 204 static const struct clksel_rate div2_rates[] = {
 205         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 206         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 207         { .div = 0 }
 208 };
 209
 210 static const struct clksel sys_clksel[] = {
 211         { .parent = &osc_sys_ck, .rates = div2_rates },
 212         { .parent = NULL }
 213 };
 214
 215 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 216 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 217 static struct clk sys_ck = {
 218         .name           = "sys_ck",
 219         .parent         = &osc_sys_ck,
 220         .init           = &omap2_init_clksel_parent,
 221         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 222         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 223         .clksel         = sys_clksel,
 224         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 225         .clkdm          = { .name = "prm_clkdm" },
 226         .recalc         = &omap2_clksel_recalc,
 227 };
 228
 229 static struct clk sys_altclk = {
 230         .name           = "sys_altclk",
 231         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 232         .clkdm          = { .name = "cm_clkdm" },
 233         .recalc         = &propagate_rate,
 234 };
 235
 236 /*
 237  * Optional external clock input for some McBSPs
 238  * Apparently this is not really in prm_clkdm, but rather is fed into
 239  * both CORE and PER separately.
 240  */
 241 static struct clk mcbsp_clks = {
 242         .name           = "mcbsp_clks",
 243         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 244         .clkdm          = { .name = "prm_clkdm" },
 245         .recalc         = &propagate_rate,
 246 };
 247
 248 /* PRM EXTERNAL CLOCK OUTPUT */
 249
 250 static struct clk sys_clkout1 = {
 251         .name           = "sys_clkout1",
 252         .parent         = &osc_sys_ck,
 253         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 254         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 255         .flags          = CLOCK_IN_OMAP343X,
 256         .clkdm          = { .name = "prm_clkdm" },
 257         .recalc         = &followparent_recalc,
 258 };
 259
 260 /* DPLLS */
 261
 262 /* CM CLOCKS */
 263
 264 static const struct clksel_rate div16_dpll_rates[] = {
 265         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 266         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 267         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 268         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 269         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 270         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 271         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 272         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 273         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 274         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 275         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 276         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 277         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 278         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 279         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 280         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 281         { .div = 0 }
 282 };
 283
 284 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 285         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 286
 287 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 288         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 289
 290 /* DPLL1 */
 291 /* MPU clock source */
 292 /* Type: DPLL */
 293 static struct dpll_data dpll1_dd = {
 294         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 295         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 296         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 297         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 298         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 299         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 300         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 301         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 302         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 303         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 304         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 305         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 306         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 307         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 308         .bypass_clk     = &dpll1_fck,
 309         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 310         .max_divider    = OMAP3_MAX_DPLL_DIV,
 311         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 312 };
 313
 314 static struct clk dpll1_ck = {
 315         .name           = "dpll1_ck",
 316         .parent         = &sys_ck,
 317         .dpll_data      = &dpll1_dd,
 318         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 319         .round_rate     = &omap2_dpll_round_rate,
 320         .set_rate       = &omap3_noncore_dpll_set_rate,
 321         .clkdm          = { .name = "dpll1_clkdm" },
 322         .recalc         = &omap3_dpll_recalc,
 323 };
 324
 325 /*
 326  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 327  * DPLL isn't bypassed.
 328  */
 329 static struct clk dpll1_x2_ck = {
 330         .name           = "dpll1_x2_ck",
 331         .parent         = &dpll1_ck,
 332         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 333                                 PARENT_CONTROLS_CLOCK,
 334         .clkdm          = { .name = "dpll1_clkdm" },
 335         .recalc         = &omap3_clkoutx2_recalc,
 336 };
 337
 338 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 339 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 340         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 341         { .parent = NULL }
 342 };
 343
 344 /*
 345  * Does not exist in the TRM - needed to separate the M2 divider from
 346  * bypass selection in mpu_ck
 347  */
 348 static struct clk dpll1_x2m2_ck = {
 349         .name           = "dpll1_x2m2_ck",
 350         .parent         = &dpll1_x2_ck,
 351         .init           = &omap2_init_clksel_parent,
 352         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 353         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 354         .clksel         = div16_dpll1_x2m2_clksel,
 355         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 356                                 PARENT_CONTROLS_CLOCK,
 357         .clkdm          = { .name = "dpll1_clkdm" },
 358         .recalc         = &omap2_clksel_recalc,
 359 };
 360
 361 /* DPLL2 */
 362 /* IVA2 clock source */
 363 /* Type: DPLL */
 364
 365 static struct dpll_data dpll2_dd = {
 366         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 367         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 368         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 369         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 370         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 371         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 372         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 373                                 (1 << DPLL_LOW_POWER_BYPASS),
 374         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 375         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 376         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 377         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 378         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 379         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 380         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 381         .bypass_clk     = &dpll2_fck,
 382         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 383         .max_divider    = OMAP3_MAX_DPLL_DIV,
 384         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 385 };
 386
 387 static struct clk dpll2_ck = {
 388         .name           = "dpll2_ck",
 389         .parent         = &sys_ck,
 390         .dpll_data      = &dpll2_dd,
 391         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 392         .enable         = &omap3_noncore_dpll_enable,
 393         .disable        = &omap3_noncore_dpll_disable,
 394         .round_rate     = &omap2_dpll_round_rate,
 395         .set_rate       = &omap3_noncore_dpll_set_rate,
 396         .clkdm          = { .name = "dpll2_clkdm" },
 397         .recalc         = &omap3_dpll_recalc,
 398 };
 399
 400 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 401         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 402         { .parent = NULL }
 403 };
 404
 405 /*
 406  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 407  * or CLKOUTX2. CLKOUT seems most plausible.
 408  */
 409 static struct clk dpll2_m2_ck = {
 410         .name           = "dpll2_m2_ck",
 411         .parent         = &dpll2_ck,
 412         .init           = &omap2_init_clksel_parent,
 413         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 414                                           OMAP3430_CM_CLKSEL2_PLL),
 415         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 416         .clksel         = div16_dpll2_m2x2_clksel,
 417         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 418                                 PARENT_CONTROLS_CLOCK,
 419         .clkdm          = { .name = "dpll2_clkdm" },
 420         .recalc         = &omap2_clksel_recalc,
 421 };
 422
 423 /*
 424  * DPLL3
 425  * Source clock for all interfaces and for some device fclks
 426  * REVISIT: Also supports fast relock bypass - not included below
 427  */
 428 static struct dpll_data dpll3_dd = {
 429         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 430         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 431         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 432         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 433         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 434         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 435         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 436         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 437         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 438         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 439         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 440         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 441         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 442         .bypass_clk     = &sys_ck,
 443         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 444         .max_divider    = OMAP3_MAX_DPLL_DIV,
 445         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 446 };
 447
 448 static struct clk dpll3_ck = {
 449         .name           = "dpll3_ck",
 450         .parent         = &sys_ck,
 451         .dpll_data      = &dpll3_dd,
 452         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 453         .round_rate     = &omap2_dpll_round_rate,
 454         .clkdm          = { .name = "dpll3_clkdm" },
 455         .recalc         = &omap3_dpll_recalc,
 456 };
 457
 458 /*
 459  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 460  * DPLL isn't bypassed
 461  */
 462 static struct clk dpll3_x2_ck = {
 463         .name           = "dpll3_x2_ck",
 464         .parent         = &dpll3_ck,
 465         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 466                                 PARENT_CONTROLS_CLOCK,
 467         .clkdm          = { .name = "dpll3_clkdm" },
 468         .recalc         = &omap3_clkoutx2_recalc,
 469 };
 470
 471 static const struct clksel_rate div31_dpll3_rates[] = {
 472         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 473         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 474         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 475         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 476         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 477         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 478         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 479         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 480         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 481         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 482         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 483         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 484         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 485         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 486         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 487         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 488         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 489         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 490         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 491         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 492         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 493         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 494         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 495         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 496         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 497         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 498         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 499         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 500         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 501         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 502         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 503         { .div = 0 },
 504 };
 505
 506 static const struct clksel div31_dpll3m2_clksel[] = {
 507         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 508         { .parent = NULL }
 509 };
 510
 511 /* DPLL3 output M2 - primary control point for CORE speed */
 512 static struct clk dpll3_m2_ck = {
 513         .name           = "dpll3_m2_ck",
 514         .parent         = &dpll3_ck,
 515         .init           = &omap2_init_clksel_parent,
 516         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 517         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 518         .clksel         = div31_dpll3m2_clksel,
 519         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 520                                 PARENT_CONTROLS_CLOCK,
 521         .clkdm          = { .name = "dpll3_clkdm" },
 522         .round_rate     = &omap2_clksel_round_rate,
 523         .set_rate       = &omap3_core_dpll_m2_set_rate,
 524         .recalc         = &omap2_clksel_recalc,
 525 };
 526
 527 static struct clk core_ck = {
 528         .name           = "core_ck",
 529         .parent         = &dpll3_m2_ck,
 530         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 531                                 PARENT_CONTROLS_CLOCK,
 532         .clkdm          = { .name = "cm_clkdm" },
 533         .recalc         = &followparent_recalc,
 534 };
 535
 536 static struct clk dpll3_m2x2_ck = {
 537         .name           = "dpll3_m2x2_ck",
 538         .parent         = &dpll3_x2_ck,
 539         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 540                                 PARENT_CONTROLS_CLOCK,
 541         .clkdm          = { .name = "dpll3_clkdm" },
 542         .recalc         = &followparent_recalc,
 543 };
 544
 545 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 546 static const struct clksel div16_dpll3_clksel[] = {
 547         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 548         { .parent = NULL }
 549 };
 550
 551 /* This virtual clock is the source for dpll3_m3x2_ck */
 552 static struct clk dpll3_m3_ck = {
 553         .name           = "dpll3_m3_ck",
 554         .parent         = &dpll3_ck,
 555         .init           = &omap2_init_clksel_parent,
 556         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 557         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 558         .clksel         = div16_dpll3_clksel,
 559         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 560                                 PARENT_CONTROLS_CLOCK,
 561         .clkdm          = { .name = "dpll3_clkdm" },
 562         .recalc         = &omap2_clksel_recalc,
 563 };
 564
 565 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 566 static struct clk dpll3_m3x2_ck = {
 567         .name           = "dpll3_m3x2_ck",
 568         .parent         = &dpll3_m3_ck,
 569         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 570         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 571         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 572         .clkdm          = { .name = "dpll3_clkdm" },
 573         .recalc         = &omap3_clkoutx2_recalc,
 574 };
 575
 576 static struct clk emu_core_alwon_ck = {
 577         .name           = "emu_core_alwon_ck",
 578         .parent         = &dpll3_m3x2_ck,
 579         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 580                                 PARENT_CONTROLS_CLOCK,
 581         .clkdm          = { .name = "dpll3_clkdm" },
 582         .recalc         = &followparent_recalc,
 583 };
 584
 585 /* DPLL4 */
 586 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 587 /* Type: DPLL */
 588 static struct dpll_data dpll4_dd = {
 589         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 590         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 591         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 592         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 593         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 594         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 595         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 596         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 597         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 598         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 599         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 600         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 601         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 602         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 603         .bypass_clk     = &sys_ck,
 604         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 605         .max_divider    = OMAP3_MAX_DPLL_DIV,
 606         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 607 };
 608
 609 static struct clk dpll4_ck = {
 610         .name           = "dpll4_ck",
 611         .parent         = &sys_ck,
 612         .dpll_data      = &dpll4_dd,
 613         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 614         .enable         = &omap3_noncore_dpll_enable,
 615         .disable        = &omap3_noncore_dpll_disable,
 616         .round_rate     = &omap2_dpll_round_rate,
 617         .set_rate       = &omap3_noncore_dpll_set_rate,
 618         .clkdm          = { .name = "dpll4_clkdm" },
 619         .recalc         = &omap3_dpll_recalc,
 620 };
 621
 622 /*
 623  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 624  * DPLL isn't bypassed --
 625  * XXX does this serve any downstream clocks?
 626  */
 627 static struct clk dpll4_x2_ck = {
 628         .name           = "dpll4_x2_ck",
 629         .parent         = &dpll4_ck,
 630         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 631                                 PARENT_CONTROLS_CLOCK,
 632         .clkdm          = { .name = "dpll4_clkdm" },
 633         .recalc         = &omap3_clkoutx2_recalc,
 634 };
 635
 636 static const struct clksel div16_dpll4_clksel[] = {
 637         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 638         { .parent = NULL }
 639 };
 640
 641 /* This virtual clock is the source for dpll4_m2x2_ck */
 642 static struct clk dpll4_m2_ck = {
 643         .name           = "dpll4_m2_ck",
 644         .parent         = &dpll4_ck,
 645         .init           = &omap2_init_clksel_parent,
 646         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 647         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 648         .clksel         = div16_dpll4_clksel,
 649         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 650                                 PARENT_CONTROLS_CLOCK,
 651         .clkdm          = { .name = "dpll4_clkdm" },
 652         .recalc         = &omap2_clksel_recalc,
 653 };
 654
 655 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 656 static struct clk dpll4_m2x2_ck = {
 657         .name           = "dpll4_m2x2_ck",
 658         .parent         = &dpll4_m2_ck,
 659         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 660         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 661         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 662         .clkdm          = { .name = "dpll4_clkdm" },
 663         .recalc         = &omap3_clkoutx2_recalc,
 664 };
 665
 666 /*
 667  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 668  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 669  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 670  * CM_96K_(F)CLK.
 671  */
 672 static struct clk omap_96m_alwon_fck = {
 673         .name           = "omap_96m_alwon_fck",
 674         .parent         = &dpll4_m2x2_ck,
 675         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 676                                 PARENT_CONTROLS_CLOCK,
 677         .clkdm          = { .name = "prm_clkdm" },
 678         .recalc         = &followparent_recalc,
 679 };
 680
 681 static struct clk cm_96m_fck = {
 682         .name           = "cm_96m_fck",
 683         .parent         = &omap_96m_alwon_fck,
 684         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 685                                 PARENT_CONTROLS_CLOCK,
 686         .clkdm          = { .name = "cm_clkdm" },
 687         .recalc         = &followparent_recalc,
 688 };
 689
 690 static const struct clksel_rate omap_96m_dpll_rates[] = {
 691         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 692         { .div = 0 }
 693 };
 694
 695 static const struct clksel_rate omap_96m_sys_rates[] = {
 696         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 697         { .div = 0 }
 698 };
 699
 700 static const struct clksel omap_96m_fck_clksel[] = {
 701         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 702         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 703         { .parent = NULL }
 704 };
 705
 706 static struct clk omap_96m_fck = {
 707         .name           = "omap_96m_fck",
 708         .parent         = &sys_ck,
 709         .init           = &omap2_init_clksel_parent,
 710         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 711         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 712         .clksel         = omap_96m_fck_clksel,
 713         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 714                                 PARENT_CONTROLS_CLOCK,
 715         .clkdm          = { .name = "cm_clkdm" },
 716         .recalc         = &omap2_clksel_recalc,
 717 };
 718
 719 /* This virtual clock is the source for dpll4_m3x2_ck */
 720 static struct clk dpll4_m3_ck = {
 721         .name           = "dpll4_m3_ck",
 722         .parent         = &dpll4_ck,
 723         .init           = &omap2_init_clksel_parent,
 724         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 725         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 726         .clksel         = div16_dpll4_clksel,
 727         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 728                                 PARENT_CONTROLS_CLOCK,
 729         .clkdm          = { .name = "dpll4_clkdm" },
 730         .recalc         = &omap2_clksel_recalc,
 731 };
 732
 733 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 734 static struct clk dpll4_m3x2_ck = {
 735         .name           = "dpll4_m3x2_ck",
 736         .parent         = &dpll4_m3_ck,
 737         .init           = &omap2_init_clksel_parent,
 738         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 739         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 740         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 741         .clkdm          = { .name = "dpll4_clkdm" },
 742         .recalc         = &omap3_clkoutx2_recalc,
 743 };
 744
 745 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 746         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 747         { .div = 0 }
 748 };
 749
 750 static const struct clksel_rate omap_54m_alt_rates[] = {
 751         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 752         { .div = 0 }
 753 };
 754
 755 static const struct clksel omap_54m_clksel[] = {
 756         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 757         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 758         { .parent = NULL }
 759 };
 760
 761 static struct clk omap_54m_fck = {
 762         .name           = "omap_54m_fck",
 763         .init           = &omap2_init_clksel_parent,
 764         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 765         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 766         .clksel         = omap_54m_clksel,
 767         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 768                                 PARENT_CONTROLS_CLOCK,
 769         .clkdm          = { .name = "cm_clkdm" },
 770         .recalc         = &omap2_clksel_recalc,
 771 };
 772
 773 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 774         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 775         { .div = 0 }
 776 };
 777
 778 static const struct clksel_rate omap_48m_alt_rates[] = {
 779         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 780         { .div = 0 }
 781 };
 782
 783 static const struct clksel omap_48m_clksel[] = {
 784         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 785         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 786         { .parent = NULL }
 787 };
 788
 789 static struct clk omap_48m_fck = {
 790         .name           = "omap_48m_fck",
 791         .init           = &omap2_init_clksel_parent,
 792         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 793         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 794         .clksel         = omap_48m_clksel,
 795         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 796                                 PARENT_CONTROLS_CLOCK,
 797         .clkdm          = { .name = "cm_clkdm" },
 798         .recalc         = &omap2_clksel_recalc,
 799 };
 800
 801 static struct clk omap_12m_fck = {
 802         .name           = "omap_12m_fck",
 803         .parent         = &omap_48m_fck,
 804         .fixed_div      = 4,
 805         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 806                                 PARENT_CONTROLS_CLOCK,
 807         .clkdm          = { .name = "cm_clkdm" },
 808         .recalc         = &omap2_fixed_divisor_recalc,
 809 };
 810
 811 /* This virstual clock is the source for dpll4_m4x2_ck */
 812 static struct clk dpll4_m4_ck = {
 813         .name           = "dpll4_m4_ck",
 814         .parent         = &dpll4_ck,
 815         .init           = &omap2_init_clksel_parent,
 816         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 817         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 818         .clksel         = div16_dpll4_clksel,
 819         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 820                                 PARENT_CONTROLS_CLOCK,
 821         .clkdm          = { .name = "dpll4_clkdm" },
 822         .recalc         = &omap2_clksel_recalc,
 823 };
 824
 825 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 826 static struct clk dpll4_m4x2_ck = {
 827         .name           = "dpll4_m4x2_ck",
 828         .parent         = &dpll4_m4_ck,
 829         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 830         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 831         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 832         .clkdm          = { .name = "dpll4_clkdm" },
 833         .recalc         = &omap3_clkoutx2_recalc,
 834 };
 835
 836 /* This virtual clock is the source for dpll4_m5x2_ck */
 837 static struct clk dpll4_m5_ck = {
 838         .name           = "dpll4_m5_ck",
 839         .parent         = &dpll4_ck,
 840         .init           = &omap2_init_clksel_parent,
 841         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 842         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 843         .clksel         = div16_dpll4_clksel,
 844         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 845                                 PARENT_CONTROLS_CLOCK,
 846         .clkdm          = { .name = "dpll4_clkdm" },
 847         .recalc         = &omap2_clksel_recalc,
 848 };
 849
 850 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 851 static struct clk dpll4_m5x2_ck = {
 852         .name           = "dpll4_m5x2_ck",
 853         .parent         = &dpll4_m5_ck,
 854         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 855         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 856         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 857         .clkdm          = { .name = "dpll4_clkdm" },
 858         .recalc         = &omap3_clkoutx2_recalc,
 859 };
 860
 861 /* This virtual clock is the source for dpll4_m6x2_ck */
 862 static struct clk dpll4_m6_ck = {
 863         .name           = "dpll4_m6_ck",
 864         .parent         = &dpll4_ck,
 865         .init           = &omap2_init_clksel_parent,
 866         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 867         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 868         .clksel         = div16_dpll4_clksel,
 869         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 870                                 PARENT_CONTROLS_CLOCK,
 871         .clkdm          = { .name = "dpll4_clkdm" },
 872         .recalc         = &omap2_clksel_recalc,
 873 };
 874
 875 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 876 static struct clk dpll4_m6x2_ck = {
 877         .name           = "dpll4_m6x2_ck",
 878         .parent         = &dpll4_m6_ck,
 879         .init           = &omap2_init_clksel_parent,
 880         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 881         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 882         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 883         .clkdm          = { .name = "dpll4_clkdm" },
 884         .recalc         = &omap3_clkoutx2_recalc,
 885 };
 886
 887 static struct clk emu_per_alwon_ck = {
 888         .name           = "emu_per_alwon_ck",
 889         .parent         = &dpll4_m6x2_ck,
 890         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 891                                 PARENT_CONTROLS_CLOCK,
 892         .clkdm          = { .name = "dpll4_clkdm" },
 893         .recalc         = &followparent_recalc,
 894 };
 895
 896 /* DPLL5 */
 897 /* Supplies 120MHz clock, USIM source clock */
 898 /* Type: DPLL */
 899 /* 3430ES2 only */
 900 static struct dpll_data dpll5_dd = {
 901         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 902         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 903         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 904         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 905         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 906         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 907         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 908         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 909         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 910         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 911         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 912         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 913         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 914         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 915         .bypass_clk     = &sys_ck,
 916         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 917         .max_divider    = OMAP3_MAX_DPLL_DIV,
 918         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 919 };
 920
 921 static struct clk dpll5_ck = {
 922         .name           = "dpll5_ck",
 923         .parent         = &sys_ck,
 924         .dpll_data      = &dpll5_dd,
 925         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 926         .enable         = &omap3_noncore_dpll_enable,
 927         .disable        = &omap3_noncore_dpll_disable,
 928         .round_rate     = &omap2_dpll_round_rate,
 929         .set_rate       = &omap3_noncore_dpll_set_rate,
 930         .clkdm          = { .name = "dpll5_clkdm" },
 931         .recalc         = &omap3_dpll_recalc,
 932 };
 933
 934 static const struct clksel div16_dpll5_clksel[] = {
 935         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 936         { .parent = NULL }
 937 };
 938
 939 static struct clk dpll5_m2_ck = {
 940         .name           = "dpll5_m2_ck",
 941         .parent         = &dpll5_ck,
 942         .init           = &omap2_init_clksel_parent,
 943         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 944         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 945         .clksel         = div16_dpll5_clksel,
 946         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 947                                 PARENT_CONTROLS_CLOCK,
 948         .clkdm          = { .name = "dpll5_clkdm" },
 949         .recalc         = &omap2_clksel_recalc,
 950 };
 951
 952 /* CM EXTERNAL CLOCK OUTPUTS */
 953
 954 static const struct clksel_rate clkout2_src_core_rates[] = {
 955         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 956         { .div = 0 }
 957 };
 958
 959 static const struct clksel_rate clkout2_src_sys_rates[] = {
 960         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 961         { .div = 0 }
 962 };
 963
 964 static const struct clksel_rate clkout2_src_96m_rates[] = {
 965         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 966         { .div = 0 }
 967 };
 968
 969 static const struct clksel_rate clkout2_src_54m_rates[] = {
 970         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 971         { .div = 0 }
 972 };
 973
 974 static const struct clksel clkout2_src_clksel[] = {
 975         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 976         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 977         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 978         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 979         { .parent = NULL }
 980 };
 981
 982 static struct clk clkout2_src_ck = {
 983         .name           = "clkout2_src_ck",
 984         .init           = &omap2_init_clksel_parent,
 985         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
 986         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 987         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
 988         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 989         .clksel         = clkout2_src_clksel,
 990         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 991         .clkdm          = { .name = "cm_clkdm" },
 992         .recalc         = &omap2_clksel_recalc,
 993 };
 994
 995 static const struct clksel_rate sys_clkout2_rates[] = {
 996         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 997         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 998         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 999         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1000         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1001         { .div = 0 },
1002 };
1003
1004 static const struct clksel sys_clkout2_clksel[] = {
1005         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1006         { .parent = NULL },
1007 };
1008
1009 static struct clk sys_clkout2 = {
1010         .name           = "sys_clkout2",
1011         .init           = &omap2_init_clksel_parent,
1012         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1013         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1014         .clksel         = sys_clkout2_clksel,
1015         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1016         .clkdm          = { .name = "cm_clkdm" },
1017         .recalc         = &omap2_clksel_recalc,
1018 };
1019
1020 /* CM OUTPUT CLOCKS */
1021
1022 static struct clk corex2_fck = {
1023         .name           = "corex2_fck",
1024         .parent         = &dpll3_m2x2_ck,
1025         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1026                                 PARENT_CONTROLS_CLOCK,
1027         .clkdm          = { .name = "cm_clkdm" },
1028         .recalc         = &followparent_recalc,
1029 };
1030
1031 /* DPLL power domain clock controls */
1032
1033 static const struct clksel_rate div4_rates[] = {
1034         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1035         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1036         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1037         { .div = 0 }
1038 };
1039
1040 static const struct clksel div4_core_clksel[] = {
1041         { .parent = &core_ck, .rates = div4_rates },
1042         { .parent = NULL }
1043 };
1044
1045 static struct clk dpll1_fck = {
1046         .name           = "dpll1_fck",
1047         .parent         = &core_ck,
1048         .init           = &omap2_init_clksel_parent,
1049         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1050         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1051         .clksel         = div4_core_clksel,
1052         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1053                                 PARENT_CONTROLS_CLOCK,
1054         .clkdm          = { .name = "cm_clkdm" },
1055         .recalc         = &omap2_clksel_recalc,
1056 };
1057
1058 static struct clk mpu_ck = {
1059         .name           = "mpu_ck",
1060         .parent         = &dpll1_x2m2_ck,
1061         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1062                                 PARENT_CONTROLS_CLOCK,
1063         .clkdm          = { .name = "mpu_clkdm" },
1064         .recalc         = &followparent_recalc,
1065 };
1066
1067 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1068 static const struct clksel_rate arm_fck_rates[] = {
1069         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1070         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1071         { .div = 0 },
1072 };
1073
1074 static const struct clksel arm_fck_clksel[] = {
1075         { .parent = &mpu_ck, .rates = arm_fck_rates },
1076         { .parent = NULL }
1077 };
1078
1079 static struct clk arm_fck = {
1080         .name           = "arm_fck",
1081         .parent         = &mpu_ck,
1082         .init           = &omap2_init_clksel_parent,
1083         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1084         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1085         .clksel         = arm_fck_clksel,
1086         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1087                                 PARENT_CONTROLS_CLOCK,
1088         .clkdm          = { .name = "mpu_clkdm" },
1089         .recalc         = &omap2_clksel_recalc,
1090 };
1091
1092 /* XXX What about neon_clkdm ? */
1093
1094 /*
1095  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1096  * although it is referenced - so this is a guess
1097  */
1098 static struct clk emu_mpu_alwon_ck = {
1099         .name           = "emu_mpu_alwon_ck",
1100         .parent         = &mpu_ck,
1101         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1102                                 PARENT_CONTROLS_CLOCK,
1103         .clkdm          = { .name = "mpu_clkdm" },
1104         .recalc         = &followparent_recalc,
1105 };
1106
1107 static struct clk dpll2_fck = {
1108         .name           = "dpll2_fck",
1109         .parent         = &core_ck,
1110         .init           = &omap2_init_clksel_parent,
1111         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1112         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1113         .clksel         = div4_core_clksel,
1114         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1115                                 PARENT_CONTROLS_CLOCK,
1116         .clkdm          = { .name = "cm_clkdm" },
1117         .recalc         = &omap2_clksel_recalc,
1118 };
1119
1120 static struct clk iva2_ck = {
1121         .name           = "iva2_ck",
1122         .parent         = &dpll2_m2_ck,
1123         .init           = &omap2_init_clksel_parent,
1124         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1125         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1126         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1127         .clkdm          = { .name = "iva2_clkdm" },
1128         .recalc         = &followparent_recalc,
1129 };
1130
1131 /* Common interface clocks */
1132
1133 static const struct clksel div2_core_clksel[] = {
1134         { .parent = &core_ck, .rates = div2_rates },
1135         { .parent = NULL }
1136 };
1137
1138 static struct clk l3_ick = {
1139         .name           = "l3_ick",
1140         .parent         = &core_ck,
1141         .init           = &omap2_init_clksel_parent,
1142         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1143         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1144         .clksel         = div2_core_clksel,
1145         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1146                                 PARENT_CONTROLS_CLOCK,
1147         .clkdm          = { .name = "core_l3_clkdm" },
1148         .recalc         = &omap2_clksel_recalc,
1149 };
1150
1151 static const struct clksel div2_l3_clksel[] = {
1152         { .parent = &l3_ick, .rates = div2_rates },
1153         { .parent = NULL }
1154 };
1155
1156 static struct clk l4_ick = {
1157         .name           = "l4_ick",
1158         .parent         = &l3_ick,
1159         .init           = &omap2_init_clksel_parent,
1160         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1161         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1162         .clksel         = div2_l3_clksel,
1163         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1164                                 PARENT_CONTROLS_CLOCK,
1165         .clkdm          = { .name = "core_l4_clkdm" },
1166         .recalc         = &omap2_clksel_recalc,
1167
1168 };
1169
1170 static const struct clksel div2_l4_clksel[] = {
1171         { .parent = &l4_ick, .rates = div2_rates },
1172         { .parent = NULL }
1173 };
1174
1175 static struct clk rm_ick = {
1176         .name           = "rm_ick",
1177         .parent         = &l4_ick,
1178         .init           = &omap2_init_clksel_parent,
1179         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1180         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1181         .clksel         = div2_l4_clksel,
1182         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1183         .clkdm          = { .name = "cm_clkdm" },
1184         .recalc         = &omap2_clksel_recalc,
1185 };
1186
1187 /* GFX power domain */
1188
1189 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1190
1191 static const struct clksel gfx_l3_clksel[] = {
1192         { .parent = &l3_ick, .rates = gfx_l3_rates },
1193         { .parent = NULL }
1194 };
1195
1196 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1197 static struct clk gfx_l3_ck = {
1198         .name           = "gfx_l3_ck",
1199         .parent         = &l3_ick,
1200         .init           = &omap2_init_clksel_parent,
1201         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1202         .enable_bit     = OMAP_EN_GFX_SHIFT,
1203         .flags          = CLOCK_IN_OMAP3430ES1,
1204         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1205         .recalc         = &followparent_recalc,
1206 };
1207
1208 static struct clk gfx_l3_fck = {
1209         .name           = "gfx_l3_fck",
1210         .parent         = &gfx_l3_ck,
1211         .init           = &omap2_init_clksel_parent,
1212         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1213         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1214         .clksel         = gfx_l3_clksel,
1215         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1216                                 PARENT_CONTROLS_CLOCK,
1217         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1218         .recalc         = &omap2_clksel_recalc,
1219 };
1220
1221 static struct clk gfx_l3_ick = {
1222         .name           = "gfx_l3_ick",
1223         .parent         = &gfx_l3_ck,
1224         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1225         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1226         .recalc         = &followparent_recalc,
1227 };
1228
1229 static struct clk gfx_cg1_ck = {
1230         .name           = "gfx_cg1_ck",
1231         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1232         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1233         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1234         .flags          = CLOCK_IN_OMAP3430ES1,
1235         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1236         .recalc         = &followparent_recalc,
1237 };
1238
1239 static struct clk gfx_cg2_ck = {
1240         .name           = "gfx_cg2_ck",
1241         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1242         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1243         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1244         .flags          = CLOCK_IN_OMAP3430ES1,
1245         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1246         .recalc         = &followparent_recalc,
1247 };
1248
1249 /* SGX power domain - 3430ES2 only */
1250
1251 static const struct clksel_rate sgx_core_rates[] = {
1252         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1253         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1254         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1255         { .div = 0 },
1256 };
1257
1258 static const struct clksel_rate sgx_96m_rates[] = {
1259         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1260         { .div = 0 },
1261 };
1262
1263 static const struct clksel sgx_clksel[] = {
1264         { .parent = &core_ck,    .rates = sgx_core_rates },
1265         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1266         { .parent = NULL },
1267 };
1268
1269 static struct clk sgx_fck = {
1270         .name           = "sgx_fck",
1271         .init           = &omap2_init_clksel_parent,
1272         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1273         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1274         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1275         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1276         .clksel         = sgx_clksel,
1277         .flags          = CLOCK_IN_OMAP3430ES2,
1278         .clkdm          = { .name = "sgx_clkdm" },
1279         .recalc         = &omap2_clksel_recalc,
1280 };
1281
1282 static struct clk sgx_ick = {
1283         .name           = "sgx_ick",
1284         .parent         = &l3_ick,
1285         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1286         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1287         .flags          = CLOCK_IN_OMAP3430ES2,
1288         .clkdm          = { .name = "sgx_clkdm" },
1289         .recalc         = &followparent_recalc,
1290 };
1291
1292 /* CORE power domain */
1293
1294 static struct clk d2d_26m_fck = {
1295         .name           = "d2d_26m_fck",
1296         .parent         = &sys_ck,
1297         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1298         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1299         .flags          = CLOCK_IN_OMAP3430ES1,
1300         .clkdm          = { .name = "d2d_clkdm" },
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 static const struct clksel omap343x_gpt_clksel[] = {
1305         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1306         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1307         { .parent = NULL}
1308 };
1309
1310 static struct clk gpt10_fck = {
1311         .name           = "gpt10_fck",
1312         .parent         = &sys_ck,
1313         .init           = &omap2_init_clksel_parent,
1314         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1315         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1316         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1317         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1318         .clksel         = omap343x_gpt_clksel,
1319         .flags          = CLOCK_IN_OMAP343X,
1320         .clkdm          = { .name = "core_l4_clkdm" },
1321         .recalc         = &omap2_clksel_recalc,
1322 };
1323
1324 static struct clk gpt11_fck = {
1325         .name           = "gpt11_fck",
1326         .parent         = &sys_ck,
1327         .init           = &omap2_init_clksel_parent,
1328         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1329         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1330         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1331         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1332         .clksel         = omap343x_gpt_clksel,
1333         .flags          = CLOCK_IN_OMAP343X,
1334         .clkdm          = { .name = "core_l4_clkdm" },
1335         .recalc         = &omap2_clksel_recalc,
1336 };
1337
1338 static struct clk cpefuse_fck = {
1339         .name           = "cpefuse_fck",
1340         .parent         = &sys_ck,
1341         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1342         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1343         .flags          = CLOCK_IN_OMAP3430ES2,
1344         .clkdm          = { .name = "cm_clkdm" },
1345         .recalc         = &followparent_recalc,
1346 };
1347
1348 static struct clk ts_fck = {
1349         .name           = "ts_fck",
1350         .parent         = &omap_32k_fck,
1351         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1352         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1353         .flags          = CLOCK_IN_OMAP3430ES2,
1354         .clkdm          = { .name = "core_l4_clkdm" },
1355         .recalc         = &followparent_recalc,
1356 };
1357
1358 static struct clk usbtll_fck = {
1359         .name           = "usbtll_fck",
1360         .parent         = &dpll5_m2_ck,
1361         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1362         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1363         .flags          = CLOCK_IN_OMAP3430ES2,
1364         .clkdm          = { .name = "core_l4_clkdm" },
1365         .recalc         = &followparent_recalc,
1366 };
1367
1368 /* CORE 96M FCLK-derived clocks */
1369
1370 static struct clk core_96m_fck = {
1371         .name           = "core_96m_fck",
1372         .parent         = &omap_96m_fck,
1373         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1374                                 PARENT_CONTROLS_CLOCK,
1375         .clkdm          = { .name = "core_l4_clkdm" },
1376         .recalc         = &followparent_recalc,
1377 };
1378
1379 static struct clk mmchs3_fck = {
1380         .name           = "mmchs_fck",
1381         .id             = 3,
1382         .parent         = &core_96m_fck,
1383         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1385         .flags          = CLOCK_IN_OMAP3430ES2,
1386         .clkdm          = { .name = "core_l4_clkdm" },
1387         .recalc         = &followparent_recalc,
1388 };
1389
1390 static struct clk mmchs2_fck = {
1391         .name           = "mmchs_fck",
1392         .id             = 2,
1393         .parent         = &core_96m_fck,
1394         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1395         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1396         .flags          = CLOCK_IN_OMAP343X,
1397         .clkdm          = { .name = "core_l4_clkdm" },
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 static struct clk mspro_fck = {
1402         .name           = "mspro_fck",
1403         .parent         = &core_96m_fck,
1404         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1405         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1406         .flags          = CLOCK_IN_OMAP343X,
1407         .clkdm          = { .name = "core_l4_clkdm" },
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk mmchs1_fck = {
1412         .name           = "mmchs_fck",
1413         .id             = 1,
1414         .parent         = &core_96m_fck,
1415         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1416         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1417         .flags          = CLOCK_IN_OMAP343X,
1418         .clkdm          = { .name = "core_l4_clkdm" },
1419         .recalc         = &followparent_recalc,
1420 };
1421
1422 static struct clk i2c3_fck = {
1423         .name           = "i2c_fck",
1424         .id             = 3,
1425         .parent         = &core_96m_fck,
1426         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1427         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1428         .flags          = CLOCK_IN_OMAP343X,
1429         .clkdm          = { .name = "core_l4_clkdm" },
1430         .recalc         = &followparent_recalc,
1431 };
1432
1433 static struct clk i2c2_fck = {
1434         .name           = "i2c_fck",
1435         .id             = 2,
1436         .parent         = &core_96m_fck,
1437         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1438         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1439         .flags          = CLOCK_IN_OMAP343X,
1440         .clkdm          = { .name = "core_l4_clkdm" },
1441         .recalc         = &followparent_recalc,
1442 };
1443
1444 static struct clk i2c1_fck = {
1445         .name           = "i2c_fck",
1446         .id             = 1,
1447         .parent         = &core_96m_fck,
1448         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1449         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1450         .flags          = CLOCK_IN_OMAP343X,
1451         .clkdm          = { .name = "core_l4_clkdm" },
1452         .recalc         = &followparent_recalc,
1453 };
1454
1455 /*
1456  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1457  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1458  */
1459 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1460         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1461         { .div = 0 }
1462 };
1463
1464 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1465         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1466         { .div = 0 }
1467 };
1468
1469 static const struct clksel mcbsp_15_clksel[] = {
1470         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1471         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1472         { .parent = NULL }
1473 };
1474
1475 static struct clk mcbsp5_src_fck = {
1476         .name           = "mcbsp_src_fck",
1477         .id             = 5,
1478         .init           = &omap2_init_clksel_parent,
1479         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1480         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1481         .clksel         = mcbsp_15_clksel,
1482         .flags          = CLOCK_IN_OMAP343X,
1483         .clkdm          = { .name = "core_l4_clkdm" },
1484         .recalc         = &omap2_clksel_recalc,
1485 };
1486
1487 static struct clk mcbsp5_fck = {
1488         .name           = "mcbsp_fck",
1489         .id             = 5,
1490         .parent         = &mcbsp5_src_fck,
1491         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1492         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1493         .flags          = CLOCK_IN_OMAP343X,
1494         .clkdm          = { .name = "core_l4_clkdm" },
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk mcbsp1_src_fck = {
1499         .name           = "mcbsp_src_fck",
1500         .id             = 1,
1501         .init           = &omap2_init_clksel_parent,
1502         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1503         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1504         .clksel         = mcbsp_15_clksel,
1505         .flags          = CLOCK_IN_OMAP343X,
1506         .clkdm          = { .name = "core_l4_clkdm" },
1507         .recalc         = &omap2_clksel_recalc,
1508 };
1509
1510 static struct clk mcbsp1_fck = {
1511         .name           = "mcbsp_fck",
1512         .id             = 1,
1513         .parent         = &mcbsp1_src_fck,
1514         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1515         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1516         .flags          = CLOCK_IN_OMAP343X,
1517         .clkdm          = { .name = "core_l4_clkdm" },
1518         .recalc         = &followparent_recalc,
1519 };
1520
1521 /* CORE_48M_FCK-derived clocks */
1522
1523 static struct clk core_48m_fck = {
1524         .name           = "core_48m_fck",
1525         .parent         = &omap_48m_fck,
1526         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1527                                 PARENT_CONTROLS_CLOCK,
1528         .clkdm          = { .name = "core_l4_clkdm" },
1529         .recalc         = &followparent_recalc,
1530 };
1531
1532 static struct clk mcspi4_fck = {
1533         .name           = "mcspi_fck",
1534         .id             = 4,
1535         .parent         = &core_48m_fck,
1536         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1538         .flags          = CLOCK_IN_OMAP343X,
1539         .clkdm          = { .name = "core_l4_clkdm" },
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk mcspi3_fck = {
1544         .name           = "mcspi_fck",
1545         .id             = 3,
1546         .parent         = &core_48m_fck,
1547         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1548         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1549         .flags          = CLOCK_IN_OMAP343X,
1550         .clkdm          = { .name = "core_l4_clkdm" },
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk mcspi2_fck = {
1555         .name           = "mcspi_fck",
1556         .id             = 2,
1557         .parent         = &core_48m_fck,
1558         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1560         .flags          = CLOCK_IN_OMAP343X,
1561         .clkdm          = { .name = "core_l4_clkdm" },
1562         .recalc         = &followparent_recalc,
1563 };
1564
1565 static struct clk mcspi1_fck = {
1566         .name           = "mcspi_fck",
1567         .id             = 1,
1568         .parent         = &core_48m_fck,
1569         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1571         .flags          = CLOCK_IN_OMAP343X,
1572         .clkdm          = { .name = "core_l4_clkdm" },
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk uart2_fck = {
1577         .name           = "uart2_fck",
1578         .parent         = &core_48m_fck,
1579         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1580         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1581         .flags          = CLOCK_IN_OMAP343X,
1582         .clkdm          = { .name = "core_l4_clkdm" },
1583         .recalc         = &followparent_recalc,
1584 };
1585
1586 static struct clk uart1_fck = {
1587         .name           = "uart1_fck",
1588         .parent         = &core_48m_fck,
1589         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1591         .flags          = CLOCK_IN_OMAP343X,
1592         .clkdm          = { .name = "core_l4_clkdm" },
1593         .recalc         = &followparent_recalc,
1594 };
1595
1596 static struct clk fshostusb_fck = {
1597         .name           = "fshostusb_fck",
1598         .parent         = &core_48m_fck,
1599         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1601         .flags          = CLOCK_IN_OMAP3430ES1,
1602         .clkdm          = { .name = "core_l4_clkdm" },
1603         .recalc         = &followparent_recalc,
1604 };
1605
1606 /* CORE_12M_FCK based clocks */
1607
1608 static struct clk core_12m_fck = {
1609         .name           = "core_12m_fck",
1610         .parent         = &omap_12m_fck,
1611         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1612                                 PARENT_CONTROLS_CLOCK,
1613         .clkdm          = { .name = "core_l4_clkdm" },
1614         .recalc         = &followparent_recalc,
1615 };
1616
1617 static struct clk hdq_fck = {
1618         .name           = "hdq_fck",
1619         .parent         = &core_12m_fck,
1620         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1621         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1622         .flags          = CLOCK_IN_OMAP343X,
1623         .clkdm          = { .name = "core_l4_clkdm" },
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 /* DPLL3-derived clock */
1628
1629 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1630         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1631         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1632         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1633         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1634         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1635         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1636         { .div = 0 }
1637 };
1638
1639 static const struct clksel ssi_ssr_clksel[] = {
1640         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1641         { .parent = NULL }
1642 };
1643
1644 static struct clk ssi_ssr_fck = {
1645         .name           = "ssi_ssr_fck",
1646         .init           = &omap2_init_clksel_parent,
1647         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1648         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1649         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1650         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1651         .clksel         = ssi_ssr_clksel,
1652         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1653         .clkdm          = { .name = "core_l4_clkdm" },
1654         .recalc         = &omap2_clksel_recalc,
1655 };
1656
1657 static struct clk ssi_sst_fck = {
1658         .name           = "ssi_sst_fck",
1659         .parent         = &ssi_ssr_fck,
1660         .fixed_div      = 2,
1661         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1662         .clkdm          = { .name = "core_l4_clkdm" },
1663         .recalc         = &omap2_fixed_divisor_recalc,
1664 };
1665
1666
1667
1668 /* CORE_L3_ICK based clocks */
1669
1670 /*
1671  * XXX must add clk_enable/clk_disable for these if standard code won't
1672  * handle it
1673  */
1674 static struct clk core_l3_ick = {
1675         .name           = "core_l3_ick",
1676         .parent         = &l3_ick,
1677         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1678                                 PARENT_CONTROLS_CLOCK,
1679         .clkdm          = { .name = "core_l3_clkdm" },
1680         .recalc         = &followparent_recalc,
1681 };
1682
1683 static struct clk hsotgusb_ick = {
1684         .name           = "hsotgusb_ick",
1685         .parent         = &core_l3_ick,
1686         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1687         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1688         .flags          = CLOCK_IN_OMAP343X,
1689         .clkdm          = { .name = "core_l3_clkdm" },
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 static struct clk sdrc_ick = {
1694         .name           = "sdrc_ick",
1695         .parent         = &core_l3_ick,
1696         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1697         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1698         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1699         .clkdm          = { .name = "core_l3_clkdm" },
1700         .recalc         = &followparent_recalc,
1701 };
1702
1703 static struct clk gpmc_fck = {
1704         .name           = "gpmc_fck",
1705         .parent         = &core_l3_ick,
1706         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1707                                 ENABLE_ON_INIT,
1708         .clkdm          = { .name = "core_l3_clkdm" },
1709         .recalc         = &followparent_recalc,
1710 };
1711
1712 /* SECURITY_L3_ICK based clocks */
1713
1714 static struct clk security_l3_ick = {
1715         .name           = "security_l3_ick",
1716         .parent         = &l3_ick,
1717         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1718                                 PARENT_CONTROLS_CLOCK,
1719         .clkdm          = { .name = "core_l3_clkdm" },
1720         .recalc         = &followparent_recalc,
1721 };
1722
1723 static struct clk pka_ick = {
1724         .name           = "pka_ick",
1725         .parent         = &security_l3_ick,
1726         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1727         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1728         .flags          = CLOCK_IN_OMAP343X,
1729         .clkdm          = { .name = "core_l3_clkdm" },
1730         .recalc         = &followparent_recalc,
1731 };
1732
1733 /* CORE_L4_ICK based clocks */
1734
1735 static struct clk core_l4_ick = {
1736         .name           = "core_l4_ick",
1737         .parent         = &l4_ick,
1738         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1739                                 PARENT_CONTROLS_CLOCK,
1740         .clkdm          = { .name = "core_l4_clkdm" },
1741         .recalc         = &followparent_recalc,
1742 };
1743
1744 static struct clk usbtll_ick = {
1745         .name           = "usbtll_ick",
1746         .parent         = &core_l4_ick,
1747         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1748         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1749         .flags          = CLOCK_IN_OMAP3430ES2,
1750         .clkdm          = { .name = "core_l4_clkdm" },
1751         .recalc         = &followparent_recalc,
1752 };
1753
1754 static struct clk mmchs3_ick = {
1755         .name           = "mmchs_ick",
1756         .id             = 3,
1757         .parent         = &core_l4_ick,
1758         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1759         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1760         .flags          = CLOCK_IN_OMAP3430ES2,
1761         .clkdm          = { .name = "core_l4_clkdm" },
1762         .recalc         = &followparent_recalc,
1763 };
1764
1765 /* Intersystem Communication Registers - chassis mode only */
1766 static struct clk icr_ick = {
1767         .name           = "icr_ick",
1768         .parent         = &core_l4_ick,
1769         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1770         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1771         .flags          = CLOCK_IN_OMAP343X,
1772         .clkdm          = { .name = "core_l4_clkdm" },
1773         .recalc         = &followparent_recalc,
1774 };
1775
1776 static struct clk aes2_ick = {
1777         .name           = "aes2_ick",
1778         .parent         = &core_l4_ick,
1779         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1780         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1781         .flags          = CLOCK_IN_OMAP343X,
1782         .clkdm          = { .name = "core_l4_clkdm" },
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk sha12_ick = {
1787         .name           = "sha12_ick",
1788         .parent         = &core_l4_ick,
1789         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1790         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1791         .flags          = CLOCK_IN_OMAP343X,
1792         .clkdm          = { .name = "core_l4_clkdm" },
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk des2_ick = {
1797         .name           = "des2_ick",
1798         .parent         = &core_l4_ick,
1799         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1800         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1801         .flags          = CLOCK_IN_OMAP343X,
1802         .clkdm          = { .name = "core_l4_clkdm" },
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mmchs2_ick = {
1807         .name           = "mmchs_ick",
1808         .id             = 2,
1809         .parent         = &core_l4_ick,
1810         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1812         .flags          = CLOCK_IN_OMAP343X,
1813         .clkdm          = { .name = "core_l4_clkdm" },
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk mmchs1_ick = {
1818         .name           = "mmchs_ick",
1819         .id             = 1,
1820         .parent         = &core_l4_ick,
1821         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1822         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1823         .flags          = CLOCK_IN_OMAP343X,
1824         .clkdm          = { .name = "core_l4_clkdm" },
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk mspro_ick = {
1829         .name           = "mspro_ick",
1830         .parent         = &core_l4_ick,
1831         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1833         .flags          = CLOCK_IN_OMAP343X,
1834         .clkdm          = { .name = "core_l4_clkdm" },
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk hdq_ick = {
1839         .name           = "hdq_ick",
1840         .parent         = &core_l4_ick,
1841         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1843         .flags          = CLOCK_IN_OMAP343X,
1844         .clkdm          = { .name = "core_l4_clkdm" },
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcspi4_ick = {
1849         .name           = "mcspi_ick",
1850         .id             = 4,
1851         .parent         = &core_l4_ick,
1852         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1854         .flags          = CLOCK_IN_OMAP343X,
1855         .clkdm          = { .name = "core_l4_clkdm" },
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk mcspi3_ick = {
1860         .name           = "mcspi_ick",
1861         .id             = 3,
1862         .parent         = &core_l4_ick,
1863         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1864         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1865         .flags          = CLOCK_IN_OMAP343X,
1866         .clkdm          = { .name = "core_l4_clkdm" },
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk mcspi2_ick = {
1871         .name           = "mcspi_ick",
1872         .id             = 2,
1873         .parent         = &core_l4_ick,
1874         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1876         .flags          = CLOCK_IN_OMAP343X,
1877         .clkdm          = { .name = "core_l4_clkdm" },
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk mcspi1_ick = {
1882         .name           = "mcspi_ick",
1883         .id             = 1,
1884         .parent         = &core_l4_ick,
1885         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1887         .flags          = CLOCK_IN_OMAP343X,
1888         .clkdm          = { .name = "core_l4_clkdm" },
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk i2c3_ick = {
1893         .name           = "i2c_ick",
1894         .id             = 3,
1895         .parent         = &core_l4_ick,
1896         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1897         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1898         .flags          = CLOCK_IN_OMAP343X,
1899         .clkdm          = { .name = "core_l4_clkdm" },
1900         .recalc         = &followparent_recalc,
1901 };
1902
1903 static struct clk i2c2_ick = {
1904         .name           = "i2c_ick",
1905         .id             = 2,
1906         .parent         = &core_l4_ick,
1907         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1908         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1909         .flags          = CLOCK_IN_OMAP343X,
1910         .clkdm          = { .name = "core_l4_clkdm" },
1911         .recalc         = &followparent_recalc,
1912 };
1913
1914 static struct clk i2c1_ick = {
1915         .name           = "i2c_ick",
1916         .id             = 1,
1917         .parent         = &core_l4_ick,
1918         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1919         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1920         .flags          = CLOCK_IN_OMAP343X,
1921         .clkdm          = { .name = "core_l4_clkdm" },
1922         .recalc         = &followparent_recalc,
1923 };
1924
1925 static struct clk uart2_ick = {
1926         .name           = "uart2_ick",
1927         .parent         = &core_l4_ick,
1928         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1929         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1930         .flags          = CLOCK_IN_OMAP343X,
1931         .clkdm          = { .name = "core_l4_clkdm" },
1932         .recalc         = &followparent_recalc,
1933 };
1934
1935 static struct clk uart1_ick = {
1936         .name           = "uart1_ick",
1937         .parent         = &core_l4_ick,
1938         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1940         .flags          = CLOCK_IN_OMAP343X,
1941         .clkdm          = { .name = "core_l4_clkdm" },
1942         .recalc         = &followparent_recalc,
1943 };
1944
1945 static struct clk gpt11_ick = {
1946         .name           = "gpt11_ick",
1947         .parent         = &core_l4_ick,
1948         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1950         .flags          = CLOCK_IN_OMAP343X,
1951         .clkdm          = { .name = "core_l4_clkdm" },
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk gpt10_ick = {
1956         .name           = "gpt10_ick",
1957         .parent         = &core_l4_ick,
1958         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1959         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1960         .flags          = CLOCK_IN_OMAP343X,
1961         .clkdm          = { .name = "core_l4_clkdm" },
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk mcbsp5_ick = {
1966         .name           = "mcbsp_ick",
1967         .id             = 5,
1968         .parent         = &core_l4_ick,
1969         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1970         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1971         .flags          = CLOCK_IN_OMAP343X,
1972         .clkdm          = { .name = "core_l4_clkdm" },
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk mcbsp1_ick = {
1977         .name           = "mcbsp_ick",
1978         .id             = 1,
1979         .parent         = &core_l4_ick,
1980         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1981         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1982         .flags          = CLOCK_IN_OMAP343X,
1983         .clkdm          = { .name = "core_l4_clkdm" },
1984         .recalc         = &followparent_recalc,
1985 };
1986
1987 static struct clk fac_ick = {
1988         .name           = "fac_ick",
1989         .parent         = &core_l4_ick,
1990         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1991         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1992         .flags          = CLOCK_IN_OMAP3430ES1,
1993         .clkdm          = { .name = "core_l4_clkdm" },
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk mailboxes_ick = {
1998         .name           = "mailboxes_ick",
1999         .parent         = &core_l4_ick,
2000         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2001         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2002         .flags          = CLOCK_IN_OMAP343X,
2003         .clkdm          = { .name = "core_l4_clkdm" },
2004         .recalc         = &followparent_recalc,
2005 };
2006
2007 static struct clk omapctrl_ick = {
2008         .name           = "omapctrl_ick",
2009         .parent         = &core_l4_ick,
2010         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2011         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2012         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2013         .clkdm          = { .name = "core_l4_clkdm" },
2014         .recalc         = &followparent_recalc,
2015 };
2016
2017 /* SSI_L4_ICK based clocks */
2018
2019 static struct clk ssi_l4_ick = {
2020         .name           = "ssi_l4_ick",
2021         .parent         = &l4_ick,
2022         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2023                                 PARENT_CONTROLS_CLOCK,
2024         .clkdm          = { .name = "core_l4_clkdm" },
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 static struct clk ssi_ick = {
2029         .name           = "ssi_ick",
2030         .parent         = &ssi_l4_ick,
2031         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2032         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2033         .flags          = CLOCK_IN_OMAP343X,
2034         .clkdm          = { .name = "core_l4_clkdm" },
2035         .recalc         = &followparent_recalc,
2036 };
2037
2038 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2039  * but l4_ick makes more sense to me */
2040
2041 static const struct clksel usb_l4_clksel[] = {
2042         { .parent = &l4_ick, .rates = div2_rates },
2043         { .parent = NULL },
2044 };
2045
2046 static struct clk usb_l4_ick = {
2047         .name           = "usb_l4_ick",
2048         .parent         = &l4_ick,
2049         .init           = &omap2_init_clksel_parent,
2050         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2051         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2052         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2053         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2054         .clksel         = usb_l4_clksel,
2055         .flags          = CLOCK_IN_OMAP3430ES1,
2056         .clkdm          = { .name = "core_l4_clkdm" },
2057         .recalc         = &omap2_clksel_recalc,
2058 };
2059
2060 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2061
2062 /* SECURITY_L4_ICK2 based clocks */
2063
2064 static struct clk security_l4_ick2 = {
2065         .name           = "security_l4_ick2",
2066         .parent         = &l4_ick,
2067         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2068                                 PARENT_CONTROLS_CLOCK,
2069         .clkdm          = { .name = "core_l4_clkdm" },
2070         .recalc         = &followparent_recalc,
2071 };
2072
2073 static struct clk aes1_ick = {
2074         .name           = "aes1_ick",
2075         .parent         = &security_l4_ick2,
2076         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2077         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2078         .flags          = CLOCK_IN_OMAP343X,
2079         .clkdm          = { .name = "core_l4_clkdm" },
2080         .recalc         = &followparent_recalc,
2081 };
2082
2083 static struct clk rng_ick = {
2084         .name           = "rng_ick",
2085         .parent         = &security_l4_ick2,
2086         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2087         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2088         .flags          = CLOCK_IN_OMAP343X,
2089         .clkdm          = { .name = "core_l4_clkdm" },
2090         .recalc         = &followparent_recalc,
2091 };
2092
2093 static struct clk sha11_ick = {
2094         .name           = "sha11_ick",
2095         .parent         = &security_l4_ick2,
2096         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2097         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2098         .flags          = CLOCK_IN_OMAP343X,
2099         .clkdm          = { .name = "core_l4_clkdm" },
2100         .recalc         = &followparent_recalc,
2101 };
2102
2103 static struct clk des1_ick = {
2104         .name           = "des1_ick",
2105         .parent         = &security_l4_ick2,
2106         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2107         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2108         .flags          = CLOCK_IN_OMAP343X,
2109         .clkdm          = { .name = "core_l4_clkdm" },
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 /* DSS */
2114 static struct clk dss1_alwon_fck = {
2115         .name           = "dss1_alwon_fck",
2116         .parent         = &dpll4_m4x2_ck,
2117         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2118         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2119         .flags          = CLOCK_IN_OMAP343X,
2120         .clkdm          = { .name = "dss_clkdm" },
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 static struct clk dss_tv_fck = {
2125         .name           = "dss_tv_fck",
2126         .parent         = &omap_54m_fck,
2127         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2128         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2129         .flags          = CLOCK_IN_OMAP343X,
2130         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2131         .recalc         = &followparent_recalc,
2132 };
2133
2134 static struct clk dss_96m_fck = {
2135         .name           = "dss_96m_fck",
2136         .parent         = &omap_96m_fck,
2137         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2138         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2139         .flags          = CLOCK_IN_OMAP343X,
2140         .clkdm          = { .name = "dss_clkdm" },
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 static struct clk dss2_alwon_fck = {
2145         .name           = "dss2_alwon_fck",
2146         .parent         = &sys_ck,
2147         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2148         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2149         .flags          = CLOCK_IN_OMAP343X,
2150         .clkdm          = { .name = "dss_clkdm" },
2151         .recalc         = &followparent_recalc,
2152 };
2153
2154 static struct clk dss_ick = {
2155         /* Handles both L3 and L4 clocks */
2156         .name           = "dss_ick",
2157         .parent         = &l4_ick,
2158         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2159         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2160         .flags          = CLOCK_IN_OMAP343X,
2161         .clkdm          = { .name = "dss_clkdm" },
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 /* CAM */
2166
2167 static struct clk cam_mclk = {
2168         .name           = "cam_mclk",
2169         .parent         = &dpll4_m5x2_ck,
2170         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2171         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2172         .flags          = CLOCK_IN_OMAP343X,
2173         .clkdm          = { .name = "cam_clkdm" },
2174         .recalc         = &followparent_recalc,
2175 };
2176
2177 static struct clk cam_ick = {
2178         /* Handles both L3 and L4 clocks */
2179         .name           = "cam_ick",
2180         .parent         = &l4_ick,
2181         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2182         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2183         .flags          = CLOCK_IN_OMAP343X,
2184         .clkdm          = { .name = "cam_clkdm" },
2185         .recalc         = &followparent_recalc,
2186 };
2187
2188 static struct clk csi2_96m_fck = {
2189         .name           = "csi2_96m_fck",
2190         .parent         = &core_96m_fck,
2191         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2192         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2193         .flags          = CLOCK_IN_OMAP343X,
2194         .clkdm          = { .name = "cam_clkdm" },
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 /* USBHOST - 3430ES2 only */
2199
2200 static struct clk usbhost_120m_fck = {
2201         .name           = "usbhost_120m_fck",
2202         .parent         = &dpll5_m2_ck,
2203         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2204         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2205         .flags          = CLOCK_IN_OMAP3430ES2,
2206         .clkdm          = { .name = "usbhost_clkdm" },
2207         .recalc         = &followparent_recalc,
2208 };
2209
2210 static struct clk usbhost_48m_fck = {
2211         .name           = "usbhost_48m_fck",
2212         .parent         = &omap_48m_fck,
2213         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2214         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2215         .flags          = CLOCK_IN_OMAP3430ES2,
2216         .clkdm          = { .name = "usbhost_clkdm" },
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 static struct clk usbhost_ick = {
2221         /* Handles both L3 and L4 clocks */
2222         .name           = "usbhost_ick",
2223         .parent         = &l4_ick,
2224         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2225         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2226         .flags          = CLOCK_IN_OMAP3430ES2,
2227         .clkdm          = { .name = "usbhost_clkdm" },
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 /* WKUP */
2232
2233 static const struct clksel_rate usim_96m_rates[] = {
2234         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2235         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2236         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2237         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2238         { .div = 0 },
2239 };
2240
2241 static const struct clksel_rate usim_120m_rates[] = {
2242         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2243         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2244         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2245         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2246         { .div = 0 },
2247 };
2248
2249 static const struct clksel usim_clksel[] = {
2250         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2251         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2252         { .parent = &sys_ck,            .rates = div2_rates },
2253         { .parent = NULL },
2254 };
2255
2256 /* 3430ES2 only */
2257 static struct clk usim_fck = {
2258         .name           = "usim_fck",
2259         .init           = &omap2_init_clksel_parent,
2260         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2261         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2262         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2263         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2264         .clksel         = usim_clksel,
2265         .flags          = CLOCK_IN_OMAP3430ES2,
2266         .clkdm          = { .name = "prm_clkdm" },
2267         .recalc         = &omap2_clksel_recalc,
2268 };
2269
2270 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2271 static struct clk gpt1_fck = {
2272         .name           = "gpt1_fck",
2273         .init           = &omap2_init_clksel_parent,
2274         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2275         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2276         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2277         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2278         .clksel         = omap343x_gpt_clksel,
2279         .flags          = CLOCK_IN_OMAP343X,
2280         .clkdm          = { .name = "prm_clkdm" },
2281         .recalc         = &omap2_clksel_recalc,
2282 };
2283
2284 static struct clk wkup_32k_fck = {
2285         .name           = "wkup_32k_fck",
2286         .parent         = &omap_32k_fck,
2287         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2288         .clkdm          = { .name = "prm_clkdm" },
2289         .recalc         = &followparent_recalc,
2290 };
2291
2292 static struct clk gpio1_fck = {
2293         .name           = "gpio1_fck",
2294         .parent         = &wkup_32k_fck,
2295         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2296         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2297         .flags          = CLOCK_IN_OMAP343X,
2298         .clkdm          = { .name = "prm_clkdm" },
2299         .recalc         = &followparent_recalc,
2300 };
2301
2302 static struct clk wdt2_fck = {
2303         .name           = "wdt2_fck",
2304         .parent         = &wkup_32k_fck,
2305         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2306         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2307         .flags          = CLOCK_IN_OMAP343X,
2308         .clkdm          = { .name = "prm_clkdm" },
2309         .recalc         = &followparent_recalc,
2310 };
2311
2312 static struct clk wkup_l4_ick = {
2313         .name           = "wkup_l4_ick",
2314         .parent         = &sys_ck,
2315         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2316         .clkdm          = { .name = "prm_clkdm" },
2317         .recalc         = &followparent_recalc,
2318 };
2319
2320 /* 3430ES2 only */
2321 /* Never specifically named in the TRM, so we have to infer a likely name */
2322 static struct clk usim_ick = {
2323         .name           = "usim_ick",
2324         .parent         = &wkup_l4_ick,
2325         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2326         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2327         .flags          = CLOCK_IN_OMAP3430ES2,
2328         .clkdm          = { .name = "prm_clkdm" },
2329         .recalc         = &followparent_recalc,
2330 };
2331
2332 static struct clk wdt2_ick = {
2333         .name           = "wdt2_ick",
2334         .parent         = &wkup_l4_ick,
2335         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2336         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2337         .flags          = CLOCK_IN_OMAP343X,
2338         .clkdm          = { .name = "prm_clkdm" },
2339         .recalc         = &followparent_recalc,
2340 };
2341
2342 static struct clk wdt1_ick = {
2343         .name           = "wdt1_ick",
2344         .parent         = &wkup_l4_ick,
2345         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2346         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2347         .flags          = CLOCK_IN_OMAP343X,
2348         .clkdm          = { .name = "prm_clkdm" },
2349         .recalc         = &followparent_recalc,
2350 };
2351
2352 static struct clk gpio1_ick = {
2353         .name           = "gpio1_ick",
2354         .parent         = &wkup_l4_ick,
2355         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2356         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2357         .flags          = CLOCK_IN_OMAP343X,
2358         .clkdm          = { .name = "prm_clkdm" },
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk omap_32ksync_ick = {
2363         .name           = "omap_32ksync_ick",
2364         .parent         = &wkup_l4_ick,
2365         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2366         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2367         .flags          = CLOCK_IN_OMAP343X,
2368         .clkdm          = { .name = "prm_clkdm" },
2369         .recalc         = &followparent_recalc,
2370 };
2371
2372 static struct clk gpt12_ick = {
2373         .name           = "gpt12_ick",
2374         .parent         = &wkup_l4_ick,
2375         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2376         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2377         .flags          = CLOCK_IN_OMAP343X,
2378         .clkdm          = { .name = "prm_clkdm" },
2379         .recalc         = &followparent_recalc,
2380 };
2381
2382 static struct clk gpt1_ick = {
2383         .name           = "gpt1_ick",
2384         .parent         = &wkup_l4_ick,
2385         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2386         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2387         .flags          = CLOCK_IN_OMAP343X,
2388         .clkdm          = { .name = "prm_clkdm" },
2389         .recalc         = &followparent_recalc,
2390 };
2391
2392
2393
2394 /* PER clock domain */
2395
2396 static struct clk per_96m_fck = {
2397         .name           = "per_96m_fck",
2398         .parent         = &omap_96m_alwon_fck,
2399         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2400                                 PARENT_CONTROLS_CLOCK,
2401         .clkdm          = { .name = "per_clkdm" },
2402         .recalc         = &followparent_recalc,
2403 };
2404
2405 static struct clk per_48m_fck = {
2406         .name           = "per_48m_fck",
2407         .parent         = &omap_48m_fck,
2408         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2409                                 PARENT_CONTROLS_CLOCK,
2410         .clkdm          = { .name = "per_clkdm" },
2411         .recalc         = &followparent_recalc,
2412 };
2413
2414 static struct clk uart3_fck = {
2415         .name           = "uart3_fck",
2416         .parent         = &per_48m_fck,
2417         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2418         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2419         .flags          = CLOCK_IN_OMAP343X,
2420         .clkdm          = { .name = "per_clkdm" },
2421         .recalc         = &followparent_recalc,
2422 };
2423
2424 static struct clk gpt2_fck = {
2425         .name           = "gpt2_fck",
2426         .init           = &omap2_init_clksel_parent,
2427         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2428         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2429         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2430         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2431         .clksel         = omap343x_gpt_clksel,
2432         .flags          = CLOCK_IN_OMAP343X,
2433         .clkdm          = { .name = "per_clkdm" },
2434         .recalc         = &omap2_clksel_recalc,
2435 };
2436
2437 static struct clk gpt3_fck = {
2438         .name           = "gpt3_fck",
2439         .init           = &omap2_init_clksel_parent,
2440         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2441         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2442         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2443         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2444         .clksel         = omap343x_gpt_clksel,
2445         .flags          = CLOCK_IN_OMAP343X,
2446         .clkdm          = { .name = "per_clkdm" },
2447         .recalc         = &omap2_clksel_recalc,
2448 };
2449
2450 static struct clk gpt4_fck = {
2451         .name           = "gpt4_fck",
2452         .init           = &omap2_init_clksel_parent,
2453         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2454         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2455         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2456         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2457         .clksel         = omap343x_gpt_clksel,
2458         .flags          = CLOCK_IN_OMAP343X,
2459         .clkdm          = { .name = "per_clkdm" },
2460         .recalc         = &omap2_clksel_recalc,
2461 };
2462
2463 static struct clk gpt5_fck = {
2464         .name           = "gpt5_fck",
2465         .init           = &omap2_init_clksel_parent,
2466         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2467         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2468         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2469         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2470         .clksel         = omap343x_gpt_clksel,
2471         .flags          = CLOCK_IN_OMAP343X,
2472         .clkdm          = { .name = "per_clkdm" },
2473         .recalc         = &omap2_clksel_recalc,
2474 };
2475
2476 static struct clk gpt6_fck = {
2477         .name           = "gpt6_fck",
2478         .init           = &omap2_init_clksel_parent,
2479         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2480         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2481         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2482         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2483         .clksel         = omap343x_gpt_clksel,
2484         .flags          = CLOCK_IN_OMAP343X,
2485         .clkdm          = { .name = "per_clkdm" },
2486         .recalc         = &omap2_clksel_recalc,
2487 };
2488
2489 static struct clk gpt7_fck = {
2490         .name           = "gpt7_fck",
2491         .init           = &omap2_init_clksel_parent,
2492         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2493         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2494         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2495         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2496         .clksel         = omap343x_gpt_clksel,
2497         .flags          = CLOCK_IN_OMAP343X,
2498         .clkdm          = { .name = "per_clkdm" },
2499         .recalc         = &omap2_clksel_recalc,
2500 };
2501
2502 static struct clk gpt8_fck = {
2503         .name           = "gpt8_fck",
2504         .init           = &omap2_init_clksel_parent,
2505         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2506         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2507         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2508         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2509         .clksel         = omap343x_gpt_clksel,
2510         .flags          = CLOCK_IN_OMAP343X,
2511         .clkdm          = { .name = "per_clkdm" },
2512         .recalc         = &omap2_clksel_recalc,
2513 };
2514
2515 static struct clk gpt9_fck = {
2516         .name           = "gpt9_fck",
2517         .init           = &omap2_init_clksel_parent,
2518         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2519         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2520         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2521         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2522         .clksel         = omap343x_gpt_clksel,
2523         .flags          = CLOCK_IN_OMAP343X,
2524         .clkdm          = { .name = "per_clkdm" },
2525         .recalc         = &omap2_clksel_recalc,
2526 };
2527
2528 static struct clk per_32k_alwon_fck = {
2529         .name           = "per_32k_alwon_fck",
2530         .parent         = &omap_32k_fck,
2531         .clkdm          = { .name = "per_clkdm" },
2532         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2533         .recalc         = &followparent_recalc,
2534 };
2535
2536 static struct clk gpio6_fck = {
2537         .name           = "gpio6_fck",
2538         .parent         = &per_32k_alwon_fck,
2539         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2540         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2541         .flags          = CLOCK_IN_OMAP343X,
2542         .clkdm          = { .name = "per_clkdm" },
2543         .recalc         = &followparent_recalc,
2544 };
2545
2546 static struct clk gpio5_fck = {
2547         .name           = "gpio5_fck",
2548         .parent         = &per_32k_alwon_fck,
2549         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2550         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2551         .flags          = CLOCK_IN_OMAP343X,
2552         .clkdm          = { .name = "per_clkdm" },
2553         .recalc         = &followparent_recalc,
2554 };
2555
2556 static struct clk gpio4_fck = {
2557         .name           = "gpio4_fck",
2558         .parent         = &per_32k_alwon_fck,
2559         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2560         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2561         .flags          = CLOCK_IN_OMAP343X,
2562         .clkdm          = { .name = "per_clkdm" },
2563         .recalc         = &followparent_recalc,
2564 };
2565
2566 static struct clk gpio3_fck = {
2567         .name           = "gpio3_fck",
2568         .parent         = &per_32k_alwon_fck,
2569         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2570         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2571         .flags          = CLOCK_IN_OMAP343X,
2572         .clkdm          = { .name = "per_clkdm" },
2573         .recalc         = &followparent_recalc,
2574 };
2575
2576 static struct clk gpio2_fck = {
2577         .name           = "gpio2_fck",
2578         .parent         = &per_32k_alwon_fck,
2579         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2580         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2581         .flags          = CLOCK_IN_OMAP343X,
2582         .clkdm          = { .name = "per_clkdm" },
2583         .recalc         = &followparent_recalc,
2584 };
2585
2586 static struct clk wdt3_fck = {
2587         .name           = "wdt3_fck",
2588         .parent         = &per_32k_alwon_fck,
2589         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2590         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2591         .flags          = CLOCK_IN_OMAP343X,
2592         .clkdm          = { .name = "per_clkdm" },
2593         .recalc         = &followparent_recalc,
2594 };
2595
2596 static struct clk per_l4_ick = {
2597         .name           = "per_l4_ick",
2598         .parent         = &l4_ick,
2599         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2600                                 PARENT_CONTROLS_CLOCK,
2601         .clkdm          = { .name = "per_clkdm" },
2602         .recalc         = &followparent_recalc,
2603 };
2604
2605 static struct clk gpio6_ick = {
2606         .name           = "gpio6_ick",
2607         .parent         = &per_l4_ick,
2608         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2609         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2610         .flags          = CLOCK_IN_OMAP343X,
2611         .clkdm          = { .name = "per_clkdm" },
2612         .recalc         = &followparent_recalc,
2613 };
2614
2615 static struct clk gpio5_ick = {
2616         .name           = "gpio5_ick",
2617         .parent         = &per_l4_ick,
2618         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2619         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2620         .flags          = CLOCK_IN_OMAP343X,
2621         .clkdm          = { .name = "per_clkdm" },
2622         .recalc         = &followparent_recalc,
2623 };
2624
2625 static struct clk gpio4_ick = {
2626         .name           = "gpio4_ick",
2627         .parent         = &per_l4_ick,
2628         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2629         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2630         .flags          = CLOCK_IN_OMAP343X,
2631         .clkdm          = { .name = "per_clkdm" },
2632         .recalc         = &followparent_recalc,
2633 };
2634
2635 static struct clk gpio3_ick = {
2636         .name           = "gpio3_ick",
2637         .parent         = &per_l4_ick,
2638         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2639         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2640         .flags          = CLOCK_IN_OMAP343X,
2641         .clkdm          = { .name = "per_clkdm" },
2642         .recalc         = &followparent_recalc,
2643 };
2644
2645 static struct clk gpio2_ick = {
2646         .name           = "gpio2_ick",
2647         .parent         = &per_l4_ick,
2648         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2649         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2650         .flags          = CLOCK_IN_OMAP343X,
2651         .clkdm          = { .name = "per_clkdm" },
2652         .recalc         = &followparent_recalc,
2653 };
2654
2655 static struct clk wdt3_ick = {
2656         .name           = "wdt3_ick",
2657         .parent         = &per_l4_ick,
2658         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2659         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2660         .flags          = CLOCK_IN_OMAP343X,
2661         .clkdm          = { .name = "per_clkdm" },
2662         .recalc         = &followparent_recalc,
2663 };
2664
2665 static struct clk uart3_ick = {
2666         .name           = "uart3_ick",
2667         .parent         = &per_l4_ick,
2668         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2669         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2670         .flags          = CLOCK_IN_OMAP343X,
2671         .clkdm          = { .name = "per_clkdm" },
2672         .recalc         = &followparent_recalc,
2673 };
2674
2675 static struct clk gpt9_ick = {
2676         .name           = "gpt9_ick",
2677         .parent         = &per_l4_ick,
2678         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2679         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2680         .flags          = CLOCK_IN_OMAP343X,
2681         .clkdm          = { .name = "per_clkdm" },
2682         .recalc         = &followparent_recalc,
2683 };
2684
2685 static struct clk gpt8_ick = {
2686         .name           = "gpt8_ick",
2687         .parent         = &per_l4_ick,
2688         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2689         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2690         .flags          = CLOCK_IN_OMAP343X,
2691         .clkdm          = { .name = "per_clkdm" },
2692         .recalc         = &followparent_recalc,
2693 };
2694
2695 static struct clk gpt7_ick = {
2696         .name           = "gpt7_ick",
2697         .parent         = &per_l4_ick,
2698         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2699         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2700         .flags          = CLOCK_IN_OMAP343X,
2701         .clkdm          = { .name = "per_clkdm" },
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk gpt6_ick = {
2706         .name           = "gpt6_ick",
2707         .parent         = &per_l4_ick,
2708         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2710         .flags          = CLOCK_IN_OMAP343X,
2711         .clkdm          = { .name = "per_clkdm" },
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk gpt5_ick = {
2716         .name           = "gpt5_ick",
2717         .parent         = &per_l4_ick,
2718         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2720         .flags          = CLOCK_IN_OMAP343X,
2721         .clkdm          = { .name = "per_clkdm" },
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk gpt4_ick = {
2726         .name           = "gpt4_ick",
2727         .parent         = &per_l4_ick,
2728         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2730         .flags          = CLOCK_IN_OMAP343X,
2731         .clkdm          = { .name = "per_clkdm" },
2732         .recalc         = &followparent_recalc,
2733 };
2734
2735 static struct clk gpt3_ick = {
2736         .name           = "gpt3_ick",
2737         .parent         = &per_l4_ick,
2738         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2740         .flags          = CLOCK_IN_OMAP343X,
2741         .clkdm          = { .name = "per_clkdm" },
2742         .recalc         = &followparent_recalc,
2743 };
2744
2745 static struct clk gpt2_ick = {
2746         .name           = "gpt2_ick",
2747         .parent         = &per_l4_ick,
2748         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2750         .flags          = CLOCK_IN_OMAP343X,
2751         .clkdm          = { .name = "per_clkdm" },
2752         .recalc         = &followparent_recalc,
2753 };
2754
2755 static struct clk mcbsp2_ick = {
2756         .name           = "mcbsp_ick",
2757         .id             = 2,
2758         .parent         = &per_l4_ick,
2759         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2760         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2761         .flags          = CLOCK_IN_OMAP343X,
2762         .clkdm          = { .name = "per_clkdm" },
2763         .recalc         = &followparent_recalc,
2764 };
2765
2766 static struct clk mcbsp3_ick = {
2767         .name           = "mcbsp_ick",
2768         .id             = 3,
2769         .parent         = &per_l4_ick,
2770         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2771         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2772         .flags          = CLOCK_IN_OMAP343X,
2773         .clkdm          = { .name = "per_clkdm" },
2774         .recalc         = &followparent_recalc,
2775 };
2776
2777 static struct clk mcbsp4_ick = {
2778         .name           = "mcbsp_ick",
2779         .id             = 4,
2780         .parent         = &per_l4_ick,
2781         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2782         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2783         .flags          = CLOCK_IN_OMAP343X,
2784         .clkdm          = { .name = "per_clkdm" },
2785         .recalc         = &followparent_recalc,
2786 };
2787
2788 static const struct clksel mcbsp_234_clksel[] = {
2789         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2790         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2791         { .parent = NULL }
2792 };
2793
2794 static struct clk mcbsp2_src_fck = {
2795         .name           = "mcbsp_src_fck",
2796         .id             = 2,
2797         .init           = &omap2_init_clksel_parent,
2798         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2799         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2800         .clksel         = mcbsp_234_clksel,
2801         .flags          = CLOCK_IN_OMAP343X,
2802         .clkdm          = { .name = "per_clkdm" },
2803         .recalc         = &omap2_clksel_recalc,
2804 };
2805
2806 static struct clk mcbsp2_fck = {
2807         .name           = "mcbsp_fck",
2808         .id             = 2,
2809         .parent         = &mcbsp2_src_fck,
2810         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2811         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2812         .flags          = CLOCK_IN_OMAP343X,
2813         .clkdm          = { .name = "per_clkdm" },
2814         .recalc         = &omap2_clksel_recalc,
2815 };
2816
2817 static struct clk mcbsp3_src_fck = {
2818         .name           = "mcbsp_src_fck",
2819         .id             = 3,
2820         .init           = &omap2_init_clksel_parent,
2821         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2822         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2823         .clksel         = mcbsp_234_clksel,
2824         .flags          = CLOCK_IN_OMAP343X,
2825         .clkdm          = { .name = "per_clkdm" },
2826         .recalc         = &omap2_clksel_recalc,
2827 };
2828
2829 static struct clk mcbsp3_fck = {
2830         .name           = "mcbsp_fck",
2831         .id             = 3,
2832         .parent         = &mcbsp3_src_fck,
2833         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2834         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2835         .flags          = CLOCK_IN_OMAP343X,
2836         .clkdm          = { .name = "per_clkdm" },
2837         .recalc         = &omap2_clksel_recalc,
2838 };
2839
2840 static struct clk mcbsp4_src_fck = {
2841         .name           = "mcbsp_src_fck",
2842         .id             = 4,
2843         .init           = &omap2_init_clksel_parent,
2844         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2845         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2846         .clksel         = mcbsp_234_clksel,
2847         .flags          = CLOCK_IN_OMAP343X,
2848         .clkdm          = { .name = "per_clkdm" },
2849         .recalc         = &omap2_clksel_recalc,
2850 };
2851
2852 static struct clk mcbsp4_fck = {
2853         .name           = "mcbsp_fck",
2854         .id             = 4,
2855         .parent         = &mcbsp4_src_fck,
2856         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2857         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2858         .flags          = CLOCK_IN_OMAP343X,
2859         .clkdm          = { .name = "per_clkdm" },
2860         .recalc         = &omap2_clksel_recalc,
2861 };
2862
2863 /* EMU clocks */
2864
2865 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2866
2867 static const struct clksel_rate emu_src_sys_rates[] = {
2868         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2869         { .div = 0 },
2870 };
2871
2872 static const struct clksel_rate emu_src_core_rates[] = {
2873         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2874         { .div = 0 },
2875 };
2876
2877 static const struct clksel_rate emu_src_per_rates[] = {
2878         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2879         { .div = 0 },
2880 };
2881
2882 static const struct clksel_rate emu_src_mpu_rates[] = {
2883         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2884         { .div = 0 },
2885 };
2886
2887 static const struct clksel emu_src_clksel[] = {
2888         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2889         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2890         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2891         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2892         { .parent = NULL },
2893 };
2894
2895 /*
2896  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2897  * to switch the source of some of the EMU clocks.
2898  * XXX Are there CLKEN bits for these EMU clks?
2899  */
2900 static struct clk emu_src_ck = {
2901         .name           = "emu_src_ck",
2902         .init           = &omap2_init_clksel_parent,
2903         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2904         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2905         .clksel         = emu_src_clksel,
2906         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2907         .clkdm          = { .name = "emu_clkdm" },
2908         .recalc         = &omap2_clksel_recalc,
2909 };
2910
2911 static const struct clksel_rate pclk_emu_rates[] = {
2912         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2913         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2914         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2915         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2916         { .div = 0 },
2917 };
2918
2919 static const struct clksel pclk_emu_clksel[] = {
2920         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2921         { .parent = NULL },
2922 };
2923
2924 static struct clk pclk_fck = {
2925         .name           = "pclk_fck",
2926         .init           = &omap2_init_clksel_parent,
2927         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2928         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2929         .clksel         = pclk_emu_clksel,
2930         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2931         .clkdm          = { .name = "emu_clkdm" },
2932         .recalc         = &omap2_clksel_recalc,
2933 };
2934
2935 static const struct clksel_rate pclkx2_emu_rates[] = {
2936         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2937         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2938         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2939         { .div = 0 },
2940 };
2941
2942 static const struct clksel pclkx2_emu_clksel[] = {
2943         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2944         { .parent = NULL },
2945 };
2946
2947 static struct clk pclkx2_fck = {
2948         .name           = "pclkx2_fck",
2949         .init           = &omap2_init_clksel_parent,
2950         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2951         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2952         .clksel         = pclkx2_emu_clksel,
2953         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2954         .clkdm          = { .name = "emu_clkdm" },
2955         .recalc         = &omap2_clksel_recalc,
2956 };
2957
2958 static const struct clksel atclk_emu_clksel[] = {
2959         { .parent = &emu_src_ck, .rates = div2_rates },
2960         { .parent = NULL },
2961 };
2962
2963 static struct clk atclk_fck = {
2964         .name           = "atclk_fck",
2965         .init           = &omap2_init_clksel_parent,
2966         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2967         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2968         .clksel         = atclk_emu_clksel,
2969         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2970         .clkdm          = { .name = "emu_clkdm" },
2971         .recalc         = &omap2_clksel_recalc,
2972 };
2973
2974 static struct clk traceclk_src_fck = {
2975         .name           = "traceclk_src_fck",
2976         .init           = &omap2_init_clksel_parent,
2977         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2978         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2979         .clksel         = emu_src_clksel,
2980         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2981         .clkdm          = { .name = "emu_clkdm" },
2982         .recalc         = &omap2_clksel_recalc,
2983 };
2984
2985 static const struct clksel_rate traceclk_rates[] = {
2986         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2987         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2988         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2989         { .div = 0 },
2990 };
2991
2992 static const struct clksel traceclk_clksel[] = {
2993         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2994         { .parent = NULL },
2995 };
2996
2997 static struct clk traceclk_fck = {
2998         .name           = "traceclk_fck",
2999         .init           = &omap2_init_clksel_parent,
3000         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3001         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3002         .clksel         = traceclk_clksel,
3003         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3004         .clkdm          = { .name = "emu_clkdm" },
3005         .recalc         = &omap2_clksel_recalc,
3006 };
3007
3008 /* SR clocks */
3009
3010 /* SmartReflex fclk (VDD1) */
3011 static struct clk sr1_fck = {
3012         .name           = "sr1_fck",
3013         .parent         = &sys_ck,
3014         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3015         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3016         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3017         .clkdm          = { .name = "prm_clkdm" },
3018         .recalc         = &followparent_recalc,
3019 };
3020
3021 /* SmartReflex fclk (VDD2) */
3022 static struct clk sr2_fck = {
3023         .name           = "sr2_fck",
3024         .parent         = &sys_ck,
3025         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3026         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3027         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3028         .clkdm          = { .name = "prm_clkdm" },
3029         .recalc         = &followparent_recalc,
3030 };
3031
3032 static struct clk sr_l4_ick = {
3033         .name           = "sr_l4_ick",
3034         .parent         = &l4_ick,
3035         .flags          = CLOCK_IN_OMAP343X,
3036         .clkdm          = { .name = "core_l4_clkdm" },
3037         .recalc         = &followparent_recalc,
3038 };
3039
3040 /* SECURE_32K_FCK clocks */
3041
3042 /* XXX This clock no longer exists in 3430 TRM rev F */
3043 static struct clk gpt12_fck = {
3044         .name           = "gpt12_fck",
3045         .parent         = &secure_32k_fck,
3046         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3047         .clkdm          = { .name = "prm_clkdm" },
3048         .recalc         = &followparent_recalc,
3049 };
3050
3051 static struct clk wdt1_fck = {
3052         .name           = "wdt1_fck",
3053         .parent         = &secure_32k_fck,
3054         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3055         .clkdm          = { .name = "prm_clkdm" },
3056         .recalc         = &followparent_recalc,
3057 };
3058
3059 static struct clk *onchip_34xx_clks[] __initdata = {
3060         &omap_32k_fck,
3061         &virt_12m_ck,
3062         &virt_13m_ck,
3063         &virt_16_8m_ck,
3064         &virt_19_2m_ck,
3065         &virt_26m_ck,
3066         &virt_38_4m_ck,
3067         &osc_sys_ck,
3068         &sys_ck,
3069         &sys_altclk,
3070         &mcbsp_clks,
3071         &sys_clkout1,
3072         &dpll1_ck,
3073         &dpll1_x2_ck,
3074         &dpll1_x2m2_ck,
3075         &dpll2_ck,
3076         &dpll2_m2_ck,
3077         &dpll3_ck,
3078         &core_ck,
3079         &dpll3_x2_ck,
3080         &dpll3_m2_ck,
3081         &dpll3_m2x2_ck,
3082         &dpll3_m3_ck,
3083         &dpll3_m3x2_ck,
3084         &emu_core_alwon_ck,
3085         &dpll4_ck,
3086         &dpll4_x2_ck,
3087         &omap_96m_alwon_fck,
3088         &omap_96m_fck,
3089         &cm_96m_fck,
3090         &omap_54m_fck,
3091         &omap_48m_fck,
3092         &omap_12m_fck,
3093         &dpll4_m2_ck,
3094         &dpll4_m2x2_ck,
3095         &dpll4_m3_ck,
3096         &dpll4_m3x2_ck,
3097         &dpll4_m4_ck,
3098         &dpll4_m4x2_ck,
3099         &dpll4_m5_ck,
3100         &dpll4_m5x2_ck,
3101         &dpll4_m6_ck,
3102         &dpll4_m6x2_ck,
3103         &emu_per_alwon_ck,
3104         &dpll5_ck,
3105         &dpll5_m2_ck,
3106         &clkout2_src_ck,
3107         &sys_clkout2,
3108         &corex2_fck,
3109         &dpll1_fck,
3110         &mpu_ck,
3111         &arm_fck,
3112         &emu_mpu_alwon_ck,
3113         &dpll2_fck,
3114         &iva2_ck,
3115         &l3_ick,
3116         &l4_ick,
3117         &rm_ick,
3118         &gfx_l3_ck,
3119         &gfx_l3_fck,
3120         &gfx_l3_ick,
3121         &gfx_cg1_ck,
3122         &gfx_cg2_ck,
3123         &sgx_fck,
3124         &sgx_ick,
3125         &d2d_26m_fck,
3126         &gpt10_fck,
3127         &gpt11_fck,
3128         &cpefuse_fck,
3129         &ts_fck,
3130         &usbtll_fck,
3131         &core_96m_fck,
3132         &mmchs3_fck,
3133         &mmchs2_fck,
3134         &mspro_fck,
3135         &mmchs1_fck,
3136         &i2c3_fck,
3137         &i2c2_fck,
3138         &i2c1_fck,
3139         &mcbsp5_src_fck,
3140         &mcbsp5_fck,
3141         &mcbsp1_src_fck,
3142         &mcbsp1_fck,
3143         &core_48m_fck,
3144         &mcspi4_fck,
3145         &mcspi3_fck,
3146         &mcspi2_fck,
3147         &mcspi1_fck,
3148         &uart2_fck,
3149         &uart1_fck,
3150         &fshostusb_fck,
3151         &core_12m_fck,
3152         &hdq_fck,
3153         &ssi_ssr_fck,
3154         &ssi_sst_fck,
3155         &core_l3_ick,
3156         &hsotgusb_ick,
3157         &sdrc_ick,
3158         &gpmc_fck,
3159         &security_l3_ick,
3160         &pka_ick,
3161         &core_l4_ick,
3162         &usbtll_ick,
3163         &mmchs3_ick,
3164         &icr_ick,
3165         &aes2_ick,
3166         &sha12_ick,
3167         &des2_ick,
3168         &mmchs2_ick,
3169         &mmchs1_ick,
3170         &mspro_ick,
3171         &hdq_ick,
3172         &mcspi4_ick,
3173         &mcspi3_ick,
3174         &mcspi2_ick,
3175         &mcspi1_ick,
3176         &i2c3_ick,
3177         &i2c2_ick,
3178         &i2c1_ick,
3179         &uart2_ick,
3180         &uart1_ick,
3181         &gpt11_ick,
3182         &gpt10_ick,
3183         &mcbsp5_ick,
3184         &mcbsp1_ick,
3185         &fac_ick,
3186         &mailboxes_ick,
3187         &omapctrl_ick,
3188         &ssi_l4_ick,
3189         &ssi_ick,
3190         &usb_l4_ick,
3191         &security_l4_ick2,
3192         &aes1_ick,
3193         &rng_ick,
3194         &sha11_ick,
3195         &des1_ick,
3196         &dss1_alwon_fck,
3197         &dss_tv_fck,
3198         &dss_96m_fck,
3199         &dss2_alwon_fck,
3200         &dss_ick,
3201         &cam_mclk,
3202         &cam_ick,
3203         &csi2_96m_fck,
3204         &usbhost_120m_fck,
3205         &usbhost_48m_fck,
3206         &usbhost_ick,
3207         &usim_fck,
3208         &gpt1_fck,
3209         &wkup_32k_fck,
3210         &gpio1_fck,
3211         &wdt2_fck,
3212         &wkup_l4_ick,
3213         &usim_ick,
3214         &wdt2_ick,
3215         &wdt1_ick,
3216         &gpio1_ick,
3217         &omap_32ksync_ick,
3218         &gpt12_ick,
3219         &gpt1_ick,
3220         &per_96m_fck,
3221         &per_48m_fck,
3222         &uart3_fck,
3223         &gpt2_fck,
3224         &gpt3_fck,
3225         &gpt4_fck,
3226         &gpt5_fck,
3227         &gpt6_fck,
3228         &gpt7_fck,
3229         &gpt8_fck,
3230         &gpt9_fck,
3231         &per_32k_alwon_fck,
3232         &gpio6_fck,
3233         &gpio5_fck,
3234         &gpio4_fck,
3235         &gpio3_fck,
3236         &gpio2_fck,
3237         &wdt3_fck,
3238         &per_l4_ick,
3239         &gpio6_ick,
3240         &gpio5_ick,
3241         &gpio4_ick,
3242         &gpio3_ick,
3243         &gpio2_ick,
3244         &wdt3_ick,
3245         &uart3_ick,
3246         &gpt9_ick,
3247         &gpt8_ick,
3248         &gpt7_ick,
3249         &gpt6_ick,
3250         &gpt5_ick,
3251         &gpt4_ick,
3252         &gpt3_ick,
3253         &gpt2_ick,
3254         &mcbsp2_ick,
3255         &mcbsp3_ick,
3256         &mcbsp4_ick,
3257         &mcbsp2_src_fck,
3258         &mcbsp2_fck,
3259         &mcbsp3_src_fck,
3260         &mcbsp3_fck,
3261         &mcbsp4_src_fck,
3262         &mcbsp4_fck,
3263         &emu_src_ck,
3264         &pclk_fck,
3265         &pclkx2_fck,
3266         &atclk_fck,
3267         &traceclk_src_fck,
3268         &traceclk_fck,
3269         &sr1_fck,
3270         &sr2_fck,
3271         &sr_l4_ick,
3272         &secure_32k_fck,
3273         &gpt12_fck,
3274         &wdt1_fck,
3275 };
3276
3277 #endif