arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* Forward declarations for DPLL bypass clocks */
  53 static struct clk dpll1_fck;
  54 static struct clk dpll2_fck;
  55
  56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  57 #define DPLL_LOW_POWER_STOP             0x1
  58 #define DPLL_LOW_POWER_BYPASS           0x5
  59 #define DPLL_LOCKED                     0x7
  60
  61 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  62         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  63
  64 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  65         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  66
  67 #define OMAP3430_PRM_CLKSEL                                             \
  68         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  69
  70 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  71         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  72
  73 /* PRM CLOCKS */
  74
  75 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  76 static struct clk omap_32k_fck = {
  77         .name           = "omap_32k_fck",
  78         .rate           = 32768,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .clkdm          = { .name = "prm_clkdm" },
  82         .recalc         = &propagate_rate,
  83 };
  84
  85 static struct clk secure_32k_fck = {
  86         .name           = "secure_32k_fck",
  87         .rate           = 32768,
  88         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  89                                 ALWAYS_ENABLED,
  90         .clkdm          = { .name = "prm_clkdm" },
  91         .recalc         = &propagate_rate,
  92 };
  93
  94 /* Virtual source clocks for osc_sys_ck */
  95 static struct clk virt_12m_ck = {
  96         .name           = "virt_12m_ck",
  97         .rate           = 12000000,
  98         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  99                                 ALWAYS_ENABLED,
 100         .clkdm          = { .name = "prm_clkdm" },
 101         .recalc         = &propagate_rate,
 102 };
 103
 104 static struct clk virt_13m_ck = {
 105         .name           = "virt_13m_ck",
 106         .rate           = 13000000,
 107         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 108                                 ALWAYS_ENABLED,
 109         .clkdm          = { .name = "prm_clkdm" },
 110         .recalc         = &propagate_rate,
 111 };
 112
 113 static struct clk virt_16_8m_ck = {
 114         .name           = "virt_16_8m_ck",
 115         .rate           = 16800000,
 116         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 117                                 ALWAYS_ENABLED,
 118         .clkdm          = { .name = "prm_clkdm" },
 119         .recalc         = &propagate_rate,
 120 };
 121
 122 static struct clk virt_19_2m_ck = {
 123         .name           = "virt_19_2m_ck",
 124         .rate           = 19200000,
 125         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 126                                 ALWAYS_ENABLED,
 127         .clkdm          = { .name = "prm_clkdm" },
 128         .recalc         = &propagate_rate,
 129 };
 130
 131 static struct clk virt_26m_ck = {
 132         .name           = "virt_26m_ck",
 133         .rate           = 26000000,
 134         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 135                                 ALWAYS_ENABLED,
 136         .clkdm          = { .name = "prm_clkdm" },
 137         .recalc         = &propagate_rate,
 138 };
 139
 140 static struct clk virt_38_4m_ck = {
 141         .name           = "virt_38_4m_ck",
 142         .rate           = 38400000,
 143         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 144                                 ALWAYS_ENABLED,
 145         .clkdm          = { .name = "prm_clkdm" },
 146         .recalc         = &propagate_rate,
 147 };
 148
 149 static const struct clksel_rate osc_sys_12m_rates[] = {
 150         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 151         { .div = 0 }
 152 };
 153
 154 static const struct clksel_rate osc_sys_13m_rates[] = {
 155         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 156         { .div = 0 }
 157 };
 158
 159 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 160         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 161         { .div = 0 }
 162 };
 163
 164 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 165         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 166         { .div = 0 }
 167 };
 168
 169 static const struct clksel_rate osc_sys_26m_rates[] = {
 170         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 171         { .div = 0 }
 172 };
 173
 174 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 175         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 176         { .div = 0 }
 177 };
 178
 179 static const struct clksel osc_sys_clksel[] = {
 180         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 181         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 182         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 183         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 184         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 185         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 186         { .parent = NULL },
 187 };
 188
 189 /* Oscillator clock */
 190 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 191 static struct clk osc_sys_ck = {
 192         .name           = "osc_sys_ck",
 193         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 194         .init           = &omap2_init_clksel_parent,
 195         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 196         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 197         .clksel         = osc_sys_clksel,
 198         /* REVISIT: deal with autoextclkmode? */
 199         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 200                                 ALWAYS_ENABLED,
 201         .clkdm          = { .name = "prm_clkdm" },
 202         .recalc         = &omap2_clksel_recalc,
 203 };
 204
 205 static const struct clksel_rate div2_rates[] = {
 206         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 207         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 208         { .div = 0 }
 209 };
 210
 211 static const struct clksel sys_clksel[] = {
 212         { .parent = &osc_sys_ck, .rates = div2_rates },
 213         { .parent = NULL }
 214 };
 215
 216 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 217 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 218 static struct clk sys_ck = {
 219         .name           = "sys_ck",
 220         .parent         = &osc_sys_ck,
 221         .prcm_mod       = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
 222         .init           = &omap2_init_clksel_parent,
 223         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 224         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 225         .clksel         = sys_clksel,
 226         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 227         .clkdm          = { .name = "prm_clkdm" },
 228         .recalc         = &omap2_clksel_recalc,
 229 };
 230
 231 static struct clk sys_altclk = {
 232         .name           = "sys_altclk",
 233         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 234         .clkdm          = { .name = "cm_clkdm" },
 235         .recalc         = &propagate_rate,
 236 };
 237
 238 /*
 239  * Optional external clock input for some McBSPs
 240  * Apparently this is not really in prm_clkdm, but rather is fed into
 241  * both CORE and PER separately.
 242  */
 243 static struct clk mcbsp_clks = {
 244         .name           = "mcbsp_clks",
 245         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 246         .clkdm          = { .name = "prm_clkdm" },
 247         .recalc         = &propagate_rate,
 248 };
 249
 250 /* PRM EXTERNAL CLOCK OUTPUT */
 251
 252 static struct clk sys_clkout1 = {
 253         .name           = "sys_clkout1",
 254         .parent         = &osc_sys_ck,
 255         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 256         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 257         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 258         .flags          = CLOCK_IN_OMAP343X,
 259         .clkdm          = { .name = "prm_clkdm" },
 260         .recalc         = &followparent_recalc,
 261 };
 262
 263 /* DPLLS */
 264
 265 /* CM CLOCKS */
 266
 267 static const struct clksel_rate div16_dpll_rates[] = {
 268         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 269         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 270         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 271         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 272         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 273         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 274         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 275         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 276         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 277         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 278         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 279         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 280         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 281         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 282         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 283         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 284         { .div = 0 }
 285 };
 286
 287 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 288         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 289
 290 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 291         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 292
 293 /* DPLL1 */
 294 /* MPU clock source */
 295 /* Type: DPLL */
 296 static struct dpll_data dpll1_dd = {
 297         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 298         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 299         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 300         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 301         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 302         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 303         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 304         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 305         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 306         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 307         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 308         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 309         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 310         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 311         .bypass_clk     = &dpll1_fck,
 312         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 313         .max_divider    = OMAP3_MAX_DPLL_DIV,
 314         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 315 };
 316
 317 static struct clk dpll1_ck = {
 318         .name           = "dpll1_ck",
 319         .parent         = &sys_ck,
 320         .prcm_mod       = MPU_MOD,
 321         .dpll_data      = &dpll1_dd,
 322         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 323         .round_rate     = &omap2_dpll_round_rate,
 324         .set_rate       = &omap3_noncore_dpll_set_rate,
 325         .clkdm          = { .name = "dpll1_clkdm" },
 326         .recalc         = &omap3_dpll_recalc,
 327 };
 328
 329 /*
 330  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 331  * DPLL isn't bypassed.
 332  */
 333 static struct clk dpll1_x2_ck = {
 334         .name           = "dpll1_x2_ck",
 335         .parent         = &dpll1_ck,
 336         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 337                                 PARENT_CONTROLS_CLOCK,
 338         .clkdm          = { .name = "dpll1_clkdm" },
 339         .recalc         = &omap3_clkoutx2_recalc,
 340 };
 341
 342 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 343 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 344         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 345         { .parent = NULL }
 346 };
 347
 348 /*
 349  * Does not exist in the TRM - needed to separate the M2 divider from
 350  * bypass selection in mpu_ck
 351  */
 352 static struct clk dpll1_x2m2_ck = {
 353         .name           = "dpll1_x2m2_ck",
 354         .parent         = &dpll1_x2_ck,
 355         .prcm_mod       = MPU_MOD,
 356         .init           = &omap2_init_clksel_parent,
 357         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 358         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 359         .clksel         = div16_dpll1_x2m2_clksel,
 360         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 361                                 PARENT_CONTROLS_CLOCK,
 362         .clkdm          = { .name = "dpll1_clkdm" },
 363         .recalc         = &omap2_clksel_recalc,
 364 };
 365
 366 /* DPLL2 */
 367 /* IVA2 clock source */
 368 /* Type: DPLL */
 369
 370 static struct dpll_data dpll2_dd = {
 371         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 372         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 373         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 374         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 375         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 376         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 377         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 378                                 (1 << DPLL_LOW_POWER_BYPASS),
 379         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 380         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 381         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 382         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 383         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 384         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 385         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 386         .bypass_clk     = &dpll2_fck,
 387         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 388         .max_divider    = OMAP3_MAX_DPLL_DIV,
 389         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 390 };
 391
 392 static struct clk dpll2_ck = {
 393         .name           = "dpll2_ck",
 394         .parent         = &sys_ck,
 395         .prcm_mod       = OMAP3430_IVA2_MOD,
 396         .dpll_data      = &dpll2_dd,
 397         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 398         .enable         = &omap3_noncore_dpll_enable,
 399         .disable        = &omap3_noncore_dpll_disable,
 400         .round_rate     = &omap2_dpll_round_rate,
 401         .set_rate       = &omap3_noncore_dpll_set_rate,
 402         .clkdm          = { .name = "dpll2_clkdm" },
 403         .recalc         = &omap3_dpll_recalc,
 404 };
 405
 406 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 407         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 408         { .parent = NULL }
 409 };
 410
 411 /*
 412  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 413  * or CLKOUTX2. CLKOUT seems most plausible.
 414  */
 415 static struct clk dpll2_m2_ck = {
 416         .name           = "dpll2_m2_ck",
 417         .parent         = &dpll2_ck,
 418         .prcm_mod       = OMAP3430_IVA2_MOD,
 419         .init           = &omap2_init_clksel_parent,
 420         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 421                                           OMAP3430_CM_CLKSEL2_PLL),
 422         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 423         .clksel         = div16_dpll2_m2x2_clksel,
 424         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 425                                 PARENT_CONTROLS_CLOCK,
 426         .clkdm          = { .name = "dpll2_clkdm" },
 427         .recalc         = &omap2_clksel_recalc,
 428 };
 429
 430 /*
 431  * DPLL3
 432  * Source clock for all interfaces and for some device fclks
 433  * REVISIT: Also supports fast relock bypass - not included below
 434  */
 435 static struct dpll_data dpll3_dd = {
 436         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 437         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 438         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 439         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 440         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 441         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 442         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 443         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 444         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 445         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 446         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 447         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 448         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 449         .bypass_clk     = &sys_ck,
 450         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 451         .max_divider    = OMAP3_MAX_DPLL_DIV,
 452         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 453 };
 454
 455 static struct clk dpll3_ck = {
 456         .name           = "dpll3_ck",
 457         .parent         = &sys_ck,
 458         .prcm_mod       = PLL_MOD,
 459         .dpll_data      = &dpll3_dd,
 460         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 461         .round_rate     = &omap2_dpll_round_rate,
 462         .clkdm          = { .name = "dpll3_clkdm" },
 463         .recalc         = &omap3_dpll_recalc,
 464 };
 465
 466 /*
 467  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 468  * DPLL isn't bypassed
 469  */
 470 static struct clk dpll3_x2_ck = {
 471         .name           = "dpll3_x2_ck",
 472         .parent         = &dpll3_ck,
 473         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 474                                 PARENT_CONTROLS_CLOCK,
 475         .clkdm          = { .name = "dpll3_clkdm" },
 476         .recalc         = &omap3_clkoutx2_recalc,
 477 };
 478
 479 static const struct clksel_rate div31_dpll3_rates[] = {
 480         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 481         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 482         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 483         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 484         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 485         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 486         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 487         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 488         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 489         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 490         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 491         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 492         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 493         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 494         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 495         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 496         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 497         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 498         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 499         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 500         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 501         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 502         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 503         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 504         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 505         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 506         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 507         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 508         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 509         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 510         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 511         { .div = 0 },
 512 };
 513
 514 static const struct clksel div31_dpll3m2_clksel[] = {
 515         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 516         { .parent = NULL }
 517 };
 518
 519 /* DPLL3 output M2 - primary control point for CORE speed */
 520 static struct clk dpll3_m2_ck = {
 521         .name           = "dpll3_m2_ck",
 522         .parent         = &dpll3_ck,
 523         .prcm_mod       = PLL_MOD,
 524         .init           = &omap2_init_clksel_parent,
 525         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 526         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 527         .clksel         = div31_dpll3m2_clksel,
 528         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 529                                 PARENT_CONTROLS_CLOCK,
 530         .clkdm          = { .name = "dpll3_clkdm" },
 531         .round_rate     = &omap2_clksel_round_rate,
 532         .set_rate       = &omap3_core_dpll_m2_set_rate,
 533         .recalc         = &omap2_clksel_recalc,
 534 };
 535
 536 static struct clk core_ck = {
 537         .name           = "core_ck",
 538         .parent         = &dpll3_m2_ck,
 539         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 540                                 PARENT_CONTROLS_CLOCK,
 541         .clkdm          = { .name = "cm_clkdm" },
 542         .recalc         = &followparent_recalc,
 543 };
 544
 545 static struct clk dpll3_m2x2_ck = {
 546         .name           = "dpll3_m2x2_ck",
 547         .parent         = &dpll3_x2_ck,
 548         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 549                                 PARENT_CONTROLS_CLOCK,
 550         .clkdm          = { .name = "dpll3_clkdm" },
 551         .recalc         = &followparent_recalc,
 552 };
 553
 554 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 555 static const struct clksel div16_dpll3_clksel[] = {
 556         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 557         { .parent = NULL }
 558 };
 559
 560 /* This virtual clock is the source for dpll3_m3x2_ck */
 561 static struct clk dpll3_m3_ck = {
 562         .name           = "dpll3_m3_ck",
 563         .parent         = &dpll3_ck,
 564         .prcm_mod       = OMAP3430_EMU_MOD,
 565         .init           = &omap2_init_clksel_parent,
 566         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 567         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 568         .clksel         = div16_dpll3_clksel,
 569         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 570                                 PARENT_CONTROLS_CLOCK,
 571         .clkdm          = { .name = "dpll3_clkdm" },
 572         .recalc         = &omap2_clksel_recalc,
 573 };
 574
 575 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 576 static struct clk dpll3_m3x2_ck = {
 577         .name           = "dpll3_m3x2_ck",
 578         .parent         = &dpll3_m3_ck,
 579         .prcm_mod       = PLL_MOD,
 580         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 581         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 582         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 583         .clkdm          = { .name = "dpll3_clkdm" },
 584         .recalc         = &omap3_clkoutx2_recalc,
 585 };
 586
 587 static struct clk emu_core_alwon_ck = {
 588         .name           = "emu_core_alwon_ck",
 589         .parent         = &dpll3_m3x2_ck,
 590         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 591                                 PARENT_CONTROLS_CLOCK,
 592         .clkdm          = { .name = "dpll3_clkdm" },
 593         .recalc         = &followparent_recalc,
 594 };
 595
 596 /* DPLL4 */
 597 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 598 /* Type: DPLL */
 599 static struct dpll_data dpll4_dd = {
 600         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 601         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 602         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 603         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 604         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 605         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 606         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 607         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 608         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 609         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 610         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 611         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 612         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 613         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 614         .bypass_clk     = &sys_ck,
 615         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 616         .max_divider    = OMAP3_MAX_DPLL_DIV,
 617         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 618 };
 619
 620 static struct clk dpll4_ck = {
 621         .name           = "dpll4_ck",
 622         .parent         = &sys_ck,
 623         .prcm_mod       = PLL_MOD,
 624         .dpll_data      = &dpll4_dd,
 625         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 626         .enable         = &omap3_noncore_dpll_enable,
 627         .disable        = &omap3_noncore_dpll_disable,
 628         .round_rate     = &omap2_dpll_round_rate,
 629         .set_rate       = &omap3_noncore_dpll_set_rate,
 630         .clkdm          = { .name = "dpll4_clkdm" },
 631         .recalc         = &omap3_dpll_recalc,
 632 };
 633
 634 /*
 635  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 636  * DPLL isn't bypassed --
 637  * XXX does this serve any downstream clocks?
 638  */
 639 static struct clk dpll4_x2_ck = {
 640         .name           = "dpll4_x2_ck",
 641         .parent         = &dpll4_ck,
 642         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 643                                 PARENT_CONTROLS_CLOCK,
 644         .clkdm          = { .name = "dpll4_clkdm" },
 645         .recalc         = &omap3_clkoutx2_recalc,
 646 };
 647
 648 static const struct clksel div16_dpll4_clksel[] = {
 649         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 650         { .parent = NULL }
 651 };
 652
 653 /* This virtual clock is the source for dpll4_m2x2_ck */
 654 static struct clk dpll4_m2_ck = {
 655         .name           = "dpll4_m2_ck",
 656         .parent         = &dpll4_ck,
 657         .prcm_mod       = PLL_MOD,
 658         .init           = &omap2_init_clksel_parent,
 659         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 660         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 661         .clksel         = div16_dpll4_clksel,
 662         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 663                                 PARENT_CONTROLS_CLOCK,
 664         .clkdm          = { .name = "dpll4_clkdm" },
 665         .recalc         = &omap2_clksel_recalc,
 666 };
 667
 668 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 669 static struct clk dpll4_m2x2_ck = {
 670         .name           = "dpll4_m2x2_ck",
 671         .parent         = &dpll4_m2_ck,
 672         .prcm_mod       = PLL_MOD,
 673         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 674         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 675         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 676         .clkdm          = { .name = "dpll4_clkdm" },
 677         .recalc         = &omap3_clkoutx2_recalc,
 678 };
 679
 680 /*
 681  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 682  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 683  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 684  * CM_96K_(F)CLK.
 685  */
 686 static struct clk omap_96m_alwon_fck = {
 687         .name           = "omap_96m_alwon_fck",
 688         .parent         = &dpll4_m2x2_ck,
 689         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 690                                 PARENT_CONTROLS_CLOCK,
 691         .clkdm          = { .name = "prm_clkdm" },
 692         .recalc         = &followparent_recalc,
 693 };
 694
 695 static struct clk cm_96m_fck = {
 696         .name           = "cm_96m_fck",
 697         .parent         = &omap_96m_alwon_fck,
 698         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 699                                 PARENT_CONTROLS_CLOCK,
 700         .clkdm          = { .name = "cm_clkdm" },
 701         .recalc         = &followparent_recalc,
 702 };
 703
 704 static const struct clksel_rate omap_96m_dpll_rates[] = {
 705         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 706         { .div = 0 }
 707 };
 708
 709 static const struct clksel_rate omap_96m_sys_rates[] = {
 710         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 711         { .div = 0 }
 712 };
 713
 714 static const struct clksel omap_96m_fck_clksel[] = {
 715         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 716         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 717         { .parent = NULL }
 718 };
 719
 720 static struct clk omap_96m_fck = {
 721         .name           = "omap_96m_fck",
 722         .parent         = &sys_ck,
 723         .prcm_mod       = PLL_MOD,
 724         .init           = &omap2_init_clksel_parent,
 725         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 726         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 727         .clksel         = omap_96m_fck_clksel,
 728         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 729                                 PARENT_CONTROLS_CLOCK,
 730         .clkdm          = { .name = "cm_clkdm" },
 731         .recalc         = &omap2_clksel_recalc,
 732 };
 733
 734 /* This virtual clock is the source for dpll4_m3x2_ck */
 735 static struct clk dpll4_m3_ck = {
 736         .name           = "dpll4_m3_ck",
 737         .parent         = &dpll4_ck,
 738         .prcm_mod       = OMAP3430_DSS_MOD,
 739         .init           = &omap2_init_clksel_parent,
 740         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 741         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 742         .clksel         = div16_dpll4_clksel,
 743         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 744                                 PARENT_CONTROLS_CLOCK,
 745         .clkdm          = { .name = "dpll4_clkdm" },
 746         .recalc         = &omap2_clksel_recalc,
 747 };
 748
 749 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 750 static struct clk dpll4_m3x2_ck = {
 751         .name           = "dpll4_m3x2_ck",
 752         .parent         = &dpll4_m3_ck,
 753         .prcm_mod       = PLL_MOD,
 754         .init           = &omap2_init_clksel_parent,
 755         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 756         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 757         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 758         .clkdm          = { .name = "dpll4_clkdm" },
 759         .recalc         = &omap3_clkoutx2_recalc,
 760 };
 761
 762 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 763         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 764         { .div = 0 }
 765 };
 766
 767 static const struct clksel_rate omap_54m_alt_rates[] = {
 768         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 769         { .div = 0 }
 770 };
 771
 772 static const struct clksel omap_54m_clksel[] = {
 773         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 774         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 775         { .parent = NULL }
 776 };
 777
 778 static struct clk omap_54m_fck = {
 779         .name           = "omap_54m_fck",
 780         .prcm_mod       = PLL_MOD,
 781         .init           = &omap2_init_clksel_parent,
 782         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 783         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 784         .clksel         = omap_54m_clksel,
 785         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 786                                 PARENT_CONTROLS_CLOCK,
 787         .clkdm          = { .name = "cm_clkdm" },
 788         .recalc         = &omap2_clksel_recalc,
 789 };
 790
 791 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 792         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 793         { .div = 0 }
 794 };
 795
 796 static const struct clksel_rate omap_48m_alt_rates[] = {
 797         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 798         { .div = 0 }
 799 };
 800
 801 static const struct clksel omap_48m_clksel[] = {
 802         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 803         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 804         { .parent = NULL }
 805 };
 806
 807 static struct clk omap_48m_fck = {
 808         .name           = "omap_48m_fck",
 809         .prcm_mod       = PLL_MOD,
 810         .init           = &omap2_init_clksel_parent,
 811         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 812         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 813         .clksel         = omap_48m_clksel,
 814         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 815                                 PARENT_CONTROLS_CLOCK,
 816         .clkdm          = { .name = "cm_clkdm" },
 817         .recalc         = &omap2_clksel_recalc,
 818 };
 819
 820 static struct clk omap_12m_fck = {
 821         .name           = "omap_12m_fck",
 822         .parent         = &omap_48m_fck,
 823         .fixed_div      = 4,
 824         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 825                                 PARENT_CONTROLS_CLOCK,
 826         .clkdm          = { .name = "cm_clkdm" },
 827         .recalc         = &omap2_fixed_divisor_recalc,
 828 };
 829
 830 /* This virstual clock is the source for dpll4_m4x2_ck */
 831 static struct clk dpll4_m4_ck = {
 832         .name           = "dpll4_m4_ck",
 833         .parent         = &dpll4_ck,
 834         .prcm_mod       = OMAP3430_DSS_MOD,
 835         .init           = &omap2_init_clksel_parent,
 836         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 837         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 838         .clksel         = div16_dpll4_clksel,
 839         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 840                                 PARENT_CONTROLS_CLOCK,
 841         .clkdm          = { .name = "dpll4_clkdm" },
 842         .recalc         = &omap2_clksel_recalc,
 843 };
 844
 845 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 846 static struct clk dpll4_m4x2_ck = {
 847         .name           = "dpll4_m4x2_ck",
 848         .parent         = &dpll4_m4_ck,
 849         .prcm_mod       = PLL_MOD,
 850         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 851         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 852         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 853         .clkdm          = { .name = "dpll4_clkdm" },
 854         .recalc         = &omap3_clkoutx2_recalc,
 855 };
 856
 857 /* This virtual clock is the source for dpll4_m5x2_ck */
 858 static struct clk dpll4_m5_ck = {
 859         .name           = "dpll4_m5_ck",
 860         .parent         = &dpll4_ck,
 861         .prcm_mod       = OMAP3430_CAM_MOD,
 862         .init           = &omap2_init_clksel_parent,
 863         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 864         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 865         .clksel         = div16_dpll4_clksel,
 866         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 867                                 PARENT_CONTROLS_CLOCK,
 868         .clkdm          = { .name = "dpll4_clkdm" },
 869         .recalc         = &omap2_clksel_recalc,
 870 };
 871
 872 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 873 static struct clk dpll4_m5x2_ck = {
 874         .name           = "dpll4_m5x2_ck",
 875         .parent         = &dpll4_m5_ck,
 876         .prcm_mod       = PLL_MOD,
 877         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 878         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 879         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 880         .clkdm          = { .name = "dpll4_clkdm" },
 881         .recalc         = &omap3_clkoutx2_recalc,
 882 };
 883
 884 /* This virtual clock is the source for dpll4_m6x2_ck */
 885 static struct clk dpll4_m6_ck = {
 886         .name           = "dpll4_m6_ck",
 887         .parent         = &dpll4_ck,
 888         .prcm_mod       = OMAP3430_EMU_MOD,
 889         .init           = &omap2_init_clksel_parent,
 890         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 891         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 892         .clksel         = div16_dpll4_clksel,
 893         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 894                                 PARENT_CONTROLS_CLOCK,
 895         .clkdm          = { .name = "dpll4_clkdm" },
 896         .recalc         = &omap2_clksel_recalc,
 897 };
 898
 899 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 900 static struct clk dpll4_m6x2_ck = {
 901         .name           = "dpll4_m6x2_ck",
 902         .parent         = &dpll4_m6_ck,
 903         .prcm_mod       = PLL_MOD,
 904         .init           = &omap2_init_clksel_parent,
 905         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 906         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 907         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 908         .clkdm          = { .name = "dpll4_clkdm" },
 909         .recalc         = &omap3_clkoutx2_recalc,
 910 };
 911
 912 static struct clk emu_per_alwon_ck = {
 913         .name           = "emu_per_alwon_ck",
 914         .parent         = &dpll4_m6x2_ck,
 915         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 916                                 PARENT_CONTROLS_CLOCK,
 917         .clkdm          = { .name = "dpll4_clkdm" },
 918         .recalc         = &followparent_recalc,
 919 };
 920
 921 /* DPLL5 */
 922 /* Supplies 120MHz clock, USIM source clock */
 923 /* Type: DPLL */
 924 /* 3430ES2 only */
 925 static struct dpll_data dpll5_dd = {
 926         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 927         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 928         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 929         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 930         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 931         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 932         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 933         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 934         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 935         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 936         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 937         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 938         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 939         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 940         .bypass_clk     = &sys_ck,
 941         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 942         .max_divider    = OMAP3_MAX_DPLL_DIV,
 943         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 944 };
 945
 946 static struct clk dpll5_ck = {
 947         .name           = "dpll5_ck",
 948         .parent         = &sys_ck,
 949         .prcm_mod       = PLL_MOD,
 950         .dpll_data      = &dpll5_dd,
 951         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 952         .enable         = &omap3_noncore_dpll_enable,
 953         .disable        = &omap3_noncore_dpll_disable,
 954         .round_rate     = &omap2_dpll_round_rate,
 955         .set_rate       = &omap3_noncore_dpll_set_rate,
 956         .clkdm          = { .name = "dpll5_clkdm" },
 957         .recalc         = &omap3_dpll_recalc,
 958 };
 959
 960 static const struct clksel div16_dpll5_clksel[] = {
 961         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 962         { .parent = NULL }
 963 };
 964
 965 static struct clk dpll5_m2_ck = {
 966         .name           = "dpll5_m2_ck",
 967         .parent         = &dpll5_ck,
 968         .prcm_mod       = PLL_MOD,
 969         .init           = &omap2_init_clksel_parent,
 970         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 971         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 972         .clksel         = div16_dpll5_clksel,
 973         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 974                                 PARENT_CONTROLS_CLOCK,
 975         .clkdm          = { .name = "dpll5_clkdm" },
 976         .recalc         = &omap2_clksel_recalc,
 977 };
 978
 979 /* CM EXTERNAL CLOCK OUTPUTS */
 980
 981 static const struct clksel_rate clkout2_src_core_rates[] = {
 982         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 983         { .div = 0 }
 984 };
 985
 986 static const struct clksel_rate clkout2_src_sys_rates[] = {
 987         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 988         { .div = 0 }
 989 };
 990
 991 static const struct clksel_rate clkout2_src_96m_rates[] = {
 992         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 993         { .div = 0 }
 994 };
 995
 996 static const struct clksel_rate clkout2_src_54m_rates[] = {
 997         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 998         { .div = 0 }
 999 };
1000
1001 static const struct clksel clkout2_src_clksel[] = {
1002         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1003         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1004         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1005         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1006         { .parent = NULL }
1007 };
1008
1009 static struct clk clkout2_src_ck = {
1010         .name           = "clkout2_src_ck",
1011         .prcm_mod       = OMAP3430_CCR_MOD,
1012         .init           = &omap2_init_clksel_parent,
1013         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1014         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1015         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1016         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1017         .clksel         = clkout2_src_clksel,
1018         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1019         .clkdm          = { .name = "cm_clkdm" },
1020         .recalc         = &omap2_clksel_recalc,
1021 };
1022
1023 static const struct clksel_rate sys_clkout2_rates[] = {
1024         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1025         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1026         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1027         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1028         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1029         { .div = 0 },
1030 };
1031
1032 static const struct clksel sys_clkout2_clksel[] = {
1033         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1034         { .parent = NULL },
1035 };
1036
1037 static struct clk sys_clkout2 = {
1038         .name           = "sys_clkout2",
1039         .prcm_mod       = OMAP3430_CCR_MOD,
1040         .init           = &omap2_init_clksel_parent,
1041         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1042         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1043         .clksel         = sys_clkout2_clksel,
1044         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1045         .clkdm          = { .name = "cm_clkdm" },
1046         .recalc         = &omap2_clksel_recalc,
1047 };
1048
1049 /* CM OUTPUT CLOCKS */
1050
1051 static struct clk corex2_fck = {
1052         .name           = "corex2_fck",
1053         .parent         = &dpll3_m2x2_ck,
1054         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1055                                 PARENT_CONTROLS_CLOCK,
1056         .clkdm          = { .name = "cm_clkdm" },
1057         .recalc         = &followparent_recalc,
1058 };
1059
1060 /* DPLL power domain clock controls */
1061
1062 static const struct clksel_rate div4_rates[] = {
1063         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1064         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1065         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1066         { .div = 0 }
1067 };
1068
1069 static const struct clksel div4_core_clksel[] = {
1070         { .parent = &core_ck, .rates = div4_rates },
1071         { .parent = NULL }
1072 };
1073
1074 static struct clk dpll1_fck = {
1075         .name           = "dpll1_fck",
1076         .parent         = &core_ck,
1077         .prcm_mod       = MPU_MOD,
1078         .init           = &omap2_init_clksel_parent,
1079         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1080         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1081         .clksel         = div4_core_clksel,
1082         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1083                                 PARENT_CONTROLS_CLOCK,
1084         .clkdm          = { .name = "cm_clkdm" },
1085         .recalc         = &omap2_clksel_recalc,
1086 };
1087
1088 static struct clk mpu_ck = {
1089         .name           = "mpu_ck",
1090         .parent         = &dpll1_x2m2_ck,
1091         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1092                                 PARENT_CONTROLS_CLOCK,
1093         .clkdm          = { .name = "mpu_clkdm" },
1094         .recalc         = &followparent_recalc,
1095 };
1096
1097 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1098 static const struct clksel_rate arm_fck_rates[] = {
1099         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1100         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1101         { .div = 0 },
1102 };
1103
1104 static const struct clksel arm_fck_clksel[] = {
1105         { .parent = &mpu_ck, .rates = arm_fck_rates },
1106         { .parent = NULL }
1107 };
1108
1109 static struct clk arm_fck = {
1110         .name           = "arm_fck",
1111         .parent         = &mpu_ck,
1112         .prcm_mod       = MPU_MOD,
1113         .init           = &omap2_init_clksel_parent,
1114         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1115         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1116         .clksel         = arm_fck_clksel,
1117         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1118                                 PARENT_CONTROLS_CLOCK,
1119         .clkdm          = { .name = "mpu_clkdm" },
1120         .recalc         = &omap2_clksel_recalc,
1121 };
1122
1123 /* XXX What about neon_clkdm ? */
1124
1125 /*
1126  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1127  * although it is referenced - so this is a guess
1128  */
1129 static struct clk emu_mpu_alwon_ck = {
1130         .name           = "emu_mpu_alwon_ck",
1131         .parent         = &mpu_ck,
1132         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1133                                 PARENT_CONTROLS_CLOCK,
1134         .clkdm          = { .name = "mpu_clkdm" },
1135         .recalc         = &followparent_recalc,
1136 };
1137
1138 static struct clk dpll2_fck = {
1139         .name           = "dpll2_fck",
1140         .parent         = &core_ck,
1141         .prcm_mod       = OMAP3430_IVA2_MOD,
1142         .init           = &omap2_init_clksel_parent,
1143         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1144         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1145         .clksel         = div4_core_clksel,
1146         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1147                                 PARENT_CONTROLS_CLOCK,
1148         .clkdm          = { .name = "cm_clkdm" },
1149         .recalc         = &omap2_clksel_recalc,
1150 };
1151
1152 static struct clk iva2_ck = {
1153         .name           = "iva2_ck",
1154         .parent         = &dpll2_m2_ck,
1155         .prcm_mod       = OMAP3430_IVA2_MOD,
1156         .init           = &omap2_init_clksel_parent,
1157         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1158         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1159         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1160         .clkdm          = { .name = "iva2_clkdm" },
1161         .recalc         = &followparent_recalc,
1162 };
1163
1164 /* Common interface clocks */
1165
1166 static const struct clksel div2_core_clksel[] = {
1167         { .parent = &core_ck, .rates = div2_rates },
1168         { .parent = NULL }
1169 };
1170
1171 static struct clk l3_ick = {
1172         .name           = "l3_ick",
1173         .parent         = &core_ck,
1174         .prcm_mod       = CORE_MOD,
1175         .init           = &omap2_init_clksel_parent,
1176         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1177         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1178         .clksel         = div2_core_clksel,
1179         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1180                                 PARENT_CONTROLS_CLOCK,
1181         .clkdm          = { .name = "core_l3_clkdm" },
1182         .recalc         = &omap2_clksel_recalc,
1183 };
1184
1185 static const struct clksel div2_l3_clksel[] = {
1186         { .parent = &l3_ick, .rates = div2_rates },
1187         { .parent = NULL }
1188 };
1189
1190 static struct clk l4_ick = {
1191         .name           = "l4_ick",
1192         .parent         = &l3_ick,
1193         .prcm_mod       = CORE_MOD,
1194         .init           = &omap2_init_clksel_parent,
1195         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1196         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1197         .clksel         = div2_l3_clksel,
1198         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1199                                 PARENT_CONTROLS_CLOCK,
1200         .clkdm          = { .name = "core_l4_clkdm" },
1201         .recalc         = &omap2_clksel_recalc,
1202
1203 };
1204
1205 static const struct clksel div2_l4_clksel[] = {
1206         { .parent = &l4_ick, .rates = div2_rates },
1207         { .parent = NULL }
1208 };
1209
1210 static struct clk rm_ick = {
1211         .name           = "rm_ick",
1212         .parent         = &l4_ick,
1213         .prcm_mod       = WKUP_MOD,
1214         .init           = &omap2_init_clksel_parent,
1215         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1216         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1217         .clksel         = div2_l4_clksel,
1218         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1219         .clkdm          = { .name = "cm_clkdm" },
1220         .recalc         = &omap2_clksel_recalc,
1221 };
1222
1223 /* GFX power domain */
1224
1225 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1226
1227 static const struct clksel gfx_l3_clksel[] = {
1228         { .parent = &l3_ick, .rates = gfx_l3_rates },
1229         { .parent = NULL }
1230 };
1231
1232 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1233 static struct clk gfx_l3_ck = {
1234         .name           = "gfx_l3_ck",
1235         .parent         = &l3_ick,
1236         .prcm_mod       = GFX_MOD,
1237         .init           = &omap2_init_clksel_parent,
1238         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1239         .enable_bit     = OMAP_EN_GFX_SHIFT,
1240         .flags          = CLOCK_IN_OMAP3430ES1,
1241         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1242         .recalc         = &followparent_recalc,
1243 };
1244
1245 static struct clk gfx_l3_fck = {
1246         .name           = "gfx_l3_fck",
1247         .parent         = &gfx_l3_ck,
1248         .prcm_mod       = GFX_MOD,
1249         .init           = &omap2_init_clksel_parent,
1250         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1251         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1252         .clksel         = gfx_l3_clksel,
1253         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1254                                 PARENT_CONTROLS_CLOCK,
1255         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1256         .recalc         = &omap2_clksel_recalc,
1257 };
1258
1259 static struct clk gfx_l3_ick = {
1260         .name           = "gfx_l3_ick",
1261         .parent         = &gfx_l3_ck,
1262         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1263         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1264         .recalc         = &followparent_recalc,
1265 };
1266
1267 static struct clk gfx_cg1_ck = {
1268         .name           = "gfx_cg1_ck",
1269         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1270         .prcm_mod       = GFX_MOD,
1271         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1272         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1273         .flags          = CLOCK_IN_OMAP3430ES1,
1274         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1275         .recalc         = &followparent_recalc,
1276 };
1277
1278 static struct clk gfx_cg2_ck = {
1279         .name           = "gfx_cg2_ck",
1280         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1281         .prcm_mod       = GFX_MOD,
1282         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1283         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1284         .flags          = CLOCK_IN_OMAP3430ES1,
1285         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1286         .recalc         = &followparent_recalc,
1287 };
1288
1289 /* SGX power domain - 3430ES2 only */
1290
1291 static const struct clksel_rate sgx_core_rates[] = {
1292         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1293         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1294         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1295         { .div = 0 },
1296 };
1297
1298 static const struct clksel_rate sgx_96m_rates[] = {
1299         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1300         { .div = 0 },
1301 };
1302
1303 static const struct clksel sgx_clksel[] = {
1304         { .parent = &core_ck,    .rates = sgx_core_rates },
1305         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1306         { .parent = NULL },
1307 };
1308
1309 static struct clk sgx_fck = {
1310         .name           = "sgx_fck",
1311         .init           = &omap2_init_clksel_parent,
1312         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1313         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1314         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1315         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1316         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1317         .clksel         = sgx_clksel,
1318         .flags          = CLOCK_IN_OMAP3430ES2,
1319         .clkdm          = { .name = "sgx_clkdm" },
1320         .recalc         = &omap2_clksel_recalc,
1321 };
1322
1323 static struct clk sgx_ick = {
1324         .name           = "sgx_ick",
1325         .parent         = &l3_ick,
1326         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1327         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1328         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1329         .flags          = CLOCK_IN_OMAP3430ES2,
1330         .clkdm          = { .name = "sgx_clkdm" },
1331         .recalc         = &followparent_recalc,
1332 };
1333
1334 /* CORE power domain */
1335
1336 static struct clk d2d_26m_fck = {
1337         .name           = "d2d_26m_fck",
1338         .parent         = &sys_ck,
1339         .prcm_mod       = CORE_MOD,
1340         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1341         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1342         .flags          = CLOCK_IN_OMAP3430ES1,
1343         .clkdm          = { .name = "d2d_clkdm" },
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 static const struct clksel omap343x_gpt_clksel[] = {
1348         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1349         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1350         { .parent = NULL}
1351 };
1352
1353 static struct clk gpt10_fck = {
1354         .name           = "gpt10_fck",
1355         .parent         = &sys_ck,
1356         .prcm_mod       = CORE_MOD,
1357         .init           = &omap2_init_clksel_parent,
1358         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1359         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1360         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1361         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1362         .clksel         = omap343x_gpt_clksel,
1363         .flags          = CLOCK_IN_OMAP343X,
1364         .clkdm          = { .name = "core_l4_clkdm" },
1365         .recalc         = &omap2_clksel_recalc,
1366 };
1367
1368 static struct clk gpt11_fck = {
1369         .name           = "gpt11_fck",
1370         .parent         = &sys_ck,
1371         .prcm_mod       = CORE_MOD,
1372         .init           = &omap2_init_clksel_parent,
1373         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1374         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1375         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1376         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1377         .clksel         = omap343x_gpt_clksel,
1378         .flags          = CLOCK_IN_OMAP343X,
1379         .clkdm          = { .name = "core_l4_clkdm" },
1380         .recalc         = &omap2_clksel_recalc,
1381 };
1382
1383 static struct clk cpefuse_fck = {
1384         .name           = "cpefuse_fck",
1385         .parent         = &sys_ck,
1386         .prcm_mod       = CORE_MOD,
1387         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1388         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1389         .flags          = CLOCK_IN_OMAP3430ES2,
1390         .clkdm          = { .name = "cm_clkdm" },
1391         .recalc         = &followparent_recalc,
1392 };
1393
1394 static struct clk ts_fck = {
1395         .name           = "ts_fck",
1396         .parent         = &omap_32k_fck,
1397         .prcm_mod       = CORE_MOD,
1398         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1399         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1400         .flags          = CLOCK_IN_OMAP3430ES2,
1401         .clkdm          = { .name = "core_l4_clkdm" },
1402         .recalc         = &followparent_recalc,
1403 };
1404
1405 static struct clk usbtll_fck = {
1406         .name           = "usbtll_fck",
1407         .parent         = &dpll5_m2_ck,
1408         .prcm_mod       = CORE_MOD,
1409         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1410         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1411         .flags          = CLOCK_IN_OMAP3430ES2,
1412         .clkdm          = { .name = "core_l4_clkdm" },
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 /* CORE 96M FCLK-derived clocks */
1417
1418 static struct clk core_96m_fck = {
1419         .name           = "core_96m_fck",
1420         .parent         = &omap_96m_fck,
1421         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1422                                 PARENT_CONTROLS_CLOCK,
1423         .clkdm          = { .name = "core_l4_clkdm" },
1424         .recalc         = &followparent_recalc,
1425 };
1426
1427 static struct clk mmchs3_fck = {
1428         .name           = "mmchs_fck",
1429         .id             = 3,
1430         .parent         = &core_96m_fck,
1431         .prcm_mod       = CORE_MOD,
1432         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1434         .flags          = CLOCK_IN_OMAP3430ES2,
1435         .clkdm          = { .name = "core_l4_clkdm" },
1436         .recalc         = &followparent_recalc,
1437 };
1438
1439 static struct clk mmchs2_fck = {
1440         .name           = "mmchs_fck",
1441         .id             = 2,
1442         .parent         = &core_96m_fck,
1443         .prcm_mod       = CORE_MOD,
1444         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1445         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1446         .flags          = CLOCK_IN_OMAP343X,
1447         .clkdm          = { .name = "core_l4_clkdm" },
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 static struct clk mspro_fck = {
1452         .name           = "mspro_fck",
1453         .parent         = &core_96m_fck,
1454         .prcm_mod       = CORE_MOD,
1455         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1456         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1457         .flags          = CLOCK_IN_OMAP343X,
1458         .clkdm          = { .name = "core_l4_clkdm" },
1459         .recalc         = &followparent_recalc,
1460 };
1461
1462 static struct clk mmchs1_fck = {
1463         .name           = "mmchs_fck",
1464         .id             = 1,
1465         .parent         = &core_96m_fck,
1466         .prcm_mod       = CORE_MOD,
1467         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1468         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1469         .flags          = CLOCK_IN_OMAP343X,
1470         .clkdm          = { .name = "core_l4_clkdm" },
1471         .recalc         = &followparent_recalc,
1472 };
1473
1474 static struct clk i2c3_fck = {
1475         .name           = "i2c_fck",
1476         .id             = 3,
1477         .parent         = &core_96m_fck,
1478         .prcm_mod       = CORE_MOD,
1479         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1480         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1481         .flags          = CLOCK_IN_OMAP343X,
1482         .clkdm          = { .name = "core_l4_clkdm" },
1483         .recalc         = &followparent_recalc,
1484 };
1485
1486 static struct clk i2c2_fck = {
1487         .name           = "i2c_fck",
1488         .id             = 2,
1489         .parent         = &core_96m_fck,
1490         .prcm_mod       = CORE_MOD,
1491         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1492         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1493         .flags          = CLOCK_IN_OMAP343X,
1494         .clkdm          = { .name = "core_l4_clkdm" },
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk i2c1_fck = {
1499         .name           = "i2c_fck",
1500         .id             = 1,
1501         .parent         = &core_96m_fck,
1502         .prcm_mod       = CORE_MOD,
1503         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1505         .flags          = CLOCK_IN_OMAP343X,
1506         .clkdm          = { .name = "core_l4_clkdm" },
1507         .recalc         = &followparent_recalc,
1508 };
1509
1510 /*
1511  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1512  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1513  */
1514 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1515         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1516         { .div = 0 }
1517 };
1518
1519 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1520         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1521         { .div = 0 }
1522 };
1523
1524 static const struct clksel mcbsp_15_clksel[] = {
1525         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1526         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1527         { .parent = NULL }
1528 };
1529
1530 static struct clk mcbsp5_src_fck = {
1531         .name           = "mcbsp_src_fck",
1532         .id             = 5,
1533         .prcm_mod       = CLK_REG_IN_SCM,
1534         .init           = &omap2_init_clksel_parent,
1535         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1536         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1537         .clksel         = mcbsp_15_clksel,
1538         .flags          = CLOCK_IN_OMAP343X,
1539         .clkdm          = { .name = "core_l4_clkdm" },
1540         .recalc         = &omap2_clksel_recalc,
1541 };
1542
1543 static struct clk mcbsp5_fck = {
1544         .name           = "mcbsp_fck",
1545         .id             = 5,
1546         .parent         = &mcbsp5_src_fck,
1547         .prcm_mod       = CORE_MOD,
1548         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1549         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1550         .flags          = CLOCK_IN_OMAP343X,
1551         .clkdm          = { .name = "core_l4_clkdm" },
1552         .recalc         = &followparent_recalc,
1553 };
1554
1555 static struct clk mcbsp1_src_fck = {
1556         .name           = "mcbsp_src_fck",
1557         .id             = 1,
1558         .prcm_mod       = CLK_REG_IN_SCM,
1559         .init           = &omap2_init_clksel_parent,
1560         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1561         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1562         .clksel         = mcbsp_15_clksel,
1563         .flags          = CLOCK_IN_OMAP343X,
1564         .clkdm          = { .name = "core_l4_clkdm" },
1565         .recalc         = &omap2_clksel_recalc,
1566 };
1567
1568 static struct clk mcbsp1_fck = {
1569         .name           = "mcbsp_fck",
1570         .id             = 1,
1571         .parent         = &mcbsp1_src_fck,
1572         .prcm_mod       = CORE_MOD,
1573         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1574         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1575         .flags          = CLOCK_IN_OMAP343X,
1576         .clkdm          = { .name = "core_l4_clkdm" },
1577         .recalc         = &followparent_recalc,
1578 };
1579
1580 /* CORE_48M_FCK-derived clocks */
1581
1582 static struct clk core_48m_fck = {
1583         .name           = "core_48m_fck",
1584         .parent         = &omap_48m_fck,
1585         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1586                                 PARENT_CONTROLS_CLOCK,
1587         .clkdm          = { .name = "core_l4_clkdm" },
1588         .recalc         = &followparent_recalc,
1589 };
1590
1591 static struct clk mcspi4_fck = {
1592         .name           = "mcspi_fck",
1593         .id             = 4,
1594         .parent         = &core_48m_fck,
1595         .prcm_mod       = CORE_MOD,
1596         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1597         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1598         .flags          = CLOCK_IN_OMAP343X,
1599         .clkdm          = { .name = "core_l4_clkdm" },
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 static struct clk mcspi3_fck = {
1604         .name           = "mcspi_fck",
1605         .id             = 3,
1606         .parent         = &core_48m_fck,
1607         .prcm_mod       = CORE_MOD,
1608         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1610         .flags          = CLOCK_IN_OMAP343X,
1611         .clkdm          = { .name = "core_l4_clkdm" },
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk mcspi2_fck = {
1616         .name           = "mcspi_fck",
1617         .id             = 2,
1618         .parent         = &core_48m_fck,
1619         .prcm_mod       = CORE_MOD,
1620         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1621         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1622         .flags          = CLOCK_IN_OMAP343X,
1623         .clkdm          = { .name = "core_l4_clkdm" },
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk mcspi1_fck = {
1628         .name           = "mcspi_fck",
1629         .id             = 1,
1630         .parent         = &core_48m_fck,
1631         .prcm_mod       = CORE_MOD,
1632         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1633         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1634         .flags          = CLOCK_IN_OMAP343X,
1635         .clkdm          = { .name = "core_l4_clkdm" },
1636         .recalc         = &followparent_recalc,
1637 };
1638
1639 static struct clk uart2_fck = {
1640         .name           = "uart2_fck",
1641         .parent         = &core_48m_fck,
1642         .prcm_mod       = CORE_MOD,
1643         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1645         .flags          = CLOCK_IN_OMAP343X,
1646         .clkdm          = { .name = "core_l4_clkdm" },
1647         .recalc         = &followparent_recalc,
1648 };
1649
1650 static struct clk uart1_fck = {
1651         .name           = "uart1_fck",
1652         .parent         = &core_48m_fck,
1653         .prcm_mod       = CORE_MOD,
1654         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1655         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1656         .flags          = CLOCK_IN_OMAP343X,
1657         .clkdm          = { .name = "core_l4_clkdm" },
1658         .recalc         = &followparent_recalc,
1659 };
1660
1661 static struct clk fshostusb_fck = {
1662         .name           = "fshostusb_fck",
1663         .parent         = &core_48m_fck,
1664         .prcm_mod       = CORE_MOD,
1665         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1666         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1667         .flags          = CLOCK_IN_OMAP3430ES1,
1668         .clkdm          = { .name = "core_l4_clkdm" },
1669         .recalc         = &followparent_recalc,
1670 };
1671
1672 /* CORE_12M_FCK based clocks */
1673
1674 static struct clk core_12m_fck = {
1675         .name           = "core_12m_fck",
1676         .parent         = &omap_12m_fck,
1677         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1678                                 PARENT_CONTROLS_CLOCK,
1679         .clkdm          = { .name = "core_l4_clkdm" },
1680         .recalc         = &followparent_recalc,
1681 };
1682
1683 static struct clk hdq_fck = {
1684         .name           = "hdq_fck",
1685         .parent         = &core_12m_fck,
1686         .prcm_mod       = CORE_MOD,
1687         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1688         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1689         .flags          = CLOCK_IN_OMAP343X,
1690         .clkdm          = { .name = "core_l4_clkdm" },
1691         .recalc         = &followparent_recalc,
1692 };
1693
1694 /* DPLL3-derived clock */
1695
1696 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1697         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1698         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1699         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1700         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1701         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1702         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1703         { .div = 0 }
1704 };
1705
1706 static const struct clksel ssi_ssr_clksel[] = {
1707         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1708         { .parent = NULL }
1709 };
1710
1711 static struct clk ssi_ssr_fck = {
1712         .name           = "ssi_ssr_fck",
1713         .init           = &omap2_init_clksel_parent,
1714         .prcm_mod       = CORE_MOD,
1715         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1716         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1717         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1718         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1719         .clksel         = ssi_ssr_clksel,
1720         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1721         .clkdm          = { .name = "core_l4_clkdm" },
1722         .recalc         = &omap2_clksel_recalc,
1723 };
1724
1725 static struct clk ssi_sst_fck = {
1726         .name           = "ssi_sst_fck",
1727         .parent         = &ssi_ssr_fck,
1728         .fixed_div      = 2,
1729         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1730         .clkdm          = { .name = "core_l4_clkdm" },
1731         .recalc         = &omap2_fixed_divisor_recalc,
1732 };
1733
1734
1735
1736 /* CORE_L3_ICK based clocks */
1737
1738 /*
1739  * XXX must add clk_enable/clk_disable for these if standard code won't
1740  * handle it
1741  */
1742 static struct clk core_l3_ick = {
1743         .name           = "core_l3_ick",
1744         .parent         = &l3_ick,
1745         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1746                                 PARENT_CONTROLS_CLOCK,
1747         .clkdm          = { .name = "core_l3_clkdm" },
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 static struct clk hsotgusb_ick = {
1752         .name           = "hsotgusb_ick",
1753         .parent         = &core_l3_ick,
1754         .prcm_mod       = CORE_MOD,
1755         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1756         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1757         .flags          = CLOCK_IN_OMAP343X,
1758         .clkdm          = { .name = "core_l3_clkdm" },
1759         .recalc         = &followparent_recalc,
1760 };
1761
1762 static struct clk sdrc_ick = {
1763         .name           = "sdrc_ick",
1764         .parent         = &core_l3_ick,
1765         .prcm_mod       = CORE_MOD,
1766         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1767         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1768         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1769         .clkdm          = { .name = "core_l3_clkdm" },
1770         .recalc         = &followparent_recalc,
1771 };
1772
1773 static struct clk gpmc_fck = {
1774         .name           = "gpmc_fck",
1775         .parent         = &core_l3_ick,
1776         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1777                                 ENABLE_ON_INIT,
1778         .clkdm          = { .name = "core_l3_clkdm" },
1779         .recalc         = &followparent_recalc,
1780 };
1781
1782 /* SECURITY_L3_ICK based clocks */
1783
1784 static struct clk security_l3_ick = {
1785         .name           = "security_l3_ick",
1786         .parent         = &l3_ick,
1787         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1788                                 PARENT_CONTROLS_CLOCK,
1789         .clkdm          = { .name = "core_l3_clkdm" },
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk pka_ick = {
1794         .name           = "pka_ick",
1795         .parent         = &security_l3_ick,
1796         .prcm_mod       = CORE_MOD,
1797         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1798         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1799         .flags          = CLOCK_IN_OMAP343X,
1800         .clkdm          = { .name = "core_l3_clkdm" },
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 /* CORE_L4_ICK based clocks */
1805
1806 static struct clk core_l4_ick = {
1807         .name           = "core_l4_ick",
1808         .parent         = &l4_ick,
1809         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1810                                 PARENT_CONTROLS_CLOCK,
1811         .clkdm          = { .name = "core_l4_clkdm" },
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk usbtll_ick = {
1816         .name           = "usbtll_ick",
1817         .parent         = &core_l4_ick,
1818         .prcm_mod       = CORE_MOD,
1819         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1820         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1821         .flags          = CLOCK_IN_OMAP3430ES2,
1822         .clkdm          = { .name = "core_l4_clkdm" },
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mmchs3_ick = {
1827         .name           = "mmchs_ick",
1828         .id             = 3,
1829         .parent         = &core_l4_ick,
1830         .prcm_mod       = CORE_MOD,
1831         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1833         .flags          = CLOCK_IN_OMAP3430ES2,
1834         .clkdm          = { .name = "core_l4_clkdm" },
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 /* Intersystem Communication Registers - chassis mode only */
1839 static struct clk icr_ick = {
1840         .name           = "icr_ick",
1841         .parent         = &core_l4_ick,
1842         .prcm_mod       = CORE_MOD,
1843         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1844         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1845         .flags          = CLOCK_IN_OMAP343X,
1846         .clkdm          = { .name = "core_l4_clkdm" },
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk aes2_ick = {
1851         .name           = "aes2_ick",
1852         .parent         = &core_l4_ick,
1853         .prcm_mod       = CORE_MOD,
1854         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1855         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1856         .flags          = CLOCK_IN_OMAP343X,
1857         .clkdm          = { .name = "core_l4_clkdm" },
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 static struct clk sha12_ick = {
1862         .name           = "sha12_ick",
1863         .parent         = &core_l4_ick,
1864         .prcm_mod       = CORE_MOD,
1865         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1867         .flags          = CLOCK_IN_OMAP343X,
1868         .clkdm          = { .name = "core_l4_clkdm" },
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk des2_ick = {
1873         .name           = "des2_ick",
1874         .parent         = &core_l4_ick,
1875         .prcm_mod       = CORE_MOD,
1876         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1877         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1878         .flags          = CLOCK_IN_OMAP343X,
1879         .clkdm          = { .name = "core_l4_clkdm" },
1880         .recalc         = &followparent_recalc,
1881 };
1882
1883 static struct clk mmchs2_ick = {
1884         .name           = "mmchs_ick",
1885         .id             = 2,
1886         .parent         = &core_l4_ick,
1887         .prcm_mod       = CORE_MOD,
1888         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1889         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1890         .flags          = CLOCK_IN_OMAP343X,
1891         .clkdm          = { .name = "core_l4_clkdm" },
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk mmchs1_ick = {
1896         .name           = "mmchs_ick",
1897         .id             = 1,
1898         .parent         = &core_l4_ick,
1899         .prcm_mod       = CORE_MOD,
1900         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1902         .flags          = CLOCK_IN_OMAP343X,
1903         .clkdm          = { .name = "core_l4_clkdm" },
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mspro_ick = {
1908         .name           = "mspro_ick",
1909         .parent         = &core_l4_ick,
1910         .prcm_mod       = CORE_MOD,
1911         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1913         .flags          = CLOCK_IN_OMAP343X,
1914         .clkdm          = { .name = "core_l4_clkdm" },
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk hdq_ick = {
1919         .name           = "hdq_ick",
1920         .parent         = &core_l4_ick,
1921         .prcm_mod       = CORE_MOD,
1922         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1924         .flags          = CLOCK_IN_OMAP343X,
1925         .clkdm          = { .name = "core_l4_clkdm" },
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk mcspi4_ick = {
1930         .name           = "mcspi_ick",
1931         .id             = 4,
1932         .parent         = &core_l4_ick,
1933         .prcm_mod       = CORE_MOD,
1934         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1935         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1936         .flags          = CLOCK_IN_OMAP343X,
1937         .clkdm          = { .name = "core_l4_clkdm" },
1938         .recalc         = &followparent_recalc,
1939 };
1940
1941 static struct clk mcspi3_ick = {
1942         .name           = "mcspi_ick",
1943         .id             = 3,
1944         .parent         = &core_l4_ick,
1945         .prcm_mod       = CORE_MOD,
1946         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1948         .flags          = CLOCK_IN_OMAP343X,
1949         .clkdm          = { .name = "core_l4_clkdm" },
1950         .recalc         = &followparent_recalc,
1951 };
1952
1953 static struct clk mcspi2_ick = {
1954         .name           = "mcspi_ick",
1955         .id             = 2,
1956         .parent         = &core_l4_ick,
1957         .prcm_mod       = CORE_MOD,
1958         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1959         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1960         .flags          = CLOCK_IN_OMAP343X,
1961         .clkdm          = { .name = "core_l4_clkdm" },
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk mcspi1_ick = {
1966         .name           = "mcspi_ick",
1967         .id             = 1,
1968         .parent         = &core_l4_ick,
1969         .prcm_mod       = CORE_MOD,
1970         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1971         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1972         .flags          = CLOCK_IN_OMAP343X,
1973         .clkdm          = { .name = "core_l4_clkdm" },
1974         .recalc         = &followparent_recalc,
1975 };
1976
1977 static struct clk i2c3_ick = {
1978         .name           = "i2c_ick",
1979         .id             = 3,
1980         .parent         = &core_l4_ick,
1981         .prcm_mod       = CORE_MOD,
1982         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1984         .flags          = CLOCK_IN_OMAP343X,
1985         .clkdm          = { .name = "core_l4_clkdm" },
1986         .recalc         = &followparent_recalc,
1987 };
1988
1989 static struct clk i2c2_ick = {
1990         .name           = "i2c_ick",
1991         .id             = 2,
1992         .parent         = &core_l4_ick,
1993         .prcm_mod       = CORE_MOD,
1994         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1995         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1996         .flags          = CLOCK_IN_OMAP343X,
1997         .clkdm          = { .name = "core_l4_clkdm" },
1998         .recalc         = &followparent_recalc,
1999 };
2000
2001 static struct clk i2c1_ick = {
2002         .name           = "i2c_ick",
2003         .id             = 1,
2004         .parent         = &core_l4_ick,
2005         .prcm_mod       = CORE_MOD,
2006         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2008         .flags          = CLOCK_IN_OMAP343X,
2009         .clkdm          = { .name = "core_l4_clkdm" },
2010         .recalc         = &followparent_recalc,
2011 };
2012
2013 static struct clk uart2_ick = {
2014         .name           = "uart2_ick",
2015         .parent         = &core_l4_ick,
2016         .prcm_mod       = CORE_MOD,
2017         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2018         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2019         .flags          = CLOCK_IN_OMAP343X,
2020         .clkdm          = { .name = "core_l4_clkdm" },
2021         .recalc         = &followparent_recalc,
2022 };
2023
2024 static struct clk uart1_ick = {
2025         .name           = "uart1_ick",
2026         .parent         = &core_l4_ick,
2027         .prcm_mod       = CORE_MOD,
2028         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2029         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2030         .flags          = CLOCK_IN_OMAP343X,
2031         .clkdm          = { .name = "core_l4_clkdm" },
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 static struct clk gpt11_ick = {
2036         .name           = "gpt11_ick",
2037         .parent         = &core_l4_ick,
2038         .prcm_mod       = CORE_MOD,
2039         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2040         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2041         .flags          = CLOCK_IN_OMAP343X,
2042         .clkdm          = { .name = "core_l4_clkdm" },
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static struct clk gpt10_ick = {
2047         .name           = "gpt10_ick",
2048         .parent         = &core_l4_ick,
2049         .prcm_mod       = CORE_MOD,
2050         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2051         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2052         .flags          = CLOCK_IN_OMAP343X,
2053         .clkdm          = { .name = "core_l4_clkdm" },
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk mcbsp5_ick = {
2058         .name           = "mcbsp_ick",
2059         .id             = 5,
2060         .parent         = &core_l4_ick,
2061         .prcm_mod       = CORE_MOD,
2062         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2063         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2064         .flags          = CLOCK_IN_OMAP343X,
2065         .clkdm          = { .name = "core_l4_clkdm" },
2066         .recalc         = &followparent_recalc,
2067 };
2068
2069 static struct clk mcbsp1_ick = {
2070         .name           = "mcbsp_ick",
2071         .id             = 1,
2072         .parent         = &core_l4_ick,
2073         .prcm_mod       = CORE_MOD,
2074         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2075         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2076         .flags          = CLOCK_IN_OMAP343X,
2077         .clkdm          = { .name = "core_l4_clkdm" },
2078         .recalc         = &followparent_recalc,
2079 };
2080
2081 static struct clk fac_ick = {
2082         .name           = "fac_ick",
2083         .parent         = &core_l4_ick,
2084         .prcm_mod       = CORE_MOD,
2085         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2086         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2087         .flags          = CLOCK_IN_OMAP3430ES1,
2088         .clkdm          = { .name = "core_l4_clkdm" },
2089         .recalc         = &followparent_recalc,
2090 };
2091
2092 static struct clk mailboxes_ick = {
2093         .name           = "mailboxes_ick",
2094         .parent         = &core_l4_ick,
2095         .prcm_mod       = CORE_MOD,
2096         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2097         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2098         .flags          = CLOCK_IN_OMAP343X,
2099         .clkdm          = { .name = "core_l4_clkdm" },
2100         .recalc         = &followparent_recalc,
2101 };
2102
2103 static struct clk omapctrl_ick = {
2104         .name           = "omapctrl_ick",
2105         .parent         = &core_l4_ick,
2106         .prcm_mod       = CORE_MOD,
2107         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2108         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2109         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2110         .clkdm          = { .name = "core_l4_clkdm" },
2111         .recalc         = &followparent_recalc,
2112 };
2113
2114 /* SSI_L4_ICK based clocks */
2115
2116 static struct clk ssi_l4_ick = {
2117         .name           = "ssi_l4_ick",
2118         .parent         = &l4_ick,
2119         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2120                                 PARENT_CONTROLS_CLOCK,
2121         .clkdm          = { .name = "core_l4_clkdm" },
2122         .recalc         = &followparent_recalc,
2123 };
2124
2125 static struct clk ssi_ick = {
2126         .name           = "ssi_ick",
2127         .parent         = &ssi_l4_ick,
2128         .prcm_mod       = CORE_MOD,
2129         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2130         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2131         .flags          = CLOCK_IN_OMAP343X,
2132         .clkdm          = { .name = "core_l4_clkdm" },
2133         .recalc         = &followparent_recalc,
2134 };
2135
2136 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2137  * but l4_ick makes more sense to me */
2138
2139 static const struct clksel usb_l4_clksel[] = {
2140         { .parent = &l4_ick, .rates = div2_rates },
2141         { .parent = NULL },
2142 };
2143
2144 static struct clk usb_l4_ick = {
2145         .name           = "usb_l4_ick",
2146         .parent         = &l4_ick,
2147         .prcm_mod       = CORE_MOD,
2148         .init           = &omap2_init_clksel_parent,
2149         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2150         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2151         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2152         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2153         .clksel         = usb_l4_clksel,
2154         .flags          = CLOCK_IN_OMAP3430ES1,
2155         .clkdm          = { .name = "core_l4_clkdm" },
2156         .recalc         = &omap2_clksel_recalc,
2157 };
2158
2159 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2160
2161 /* SECURITY_L4_ICK2 based clocks */
2162
2163 static struct clk security_l4_ick2 = {
2164         .name           = "security_l4_ick2",
2165         .parent         = &l4_ick,
2166         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2167                                 PARENT_CONTROLS_CLOCK,
2168         .clkdm          = { .name = "core_l4_clkdm" },
2169         .recalc         = &followparent_recalc,
2170 };
2171
2172 static struct clk aes1_ick = {
2173         .name           = "aes1_ick",
2174         .parent         = &security_l4_ick2,
2175         .prcm_mod       = CORE_MOD,
2176         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2177         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2178         .flags          = CLOCK_IN_OMAP343X,
2179         .clkdm          = { .name = "core_l4_clkdm" },
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk rng_ick = {
2184         .name           = "rng_ick",
2185         .parent         = &security_l4_ick2,
2186         .prcm_mod       = CORE_MOD,
2187         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2188         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2189         .flags          = CLOCK_IN_OMAP343X,
2190         .clkdm          = { .name = "core_l4_clkdm" },
2191         .recalc         = &followparent_recalc,
2192 };
2193
2194 static struct clk sha11_ick = {
2195         .name           = "sha11_ick",
2196         .parent         = &security_l4_ick2,
2197         .prcm_mod       = CORE_MOD,
2198         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2199         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2200         .flags          = CLOCK_IN_OMAP343X,
2201         .clkdm          = { .name = "core_l4_clkdm" },
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk des1_ick = {
2206         .name           = "des1_ick",
2207         .parent         = &security_l4_ick2,
2208         .prcm_mod       = CORE_MOD,
2209         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2210         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2211         .flags          = CLOCK_IN_OMAP343X,
2212         .clkdm          = { .name = "core_l4_clkdm" },
2213         .recalc         = &followparent_recalc,
2214 };
2215
2216 /* DSS */
2217 static struct clk dss1_alwon_fck = {
2218         .name           = "dss1_alwon_fck",
2219         .parent         = &dpll4_m4x2_ck,
2220         .prcm_mod       = OMAP3430_DSS_MOD,
2221         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2222         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2223         .flags          = CLOCK_IN_OMAP343X,
2224         .clkdm          = { .name = "dss_clkdm" },
2225         .recalc         = &followparent_recalc,
2226 };
2227
2228 static struct clk dss_tv_fck = {
2229         .name           = "dss_tv_fck",
2230         .parent         = &omap_54m_fck,
2231         .prcm_mod       = OMAP3430_DSS_MOD,
2232         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2233         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2234         .flags          = CLOCK_IN_OMAP343X,
2235         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2236         .recalc         = &followparent_recalc,
2237 };
2238
2239 static struct clk dss_96m_fck = {
2240         .name           = "dss_96m_fck",
2241         .parent         = &omap_96m_fck,
2242         .prcm_mod       = OMAP3430_DSS_MOD,
2243         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2244         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2245         .flags          = CLOCK_IN_OMAP343X,
2246         .clkdm          = { .name = "dss_clkdm" },
2247         .recalc         = &followparent_recalc,
2248 };
2249
2250 static struct clk dss2_alwon_fck = {
2251         .name           = "dss2_alwon_fck",
2252         .parent         = &sys_ck,
2253         .prcm_mod       = OMAP3430_DSS_MOD,
2254         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2255         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2256         .flags          = CLOCK_IN_OMAP343X,
2257         .clkdm          = { .name = "dss_clkdm" },
2258         .recalc         = &followparent_recalc,
2259 };
2260
2261 static struct clk dss_ick = {
2262         /* Handles both L3 and L4 clocks */
2263         .name           = "dss_ick",
2264         .parent         = &l4_ick,
2265         .prcm_mod       = OMAP3430_DSS_MOD,
2266         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2267         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2268         .flags          = CLOCK_IN_OMAP343X,
2269         .clkdm          = { .name = "dss_clkdm" },
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 /* CAM */
2274
2275 static struct clk cam_mclk = {
2276         .name           = "cam_mclk",
2277         .parent         = &dpll4_m5x2_ck,
2278         .prcm_mod       = OMAP3430_CAM_MOD,
2279         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2280         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2281         .flags          = CLOCK_IN_OMAP343X,
2282         .clkdm          = { .name = "cam_clkdm" },
2283         .recalc         = &followparent_recalc,
2284 };
2285
2286 static struct clk cam_ick = {
2287         /* Handles both L3 and L4 clocks */
2288         .name           = "cam_ick",
2289         .parent         = &l4_ick,
2290         .prcm_mod       = OMAP3430_CAM_MOD,
2291         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2292         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2293         .flags          = CLOCK_IN_OMAP343X,
2294         .clkdm          = { .name = "cam_clkdm" },
2295         .recalc         = &followparent_recalc,
2296 };
2297
2298 static struct clk csi2_96m_fck = {
2299         .name           = "csi2_96m_fck",
2300         .parent         = &core_96m_fck,
2301         .prcm_mod       = OMAP3430_CAM_MOD,
2302         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2303         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2304         .flags          = CLOCK_IN_OMAP343X,
2305         .clkdm          = { .name = "cam_clkdm" },
2306         .recalc         = &followparent_recalc,
2307 };
2308
2309 /* USBHOST - 3430ES2 only */
2310
2311 static struct clk usbhost_120m_fck = {
2312         .name           = "usbhost_120m_fck",
2313         .parent         = &dpll5_m2_ck,
2314         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2315         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2316         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2317         .flags          = CLOCK_IN_OMAP3430ES2,
2318         .clkdm          = { .name = "usbhost_clkdm" },
2319         .recalc         = &followparent_recalc,
2320 };
2321
2322 static struct clk usbhost_48m_fck = {
2323         .name           = "usbhost_48m_fck",
2324         .parent         = &omap_48m_fck,
2325         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2326         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2327         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2328         .flags          = CLOCK_IN_OMAP3430ES2,
2329         .clkdm          = { .name = "usbhost_clkdm" },
2330         .recalc         = &followparent_recalc,
2331 };
2332
2333 static struct clk usbhost_ick = {
2334         /* Handles both L3 and L4 clocks */
2335         .name           = "usbhost_ick",
2336         .parent         = &l4_ick,
2337         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2338         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2339         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2340         .flags          = CLOCK_IN_OMAP3430ES2,
2341         .clkdm          = { .name = "usbhost_clkdm" },
2342         .recalc         = &followparent_recalc,
2343 };
2344
2345 /* WKUP */
2346
2347 static const struct clksel_rate usim_96m_rates[] = {
2348         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2349         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2350         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2351         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2352         { .div = 0 },
2353 };
2354
2355 static const struct clksel_rate usim_120m_rates[] = {
2356         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2357         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2358         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2359         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2360         { .div = 0 },
2361 };
2362
2363 static const struct clksel usim_clksel[] = {
2364         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2365         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2366         { .parent = &sys_ck,            .rates = div2_rates },
2367         { .parent = NULL },
2368 };
2369
2370 /* 3430ES2 only */
2371 static struct clk usim_fck = {
2372         .name           = "usim_fck",
2373         .prcm_mod       = WKUP_MOD,
2374         .init           = &omap2_init_clksel_parent,
2375         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2376         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2377         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2378         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2379         .clksel         = usim_clksel,
2380         .flags          = CLOCK_IN_OMAP3430ES2,
2381         .clkdm          = { .name = "prm_clkdm" },
2382         .recalc         = &omap2_clksel_recalc,
2383 };
2384
2385 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2386 static struct clk gpt1_fck = {
2387         .name           = "gpt1_fck",
2388         .prcm_mod       = WKUP_MOD,
2389         .init           = &omap2_init_clksel_parent,
2390         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2391         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2392         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2393         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2394         .clksel         = omap343x_gpt_clksel,
2395         .flags          = CLOCK_IN_OMAP343X,
2396         .clkdm          = { .name = "prm_clkdm" },
2397         .recalc         = &omap2_clksel_recalc,
2398 };
2399
2400 static struct clk wkup_32k_fck = {
2401         .name           = "wkup_32k_fck",
2402         .parent         = &omap_32k_fck,
2403         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2404         .clkdm          = { .name = "prm_clkdm" },
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk gpio1_fck = {
2409         .name           = "gpio1_fck",
2410         .parent         = &wkup_32k_fck,
2411         .prcm_mod       = WKUP_MOD,
2412         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2413         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2414         .flags          = CLOCK_IN_OMAP343X,
2415         .clkdm          = { .name = "prm_clkdm" },
2416         .recalc         = &followparent_recalc,
2417 };
2418
2419 static struct clk wdt2_fck = {
2420         .name           = "wdt2_fck",
2421         .parent         = &wkup_32k_fck,
2422         .prcm_mod       = WKUP_MOD,
2423         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2424         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2425         .flags          = CLOCK_IN_OMAP343X,
2426         .clkdm          = { .name = "prm_clkdm" },
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk wkup_l4_ick = {
2431         .name           = "wkup_l4_ick",
2432         .parent         = &sys_ck,
2433         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2434         .clkdm          = { .name = "prm_clkdm" },
2435         .recalc         = &followparent_recalc,
2436 };
2437
2438 /* 3430ES2 only */
2439 /* Never specifically named in the TRM, so we have to infer a likely name */
2440 static struct clk usim_ick = {
2441         .name           = "usim_ick",
2442         .parent         = &wkup_l4_ick,
2443         .prcm_mod       = WKUP_MOD,
2444         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2445         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2446         .flags          = CLOCK_IN_OMAP3430ES2,
2447         .clkdm          = { .name = "prm_clkdm" },
2448         .recalc         = &followparent_recalc,
2449 };
2450
2451 static struct clk wdt2_ick = {
2452         .name           = "wdt2_ick",
2453         .parent         = &wkup_l4_ick,
2454         .prcm_mod       = WKUP_MOD,
2455         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2456         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2457         .flags          = CLOCK_IN_OMAP343X,
2458         .clkdm          = { .name = "prm_clkdm" },
2459         .recalc         = &followparent_recalc,
2460 };
2461
2462 static struct clk wdt1_ick = {
2463         .name           = "wdt1_ick",
2464         .parent         = &wkup_l4_ick,
2465         .prcm_mod       = WKUP_MOD,
2466         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2467         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2468         .flags          = CLOCK_IN_OMAP343X,
2469         .clkdm          = { .name = "prm_clkdm" },
2470         .recalc         = &followparent_recalc,
2471 };
2472
2473 static struct clk gpio1_ick = {
2474         .name           = "gpio1_ick",
2475         .parent         = &wkup_l4_ick,
2476         .prcm_mod       = WKUP_MOD,
2477         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2478         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2479         .flags          = CLOCK_IN_OMAP343X,
2480         .clkdm          = { .name = "prm_clkdm" },
2481         .recalc         = &followparent_recalc,
2482 };
2483
2484 static struct clk omap_32ksync_ick = {
2485         .name           = "omap_32ksync_ick",
2486         .parent         = &wkup_l4_ick,
2487         .prcm_mod       = WKUP_MOD,
2488         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2489         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2490         .flags          = CLOCK_IN_OMAP343X,
2491         .clkdm          = { .name = "prm_clkdm" },
2492         .recalc         = &followparent_recalc,
2493 };
2494
2495 static struct clk gpt12_ick = {
2496         .name           = "gpt12_ick",
2497         .parent         = &wkup_l4_ick,
2498         .prcm_mod       = WKUP_MOD,
2499         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2500         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2501         .flags          = CLOCK_IN_OMAP343X,
2502         .clkdm          = { .name = "prm_clkdm" },
2503         .recalc         = &followparent_recalc,
2504 };
2505
2506 static struct clk gpt1_ick = {
2507         .name           = "gpt1_ick",
2508         .parent         = &wkup_l4_ick,
2509         .prcm_mod       = WKUP_MOD,
2510         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2511         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2512         .flags          = CLOCK_IN_OMAP343X,
2513         .clkdm          = { .name = "prm_clkdm" },
2514         .recalc         = &followparent_recalc,
2515 };
2516
2517
2518
2519 /* PER clock domain */
2520
2521 static struct clk per_96m_fck = {
2522         .name           = "per_96m_fck",
2523         .parent         = &omap_96m_alwon_fck,
2524         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2525                                 PARENT_CONTROLS_CLOCK,
2526         .clkdm          = { .name = "per_clkdm" },
2527         .recalc         = &followparent_recalc,
2528 };
2529
2530 static struct clk per_48m_fck = {
2531         .name           = "per_48m_fck",
2532         .parent         = &omap_48m_fck,
2533         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2534                                 PARENT_CONTROLS_CLOCK,
2535         .clkdm          = { .name = "per_clkdm" },
2536         .recalc         = &followparent_recalc,
2537 };
2538
2539 static struct clk uart3_fck = {
2540         .name           = "uart3_fck",
2541         .parent         = &per_48m_fck,
2542         .prcm_mod       = OMAP3430_PER_MOD,
2543         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2544         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2545         .flags          = CLOCK_IN_OMAP343X,
2546         .clkdm          = { .name = "per_clkdm" },
2547         .recalc         = &followparent_recalc,
2548 };
2549
2550 static struct clk gpt2_fck = {
2551         .name           = "gpt2_fck",
2552         .prcm_mod       = OMAP3430_PER_MOD,
2553         .init           = &omap2_init_clksel_parent,
2554         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2555         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2556         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2557         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2558         .clksel         = omap343x_gpt_clksel,
2559         .flags          = CLOCK_IN_OMAP343X,
2560         .clkdm          = { .name = "per_clkdm" },
2561         .recalc         = &omap2_clksel_recalc,
2562 };
2563
2564 static struct clk gpt3_fck = {
2565         .name           = "gpt3_fck",
2566         .prcm_mod       = OMAP3430_PER_MOD,
2567         .init           = &omap2_init_clksel_parent,
2568         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2569         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2570         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2571         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2572         .clksel         = omap343x_gpt_clksel,
2573         .flags          = CLOCK_IN_OMAP343X,
2574         .clkdm          = { .name = "per_clkdm" },
2575         .recalc         = &omap2_clksel_recalc,
2576 };
2577
2578 static struct clk gpt4_fck = {
2579         .name           = "gpt4_fck",
2580         .prcm_mod       = OMAP3430_PER_MOD,
2581         .init           = &omap2_init_clksel_parent,
2582         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2583         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2584         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2585         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2586         .clksel         = omap343x_gpt_clksel,
2587         .flags          = CLOCK_IN_OMAP343X,
2588         .clkdm          = { .name = "per_clkdm" },
2589         .recalc         = &omap2_clksel_recalc,
2590 };
2591
2592 static struct clk gpt5_fck = {
2593         .name           = "gpt5_fck",
2594         .prcm_mod       = OMAP3430_PER_MOD,
2595         .init           = &omap2_init_clksel_parent,
2596         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2597         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2598         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2599         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2600         .clksel         = omap343x_gpt_clksel,
2601         .flags          = CLOCK_IN_OMAP343X,
2602         .clkdm          = { .name = "per_clkdm" },
2603         .recalc         = &omap2_clksel_recalc,
2604 };
2605
2606 static struct clk gpt6_fck = {
2607         .name           = "gpt6_fck",
2608         .prcm_mod       = OMAP3430_PER_MOD,
2609         .init           = &omap2_init_clksel_parent,
2610         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2611         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2612         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2613         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2614         .clksel         = omap343x_gpt_clksel,
2615         .flags          = CLOCK_IN_OMAP343X,
2616         .clkdm          = { .name = "per_clkdm" },
2617         .recalc         = &omap2_clksel_recalc,
2618 };
2619
2620 static struct clk gpt7_fck = {
2621         .name           = "gpt7_fck",
2622         .prcm_mod       = OMAP3430_PER_MOD,
2623         .init           = &omap2_init_clksel_parent,
2624         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2625         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2626         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2627         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2628         .clksel         = omap343x_gpt_clksel,
2629         .flags          = CLOCK_IN_OMAP343X,
2630         .clkdm          = { .name = "per_clkdm" },
2631         .recalc         = &omap2_clksel_recalc,
2632 };
2633
2634 static struct clk gpt8_fck = {
2635         .name           = "gpt8_fck",
2636         .prcm_mod       = OMAP3430_PER_MOD,
2637         .init           = &omap2_init_clksel_parent,
2638         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2639         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2640         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2641         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2642         .clksel         = omap343x_gpt_clksel,
2643         .flags          = CLOCK_IN_OMAP343X,
2644         .clkdm          = { .name = "per_clkdm" },
2645         .recalc         = &omap2_clksel_recalc,
2646 };
2647
2648 static struct clk gpt9_fck = {
2649         .name           = "gpt9_fck",
2650         .prcm_mod       = OMAP3430_PER_MOD,
2651         .init           = &omap2_init_clksel_parent,
2652         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2653         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2654         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2655         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2656         .clksel         = omap343x_gpt_clksel,
2657         .flags          = CLOCK_IN_OMAP343X,
2658         .clkdm          = { .name = "per_clkdm" },
2659         .recalc         = &omap2_clksel_recalc,
2660 };
2661
2662 static struct clk per_32k_alwon_fck = {
2663         .name           = "per_32k_alwon_fck",
2664         .parent         = &omap_32k_fck,
2665         .clkdm          = { .name = "per_clkdm" },
2666         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2667         .recalc         = &followparent_recalc,
2668 };
2669
2670 static struct clk gpio6_fck = {
2671         .name           = "gpio6_fck",
2672         .parent         = &per_32k_alwon_fck,
2673         .prcm_mod       = OMAP3430_PER_MOD,
2674         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2675         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2676         .flags          = CLOCK_IN_OMAP343X,
2677         .clkdm          = { .name = "per_clkdm" },
2678         .recalc         = &followparent_recalc,
2679 };
2680
2681 static struct clk gpio5_fck = {
2682         .name           = "gpio5_fck",
2683         .parent         = &per_32k_alwon_fck,
2684         .prcm_mod       = OMAP3430_PER_MOD,
2685         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2686         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2687         .flags          = CLOCK_IN_OMAP343X,
2688         .clkdm          = { .name = "per_clkdm" },
2689         .recalc         = &followparent_recalc,
2690 };
2691
2692 static struct clk gpio4_fck = {
2693         .name           = "gpio4_fck",
2694         .parent         = &per_32k_alwon_fck,
2695         .prcm_mod       = OMAP3430_PER_MOD,
2696         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2697         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2698         .flags          = CLOCK_IN_OMAP343X,
2699         .clkdm          = { .name = "per_clkdm" },
2700         .recalc         = &followparent_recalc,
2701 };
2702
2703 static struct clk gpio3_fck = {
2704         .name           = "gpio3_fck",
2705         .parent         = &per_32k_alwon_fck,
2706         .prcm_mod       = OMAP3430_PER_MOD,
2707         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2708         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2709         .flags          = CLOCK_IN_OMAP343X,
2710         .clkdm          = { .name = "per_clkdm" },
2711         .recalc         = &followparent_recalc,
2712 };
2713
2714 static struct clk gpio2_fck = {
2715         .name           = "gpio2_fck",
2716         .parent         = &per_32k_alwon_fck,
2717         .prcm_mod       = OMAP3430_PER_MOD,
2718         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2719         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2720         .flags          = CLOCK_IN_OMAP343X,
2721         .clkdm          = { .name = "per_clkdm" },
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk wdt3_fck = {
2726         .name           = "wdt3_fck",
2727         .parent         = &per_32k_alwon_fck,
2728         .prcm_mod       = OMAP3430_PER_MOD,
2729         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2730         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2731         .flags          = CLOCK_IN_OMAP343X,
2732         .clkdm          = { .name = "per_clkdm" },
2733         .recalc         = &followparent_recalc,
2734 };
2735
2736 static struct clk per_l4_ick = {
2737         .name           = "per_l4_ick",
2738         .parent         = &l4_ick,
2739         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2740                                 PARENT_CONTROLS_CLOCK,
2741         .clkdm          = { .name = "per_clkdm" },
2742         .recalc         = &followparent_recalc,
2743 };
2744
2745 static struct clk gpio6_ick = {
2746         .name           = "gpio6_ick",
2747         .parent         = &per_l4_ick,
2748         .prcm_mod       = OMAP3430_PER_MOD,
2749         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2750         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2751         .flags          = CLOCK_IN_OMAP343X,
2752         .clkdm          = { .name = "per_clkdm" },
2753         .recalc         = &followparent_recalc,
2754 };
2755
2756 static struct clk gpio5_ick = {
2757         .name           = "gpio5_ick",
2758         .parent         = &per_l4_ick,
2759         .prcm_mod       = OMAP3430_PER_MOD,
2760         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2761         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2762         .flags          = CLOCK_IN_OMAP343X,
2763         .clkdm          = { .name = "per_clkdm" },
2764         .recalc         = &followparent_recalc,
2765 };
2766
2767 static struct clk gpio4_ick = {
2768         .name           = "gpio4_ick",
2769         .parent         = &per_l4_ick,
2770         .prcm_mod       = OMAP3430_PER_MOD,
2771         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2772         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2773         .flags          = CLOCK_IN_OMAP343X,
2774         .clkdm          = { .name = "per_clkdm" },
2775         .recalc         = &followparent_recalc,
2776 };
2777
2778 static struct clk gpio3_ick = {
2779         .name           = "gpio3_ick",
2780         .parent         = &per_l4_ick,
2781         .prcm_mod       = OMAP3430_PER_MOD,
2782         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2783         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2784         .flags          = CLOCK_IN_OMAP343X,
2785         .clkdm          = { .name = "per_clkdm" },
2786         .recalc         = &followparent_recalc,
2787 };
2788
2789 static struct clk gpio2_ick = {
2790         .name           = "gpio2_ick",
2791         .parent         = &per_l4_ick,
2792         .prcm_mod       = OMAP3430_PER_MOD,
2793         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2794         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2795         .flags          = CLOCK_IN_OMAP343X,
2796         .clkdm          = { .name = "per_clkdm" },
2797         .recalc         = &followparent_recalc,
2798 };
2799
2800 static struct clk wdt3_ick = {
2801         .name           = "wdt3_ick",
2802         .parent         = &per_l4_ick,
2803         .prcm_mod       = OMAP3430_PER_MOD,
2804         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2805         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2806         .flags          = CLOCK_IN_OMAP343X,
2807         .clkdm          = { .name = "per_clkdm" },
2808         .recalc         = &followparent_recalc,
2809 };
2810
2811 static struct clk uart3_ick = {
2812         .name           = "uart3_ick",
2813         .parent         = &per_l4_ick,
2814         .prcm_mod       = OMAP3430_PER_MOD,
2815         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2816         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2817         .flags          = CLOCK_IN_OMAP343X,
2818         .clkdm          = { .name = "per_clkdm" },
2819         .recalc         = &followparent_recalc,
2820 };
2821
2822 static struct clk gpt9_ick = {
2823         .name           = "gpt9_ick",
2824         .parent         = &per_l4_ick,
2825         .prcm_mod       = OMAP3430_PER_MOD,
2826         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2827         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2828         .flags          = CLOCK_IN_OMAP343X,
2829         .clkdm          = { .name = "per_clkdm" },
2830         .recalc         = &followparent_recalc,
2831 };
2832
2833 static struct clk gpt8_ick = {
2834         .name           = "gpt8_ick",
2835         .parent         = &per_l4_ick,
2836         .prcm_mod       = OMAP3430_PER_MOD,
2837         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2838         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2839         .flags          = CLOCK_IN_OMAP343X,
2840         .clkdm          = { .name = "per_clkdm" },
2841         .recalc         = &followparent_recalc,
2842 };
2843
2844 static struct clk gpt7_ick = {
2845         .name           = "gpt7_ick",
2846         .parent         = &per_l4_ick,
2847         .prcm_mod       = OMAP3430_PER_MOD,
2848         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2849         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2850         .flags          = CLOCK_IN_OMAP343X,
2851         .clkdm          = { .name = "per_clkdm" },
2852         .recalc         = &followparent_recalc,
2853 };
2854
2855 static struct clk gpt6_ick = {
2856         .name           = "gpt6_ick",
2857         .parent         = &per_l4_ick,
2858         .prcm_mod       = OMAP3430_PER_MOD,
2859         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2860         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2861         .flags          = CLOCK_IN_OMAP343X,
2862         .clkdm          = { .name = "per_clkdm" },
2863         .recalc         = &followparent_recalc,
2864 };
2865
2866 static struct clk gpt5_ick = {
2867         .name           = "gpt5_ick",
2868         .parent         = &per_l4_ick,
2869         .prcm_mod       = OMAP3430_PER_MOD,
2870         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2871         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2872         .flags          = CLOCK_IN_OMAP343X,
2873         .clkdm          = { .name = "per_clkdm" },
2874         .recalc         = &followparent_recalc,
2875 };
2876
2877 static struct clk gpt4_ick = {
2878         .name           = "gpt4_ick",
2879         .parent         = &per_l4_ick,
2880         .prcm_mod       = OMAP3430_PER_MOD,
2881         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2882         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2883         .flags          = CLOCK_IN_OMAP343X,
2884         .clkdm          = { .name = "per_clkdm" },
2885         .recalc         = &followparent_recalc,
2886 };
2887
2888 static struct clk gpt3_ick = {
2889         .name           = "gpt3_ick",
2890         .parent         = &per_l4_ick,
2891         .prcm_mod       = OMAP3430_PER_MOD,
2892         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2893         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2894         .flags          = CLOCK_IN_OMAP343X,
2895         .clkdm          = { .name = "per_clkdm" },
2896         .recalc         = &followparent_recalc,
2897 };
2898
2899 static struct clk gpt2_ick = {
2900         .name           = "gpt2_ick",
2901         .parent         = &per_l4_ick,
2902         .prcm_mod       = OMAP3430_PER_MOD,
2903         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2904         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2905         .flags          = CLOCK_IN_OMAP343X,
2906         .clkdm          = { .name = "per_clkdm" },
2907         .recalc         = &followparent_recalc,
2908 };
2909
2910 static struct clk mcbsp2_ick = {
2911         .name           = "mcbsp_ick",
2912         .id             = 2,
2913         .parent         = &per_l4_ick,
2914         .prcm_mod       = OMAP3430_PER_MOD,
2915         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2916         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2917         .flags          = CLOCK_IN_OMAP343X,
2918         .clkdm          = { .name = "per_clkdm" },
2919         .recalc         = &followparent_recalc,
2920 };
2921
2922 static struct clk mcbsp3_ick = {
2923         .name           = "mcbsp_ick",
2924         .id             = 3,
2925         .parent         = &per_l4_ick,
2926         .prcm_mod       = OMAP3430_PER_MOD,
2927         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2928         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2929         .flags          = CLOCK_IN_OMAP343X,
2930         .clkdm          = { .name = "per_clkdm" },
2931         .recalc         = &followparent_recalc,
2932 };
2933
2934 static struct clk mcbsp4_ick = {
2935         .name           = "mcbsp_ick",
2936         .id             = 4,
2937         .parent         = &per_l4_ick,
2938         .prcm_mod       = OMAP3430_PER_MOD,
2939         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2940         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2941         .flags          = CLOCK_IN_OMAP343X,
2942         .clkdm          = { .name = "per_clkdm" },
2943         .recalc         = &followparent_recalc,
2944 };
2945
2946 static const struct clksel mcbsp_234_clksel[] = {
2947         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2948         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2949         { .parent = NULL }
2950 };
2951
2952 static struct clk mcbsp2_src_fck = {
2953         .name           = "mcbsp_src_fck",
2954         .id             = 2,
2955         .prcm_mod       = CLK_REG_IN_SCM,
2956         .init           = &omap2_init_clksel_parent,
2957         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2958         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2959         .clksel         = mcbsp_234_clksel,
2960         .flags          = CLOCK_IN_OMAP343X,
2961         .clkdm          = { .name = "per_clkdm" },
2962         .recalc         = &omap2_clksel_recalc,
2963 };
2964
2965 static struct clk mcbsp2_fck = {
2966         .name           = "mcbsp_fck",
2967         .id             = 2,
2968         .parent         = &mcbsp2_src_fck,
2969         .prcm_mod       = OMAP3430_PER_MOD,
2970         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2971         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2972         .flags          = CLOCK_IN_OMAP343X,
2973         .clkdm          = { .name = "per_clkdm" },
2974         .recalc         = &omap2_clksel_recalc,
2975 };
2976
2977 static struct clk mcbsp3_src_fck = {
2978         .name           = "mcbsp_src_fck",
2979         .id             = 3,
2980         .prcm_mod       = CLK_REG_IN_SCM,
2981         .init           = &omap2_init_clksel_parent,
2982         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2983         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2984         .clksel         = mcbsp_234_clksel,
2985         .flags          = CLOCK_IN_OMAP343X,
2986         .clkdm          = { .name = "per_clkdm" },
2987         .recalc         = &omap2_clksel_recalc,
2988 };
2989
2990 static struct clk mcbsp3_fck = {
2991         .name           = "mcbsp_fck",
2992         .id             = 3,
2993         .parent         = &mcbsp3_src_fck,
2994         .prcm_mod       = OMAP3430_PER_MOD,
2995         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2996         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2997         .flags          = CLOCK_IN_OMAP343X,
2998         .clkdm          = { .name = "per_clkdm" },
2999         .recalc         = &omap2_clksel_recalc,
3000 };
3001
3002 static struct clk mcbsp4_src_fck = {
3003         .name           = "mcbsp_src_fck",
3004         .id             = 4,
3005         .prcm_mod       = CLK_REG_IN_SCM,
3006         .init           = &omap2_init_clksel_parent,
3007         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
3008         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
3009         .clksel         = mcbsp_234_clksel,
3010         .flags          = CLOCK_IN_OMAP343X,
3011         .clkdm          = { .name = "per_clkdm" },
3012         .recalc         = &omap2_clksel_recalc,
3013 };
3014
3015 static struct clk mcbsp4_fck = {
3016         .name           = "mcbsp_fck",
3017         .id             = 4,
3018         .parent         = &mcbsp4_src_fck,
3019         .prcm_mod       = OMAP3430_PER_MOD,
3020         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3021         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3022         .flags          = CLOCK_IN_OMAP343X,
3023         .clkdm          = { .name = "per_clkdm" },
3024         .recalc         = &omap2_clksel_recalc,
3025 };
3026
3027 /* EMU clocks */
3028
3029 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3030
3031 static const struct clksel_rate emu_src_sys_rates[] = {
3032         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3033         { .div = 0 },
3034 };
3035
3036 static const struct clksel_rate emu_src_core_rates[] = {
3037         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3038         { .div = 0 },
3039 };
3040
3041 static const struct clksel_rate emu_src_per_rates[] = {
3042         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3043         { .div = 0 },
3044 };
3045
3046 static const struct clksel_rate emu_src_mpu_rates[] = {
3047         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3048         { .div = 0 },
3049 };
3050
3051 static const struct clksel emu_src_clksel[] = {
3052         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
3053         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3054         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
3055         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
3056         { .parent = NULL },
3057 };
3058
3059 /*
3060  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3061  * to switch the source of some of the EMU clocks.
3062  * XXX Are there CLKEN bits for these EMU clks?
3063  */
3064 static struct clk emu_src_ck = {
3065         .name           = "emu_src_ck",
3066         .prcm_mod       = OMAP3430_EMU_MOD,
3067         .init           = &omap2_init_clksel_parent,
3068         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3069         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
3070         .clksel         = emu_src_clksel,
3071         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3072         .clkdm          = { .name = "emu_clkdm" },
3073         .recalc         = &omap2_clksel_recalc,
3074 };
3075
3076 static const struct clksel_rate pclk_emu_rates[] = {
3077         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3078         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3079         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3080         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3081         { .div = 0 },
3082 };
3083
3084 static const struct clksel pclk_emu_clksel[] = {
3085         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3086         { .parent = NULL },
3087 };
3088
3089 static struct clk pclk_fck = {
3090         .name           = "pclk_fck",
3091         .prcm_mod       = OMAP3430_EMU_MOD,
3092         .init           = &omap2_init_clksel_parent,
3093         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3094         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3095         .clksel         = pclk_emu_clksel,
3096         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3097         .clkdm          = { .name = "emu_clkdm" },
3098         .recalc         = &omap2_clksel_recalc,
3099 };
3100
3101 static const struct clksel_rate pclkx2_emu_rates[] = {
3102         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3103         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3104         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3105         { .div = 0 },
3106 };
3107
3108 static const struct clksel pclkx2_emu_clksel[] = {
3109         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3110         { .parent = NULL },
3111 };
3112
3113 static struct clk pclkx2_fck = {
3114         .name           = "pclkx2_fck",
3115         .prcm_mod       = OMAP3430_EMU_MOD,
3116         .init           = &omap2_init_clksel_parent,
3117         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3118         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3119         .clksel         = pclkx2_emu_clksel,
3120         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3121         .clkdm          = { .name = "emu_clkdm" },
3122         .recalc         = &omap2_clksel_recalc,
3123 };
3124
3125 static const struct clksel atclk_emu_clksel[] = {
3126         { .parent = &emu_src_ck, .rates = div2_rates },
3127         { .parent = NULL },
3128 };
3129
3130 static struct clk atclk_fck = {
3131         .name           = "atclk_fck",
3132         .prcm_mod       = OMAP3430_EMU_MOD,
3133         .init           = &omap2_init_clksel_parent,
3134         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3135         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3136         .clksel         = atclk_emu_clksel,
3137         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3138         .clkdm          = { .name = "emu_clkdm" },
3139         .recalc         = &omap2_clksel_recalc,
3140 };
3141
3142 static struct clk traceclk_src_fck = {
3143         .name           = "traceclk_src_fck",
3144         .prcm_mod       = OMAP3430_EMU_MOD,
3145         .init           = &omap2_init_clksel_parent,
3146         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3147         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3148         .clksel         = emu_src_clksel,
3149         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3150         .clkdm          = { .name = "emu_clkdm" },
3151         .recalc         = &omap2_clksel_recalc,
3152 };
3153
3154 static const struct clksel_rate traceclk_rates[] = {
3155         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3156         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3157         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3158         { .div = 0 },
3159 };
3160
3161 static const struct clksel traceclk_clksel[] = {
3162         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3163         { .parent = NULL },
3164 };
3165
3166 static struct clk traceclk_fck = {
3167         .name           = "traceclk_fck",
3168         .prcm_mod       = OMAP3430_EMU_MOD,
3169         .init           = &omap2_init_clksel_parent,
3170         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3171         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3172         .clksel         = traceclk_clksel,
3173         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3174         .clkdm          = { .name = "emu_clkdm" },
3175         .recalc         = &omap2_clksel_recalc,
3176 };
3177
3178 /* SR clocks */
3179
3180 /* SmartReflex fclk (VDD1) */
3181 static struct clk sr1_fck = {
3182         .name           = "sr1_fck",
3183         .parent         = &sys_ck,
3184         .prcm_mod       = WKUP_MOD,
3185         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3186         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3187         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3188         .clkdm          = { .name = "prm_clkdm" },
3189         .recalc         = &followparent_recalc,
3190 };
3191
3192 /* SmartReflex fclk (VDD2) */
3193 static struct clk sr2_fck = {
3194         .name           = "sr2_fck",
3195         .parent         = &sys_ck,
3196         .prcm_mod       = WKUP_MOD,
3197         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3198         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3199         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3200         .clkdm          = { .name = "prm_clkdm" },
3201         .recalc         = &followparent_recalc,
3202 };
3203
3204 static struct clk sr_l4_ick = {
3205         .name           = "sr_l4_ick",
3206         .parent         = &l4_ick,
3207         .flags          = CLOCK_IN_OMAP343X,
3208         .clkdm          = { .name = "core_l4_clkdm" },
3209         .recalc         = &followparent_recalc,
3210 };
3211
3212 /* SECURE_32K_FCK clocks */
3213
3214 /* XXX This clock no longer exists in 3430 TRM rev F */
3215 static struct clk gpt12_fck = {
3216         .name           = "gpt12_fck",
3217         .parent         = &secure_32k_fck,
3218         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3219         .clkdm          = { .name = "prm_clkdm" },
3220         .recalc         = &followparent_recalc,
3221 };
3222
3223 static struct clk wdt1_fck = {
3224         .name           = "wdt1_fck",
3225         .parent         = &secure_32k_fck,
3226         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3227         .clkdm          = { .name = "prm_clkdm" },
3228         .recalc         = &followparent_recalc,
3229 };
3230
3231 static struct clk *onchip_34xx_clks[] __initdata = {
3232         &omap_32k_fck,
3233         &virt_12m_ck,
3234         &virt_13m_ck,
3235         &virt_16_8m_ck,
3236         &virt_19_2m_ck,
3237         &virt_26m_ck,
3238         &virt_38_4m_ck,
3239         &osc_sys_ck,
3240         &sys_ck,
3241         &sys_altclk,
3242         &mcbsp_clks,
3243         &sys_clkout1,
3244         &dpll1_ck,
3245         &dpll1_x2_ck,
3246         &dpll1_x2m2_ck,
3247         &dpll2_ck,
3248         &dpll2_m2_ck,
3249         &dpll3_ck,
3250         &core_ck,
3251         &dpll3_x2_ck,
3252         &dpll3_m2_ck,
3253         &dpll3_m2x2_ck,
3254         &dpll3_m3_ck,
3255         &dpll3_m3x2_ck,
3256         &emu_core_alwon_ck,
3257         &dpll4_ck,
3258         &dpll4_x2_ck,
3259         &omap_96m_alwon_fck,
3260         &omap_96m_fck,
3261         &cm_96m_fck,
3262         &omap_54m_fck,
3263         &omap_48m_fck,
3264         &omap_12m_fck,
3265         &dpll4_m2_ck,
3266         &dpll4_m2x2_ck,
3267         &dpll4_m3_ck,
3268         &dpll4_m3x2_ck,
3269         &dpll4_m4_ck,
3270         &dpll4_m4x2_ck,
3271         &dpll4_m5_ck,
3272         &dpll4_m5x2_ck,
3273         &dpll4_m6_ck,
3274         &dpll4_m6x2_ck,
3275         &emu_per_alwon_ck,
3276         &dpll5_ck,
3277         &dpll5_m2_ck,
3278         &clkout2_src_ck,
3279         &sys_clkout2,
3280         &corex2_fck,
3281         &dpll1_fck,
3282         &mpu_ck,
3283         &arm_fck,
3284         &emu_mpu_alwon_ck,
3285         &dpll2_fck,
3286         &iva2_ck,
3287         &l3_ick,
3288         &l4_ick,
3289         &rm_ick,
3290         &gfx_l3_ck,
3291         &gfx_l3_fck,
3292         &gfx_l3_ick,
3293         &gfx_cg1_ck,
3294         &gfx_cg2_ck,
3295         &sgx_fck,
3296         &sgx_ick,
3297         &d2d_26m_fck,
3298         &gpt10_fck,
3299         &gpt11_fck,
3300         &cpefuse_fck,
3301         &ts_fck,
3302         &usbtll_fck,
3303         &core_96m_fck,
3304         &mmchs3_fck,
3305         &mmchs2_fck,
3306         &mspro_fck,
3307         &mmchs1_fck,
3308         &i2c3_fck,
3309         &i2c2_fck,
3310         &i2c1_fck,
3311         &mcbsp5_src_fck,
3312         &mcbsp5_fck,
3313         &mcbsp1_src_fck,
3314         &mcbsp1_fck,
3315         &core_48m_fck,
3316         &mcspi4_fck,
3317         &mcspi3_fck,
3318         &mcspi2_fck,
3319         &mcspi1_fck,
3320         &uart2_fck,
3321         &uart1_fck,
3322         &fshostusb_fck,
3323         &core_12m_fck,
3324         &hdq_fck,
3325         &ssi_ssr_fck,
3326         &ssi_sst_fck,
3327         &core_l3_ick,
3328         &hsotgusb_ick,
3329         &sdrc_ick,
3330         &gpmc_fck,
3331         &security_l3_ick,
3332         &pka_ick,
3333         &core_l4_ick,
3334         &usbtll_ick,
3335         &mmchs3_ick,
3336         &icr_ick,
3337         &aes2_ick,
3338         &sha12_ick,
3339         &des2_ick,
3340         &mmchs2_ick,
3341         &mmchs1_ick,
3342         &mspro_ick,
3343         &hdq_ick,
3344         &mcspi4_ick,
3345         &mcspi3_ick,
3346         &mcspi2_ick,
3347         &mcspi1_ick,
3348         &i2c3_ick,
3349         &i2c2_ick,
3350         &i2c1_ick,
3351         &uart2_ick,
3352         &uart1_ick,
3353         &gpt11_ick,
3354         &gpt10_ick,
3355         &mcbsp5_ick,
3356         &mcbsp1_ick,
3357         &fac_ick,
3358         &mailboxes_ick,
3359         &omapctrl_ick,
3360         &ssi_l4_ick,
3361         &ssi_ick,
3362         &usb_l4_ick,
3363         &security_l4_ick2,
3364         &aes1_ick,
3365         &rng_ick,
3366         &sha11_ick,
3367         &des1_ick,
3368         &dss1_alwon_fck,
3369         &dss_tv_fck,
3370         &dss_96m_fck,
3371         &dss2_alwon_fck,
3372         &dss_ick,
3373         &cam_mclk,
3374         &cam_ick,
3375         &csi2_96m_fck,
3376         &usbhost_120m_fck,
3377         &usbhost_48m_fck,
3378         &usbhost_ick,
3379         &usim_fck,
3380         &gpt1_fck,
3381         &wkup_32k_fck,
3382         &gpio1_fck,
3383         &wdt2_fck,
3384         &wkup_l4_ick,
3385         &usim_ick,
3386         &wdt2_ick,
3387         &wdt1_ick,
3388         &gpio1_ick,
3389         &omap_32ksync_ick,
3390         &gpt12_ick,
3391         &gpt1_ick,
3392         &per_96m_fck,
3393         &per_48m_fck,
3394         &uart3_fck,
3395         &gpt2_fck,
3396         &gpt3_fck,
3397         &gpt4_fck,
3398         &gpt5_fck,
3399         &gpt6_fck,
3400         &gpt7_fck,
3401         &gpt8_fck,
3402         &gpt9_fck,
3403         &per_32k_alwon_fck,
3404         &gpio6_fck,
3405         &gpio5_fck,
3406         &gpio4_fck,
3407         &gpio3_fck,
3408         &gpio2_fck,
3409         &wdt3_fck,
3410         &per_l4_ick,
3411         &gpio6_ick,
3412         &gpio5_ick,
3413         &gpio4_ick,
3414         &gpio3_ick,
3415         &gpio2_ick,
3416         &wdt3_ick,
3417         &uart3_ick,
3418         &gpt9_ick,
3419         &gpt8_ick,
3420         &gpt7_ick,
3421         &gpt6_ick,
3422         &gpt5_ick,
3423         &gpt4_ick,
3424         &gpt3_ick,
3425         &gpt2_ick,
3426         &mcbsp2_ick,
3427         &mcbsp3_ick,
3428         &mcbsp4_ick,
3429         &mcbsp2_src_fck,
3430         &mcbsp2_fck,
3431         &mcbsp3_src_fck,
3432         &mcbsp3_fck,
3433         &mcbsp4_src_fck,
3434         &mcbsp4_fck,
3435         &emu_src_ck,
3436         &pclk_fck,
3437         &pclkx2_fck,
3438         &atclk_fck,
3439         &traceclk_src_fck,
3440         &traceclk_fck,
3441         &sr1_fck,
3442         &sr2_fck,
3443         &sr_l4_ick,
3444         &secure_32k_fck,
3445         &gpt12_fck,
3446         &wdt1_fck,
3447 };
3448
3449 #endif