arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <asm/arch/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  52 #define DPLL_LOW_POWER_STOP             0x1
  53 #define DPLL_LOW_POWER_BYPASS           0x5
  54 #define DPLL_LOCKED                     0x7
  55
  56 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  57         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
  58
  59 #define OMAP3430_PRM_CLKSEL                                             \
  60         OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  61
  62 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  63         OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  64
  65 /* PRM CLOCKS */
  66
  67 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  68 static struct clk omap_32k_fck = {
  69         .name           = "omap_32k_fck",
  70         .rate           = 32768,
  71         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  72                                 ALWAYS_ENABLED,
  73         .recalc         = &propagate_rate,
  74 };
  75
  76 static struct clk secure_32k_fck = {
  77         .name           = "secure_32k_fck",
  78         .rate           = 32768,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .recalc         = &propagate_rate,
  82 };
  83
  84 /* Virtual source clocks for osc_sys_ck */
  85 static struct clk virt_12m_ck = {
  86         .name           = "virt_12m_ck",
  87         .rate           = 12000000,
  88         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  89                                 ALWAYS_ENABLED,
  90         .recalc         = &propagate_rate,
  91 };
  92
  93 static struct clk virt_13m_ck = {
  94         .name           = "virt_13m_ck",
  95         .rate           = 13000000,
  96         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  97                                 ALWAYS_ENABLED,
  98         .recalc         = &propagate_rate,
  99 };
 100
 101 static struct clk virt_16_8m_ck = {
 102         .name           = "virt_16_8m_ck",
 103         .rate           = 16800000,
 104         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 105                                 ALWAYS_ENABLED,
 106         .recalc         = &propagate_rate,
 107 };
 108
 109 static struct clk virt_19_2m_ck = {
 110         .name           = "virt_19_2m_ck",
 111         .rate           = 19200000,
 112         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 113                                 ALWAYS_ENABLED,
 114         .recalc         = &propagate_rate,
 115 };
 116
 117 static struct clk virt_26m_ck = {
 118         .name           = "virt_26m_ck",
 119         .rate           = 26000000,
 120         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 121                                 ALWAYS_ENABLED,
 122         .recalc         = &propagate_rate,
 123 };
 124
 125 static struct clk virt_38_4m_ck = {
 126         .name           = "virt_38_4m_ck",
 127         .rate           = 38400000,
 128         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 129                                 ALWAYS_ENABLED,
 130         .recalc         = &propagate_rate,
 131 };
 132
 133 static const struct clksel_rate osc_sys_12m_rates[] = {
 134         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 135         { .div = 0 }
 136 };
 137
 138 static const struct clksel_rate osc_sys_13m_rates[] = {
 139         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 140         { .div = 0 }
 141 };
 142
 143 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 144         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 145         { .div = 0 }
 146 };
 147
 148 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 149         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 150         { .div = 0 }
 151 };
 152
 153 static const struct clksel_rate osc_sys_26m_rates[] = {
 154         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 155         { .div = 0 }
 156 };
 157
 158 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 159         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 160         { .div = 0 }
 161 };
 162
 163 static const struct clksel osc_sys_clksel[] = {
 164         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 165         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 166         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 167         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 168         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 169         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 170         { .parent = NULL },
 171 };
 172
 173 /* Oscillator clock */
 174 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 175 static struct clk osc_sys_ck = {
 176         .name           = "osc_sys_ck",
 177         .init           = &omap2_init_clksel_parent,
 178         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 179         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 180         .clksel         = osc_sys_clksel,
 181         /* REVISIT: deal with autoextclkmode? */
 182         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 183                                 ALWAYS_ENABLED,
 184         .recalc         = &omap2_clksel_recalc,
 185 };
 186
 187 static const struct clksel_rate div2_rates[] = {
 188         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 189         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 190         { .div = 0 }
 191 };
 192
 193 static const struct clksel sys_clksel[] = {
 194         { .parent = &osc_sys_ck, .rates = div2_rates },
 195         { .parent = NULL }
 196 };
 197
 198 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 199 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 200 static struct clk sys_ck = {
 201         .name           = "sys_ck",
 202         .parent         = &osc_sys_ck,
 203         .init           = &omap2_init_clksel_parent,
 204         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 205         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 206         .clksel         = sys_clksel,
 207         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 208         .recalc         = &omap2_clksel_recalc,
 209 };
 210
 211 static struct clk sys_altclk = {
 212         .name           = "sys_altclk",
 213         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 214         .recalc         = &propagate_rate,
 215 };
 216
 217 /* Optional external clock input for some McBSPs */
 218 static struct clk mcbsp_clks = {
 219         .name           = "mcbsp_clks",
 220         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 221         .recalc         = &propagate_rate,
 222 };
 223
 224 /* PRM EXTERNAL CLOCK OUTPUT */
 225
 226 static struct clk sys_clkout1 = {
 227         .name           = "sys_clkout1",
 228         .parent         = &osc_sys_ck,
 229         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 230         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 231         .flags          = CLOCK_IN_OMAP343X,
 232         .recalc         = &followparent_recalc,
 233 };
 234
 235 /* DPLLS */
 236
 237 /* CM CLOCKS */
 238
 239 static const struct clksel_rate dpll_bypass_rates[] = {
 240         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 241         { .div = 0 }
 242 };
 243
 244 static const struct clksel_rate dpll_locked_rates[] = {
 245         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 246         { .div = 0 }
 247 };
 248
 249 static const struct clksel_rate div16_dpll_rates[] = {
 250         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 251         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 252         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 253         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 254         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 255         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 256         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 257         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 258         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 259         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 260         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 261         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 262         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 263         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 264         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 265         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 266         { .div = 0 }
 267 };
 268
 269 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 270         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 271
 272 /* DPLL1 */
 273 /* MPU clock source */
 274 /* Type: DPLL */
 275 static struct dpll_data dpll1_dd = {
 276         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 277         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 278         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 279         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 280         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 281         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 282         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 283         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 284         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 285         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 286         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 287         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 288         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 289         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 290         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 291         .max_divider    = OMAP3_MAX_DPLL_DIV,
 292         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 293 };
 294
 295 static struct clk dpll1_ck = {
 296         .name           = "dpll1_ck",
 297         .parent         = &sys_ck,
 298         .dpll_data      = &dpll1_dd,
 299         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 300         .round_rate     = &omap2_dpll_round_rate,
 301         .set_rate       = &omap3_noncore_dpll_set_rate,
 302         .recalc         = &omap3_dpll_recalc,
 303 };
 304
 305 /*
 306  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 307  * DPLL isn't bypassed.
 308  */
 309 static struct clk dpll1_x2_ck = {
 310         .name           = "dpll1_x2_ck",
 311         .parent         = &dpll1_ck,
 312         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 313                                 PARENT_CONTROLS_CLOCK,
 314         .recalc         = &omap3_clkoutx2_recalc,
 315 };
 316
 317 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 318 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 319         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 320         { .parent = NULL }
 321 };
 322
 323 /*
 324  * Does not exist in the TRM - needed to separate the M2 divider from
 325  * bypass selection in mpu_ck
 326  */
 327 static struct clk dpll1_x2m2_ck = {
 328         .name           = "dpll1_x2m2_ck",
 329         .parent         = &dpll1_x2_ck,
 330         .init           = &omap2_init_clksel_parent,
 331         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 332         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 333         .clksel         = div16_dpll1_x2m2_clksel,
 334         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 335                                 PARENT_CONTROLS_CLOCK,
 336         .recalc         = &omap2_clksel_recalc,
 337 };
 338
 339 /* DPLL2 */
 340 /* IVA2 clock source */
 341 /* Type: DPLL */
 342
 343 static struct dpll_data dpll2_dd = {
 344         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 345         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 346         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 347         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 348         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 349         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 350         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 351                                 (1 << DPLL_LOW_POWER_BYPASS),
 352         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 353         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 354         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 355         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 356         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 357         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 358         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 359         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 360         .max_divider    = OMAP3_MAX_DPLL_DIV,
 361         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 362 };
 363
 364 static struct clk dpll2_ck = {
 365         .name           = "dpll2_ck",
 366         .parent         = &sys_ck,
 367         .dpll_data      = &dpll2_dd,
 368         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 369         .enable         = &omap3_noncore_dpll_enable,
 370         .disable        = &omap3_noncore_dpll_disable,
 371         .round_rate     = &omap2_dpll_round_rate,
 372         .set_rate       = &omap3_noncore_dpll_set_rate,
 373         .recalc         = &omap3_dpll_recalc,
 374 };
 375
 376 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 377         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 378         { .parent = NULL }
 379 };
 380
 381 /*
 382  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 383  * or CLKOUTX2. CLKOUT seems most plausible.
 384  */
 385 static struct clk dpll2_m2_ck = {
 386         .name           = "dpll2_m2_ck",
 387         .parent         = &dpll2_ck,
 388         .init           = &omap2_init_clksel_parent,
 389         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 390                                           OMAP3430_CM_CLKSEL2_PLL),
 391         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 392         .clksel         = div16_dpll2_m2x2_clksel,
 393         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 394                                 PARENT_CONTROLS_CLOCK,
 395         .recalc         = &omap2_clksel_recalc,
 396 };
 397
 398 /*
 399  * DPLL3
 400  * Source clock for all interfaces and for some device fclks
 401  * REVISIT: Also supports fast relock bypass - not included below
 402  */
 403 static struct dpll_data dpll3_dd = {
 404         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 405         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 406         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 407         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 408         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 409         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 410         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 411         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 412         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 413         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 414         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 415         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 416         .max_divider    = OMAP3_MAX_DPLL_DIV,
 417         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 418 };
 419
 420 static struct clk dpll3_ck = {
 421         .name           = "dpll3_ck",
 422         .parent         = &sys_ck,
 423         .dpll_data      = &dpll3_dd,
 424         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 425         .round_rate     = &omap2_dpll_round_rate,
 426         .recalc         = &omap3_dpll_recalc,
 427 };
 428
 429 /*
 430  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 431  * DPLL isn't bypassed
 432  */
 433 static struct clk dpll3_x2_ck = {
 434         .name           = "dpll3_x2_ck",
 435         .parent         = &dpll3_ck,
 436         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 437                                 PARENT_CONTROLS_CLOCK,
 438         .recalc         = &omap3_clkoutx2_recalc,
 439 };
 440
 441 static const struct clksel_rate div31_dpll3_rates[] = {
 442         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 443         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 444         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 445         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 446         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 447         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 448         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 449         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 450         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 451         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 452         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 453         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 454         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 455         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 456         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 457         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 458         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 459         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 460         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 461         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 462         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 463         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 464         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 465         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 466         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 467         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 468         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 469         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 470         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 471         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 472         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 473         { .div = 0 },
 474 };
 475
 476 static const struct clksel div31_dpll3m2_clksel[] = {
 477         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 478         { .parent = NULL }
 479 };
 480
 481 /*
 482  * DPLL3 output M2
 483  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 484  * that code is ready, this should remain a 'read-only' clksel clock.
 485  */
 486 static struct clk dpll3_m2_ck = {
 487         .name           = "dpll3_m2_ck",
 488         .parent         = &dpll3_ck,
 489         .init           = &omap2_init_clksel_parent,
 490         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 491         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 492         .clksel         = div31_dpll3m2_clksel,
 493         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 494                                 PARENT_CONTROLS_CLOCK,
 495         .recalc         = &omap2_clksel_recalc,
 496 };
 497
 498 static const struct clksel core_ck_clksel[] = {
 499         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 500         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 501         { .parent = NULL }
 502 };
 503
 504 static struct clk core_ck = {
 505         .name           = "core_ck",
 506         .init           = &omap2_init_clksel_parent,
 507         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 508         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 509         .clksel         = core_ck_clksel,
 510         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 511                                 PARENT_CONTROLS_CLOCK,
 512         .recalc         = &omap2_clksel_recalc,
 513 };
 514
 515 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 516         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 517         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 518         { .parent = NULL }
 519 };
 520
 521 static struct clk dpll3_m2x2_ck = {
 522         .name           = "dpll3_m2x2_ck",
 523         .init           = &omap2_init_clksel_parent,
 524         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 525         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 526         .clksel         = dpll3_m2x2_ck_clksel,
 527         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 528                                 PARENT_CONTROLS_CLOCK,
 529         .recalc         = &omap2_clksel_recalc,
 530 };
 531
 532 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 533 static const struct clksel div16_dpll3_clksel[] = {
 534         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 535         { .parent = NULL }
 536 };
 537
 538 /* This virtual clock is the source for dpll3_m3x2_ck */
 539 static struct clk dpll3_m3_ck = {
 540         .name           = "dpll3_m3_ck",
 541         .parent         = &dpll3_ck,
 542         .init           = &omap2_init_clksel_parent,
 543         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 544         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 545         .clksel         = div16_dpll3_clksel,
 546         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 547                                 PARENT_CONTROLS_CLOCK,
 548         .recalc         = &omap2_clksel_recalc,
 549 };
 550
 551 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 552 static struct clk dpll3_m3x2_ck = {
 553         .name           = "dpll3_m3x2_ck",
 554         .parent         = &dpll3_m3_ck,
 555         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 556         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 557         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 558         .recalc         = &omap3_clkoutx2_recalc,
 559 };
 560
 561 static const struct clksel emu_core_alwon_ck_clksel[] = {
 562         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 563         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 564         { .parent = NULL }
 565 };
 566
 567 static struct clk emu_core_alwon_ck = {
 568         .name           = "emu_core_alwon_ck",
 569         .parent         = &dpll3_m3x2_ck,
 570         .init           = &omap2_init_clksel_parent,
 571         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 572         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 573         .clksel         = emu_core_alwon_ck_clksel,
 574         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 575                                 PARENT_CONTROLS_CLOCK,
 576         .recalc         = &omap2_clksel_recalc,
 577 };
 578
 579 /* DPLL4 */
 580 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 581 /* Type: DPLL */
 582 static struct dpll_data dpll4_dd = {
 583         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 584         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 585         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 586         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 587         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 588         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 589         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 590         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 591         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 592         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 593         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 594         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 595         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 596         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 597         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 598         .max_divider    = OMAP3_MAX_DPLL_DIV,
 599         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 600 };
 601
 602 static struct clk dpll4_ck = {
 603         .name           = "dpll4_ck",
 604         .parent         = &sys_ck,
 605         .dpll_data      = &dpll4_dd,
 606         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 607         .enable         = &omap3_noncore_dpll_enable,
 608         .disable        = &omap3_noncore_dpll_disable,
 609         .round_rate     = &omap2_dpll_round_rate,
 610         .set_rate       = &omap3_noncore_dpll_set_rate,
 611         .recalc         = &omap3_dpll_recalc,
 612 };
 613
 614 /*
 615  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 616  * DPLL isn't bypassed --
 617  * XXX does this serve any downstream clocks?
 618  */
 619 static struct clk dpll4_x2_ck = {
 620         .name           = "dpll4_x2_ck",
 621         .parent         = &dpll4_ck,
 622         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 623                                 PARENT_CONTROLS_CLOCK,
 624         .recalc         = &omap3_clkoutx2_recalc,
 625 };
 626
 627 static const struct clksel div16_dpll4_clksel[] = {
 628         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 629         { .parent = NULL }
 630 };
 631
 632 /* This virtual clock is the source for dpll4_m2x2_ck */
 633 static struct clk dpll4_m2_ck = {
 634         .name           = "dpll4_m2_ck",
 635         .parent         = &dpll4_ck,
 636         .init           = &omap2_init_clksel_parent,
 637         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 638         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 639         .clksel         = div16_dpll4_clksel,
 640         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 641                                 PARENT_CONTROLS_CLOCK,
 642         .recalc         = &omap2_clksel_recalc,
 643 };
 644
 645 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 646 static struct clk dpll4_m2x2_ck = {
 647         .name           = "dpll4_m2x2_ck",
 648         .parent         = &dpll4_m2_ck,
 649         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 650         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 651         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 652         .recalc         = &omap3_clkoutx2_recalc,
 653 };
 654
 655 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 656         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 657         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 658         { .parent = NULL }
 659 };
 660
 661 static struct clk omap_96m_alwon_fck = {
 662         .name           = "omap_96m_alwon_fck",
 663         .parent         = &dpll4_m2x2_ck,
 664         .init           = &omap2_init_clksel_parent,
 665         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 666         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 667         .clksel         = omap_96m_alwon_fck_clksel,
 668         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 669                                  PARENT_CONTROLS_CLOCK,
 670         .recalc         = &omap2_clksel_recalc,
 671 };
 672
 673 static struct clk omap_96m_fck = {
 674         .name           = "omap_96m_fck",
 675         .parent         = &omap_96m_alwon_fck,
 676         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 677                                 PARENT_CONTROLS_CLOCK,
 678         .recalc         = &followparent_recalc,
 679 };
 680
 681 static const struct clksel cm_96m_fck_clksel[] = {
 682         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 683         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 684         { .parent = NULL }
 685 };
 686
 687 static struct clk cm_96m_fck = {
 688         .name           = "cm_96m_fck",
 689         .parent         = &dpll4_m2x2_ck,
 690         .init           = &omap2_init_clksel_parent,
 691         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 692         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 693         .clksel         = cm_96m_fck_clksel,
 694         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 695                                 PARENT_CONTROLS_CLOCK,
 696         .recalc         = &omap2_clksel_recalc,
 697 };
 698
 699 /* This virtual clock is the source for dpll4_m3x2_ck */
 700 static struct clk dpll4_m3_ck = {
 701         .name           = "dpll4_m3_ck",
 702         .parent         = &dpll4_ck,
 703         .init           = &omap2_init_clksel_parent,
 704         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 705         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 706         .clksel         = div16_dpll4_clksel,
 707         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 708                                 PARENT_CONTROLS_CLOCK,
 709         .recalc         = &omap2_clksel_recalc,
 710 };
 711
 712 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 713 static struct clk dpll4_m3x2_ck = {
 714         .name           = "dpll4_m3x2_ck",
 715         .parent         = &dpll4_m3_ck,
 716         .init           = &omap2_init_clksel_parent,
 717         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 718         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 719         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 720         .recalc         = &omap3_clkoutx2_recalc,
 721 };
 722
 723 static const struct clksel virt_omap_54m_fck_clksel[] = {
 724         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 725         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 726         { .parent = NULL }
 727 };
 728
 729 static struct clk virt_omap_54m_fck = {
 730         .name           = "virt_omap_54m_fck",
 731         .parent         = &dpll4_m3x2_ck,
 732         .init           = &omap2_init_clksel_parent,
 733         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 734         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 735         .clksel         = virt_omap_54m_fck_clksel,
 736         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 737                                 PARENT_CONTROLS_CLOCK,
 738         .recalc         = &omap2_clksel_recalc,
 739 };
 740
 741 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 742         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 743         { .div = 0 }
 744 };
 745
 746 static const struct clksel_rate omap_54m_alt_rates[] = {
 747         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 748         { .div = 0 }
 749 };
 750
 751 static const struct clksel omap_54m_clksel[] = {
 752         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 753         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 754         { .parent = NULL }
 755 };
 756
 757 static struct clk omap_54m_fck = {
 758         .name           = "omap_54m_fck",
 759         .init           = &omap2_init_clksel_parent,
 760         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 761         .clksel_mask    = OMAP3430_SOURCE_54M,
 762         .clksel         = omap_54m_clksel,
 763         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 764                                 PARENT_CONTROLS_CLOCK,
 765         .recalc         = &omap2_clksel_recalc,
 766 };
 767
 768 static const struct clksel_rate omap_48m_96md2_rates[] = {
 769         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 770         { .div = 0 }
 771 };
 772
 773 static const struct clksel_rate omap_48m_alt_rates[] = {
 774         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 775         { .div = 0 }
 776 };
 777
 778 static const struct clksel omap_48m_clksel[] = {
 779         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 780         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 781         { .parent = NULL }
 782 };
 783
 784 static struct clk omap_48m_fck = {
 785         .name           = "omap_48m_fck",
 786         .init           = &omap2_init_clksel_parent,
 787         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 788         .clksel_mask    = OMAP3430_SOURCE_48M,
 789         .clksel         = omap_48m_clksel,
 790         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 791                                 PARENT_CONTROLS_CLOCK,
 792         .recalc         = &omap2_clksel_recalc,
 793 };
 794
 795 static struct clk omap_12m_fck = {
 796         .name           = "omap_12m_fck",
 797         .parent         = &omap_48m_fck,
 798         .fixed_div      = 4,
 799         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 800                                 PARENT_CONTROLS_CLOCK,
 801         .recalc         = &omap2_fixed_divisor_recalc,
 802 };
 803
 804 /* This virstual clock is the source for dpll4_m4x2_ck */
 805 static struct clk dpll4_m4_ck = {
 806         .name           = "dpll4_m4_ck",
 807         .parent         = &dpll4_ck,
 808         .init           = &omap2_init_clksel_parent,
 809         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 810         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 811         .clksel         = div16_dpll4_clksel,
 812         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 813                                 PARENT_CONTROLS_CLOCK,
 814         .recalc         = &omap2_clksel_recalc,
 815 };
 816
 817 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 818 static struct clk dpll4_m4x2_ck = {
 819         .name           = "dpll4_m4x2_ck",
 820         .parent         = &dpll4_m4_ck,
 821         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 822         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 823         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 824         .recalc         = &omap3_clkoutx2_recalc,
 825 };
 826
 827 /* This virtual clock is the source for dpll4_m5x2_ck */
 828 static struct clk dpll4_m5_ck = {
 829         .name           = "dpll4_m5_ck",
 830         .parent         = &dpll4_ck,
 831         .init           = &omap2_init_clksel_parent,
 832         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 833         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 834         .clksel         = div16_dpll4_clksel,
 835         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 836                                 PARENT_CONTROLS_CLOCK,
 837         .recalc         = &omap2_clksel_recalc,
 838 };
 839
 840 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 841 static struct clk dpll4_m5x2_ck = {
 842         .name           = "dpll4_m5x2_ck",
 843         .parent         = &dpll4_m5_ck,
 844         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 845         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 846         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 847         .recalc         = &omap3_clkoutx2_recalc,
 848 };
 849
 850 /* This virtual clock is the source for dpll4_m6x2_ck */
 851 static struct clk dpll4_m6_ck = {
 852         .name           = "dpll4_m6_ck",
 853         .parent         = &dpll4_ck,
 854         .init           = &omap2_init_clksel_parent,
 855         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 856         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 857         .clksel         = div16_dpll4_clksel,
 858         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 859                                 PARENT_CONTROLS_CLOCK,
 860         .recalc         = &omap2_clksel_recalc,
 861 };
 862
 863 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 864 static struct clk dpll4_m6x2_ck = {
 865         .name           = "dpll4_m6x2_ck",
 866         .parent         = &dpll4_m6_ck,
 867         .init           = &omap2_init_clksel_parent,
 868         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 869         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 870         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 871         .recalc         = &omap3_clkoutx2_recalc,
 872 };
 873
 874 static struct clk emu_per_alwon_ck = {
 875         .name           = "emu_per_alwon_ck",
 876         .parent         = &dpll4_m6x2_ck,
 877         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 878                                 PARENT_CONTROLS_CLOCK,
 879         .recalc         = &followparent_recalc,
 880 };
 881
 882 /* DPLL5 */
 883 /* Supplies 120MHz clock, USIM source clock */
 884 /* Type: DPLL */
 885 /* 3430ES2 only */
 886 static struct dpll_data dpll5_dd = {
 887         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 888         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 889         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 890         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 891         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 892         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 893         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 894         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 895         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 896         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 897         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 898         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 899         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 900         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 901         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 902         .max_divider    = OMAP3_MAX_DPLL_DIV,
 903         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 904 };
 905
 906 static struct clk dpll5_ck = {
 907         .name           = "dpll5_ck",
 908         .parent         = &sys_ck,
 909         .dpll_data      = &dpll5_dd,
 910         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 911         .enable         = &omap3_noncore_dpll_enable,
 912         .disable        = &omap3_noncore_dpll_disable,
 913         .round_rate     = &omap2_dpll_round_rate,
 914         .set_rate       = &omap3_noncore_dpll_set_rate,
 915         .recalc         = &omap3_dpll_recalc,
 916 };
 917
 918 static const struct clksel div16_dpll5_clksel[] = {
 919         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 920         { .parent = NULL }
 921 };
 922
 923 static struct clk dpll5_m2_ck = {
 924         .name           = "dpll5_m2_ck",
 925         .parent         = &dpll5_ck,
 926         .init           = &omap2_init_clksel_parent,
 927         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 928         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 929         .clksel         = div16_dpll5_clksel,
 930         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 931                                 PARENT_CONTROLS_CLOCK,
 932         .recalc         = &omap2_clksel_recalc,
 933 };
 934
 935 static const struct clksel omap_120m_fck_clksel[] = {
 936         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 937         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 938         { .parent = NULL }
 939 };
 940
 941 static struct clk omap_120m_fck = {
 942         .name           = "omap_120m_fck",
 943         .parent         = &dpll5_m2_ck,
 944         .init           = &omap2_init_clksel_parent,
 945         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 946         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 947         .clksel         = omap_120m_fck_clksel,
 948         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 949                                 PARENT_CONTROLS_CLOCK,
 950         .recalc         = &omap2_clksel_recalc,
 951 };
 952
 953 /* CM EXTERNAL CLOCK OUTPUTS */
 954
 955 static const struct clksel_rate clkout2_src_core_rates[] = {
 956         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 957         { .div = 0 }
 958 };
 959
 960 static const struct clksel_rate clkout2_src_sys_rates[] = {
 961         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 962         { .div = 0 }
 963 };
 964
 965 static const struct clksel_rate clkout2_src_96m_rates[] = {
 966         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 967         { .div = 0 }
 968 };
 969
 970 static const struct clksel_rate clkout2_src_54m_rates[] = {
 971         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 972         { .div = 0 }
 973 };
 974
 975 static const struct clksel clkout2_src_clksel[] = {
 976         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 977         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 978         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 979         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 980         { .parent = NULL }
 981 };
 982
 983 static struct clk clkout2_src_ck = {
 984         .name           = "clkout2_src_ck",
 985         .init           = &omap2_init_clksel_parent,
 986         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
 987         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 988         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
 989         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 990         .clksel         = clkout2_src_clksel,
 991         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 992         .clkdm_name     = "core_clkdm",
 993         .recalc         = &omap2_clksel_recalc,
 994 };
 995
 996 static const struct clksel_rate sys_clkout2_rates[] = {
 997         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 998         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 999         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1000         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1001         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1002         { .div = 0 },
1003 };
1004
1005 static const struct clksel sys_clkout2_clksel[] = {
1006         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1007         { .parent = NULL },
1008 };
1009
1010 static struct clk sys_clkout2 = {
1011         .name           = "sys_clkout2",
1012         .init           = &omap2_init_clksel_parent,
1013         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1014         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1015         .clksel         = sys_clkout2_clksel,
1016         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1017         .recalc         = &omap2_clksel_recalc,
1018 };
1019
1020 /* CM OUTPUT CLOCKS */
1021
1022 static struct clk corex2_fck = {
1023         .name           = "corex2_fck",
1024         .parent         = &dpll3_m2x2_ck,
1025         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1026                                 PARENT_CONTROLS_CLOCK,
1027         .recalc         = &followparent_recalc,
1028 };
1029
1030 /* DPLL power domain clock controls */
1031
1032 static const struct clksel div2_core_clksel[] = {
1033         { .parent = &core_ck, .rates = div2_rates },
1034         { .parent = NULL }
1035 };
1036
1037 /*
1038  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1039  * may be inconsistent here?
1040  */
1041 static struct clk dpll1_fck = {
1042         .name           = "dpll1_fck",
1043         .parent         = &core_ck,
1044         .init           = &omap2_init_clksel_parent,
1045         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1046         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1047         .clksel         = div2_core_clksel,
1048         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1049                                 PARENT_CONTROLS_CLOCK,
1050         .recalc         = &omap2_clksel_recalc,
1051 };
1052
1053 /*
1054  * MPU clksel:
1055  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1056  * derives from the high-frequency bypass clock originating from DPLL3,
1057  * called 'dpll1_fck'
1058  */
1059 static const struct clksel mpu_clksel[] = {
1060         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1061         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1062         { .parent = NULL }
1063 };
1064
1065 static struct clk mpu_ck = {
1066         .name           = "mpu_ck",
1067         .parent         = &dpll1_x2m2_ck,
1068         .init           = &omap2_init_clksel_parent,
1069         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1070         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1071         .clksel         = mpu_clksel,
1072         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1073                                 PARENT_CONTROLS_CLOCK,
1074         .clkdm_name     = "mpu_clkdm",
1075         .recalc         = &omap2_clksel_recalc,
1076 };
1077
1078 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1079 static const struct clksel_rate arm_fck_rates[] = {
1080         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1081         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1082         { .div = 0 },
1083 };
1084
1085 static const struct clksel arm_fck_clksel[] = {
1086         { .parent = &mpu_ck, .rates = arm_fck_rates },
1087         { .parent = NULL }
1088 };
1089
1090 static struct clk arm_fck = {
1091         .name           = "arm_fck",
1092         .parent         = &mpu_ck,
1093         .init           = &omap2_init_clksel_parent,
1094         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1095         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1096         .clksel         = arm_fck_clksel,
1097         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1098                                 PARENT_CONTROLS_CLOCK,
1099         .recalc         = &omap2_clksel_recalc,
1100 };
1101
1102 /* XXX What about neon_clkdm ? */
1103
1104 /*
1105  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1106  * although it is referenced - so this is a guess
1107  */
1108 static struct clk emu_mpu_alwon_ck = {
1109         .name           = "emu_mpu_alwon_ck",
1110         .parent         = &mpu_ck,
1111         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1112                                 PARENT_CONTROLS_CLOCK,
1113         .recalc         = &followparent_recalc,
1114 };
1115
1116 static struct clk dpll2_fck = {
1117         .name           = "dpll2_fck",
1118         .parent         = &core_ck,
1119         .init           = &omap2_init_clksel_parent,
1120         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1121         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1122         .clksel         = div2_core_clksel,
1123         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1124                                 PARENT_CONTROLS_CLOCK,
1125         .recalc         = &omap2_clksel_recalc,
1126 };
1127
1128 /*
1129  * IVA2 clksel:
1130  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1131  * derives from the high-frequency bypass clock originating from DPLL3,
1132  * called 'dpll2_fck'
1133  */
1134
1135 static const struct clksel iva2_clksel[] = {
1136         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1137         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1138         { .parent = NULL }
1139 };
1140
1141 static struct clk iva2_ck = {
1142         .name           = "iva2_ck",
1143         .parent         = &dpll2_m2_ck,
1144         .init           = &omap2_init_clksel_parent,
1145         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1146         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1147         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1148                                           OMAP3430_CM_IDLEST_PLL),
1149         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1150         .clksel         = iva2_clksel,
1151         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1152         .clkdm_name     = "iva2_clkdm",
1153         .recalc         = &omap2_clksel_recalc,
1154 };
1155
1156 /* Common interface clocks */
1157
1158 static struct clk l3_ick = {
1159         .name           = "l3_ick",
1160         .parent         = &core_ck,
1161         .init           = &omap2_init_clksel_parent,
1162         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1163         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1164         .clksel         = div2_core_clksel,
1165         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1166                                 PARENT_CONTROLS_CLOCK,
1167         .clkdm_name     = "core_l3_clkdm",
1168         .recalc         = &omap2_clksel_recalc,
1169 };
1170
1171 static const struct clksel div2_l3_clksel[] = {
1172         { .parent = &l3_ick, .rates = div2_rates },
1173         { .parent = NULL }
1174 };
1175
1176 static struct clk l4_ick = {
1177         .name           = "l4_ick",
1178         .parent         = &l3_ick,
1179         .init           = &omap2_init_clksel_parent,
1180         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1181         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1182         .clksel         = div2_l3_clksel,
1183         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1184                                 PARENT_CONTROLS_CLOCK,
1185         .clkdm_name     = "core_l4_clkdm",
1186         .recalc         = &omap2_clksel_recalc,
1187
1188 };
1189
1190 static const struct clksel div2_l4_clksel[] = {
1191         { .parent = &l4_ick, .rates = div2_rates },
1192         { .parent = NULL }
1193 };
1194
1195 static struct clk rm_ick = {
1196         .name           = "rm_ick",
1197         .parent         = &l4_ick,
1198         .init           = &omap2_init_clksel_parent,
1199         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1200         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1201         .clksel         = div2_l4_clksel,
1202         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1203         .recalc         = &omap2_clksel_recalc,
1204 };
1205
1206 /* GFX power domain */
1207
1208 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1209
1210 static const struct clksel gfx_l3_clksel[] = {
1211         { .parent = &l3_ick, .rates = gfx_l3_rates },
1212         { .parent = NULL }
1213 };
1214
1215 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1216 static struct clk gfx_l3_ck = {
1217         .name           = "gfx_l3_ck",
1218         .parent         = &l3_ick,
1219         .init           = &omap2_init_clksel_parent,
1220         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1221         .enable_bit     = OMAP_EN_GFX_SHIFT,
1222         .flags          = CLOCK_IN_OMAP3430ES1,
1223         .recalc         = &followparent_recalc,
1224 };
1225
1226 static struct clk gfx_l3_fck = {
1227         .name           = "gfx_l3_fck",
1228         .parent         = &gfx_l3_ck,
1229         .init           = &omap2_init_clksel_parent,
1230         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1231         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1232         .clksel         = gfx_l3_clksel,
1233         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1234                                 PARENT_CONTROLS_CLOCK,
1235         .clkdm_name     = "gfx_3430es1_clkdm",
1236         .recalc         = &omap2_clksel_recalc,
1237 };
1238
1239 static struct clk gfx_l3_ick = {
1240         .name           = "gfx_l3_ick",
1241         .parent         = &gfx_l3_ck,
1242         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1243         .clkdm_name     = "gfx_3430es1_clkdm",
1244         .recalc         = &followparent_recalc,
1245 };
1246
1247 static struct clk gfx_cg1_ck = {
1248         .name           = "gfx_cg1_ck",
1249         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1250         .init           = &omap2_init_clk_clkdm,
1251         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1252         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1253         .flags          = CLOCK_IN_OMAP3430ES1,
1254         .clkdm_name     = "gfx_3430es1_clkdm",
1255         .recalc         = &followparent_recalc,
1256 };
1257
1258 static struct clk gfx_cg2_ck = {
1259         .name           = "gfx_cg2_ck",
1260         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1261         .init           = &omap2_init_clk_clkdm,
1262         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1263         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1264         .flags          = CLOCK_IN_OMAP3430ES1,
1265         .clkdm_name     = "gfx_3430es1_clkdm",
1266         .recalc         = &followparent_recalc,
1267 };
1268
1269 /* SGX power domain - 3430ES2 only */
1270
1271 static const struct clksel_rate sgx_core_rates[] = {
1272         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1273         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1274         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1275         { .div = 0 },
1276 };
1277
1278 static const struct clksel_rate sgx_96m_rates[] = {
1279         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1280         { .div = 0 },
1281 };
1282
1283 static const struct clksel sgx_clksel[] = {
1284         { .parent = &core_ck,    .rates = sgx_core_rates },
1285         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1286         { .parent = NULL },
1287 };
1288
1289 static struct clk sgx_fck = {
1290         .name           = "sgx_fck",
1291         .init           = &omap2_init_clksel_parent,
1292         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1293         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1294         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1295         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1296         .clksel         = sgx_clksel,
1297         .flags          = CLOCK_IN_OMAP3430ES2,
1298         .clkdm_name     = "sgx_clkdm",
1299         .recalc         = &omap2_clksel_recalc,
1300 };
1301
1302 static struct clk sgx_ick = {
1303         .name           = "sgx_ick",
1304         .parent         = &l3_ick,
1305         .init           = &omap2_init_clk_clkdm,
1306         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1307         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1308         .flags          = CLOCK_IN_OMAP3430ES2,
1309         .clkdm_name     = "sgx_clkdm",
1310         .recalc         = &followparent_recalc,
1311 };
1312
1313 /* CORE power domain */
1314
1315 static struct clk d2d_26m_fck = {
1316         .name           = "d2d_26m_fck",
1317         .parent         = &sys_ck,
1318         .init           = &omap2_init_clk_clkdm,
1319         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1320         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1321         .flags          = CLOCK_IN_OMAP3430ES1,
1322         .clkdm_name     = "d2d_clkdm",
1323         .recalc         = &followparent_recalc,
1324 };
1325
1326 static const struct clksel omap343x_gpt_clksel[] = {
1327         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1328         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1329         { .parent = NULL}
1330 };
1331
1332 static struct clk gpt10_fck = {
1333         .name           = "gpt10_fck",
1334         .parent         = &sys_ck,
1335         .init           = &omap2_init_clksel_parent,
1336         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1337         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1338         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1339         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1340         .clksel         = omap343x_gpt_clksel,
1341         .flags          = CLOCK_IN_OMAP343X,
1342         .clkdm_name     = "core_l4_clkdm",
1343         .recalc         = &omap2_clksel_recalc,
1344 };
1345
1346 static struct clk gpt11_fck = {
1347         .name           = "gpt11_fck",
1348         .parent         = &sys_ck,
1349         .init           = &omap2_init_clksel_parent,
1350         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1351         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1352         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1353         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1354         .clksel         = omap343x_gpt_clksel,
1355         .flags          = CLOCK_IN_OMAP343X,
1356         .clkdm_name     = "core_l4_clkdm",
1357         .recalc         = &omap2_clksel_recalc,
1358 };
1359
1360 static struct clk cpefuse_fck = {
1361         .name           = "cpefuse_fck",
1362         .parent         = &sys_ck,
1363         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1364         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1365         .flags          = CLOCK_IN_OMAP3430ES2,
1366         .recalc         = &followparent_recalc,
1367 };
1368
1369 static struct clk ts_fck = {
1370         .name           = "ts_fck",
1371         .parent         = &omap_32k_fck,
1372         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1373         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1374         .flags          = CLOCK_IN_OMAP3430ES2,
1375         .recalc         = &followparent_recalc,
1376 };
1377
1378 static struct clk usbtll_fck = {
1379         .name           = "usbtll_fck",
1380         .parent         = &omap_120m_fck,
1381         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1382         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1383         .flags          = CLOCK_IN_OMAP3430ES2,
1384         .recalc         = &followparent_recalc,
1385 };
1386
1387 /* CORE 96M FCLK-derived clocks */
1388
1389 static struct clk core_96m_fck = {
1390         .name           = "core_96m_fck",
1391         .parent         = &omap_96m_fck,
1392         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1393                                 PARENT_CONTROLS_CLOCK,
1394         .clkdm_name     = "core_l4_clkdm",
1395         .recalc         = &followparent_recalc,
1396 };
1397
1398 static struct clk mmchs3_fck = {
1399         .name           = "mmchs_fck",
1400         .id             = 3,
1401         .parent         = &core_96m_fck,
1402         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1403         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1404         .flags          = CLOCK_IN_OMAP3430ES2,
1405         .clkdm_name     = "core_l4_clkdm",
1406         .recalc         = &followparent_recalc,
1407 };
1408
1409 static struct clk mmchs2_fck = {
1410         .name           = "mmchs_fck",
1411         .id             = 2,
1412         .parent         = &core_96m_fck,
1413         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1414         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1415         .flags          = CLOCK_IN_OMAP343X,
1416         .clkdm_name     = "core_l4_clkdm",
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 static struct clk mspro_fck = {
1421         .name           = "mspro_fck",
1422         .parent         = &core_96m_fck,
1423         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1424         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1425         .flags          = CLOCK_IN_OMAP343X,
1426         .clkdm_name     = "core_l4_clkdm",
1427         .recalc         = &followparent_recalc,
1428 };
1429
1430 static struct clk mmchs1_fck = {
1431         .name           = "mmchs_fck",
1432         .id             = 1,
1433         .parent         = &core_96m_fck,
1434         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1435         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1436         .flags          = CLOCK_IN_OMAP343X,
1437         .clkdm_name     = "core_l4_clkdm",
1438         .recalc         = &followparent_recalc,
1439 };
1440
1441 static struct clk i2c3_fck = {
1442         .name           = "i2c_fck",
1443         .id             = 3,
1444         .parent         = &core_96m_fck,
1445         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1446         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1447         .flags          = CLOCK_IN_OMAP343X,
1448         .clkdm_name     = "core_l4_clkdm",
1449         .recalc         = &followparent_recalc,
1450 };
1451
1452 static struct clk i2c2_fck = {
1453         .name           = "i2c_fck",
1454         .id             = 2,
1455         .parent         = &core_96m_fck,
1456         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1457         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1458         .flags          = CLOCK_IN_OMAP343X,
1459         .clkdm_name     = "core_l4_clkdm",
1460         .recalc         = &followparent_recalc,
1461 };
1462
1463 static struct clk i2c1_fck = {
1464         .name           = "i2c_fck",
1465         .id             = 1,
1466         .parent         = &core_96m_fck,
1467         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1468         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1469         .flags          = CLOCK_IN_OMAP343X,
1470         .clkdm_name     = "core_l4_clkdm",
1471         .recalc         = &followparent_recalc,
1472 };
1473
1474 /*
1475  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1476  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1477  */
1478 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1479         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1480         { .div = 0 }
1481 };
1482
1483 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1484         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1485         { .div = 0 }
1486 };
1487
1488 static const struct clksel mcbsp_15_clksel[] = {
1489         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1490         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1491         { .parent = NULL }
1492 };
1493
1494 static struct clk mcbsp5_fck = {
1495         .name           = "mcbsp_fck",
1496         .id             = 5,
1497         .init           = &omap2_init_clksel_parent,
1498         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1499         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1500         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1501         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1502         .clksel         = mcbsp_15_clksel,
1503         .flags          = CLOCK_IN_OMAP343X,
1504         .clkdm_name     = "core_l4_clkdm",
1505         .recalc         = &omap2_clksel_recalc,
1506 };
1507
1508 static struct clk mcbsp1_fck = {
1509         .name           = "mcbsp_fck",
1510         .id             = 1,
1511         .init           = &omap2_init_clksel_parent,
1512         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1513         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1514         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1515         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1516         .clksel         = mcbsp_15_clksel,
1517         .flags          = CLOCK_IN_OMAP343X,
1518         .clkdm_name     = "core_l4_clkdm",
1519         .recalc         = &omap2_clksel_recalc,
1520 };
1521
1522 /* CORE_48M_FCK-derived clocks */
1523
1524 static struct clk core_48m_fck = {
1525         .name           = "core_48m_fck",
1526         .parent         = &omap_48m_fck,
1527         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1528                                 PARENT_CONTROLS_CLOCK,
1529         .clkdm_name     = "core_l4_clkdm",
1530         .recalc         = &followparent_recalc,
1531 };
1532
1533 static struct clk mcspi4_fck = {
1534         .name           = "mcspi_fck",
1535         .id             = 4,
1536         .parent         = &core_48m_fck,
1537         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1538         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1539         .flags          = CLOCK_IN_OMAP343X,
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk mcspi3_fck = {
1544         .name           = "mcspi_fck",
1545         .id             = 3,
1546         .parent         = &core_48m_fck,
1547         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1548         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1549         .flags          = CLOCK_IN_OMAP343X,
1550         .recalc         = &followparent_recalc,
1551 };
1552
1553 static struct clk mcspi2_fck = {
1554         .name           = "mcspi_fck",
1555         .id             = 2,
1556         .parent         = &core_48m_fck,
1557         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1558         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1559         .flags          = CLOCK_IN_OMAP343X,
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 static struct clk mcspi1_fck = {
1564         .name           = "mcspi_fck",
1565         .id             = 1,
1566         .parent         = &core_48m_fck,
1567         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1568         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1569         .flags          = CLOCK_IN_OMAP343X,
1570         .recalc         = &followparent_recalc,
1571 };
1572
1573 static struct clk uart2_fck = {
1574         .name           = "uart2_fck",
1575         .parent         = &core_48m_fck,
1576         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1578         .flags          = CLOCK_IN_OMAP343X,
1579         .recalc         = &followparent_recalc,
1580 };
1581
1582 static struct clk uart1_fck = {
1583         .name           = "uart1_fck",
1584         .parent         = &core_48m_fck,
1585         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1587         .flags          = CLOCK_IN_OMAP343X,
1588         .recalc         = &followparent_recalc,
1589 };
1590
1591 static struct clk fshostusb_fck = {
1592         .name           = "fshostusb_fck",
1593         .parent         = &core_48m_fck,
1594         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1595         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1596         .flags          = CLOCK_IN_OMAP3430ES1,
1597         .recalc         = &followparent_recalc,
1598 };
1599
1600 /* CORE_12M_FCK based clocks */
1601
1602 static struct clk core_12m_fck = {
1603         .name           = "core_12m_fck",
1604         .parent         = &omap_12m_fck,
1605         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1606                                 PARENT_CONTROLS_CLOCK,
1607         .clkdm_name     = "core_l4_clkdm",
1608         .recalc         = &followparent_recalc,
1609 };
1610
1611 static struct clk hdq_fck = {
1612         .name           = "hdq_fck",
1613         .parent         = &core_12m_fck,
1614         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1615         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1616         .flags          = CLOCK_IN_OMAP343X,
1617         .recalc         = &followparent_recalc,
1618 };
1619
1620 /* DPLL3-derived clock */
1621
1622 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1623         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1624         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1625         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1626         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1627         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1628         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1629         { .div = 0 }
1630 };
1631
1632 static const struct clksel ssi_ssr_clksel[] = {
1633         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1634         { .parent = NULL }
1635 };
1636
1637 static struct clk ssi_ssr_fck = {
1638         .name           = "ssi_ssr_fck",
1639         .init           = &omap2_init_clksel_parent,
1640         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1641         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1642         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1643         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1644         .clksel         = ssi_ssr_clksel,
1645         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1646         .clkdm_name     = "core_l4_clkdm",
1647         .recalc         = &omap2_clksel_recalc,
1648 };
1649
1650 static struct clk ssi_sst_fck = {
1651         .name           = "ssi_sst_fck",
1652         .parent         = &ssi_ssr_fck,
1653         .fixed_div      = 2,
1654         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1655         .recalc         = &omap2_fixed_divisor_recalc,
1656 };
1657
1658
1659
1660 /* CORE_L3_ICK based clocks */
1661
1662 /*
1663  * XXX must add clk_enable/clk_disable for these if standard code won't
1664  * handle it
1665  */
1666 static struct clk core_l3_ick = {
1667         .name           = "core_l3_ick",
1668         .parent         = &l3_ick,
1669         .init           = &omap2_init_clk_clkdm,
1670         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1671                                 PARENT_CONTROLS_CLOCK,
1672         .clkdm_name     = "core_l3_clkdm",
1673         .recalc         = &followparent_recalc,
1674 };
1675
1676 static struct clk hsotgusb_ick = {
1677         .name           = "hsotgusb_ick",
1678         .parent         = &core_l3_ick,
1679         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1680         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1681         .flags          = CLOCK_IN_OMAP343X,
1682         .clkdm_name     = "core_l3_clkdm",
1683         .recalc         = &followparent_recalc,
1684 };
1685
1686 static struct clk sdrc_ick = {
1687         .name           = "sdrc_ick",
1688         .parent         = &core_l3_ick,
1689         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1690         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1691         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1692         .clkdm_name     = "core_l3_clkdm",
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 static struct clk gpmc_fck = {
1697         .name           = "gpmc_fck",
1698         .parent         = &core_l3_ick,
1699         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1700                                 ENABLE_ON_INIT,
1701         .clkdm_name     = "core_l3_clkdm",
1702         .recalc         = &followparent_recalc,
1703 };
1704
1705 /* SECURITY_L3_ICK based clocks */
1706
1707 static struct clk security_l3_ick = {
1708         .name           = "security_l3_ick",
1709         .parent         = &l3_ick,
1710         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1711                                 PARENT_CONTROLS_CLOCK,
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 static struct clk pka_ick = {
1716         .name           = "pka_ick",
1717         .parent         = &security_l3_ick,
1718         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1719         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1720         .flags          = CLOCK_IN_OMAP343X,
1721         .recalc         = &followparent_recalc,
1722 };
1723
1724 /* CORE_L4_ICK based clocks */
1725
1726 static struct clk core_l4_ick = {
1727         .name           = "core_l4_ick",
1728         .parent         = &l4_ick,
1729         .init           = &omap2_init_clk_clkdm,
1730         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1731                                 PARENT_CONTROLS_CLOCK,
1732         .clkdm_name     = "core_l4_clkdm",
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static struct clk usbtll_ick = {
1737         .name           = "usbtll_ick",
1738         .parent         = &core_l4_ick,
1739         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1740         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1741         .flags          = CLOCK_IN_OMAP3430ES2,
1742         .clkdm_name     = "core_l4_clkdm",
1743         .recalc         = &followparent_recalc,
1744 };
1745
1746 static struct clk mmchs3_ick = {
1747         .name           = "mmchs_ick",
1748         .id             = 3,
1749         .parent         = &core_l4_ick,
1750         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1751         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1752         .flags          = CLOCK_IN_OMAP3430ES2,
1753         .clkdm_name     = "core_l4_clkdm",
1754         .recalc         = &followparent_recalc,
1755 };
1756
1757 /* Intersystem Communication Registers - chassis mode only */
1758 static struct clk icr_ick = {
1759         .name           = "icr_ick",
1760         .parent         = &core_l4_ick,
1761         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1762         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1763         .flags          = CLOCK_IN_OMAP343X,
1764         .clkdm_name     = "core_l4_clkdm",
1765         .recalc         = &followparent_recalc,
1766 };
1767
1768 static struct clk aes2_ick = {
1769         .name           = "aes2_ick",
1770         .parent         = &core_l4_ick,
1771         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1772         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1773         .flags          = CLOCK_IN_OMAP343X,
1774         .clkdm_name     = "core_l4_clkdm",
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 static struct clk sha12_ick = {
1779         .name           = "sha12_ick",
1780         .parent         = &core_l4_ick,
1781         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1782         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1783         .flags          = CLOCK_IN_OMAP343X,
1784         .clkdm_name     = "core_l4_clkdm",
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk des2_ick = {
1789         .name           = "des2_ick",
1790         .parent         = &core_l4_ick,
1791         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1792         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1793         .flags          = CLOCK_IN_OMAP343X,
1794         .clkdm_name     = "core_l4_clkdm",
1795         .recalc         = &followparent_recalc,
1796 };
1797
1798 static struct clk mmchs2_ick = {
1799         .name           = "mmchs_ick",
1800         .id             = 2,
1801         .parent         = &core_l4_ick,
1802         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1803         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1804         .flags          = CLOCK_IN_OMAP343X,
1805         .clkdm_name     = "core_l4_clkdm",
1806         .recalc         = &followparent_recalc,
1807 };
1808
1809 static struct clk mmchs1_ick = {
1810         .name           = "mmchs_ick",
1811         .id             = 1,
1812         .parent         = &core_l4_ick,
1813         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1814         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1815         .flags          = CLOCK_IN_OMAP343X,
1816         .clkdm_name     = "core_l4_clkdm",
1817         .recalc         = &followparent_recalc,
1818 };
1819
1820 static struct clk mspro_ick = {
1821         .name           = "mspro_ick",
1822         .parent         = &core_l4_ick,
1823         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1824         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1825         .flags          = CLOCK_IN_OMAP343X,
1826         .clkdm_name     = "core_l4_clkdm",
1827         .recalc         = &followparent_recalc,
1828 };
1829
1830 static struct clk hdq_ick = {
1831         .name           = "hdq_ick",
1832         .parent         = &core_l4_ick,
1833         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1834         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1835         .flags          = CLOCK_IN_OMAP343X,
1836         .clkdm_name     = "core_l4_clkdm",
1837         .recalc         = &followparent_recalc,
1838 };
1839
1840 static struct clk mcspi4_ick = {
1841         .name           = "mcspi_ick",
1842         .id             = 4,
1843         .parent         = &core_l4_ick,
1844         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1845         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1846         .flags          = CLOCK_IN_OMAP343X,
1847         .clkdm_name     = "core_l4_clkdm",
1848         .recalc         = &followparent_recalc,
1849 };
1850
1851 static struct clk mcspi3_ick = {
1852         .name           = "mcspi_ick",
1853         .id             = 3,
1854         .parent         = &core_l4_ick,
1855         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1856         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1857         .flags          = CLOCK_IN_OMAP343X,
1858         .clkdm_name     = "core_l4_clkdm",
1859         .recalc         = &followparent_recalc,
1860 };
1861
1862 static struct clk mcspi2_ick = {
1863         .name           = "mcspi_ick",
1864         .id             = 2,
1865         .parent         = &core_l4_ick,
1866         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1868         .flags          = CLOCK_IN_OMAP343X,
1869         .clkdm_name     = "core_l4_clkdm",
1870         .recalc         = &followparent_recalc,
1871 };
1872
1873 static struct clk mcspi1_ick = {
1874         .name           = "mcspi_ick",
1875         .id             = 1,
1876         .parent         = &core_l4_ick,
1877         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1878         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1879         .flags          = CLOCK_IN_OMAP343X,
1880         .clkdm_name     = "core_l4_clkdm",
1881         .recalc         = &followparent_recalc,
1882 };
1883
1884 static struct clk i2c3_ick = {
1885         .name           = "i2c_ick",
1886         .id             = 3,
1887         .parent         = &core_l4_ick,
1888         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1889         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1890         .flags          = CLOCK_IN_OMAP343X,
1891         .clkdm_name     = "core_l4_clkdm",
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk i2c2_ick = {
1896         .name           = "i2c_ick",
1897         .id             = 2,
1898         .parent         = &core_l4_ick,
1899         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1900         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1901         .flags          = CLOCK_IN_OMAP343X,
1902         .clkdm_name     = "core_l4_clkdm",
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk i2c1_ick = {
1907         .name           = "i2c_ick",
1908         .id             = 1,
1909         .parent         = &core_l4_ick,
1910         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1911         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1912         .flags          = CLOCK_IN_OMAP343X,
1913         .clkdm_name     = "core_l4_clkdm",
1914         .recalc         = &followparent_recalc,
1915 };
1916
1917 static struct clk uart2_ick = {
1918         .name           = "uart2_ick",
1919         .parent         = &core_l4_ick,
1920         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1922         .flags          = CLOCK_IN_OMAP343X,
1923         .clkdm_name     = "core_l4_clkdm",
1924         .recalc         = &followparent_recalc,
1925 };
1926
1927 static struct clk uart1_ick = {
1928         .name           = "uart1_ick",
1929         .parent         = &core_l4_ick,
1930         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1931         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1932         .flags          = CLOCK_IN_OMAP343X,
1933         .clkdm_name     = "core_l4_clkdm",
1934         .recalc         = &followparent_recalc,
1935 };
1936
1937 static struct clk gpt11_ick = {
1938         .name           = "gpt11_ick",
1939         .parent         = &core_l4_ick,
1940         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1942         .flags          = CLOCK_IN_OMAP343X,
1943         .clkdm_name     = "core_l4_clkdm",
1944         .recalc         = &followparent_recalc,
1945 };
1946
1947 static struct clk gpt10_ick = {
1948         .name           = "gpt10_ick",
1949         .parent         = &core_l4_ick,
1950         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1951         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1952         .flags          = CLOCK_IN_OMAP343X,
1953         .clkdm_name     = "core_l4_clkdm",
1954         .recalc         = &followparent_recalc,
1955 };
1956
1957 static struct clk mcbsp5_ick = {
1958         .name           = "mcbsp_ick",
1959         .id             = 5,
1960         .parent         = &core_l4_ick,
1961         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1962         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1963         .flags          = CLOCK_IN_OMAP343X,
1964         .clkdm_name     = "core_l4_clkdm",
1965         .recalc         = &followparent_recalc,
1966 };
1967
1968 static struct clk mcbsp1_ick = {
1969         .name           = "mcbsp_ick",
1970         .id             = 1,
1971         .parent         = &core_l4_ick,
1972         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1974         .flags          = CLOCK_IN_OMAP343X,
1975         .clkdm_name     = "core_l4_clkdm",
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk fac_ick = {
1980         .name           = "fac_ick",
1981         .parent         = &core_l4_ick,
1982         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1984         .flags          = CLOCK_IN_OMAP3430ES1,
1985         .clkdm_name     = "core_l4_clkdm",
1986         .recalc         = &followparent_recalc,
1987 };
1988
1989 static struct clk mailboxes_ick = {
1990         .name           = "mailboxes_ick",
1991         .parent         = &core_l4_ick,
1992         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1994         .flags          = CLOCK_IN_OMAP343X,
1995         .clkdm_name     = "core_l4_clkdm",
1996         .recalc         = &followparent_recalc,
1997 };
1998
1999 static struct clk omapctrl_ick = {
2000         .name           = "omapctrl_ick",
2001         .parent         = &core_l4_ick,
2002         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2004         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 /* SSI_L4_ICK based clocks */
2009
2010 static struct clk ssi_l4_ick = {
2011         .name           = "ssi_l4_ick",
2012         .parent         = &l4_ick,
2013         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2014                                 PARENT_CONTROLS_CLOCK,
2015         .clkdm_name     = "core_l4_clkdm",
2016         .recalc         = &followparent_recalc,
2017 };
2018
2019 static struct clk ssi_ick = {
2020         .name           = "ssi_ick",
2021         .parent         = &ssi_l4_ick,
2022         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2023         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2024         .flags          = CLOCK_IN_OMAP343X,
2025         .clkdm_name     = "core_l4_clkdm",
2026         .recalc         = &followparent_recalc,
2027 };
2028
2029 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2030  * but l4_ick makes more sense to me */
2031
2032 static const struct clksel usb_l4_clksel[] = {
2033         { .parent = &l4_ick, .rates = div2_rates },
2034         { .parent = NULL },
2035 };
2036
2037 static struct clk usb_l4_ick = {
2038         .name           = "usb_l4_ick",
2039         .parent         = &l4_ick,
2040         .init           = &omap2_init_clksel_parent,
2041         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2042         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2043         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2044         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2045         .clksel         = usb_l4_clksel,
2046         .flags          = CLOCK_IN_OMAP3430ES1,
2047         .recalc         = &omap2_clksel_recalc,
2048 };
2049
2050 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2051
2052 /* SECURITY_L4_ICK2 based clocks */
2053
2054 static struct clk security_l4_ick2 = {
2055         .name           = "security_l4_ick2",
2056         .parent         = &l4_ick,
2057         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2058                                 PARENT_CONTROLS_CLOCK,
2059         .recalc         = &followparent_recalc,
2060 };
2061
2062 static struct clk aes1_ick = {
2063         .name           = "aes1_ick",
2064         .parent         = &security_l4_ick2,
2065         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2066         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2067         .flags          = CLOCK_IN_OMAP343X,
2068         .recalc         = &followparent_recalc,
2069 };
2070
2071 static struct clk rng_ick = {
2072         .name           = "rng_ick",
2073         .parent         = &security_l4_ick2,
2074         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2075         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2076         .flags          = CLOCK_IN_OMAP343X,
2077         .recalc         = &followparent_recalc,
2078 };
2079
2080 static struct clk sha11_ick = {
2081         .name           = "sha11_ick",
2082         .parent         = &security_l4_ick2,
2083         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2084         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2085         .flags          = CLOCK_IN_OMAP343X,
2086         .recalc         = &followparent_recalc,
2087 };
2088
2089 static struct clk des1_ick = {
2090         .name           = "des1_ick",
2091         .parent         = &security_l4_ick2,
2092         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2093         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2094         .flags          = CLOCK_IN_OMAP343X,
2095         .recalc         = &followparent_recalc,
2096 };
2097
2098 /* DSS */
2099 static const struct clksel dss1_alwon_fck_clksel[] = {
2100         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2101         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2102         { .parent = NULL }
2103 };
2104
2105 static struct clk dss1_alwon_fck = {
2106         .name           = "dss1_alwon_fck",
2107         .parent         = &dpll4_m4x2_ck,
2108         .init           = &omap2_init_clksel_parent,
2109         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2110         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2111         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2112         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2113         .clksel         = dss1_alwon_fck_clksel,
2114         .flags          = CLOCK_IN_OMAP343X,
2115         .clkdm_name     = "dss_clkdm",
2116         .recalc         = &omap2_clksel_recalc,
2117 };
2118
2119 static struct clk dss_tv_fck = {
2120         .name           = "dss_tv_fck",
2121         .parent         = &omap_54m_fck,
2122         .init           = &omap2_init_clk_clkdm,
2123         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2124         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2125         .flags          = CLOCK_IN_OMAP343X,
2126         .clkdm_name     = "dss_clkdm",
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 static struct clk dss_96m_fck = {
2131         .name           = "dss_96m_fck",
2132         .parent         = &omap_96m_fck,
2133         .init           = &omap2_init_clk_clkdm,
2134         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2135         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2136         .flags          = CLOCK_IN_OMAP343X,
2137         .clkdm_name     = "dss_clkdm",
2138         .recalc         = &followparent_recalc,
2139 };
2140
2141 static struct clk dss2_alwon_fck = {
2142         .name           = "dss2_alwon_fck",
2143         .parent         = &sys_ck,
2144         .init           = &omap2_init_clk_clkdm,
2145         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2146         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2147         .flags          = CLOCK_IN_OMAP343X,
2148         .clkdm_name     = "dss_clkdm",
2149         .recalc         = &followparent_recalc,
2150 };
2151
2152 static struct clk dss_ick = {
2153         /* Handles both L3 and L4 clocks */
2154         .name           = "dss_ick",
2155         .parent         = &l4_ick,
2156         .init           = &omap2_init_clk_clkdm,
2157         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2158         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2159         .flags          = CLOCK_IN_OMAP343X,
2160         .clkdm_name     = "dss_clkdm",
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 /* CAM */
2165
2166 static const struct clksel cam_mclk_clksel[] = {
2167         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2168         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2169         { .parent = NULL }
2170 };
2171
2172 static struct clk cam_mclk = {
2173         .name           = "cam_mclk",
2174         .parent         = &dpll4_m5x2_ck,
2175         .init           = &omap2_init_clksel_parent,
2176         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2177         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2178         .clksel         = cam_mclk_clksel,
2179         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2180         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2181         .flags          = CLOCK_IN_OMAP343X,
2182         .clkdm_name     = "cam_clkdm",
2183         .recalc         = &omap2_clksel_recalc,
2184 };
2185
2186 static struct clk cam_ick = {
2187         /* Handles both L3 and L4 clocks */
2188         .name           = "cam_ick",
2189         .parent         = &l4_ick,
2190         .init           = &omap2_init_clk_clkdm,
2191         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2192         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2193         .flags          = CLOCK_IN_OMAP343X,
2194         .clkdm_name     = "cam_clkdm",
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 /* USBHOST - 3430ES2 only */
2199
2200 static struct clk usbhost_120m_fck = {
2201         .name           = "usbhost_120m_fck",
2202         .parent         = &omap_120m_fck,
2203         .init           = &omap2_init_clk_clkdm,
2204         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2205         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2206         .flags          = CLOCK_IN_OMAP3430ES2,
2207         .clkdm_name     = "usbhost_clkdm",
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk usbhost_48m_fck = {
2212         .name           = "usbhost_48m_fck",
2213         .parent         = &omap_48m_fck,
2214         .init           = &omap2_init_clk_clkdm,
2215         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2216         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2217         .flags          = CLOCK_IN_OMAP3430ES2,
2218         .clkdm_name     = "usbhost_clkdm",
2219         .recalc         = &followparent_recalc,
2220 };
2221
2222 static struct clk usbhost_ick = {
2223         /* Handles both L3 and L4 clocks */
2224         .name           = "usbhost_ick",
2225         .parent         = &l4_ick,
2226         .init           = &omap2_init_clk_clkdm,
2227         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2228         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2229         .flags          = CLOCK_IN_OMAP3430ES2,
2230         .clkdm_name     = "usbhost_clkdm",
2231         .recalc         = &followparent_recalc,
2232 };
2233
2234 /* WKUP */
2235
2236 static const struct clksel_rate usim_96m_rates[] = {
2237         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2238         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2239         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2240         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2241         { .div = 0 },
2242 };
2243
2244 static const struct clksel_rate usim_120m_rates[] = {
2245         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2246         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2247         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2248         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2249         { .div = 0 },
2250 };
2251
2252 static const struct clksel usim_clksel[] = {
2253         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2254         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2255         { .parent = &sys_ck,            .rates = div2_rates },
2256         { .parent = NULL },
2257 };
2258
2259 /* 3430ES2 only */
2260 static struct clk usim_fck = {
2261         .name           = "usim_fck",
2262         .init           = &omap2_init_clksel_parent,
2263         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2264         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2265         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2266         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2267         .clksel         = usim_clksel,
2268         .flags          = CLOCK_IN_OMAP3430ES2,
2269         .recalc         = &omap2_clksel_recalc,
2270 };
2271
2272 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2273 static struct clk gpt1_fck = {
2274         .name           = "gpt1_fck",
2275         .init           = &omap2_init_clksel_parent,
2276         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2277         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2278         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2279         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2280         .clksel         = omap343x_gpt_clksel,
2281         .flags          = CLOCK_IN_OMAP343X,
2282         .clkdm_name     = "wkup_clkdm",
2283         .recalc         = &omap2_clksel_recalc,
2284 };
2285
2286 static struct clk wkup_32k_fck = {
2287         .name           = "wkup_32k_fck",
2288         .init           = &omap2_init_clk_clkdm,
2289         .parent         = &omap_32k_fck,
2290         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2291         .clkdm_name     = "wkup_clkdm",
2292         .recalc         = &followparent_recalc,
2293 };
2294
2295 static struct clk gpio1_fck = {
2296         .name           = "gpio1_fck",
2297         .parent         = &wkup_32k_fck,
2298         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2299         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2300         .flags          = CLOCK_IN_OMAP343X,
2301         .clkdm_name     = "wkup_clkdm",
2302         .recalc         = &followparent_recalc,
2303 };
2304
2305 static struct clk wdt2_fck = {
2306         .name           = "wdt2_fck",
2307         .parent         = &wkup_32k_fck,
2308         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2309         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2310         .flags          = CLOCK_IN_OMAP343X,
2311         .clkdm_name     = "wkup_clkdm",
2312         .recalc         = &followparent_recalc,
2313 };
2314
2315 static struct clk wkup_l4_ick = {
2316         .name           = "wkup_l4_ick",
2317         .parent         = &sys_ck,
2318         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2319         .clkdm_name     = "wkup_clkdm",
2320         .recalc         = &followparent_recalc,
2321 };
2322
2323 /* 3430ES2 only */
2324 /* Never specifically named in the TRM, so we have to infer a likely name */
2325 static struct clk usim_ick = {
2326         .name           = "usim_ick",
2327         .parent         = &wkup_l4_ick,
2328         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2329         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2330         .flags          = CLOCK_IN_OMAP3430ES2,
2331         .clkdm_name     = "wkup_clkdm",
2332         .recalc         = &followparent_recalc,
2333 };
2334
2335 static struct clk wdt2_ick = {
2336         .name           = "wdt2_ick",
2337         .parent         = &wkup_l4_ick,
2338         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2339         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2340         .flags          = CLOCK_IN_OMAP343X,
2341         .clkdm_name     = "wkup_clkdm",
2342         .recalc         = &followparent_recalc,
2343 };
2344
2345 static struct clk wdt1_ick = {
2346         .name           = "wdt1_ick",
2347         .parent         = &wkup_l4_ick,
2348         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2349         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2350         .flags          = CLOCK_IN_OMAP343X,
2351         .clkdm_name     = "wkup_clkdm",
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk gpio1_ick = {
2356         .name           = "gpio1_ick",
2357         .parent         = &wkup_l4_ick,
2358         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2359         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2360         .flags          = CLOCK_IN_OMAP343X,
2361         .clkdm_name     = "wkup_clkdm",
2362         .recalc         = &followparent_recalc,
2363 };
2364
2365 static struct clk omap_32ksync_ick = {
2366         .name           = "omap_32ksync_ick",
2367         .parent         = &wkup_l4_ick,
2368         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2369         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2370         .flags          = CLOCK_IN_OMAP343X,
2371         .clkdm_name     = "wkup_clkdm",
2372         .recalc         = &followparent_recalc,
2373 };
2374
2375 /* XXX This clock no longer exists in 3430 TRM rev F */
2376 static struct clk gpt12_ick = {
2377         .name           = "gpt12_ick",
2378         .parent         = &wkup_l4_ick,
2379         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2380         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2381         .flags          = CLOCK_IN_OMAP343X,
2382         .clkdm_name     = "wkup_clkdm",
2383         .recalc         = &followparent_recalc,
2384 };
2385
2386 static struct clk gpt1_ick = {
2387         .name           = "gpt1_ick",
2388         .parent         = &wkup_l4_ick,
2389         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2390         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2391         .flags          = CLOCK_IN_OMAP343X,
2392         .clkdm_name     = "wkup_clkdm",
2393         .recalc         = &followparent_recalc,
2394 };
2395
2396
2397
2398 /* PER clock domain */
2399
2400 static struct clk per_96m_fck = {
2401         .name           = "per_96m_fck",
2402         .parent         = &omap_96m_alwon_fck,
2403         .init           = &omap2_init_clk_clkdm,
2404         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2405                                 PARENT_CONTROLS_CLOCK,
2406         .clkdm_name     = "per_clkdm",
2407         .recalc         = &followparent_recalc,
2408 };
2409
2410 static struct clk per_48m_fck = {
2411         .name           = "per_48m_fck",
2412         .parent         = &omap_48m_fck,
2413         .init           = &omap2_init_clk_clkdm,
2414         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2415                                 PARENT_CONTROLS_CLOCK,
2416         .clkdm_name     = "per_clkdm",
2417         .recalc         = &followparent_recalc,
2418 };
2419
2420 static struct clk uart3_fck = {
2421         .name           = "uart3_fck",
2422         .parent         = &per_48m_fck,
2423         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2424         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2425         .flags          = CLOCK_IN_OMAP343X,
2426         .clkdm_name     = "per_clkdm",
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk gpt2_fck = {
2431         .name           = "gpt2_fck",
2432         .init           = &omap2_init_clksel_parent,
2433         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2434         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2435         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2436         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2437         .clksel         = omap343x_gpt_clksel,
2438         .flags          = CLOCK_IN_OMAP343X,
2439         .clkdm_name     = "per_clkdm",
2440         .recalc         = &omap2_clksel_recalc,
2441 };
2442
2443 static struct clk gpt3_fck = {
2444         .name           = "gpt3_fck",
2445         .init           = &omap2_init_clksel_parent,
2446         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2447         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2448         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2449         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2450         .clksel         = omap343x_gpt_clksel,
2451         .flags          = CLOCK_IN_OMAP343X,
2452         .clkdm_name     = "per_clkdm",
2453         .recalc         = &omap2_clksel_recalc,
2454 };
2455
2456 static struct clk gpt4_fck = {
2457         .name           = "gpt4_fck",
2458         .init           = &omap2_init_clksel_parent,
2459         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2460         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2461         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2462         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2463         .clksel         = omap343x_gpt_clksel,
2464         .flags          = CLOCK_IN_OMAP343X,
2465         .clkdm_name     = "per_clkdm",
2466         .recalc         = &omap2_clksel_recalc,
2467 };
2468
2469 static struct clk gpt5_fck = {
2470         .name           = "gpt5_fck",
2471         .init           = &omap2_init_clksel_parent,
2472         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2473         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2474         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2475         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2476         .clksel         = omap343x_gpt_clksel,
2477         .flags          = CLOCK_IN_OMAP343X,
2478         .clkdm_name     = "per_clkdm",
2479         .recalc         = &omap2_clksel_recalc,
2480 };
2481
2482 static struct clk gpt6_fck = {
2483         .name           = "gpt6_fck",
2484         .init           = &omap2_init_clksel_parent,
2485         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2486         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2487         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2488         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2489         .clksel         = omap343x_gpt_clksel,
2490         .flags          = CLOCK_IN_OMAP343X,
2491         .clkdm_name     = "per_clkdm",
2492         .recalc         = &omap2_clksel_recalc,
2493 };
2494
2495 static struct clk gpt7_fck = {
2496         .name           = "gpt7_fck",
2497         .init           = &omap2_init_clksel_parent,
2498         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2499         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2500         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2501         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2502         .clksel         = omap343x_gpt_clksel,
2503         .flags          = CLOCK_IN_OMAP343X,
2504         .clkdm_name     = "per_clkdm",
2505         .recalc         = &omap2_clksel_recalc,
2506 };
2507
2508 static struct clk gpt8_fck = {
2509         .name           = "gpt8_fck",
2510         .init           = &omap2_init_clksel_parent,
2511         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2512         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2513         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2514         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2515         .clksel         = omap343x_gpt_clksel,
2516         .flags          = CLOCK_IN_OMAP343X,
2517         .clkdm_name     = "per_clkdm",
2518         .recalc         = &omap2_clksel_recalc,
2519 };
2520
2521 static struct clk gpt9_fck = {
2522         .name           = "gpt9_fck",
2523         .init           = &omap2_init_clksel_parent,
2524         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2525         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2526         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2527         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2528         .clksel         = omap343x_gpt_clksel,
2529         .flags          = CLOCK_IN_OMAP343X,
2530         .clkdm_name     = "per_clkdm",
2531         .recalc         = &omap2_clksel_recalc,
2532 };
2533
2534 static struct clk per_32k_alwon_fck = {
2535         .name           = "per_32k_alwon_fck",
2536         .parent         = &omap_32k_fck,
2537         .clkdm_name     = "per_clkdm",
2538         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2539         .recalc         = &followparent_recalc,
2540 };
2541
2542 static struct clk gpio6_fck = {
2543         .name           = "gpio6_fck",
2544         .parent         = &per_32k_alwon_fck,
2545         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2546         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2547         .flags          = CLOCK_IN_OMAP343X,
2548         .clkdm_name     = "per_clkdm",
2549         .recalc         = &followparent_recalc,
2550 };
2551
2552 static struct clk gpio5_fck = {
2553         .name           = "gpio5_fck",
2554         .parent         = &per_32k_alwon_fck,
2555         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2556         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2557         .flags          = CLOCK_IN_OMAP343X,
2558         .clkdm_name     = "per_clkdm",
2559         .recalc         = &followparent_recalc,
2560 };
2561
2562 static struct clk gpio4_fck = {
2563         .name           = "gpio4_fck",
2564         .parent         = &per_32k_alwon_fck,
2565         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2566         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2567         .flags          = CLOCK_IN_OMAP343X,
2568         .clkdm_name     = "per_clkdm",
2569         .recalc         = &followparent_recalc,
2570 };
2571
2572 static struct clk gpio3_fck = {
2573         .name           = "gpio3_fck",
2574         .parent         = &per_32k_alwon_fck,
2575         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2576         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2577         .flags          = CLOCK_IN_OMAP343X,
2578         .clkdm_name     = "per_clkdm",
2579         .recalc         = &followparent_recalc,
2580 };
2581
2582 static struct clk gpio2_fck = {
2583         .name           = "gpio2_fck",
2584         .parent         = &per_32k_alwon_fck,
2585         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2586         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2587         .flags          = CLOCK_IN_OMAP343X,
2588         .clkdm_name     = "per_clkdm",
2589         .recalc         = &followparent_recalc,
2590 };
2591
2592 static struct clk wdt3_fck = {
2593         .name           = "wdt3_fck",
2594         .parent         = &per_32k_alwon_fck,
2595         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2596         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2597         .flags          = CLOCK_IN_OMAP343X,
2598         .clkdm_name     = "per_clkdm",
2599         .recalc         = &followparent_recalc,
2600 };
2601
2602 static struct clk per_l4_ick = {
2603         .name           = "per_l4_ick",
2604         .parent         = &l4_ick,
2605         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2606                                 PARENT_CONTROLS_CLOCK,
2607         .clkdm_name     = "per_clkdm",
2608         .recalc         = &followparent_recalc,
2609 };
2610
2611 static struct clk gpio6_ick = {
2612         .name           = "gpio6_ick",
2613         .parent         = &per_l4_ick,
2614         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2615         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2616         .flags          = CLOCK_IN_OMAP343X,
2617         .clkdm_name     = "per_clkdm",
2618         .recalc         = &followparent_recalc,
2619 };
2620
2621 static struct clk gpio5_ick = {
2622         .name           = "gpio5_ick",
2623         .parent         = &per_l4_ick,
2624         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2625         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2626         .flags          = CLOCK_IN_OMAP343X,
2627         .clkdm_name     = "per_clkdm",
2628         .recalc         = &followparent_recalc,
2629 };
2630
2631 static struct clk gpio4_ick = {
2632         .name           = "gpio4_ick",
2633         .parent         = &per_l4_ick,
2634         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2635         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2636         .flags          = CLOCK_IN_OMAP343X,
2637         .clkdm_name     = "per_clkdm",
2638         .recalc         = &followparent_recalc,
2639 };
2640
2641 static struct clk gpio3_ick = {
2642         .name           = "gpio3_ick",
2643         .parent         = &per_l4_ick,
2644         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2645         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2646         .flags          = CLOCK_IN_OMAP343X,
2647         .clkdm_name     = "per_clkdm",
2648         .recalc         = &followparent_recalc,
2649 };
2650
2651 static struct clk gpio2_ick = {
2652         .name           = "gpio2_ick",
2653         .parent         = &per_l4_ick,
2654         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2655         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2656         .flags          = CLOCK_IN_OMAP343X,
2657         .clkdm_name     = "per_clkdm",
2658         .recalc         = &followparent_recalc,
2659 };
2660
2661 static struct clk wdt3_ick = {
2662         .name           = "wdt3_ick",
2663         .parent         = &per_l4_ick,
2664         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2665         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2666         .flags          = CLOCK_IN_OMAP343X,
2667         .clkdm_name     = "per_clkdm",
2668         .recalc         = &followparent_recalc,
2669 };
2670
2671 static struct clk uart3_ick = {
2672         .name           = "uart3_ick",
2673         .parent         = &per_l4_ick,
2674         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2675         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2676         .flags          = CLOCK_IN_OMAP343X,
2677         .clkdm_name     = "per_clkdm",
2678         .recalc         = &followparent_recalc,
2679 };
2680
2681 static struct clk gpt9_ick = {
2682         .name           = "gpt9_ick",
2683         .parent         = &per_l4_ick,
2684         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2685         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2686         .flags          = CLOCK_IN_OMAP343X,
2687         .clkdm_name     = "per_clkdm",
2688         .recalc         = &followparent_recalc,
2689 };
2690
2691 static struct clk gpt8_ick = {
2692         .name           = "gpt8_ick",
2693         .parent         = &per_l4_ick,
2694         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2695         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2696         .flags          = CLOCK_IN_OMAP343X,
2697         .clkdm_name     = "per_clkdm",
2698         .recalc         = &followparent_recalc,
2699 };
2700
2701 static struct clk gpt7_ick = {
2702         .name           = "gpt7_ick",
2703         .parent         = &per_l4_ick,
2704         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2705         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2706         .flags          = CLOCK_IN_OMAP343X,
2707         .clkdm_name     = "per_clkdm",
2708         .recalc         = &followparent_recalc,
2709 };
2710
2711 static struct clk gpt6_ick = {
2712         .name           = "gpt6_ick",
2713         .parent         = &per_l4_ick,
2714         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2715         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2716         .flags          = CLOCK_IN_OMAP343X,
2717         .clkdm_name     = "per_clkdm",
2718         .recalc         = &followparent_recalc,
2719 };
2720
2721 static struct clk gpt5_ick = {
2722         .name           = "gpt5_ick",
2723         .parent         = &per_l4_ick,
2724         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2725         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2726         .flags          = CLOCK_IN_OMAP343X,
2727         .clkdm_name     = "per_clkdm",
2728         .recalc         = &followparent_recalc,
2729 };
2730
2731 static struct clk gpt4_ick = {
2732         .name           = "gpt4_ick",
2733         .parent         = &per_l4_ick,
2734         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2735         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2736         .flags          = CLOCK_IN_OMAP343X,
2737         .clkdm_name     = "per_clkdm",
2738         .recalc         = &followparent_recalc,
2739 };
2740
2741 static struct clk gpt3_ick = {
2742         .name           = "gpt3_ick",
2743         .parent         = &per_l4_ick,
2744         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2745         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2746         .flags          = CLOCK_IN_OMAP343X,
2747         .clkdm_name     = "per_clkdm",
2748         .recalc         = &followparent_recalc,
2749 };
2750
2751 static struct clk gpt2_ick = {
2752         .name           = "gpt2_ick",
2753         .parent         = &per_l4_ick,
2754         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2755         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2756         .flags          = CLOCK_IN_OMAP343X,
2757         .clkdm_name     = "per_clkdm",
2758         .recalc         = &followparent_recalc,
2759 };
2760
2761 static struct clk mcbsp2_ick = {
2762         .name           = "mcbsp_ick",
2763         .id             = 2,
2764         .parent         = &per_l4_ick,
2765         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2766         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2767         .flags          = CLOCK_IN_OMAP343X,
2768         .clkdm_name     = "per_clkdm",
2769         .recalc         = &followparent_recalc,
2770 };
2771
2772 static struct clk mcbsp3_ick = {
2773         .name           = "mcbsp_ick",
2774         .id             = 3,
2775         .parent         = &per_l4_ick,
2776         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2777         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2778         .flags          = CLOCK_IN_OMAP343X,
2779         .clkdm_name     = "per_clkdm",
2780         .recalc         = &followparent_recalc,
2781 };
2782
2783 static struct clk mcbsp4_ick = {
2784         .name           = "mcbsp_ick",
2785         .id             = 4,
2786         .parent         = &per_l4_ick,
2787         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2788         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2789         .flags          = CLOCK_IN_OMAP343X,
2790         .clkdm_name     = "per_clkdm",
2791         .recalc         = &followparent_recalc,
2792 };
2793
2794 static const struct clksel mcbsp_234_clksel[] = {
2795         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2796         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2797         { .parent = NULL }
2798 };
2799
2800 static struct clk mcbsp2_fck = {
2801         .name           = "mcbsp_fck",
2802         .id             = 2,
2803         .init           = &omap2_init_clksel_parent,
2804         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2805         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2806         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2807         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2808         .clksel         = mcbsp_234_clksel,
2809         .flags          = CLOCK_IN_OMAP343X,
2810         .clkdm_name     = "per_clkdm",
2811         .recalc         = &omap2_clksel_recalc,
2812 };
2813
2814 static struct clk mcbsp3_fck = {
2815         .name           = "mcbsp_fck",
2816         .id             = 3,
2817         .init           = &omap2_init_clksel_parent,
2818         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2819         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2820         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2821         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2822         .clksel         = mcbsp_234_clksel,
2823         .flags          = CLOCK_IN_OMAP343X,
2824         .clkdm_name     = "per_clkdm",
2825         .recalc         = &omap2_clksel_recalc,
2826 };
2827
2828 static struct clk mcbsp4_fck = {
2829         .name           = "mcbsp_fck",
2830         .id             = 4,
2831         .init           = &omap2_init_clksel_parent,
2832         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2833         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2834         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2835         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2836         .clksel         = mcbsp_234_clksel,
2837         .flags          = CLOCK_IN_OMAP343X,
2838         .clkdm_name     = "per_clkdm",
2839         .recalc         = &omap2_clksel_recalc,
2840 };
2841
2842 /* EMU clocks */
2843
2844 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2845
2846 static const struct clksel_rate emu_src_sys_rates[] = {
2847         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2848         { .div = 0 },
2849 };
2850
2851 static const struct clksel_rate emu_src_core_rates[] = {
2852         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2853         { .div = 0 },
2854 };
2855
2856 static const struct clksel_rate emu_src_per_rates[] = {
2857         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2858         { .div = 0 },
2859 };
2860
2861 static const struct clksel_rate emu_src_mpu_rates[] = {
2862         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2863         { .div = 0 },
2864 };
2865
2866 static const struct clksel emu_src_clksel[] = {
2867         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2868         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2869         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2870         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2871         { .parent = NULL },
2872 };
2873
2874 /*
2875  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2876  * to switch the source of some of the EMU clocks.
2877  * XXX Are there CLKEN bits for these EMU clks?
2878  */
2879 static struct clk emu_src_ck = {
2880         .name           = "emu_src_ck",
2881         .init           = &omap2_init_clksel_parent,
2882         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2883         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2884         .clksel         = emu_src_clksel,
2885         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2886         .clkdm_name     = "emu_clkdm",
2887         .recalc         = &omap2_clksel_recalc,
2888 };
2889
2890 static const struct clksel_rate pclk_emu_rates[] = {
2891         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2892         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2893         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2894         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2895         { .div = 0 },
2896 };
2897
2898 static const struct clksel pclk_emu_clksel[] = {
2899         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2900         { .parent = NULL },
2901 };
2902
2903 static struct clk pclk_fck = {
2904         .name           = "pclk_fck",
2905         .init           = &omap2_init_clksel_parent,
2906         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2907         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2908         .clksel         = pclk_emu_clksel,
2909         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2910         .clkdm_name     = "emu_clkdm",
2911         .recalc         = &omap2_clksel_recalc,
2912 };
2913
2914 static const struct clksel_rate pclkx2_emu_rates[] = {
2915         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2916         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2917         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2918         { .div = 0 },
2919 };
2920
2921 static const struct clksel pclkx2_emu_clksel[] = {
2922         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2923         { .parent = NULL },
2924 };
2925
2926 static struct clk pclkx2_fck = {
2927         .name           = "pclkx2_fck",
2928         .init           = &omap2_init_clksel_parent,
2929         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2930         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2931         .clksel         = pclkx2_emu_clksel,
2932         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2933         .clkdm_name     = "emu_clkdm",
2934         .recalc         = &omap2_clksel_recalc,
2935 };
2936
2937 static const struct clksel atclk_emu_clksel[] = {
2938         { .parent = &emu_src_ck, .rates = div2_rates },
2939         { .parent = NULL },
2940 };
2941
2942 static struct clk atclk_fck = {
2943         .name           = "atclk_fck",
2944         .init           = &omap2_init_clksel_parent,
2945         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2946         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2947         .clksel         = atclk_emu_clksel,
2948         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2949         .clkdm_name     = "emu_clkdm",
2950         .recalc         = &omap2_clksel_recalc,
2951 };
2952
2953 static struct clk traceclk_src_fck = {
2954         .name           = "traceclk_src_fck",
2955         .init           = &omap2_init_clksel_parent,
2956         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2957         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2958         .clksel         = emu_src_clksel,
2959         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2960         .clkdm_name     = "emu_clkdm",
2961         .recalc         = &omap2_clksel_recalc,
2962 };
2963
2964 static const struct clksel_rate traceclk_rates[] = {
2965         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2966         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2967         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2968         { .div = 0 },
2969 };
2970
2971 static const struct clksel traceclk_clksel[] = {
2972         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2973         { .parent = NULL },
2974 };
2975
2976 static struct clk traceclk_fck = {
2977         .name           = "traceclk_fck",
2978         .init           = &omap2_init_clksel_parent,
2979         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2980         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2981         .clksel         = traceclk_clksel,
2982         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2983         .clkdm_name     = "emu_clkdm",
2984         .recalc         = &omap2_clksel_recalc,
2985 };
2986
2987 /* SR clocks */
2988
2989 /* SmartReflex fclk (VDD1) */
2990 static struct clk sr1_fck = {
2991         .name           = "sr1_fck",
2992         .parent         = &sys_ck,
2993         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2994         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2995         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2996         .recalc         = &followparent_recalc,
2997 };
2998
2999 /* SmartReflex fclk (VDD2) */
3000 static struct clk sr2_fck = {
3001         .name           = "sr2_fck",
3002         .parent         = &sys_ck,
3003         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3004         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3005         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3006         .recalc         = &followparent_recalc,
3007 };
3008
3009 static struct clk sr_l4_ick = {
3010         .name           = "sr_l4_ick",
3011         .parent         = &l4_ick,
3012         .flags          = CLOCK_IN_OMAP343X,
3013         .clkdm_name     = "core_l4_clkdm",
3014         .recalc         = &followparent_recalc,
3015 };
3016
3017 /* SECURE_32K_FCK clocks */
3018
3019 /* XXX This clock no longer exists in 3430 TRM rev F */
3020 static struct clk gpt12_fck = {
3021         .name           = "gpt12_fck",
3022         .parent         = &secure_32k_fck,
3023         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3024         .recalc         = &followparent_recalc,
3025 };
3026
3027 static struct clk wdt1_fck = {
3028         .name           = "wdt1_fck",
3029         .parent         = &secure_32k_fck,
3030         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3031         .recalc         = &followparent_recalc,
3032 };
3033
3034 static struct clk *onchip_34xx_clks[] __initdata = {
3035         &omap_32k_fck,
3036         &virt_12m_ck,
3037         &virt_13m_ck,
3038         &virt_16_8m_ck,
3039         &virt_19_2m_ck,
3040         &virt_26m_ck,
3041         &virt_38_4m_ck,
3042         &osc_sys_ck,
3043         &sys_ck,
3044         &sys_altclk,
3045         &mcbsp_clks,
3046         &sys_clkout1,
3047         &dpll1_ck,
3048         &dpll1_x2_ck,
3049         &dpll1_x2m2_ck,
3050         &dpll2_ck,
3051         &dpll2_m2_ck,
3052         &dpll3_ck,
3053         &core_ck,
3054         &dpll3_x2_ck,
3055         &dpll3_m2_ck,
3056         &dpll3_m2x2_ck,
3057         &dpll3_m3_ck,
3058         &dpll3_m3x2_ck,
3059         &emu_core_alwon_ck,
3060         &dpll4_ck,
3061         &dpll4_x2_ck,
3062         &omap_96m_alwon_fck,
3063         &omap_96m_fck,
3064         &cm_96m_fck,
3065         &virt_omap_54m_fck,
3066         &omap_54m_fck,
3067         &omap_48m_fck,
3068         &omap_12m_fck,
3069         &dpll4_m2_ck,
3070         &dpll4_m2x2_ck,
3071         &dpll4_m3_ck,
3072         &dpll4_m3x2_ck,
3073         &dpll4_m4_ck,
3074         &dpll4_m4x2_ck,
3075         &dpll4_m5_ck,
3076         &dpll4_m5x2_ck,
3077         &dpll4_m6_ck,
3078         &dpll4_m6x2_ck,
3079         &emu_per_alwon_ck,
3080         &dpll5_ck,
3081         &dpll5_m2_ck,
3082         &omap_120m_fck,
3083         &clkout2_src_ck,
3084         &sys_clkout2,
3085         &corex2_fck,
3086         &dpll1_fck,
3087         &mpu_ck,
3088         &arm_fck,
3089         &emu_mpu_alwon_ck,
3090         &dpll2_fck,
3091         &iva2_ck,
3092         &l3_ick,
3093         &l4_ick,
3094         &rm_ick,
3095         &gfx_l3_ck,
3096         &gfx_l3_fck,
3097         &gfx_l3_ick,
3098         &gfx_cg1_ck,
3099         &gfx_cg2_ck,
3100         &sgx_fck,
3101         &sgx_ick,
3102         &d2d_26m_fck,
3103         &gpt10_fck,
3104         &gpt11_fck,
3105         &cpefuse_fck,
3106         &ts_fck,
3107         &usbtll_fck,
3108         &core_96m_fck,
3109         &mmchs3_fck,
3110         &mmchs2_fck,
3111         &mspro_fck,
3112         &mmchs1_fck,
3113         &i2c3_fck,
3114         &i2c2_fck,
3115         &i2c1_fck,
3116         &mcbsp5_fck,
3117         &mcbsp1_fck,
3118         &core_48m_fck,
3119         &mcspi4_fck,
3120         &mcspi3_fck,
3121         &mcspi2_fck,
3122         &mcspi1_fck,
3123         &uart2_fck,
3124         &uart1_fck,
3125         &fshostusb_fck,
3126         &core_12m_fck,
3127         &hdq_fck,
3128         &ssi_ssr_fck,
3129         &ssi_sst_fck,
3130         &core_l3_ick,
3131         &hsotgusb_ick,
3132         &sdrc_ick,
3133         &gpmc_fck,
3134         &security_l3_ick,
3135         &pka_ick,
3136         &core_l4_ick,
3137         &usbtll_ick,
3138         &mmchs3_ick,
3139         &icr_ick,
3140         &aes2_ick,
3141         &sha12_ick,
3142         &des2_ick,
3143         &mmchs2_ick,
3144         &mmchs1_ick,
3145         &mspro_ick,
3146         &hdq_ick,
3147         &mcspi4_ick,
3148         &mcspi3_ick,
3149         &mcspi2_ick,
3150         &mcspi1_ick,
3151         &i2c3_ick,
3152         &i2c2_ick,
3153         &i2c1_ick,
3154         &uart2_ick,
3155         &uart1_ick,
3156         &gpt11_ick,
3157         &gpt10_ick,
3158         &mcbsp5_ick,
3159         &mcbsp1_ick,
3160         &fac_ick,
3161         &mailboxes_ick,
3162         &omapctrl_ick,
3163         &ssi_l4_ick,
3164         &ssi_ick,
3165         &usb_l4_ick,
3166         &security_l4_ick2,
3167         &aes1_ick,
3168         &rng_ick,
3169         &sha11_ick,
3170         &des1_ick,
3171         &dss1_alwon_fck,
3172         &dss_tv_fck,
3173         &dss_96m_fck,
3174         &dss2_alwon_fck,
3175         &dss_ick,
3176         &cam_mclk,
3177         &cam_ick,
3178         &usbhost_120m_fck,
3179         &usbhost_48m_fck,
3180         &usbhost_ick,
3181         &usim_fck,
3182         &gpt1_fck,
3183         &wkup_32k_fck,
3184         &gpio1_fck,
3185         &wdt2_fck,
3186         &wkup_l4_ick,
3187         &usim_ick,
3188         &wdt2_ick,
3189         &wdt1_ick,
3190         &gpio1_ick,
3191         &omap_32ksync_ick,
3192         &gpt12_ick,
3193         &gpt1_ick,
3194         &per_96m_fck,
3195         &per_48m_fck,
3196         &uart3_fck,
3197         &gpt2_fck,
3198         &gpt3_fck,
3199         &gpt4_fck,
3200         &gpt5_fck,
3201         &gpt6_fck,
3202         &gpt7_fck,
3203         &gpt8_fck,
3204         &gpt9_fck,
3205         &per_32k_alwon_fck,
3206         &gpio6_fck,
3207         &gpio5_fck,
3208         &gpio4_fck,
3209         &gpio3_fck,
3210         &gpio2_fck,
3211         &wdt3_fck,
3212         &per_l4_ick,
3213         &gpio6_ick,
3214         &gpio5_ick,
3215         &gpio4_ick,
3216         &gpio3_ick,
3217         &gpio2_ick,
3218         &wdt3_ick,
3219         &uart3_ick,
3220         &gpt9_ick,
3221         &gpt8_ick,
3222         &gpt7_ick,
3223         &gpt6_ick,
3224         &gpt5_ick,
3225         &gpt4_ick,
3226         &gpt3_ick,
3227         &gpt2_ick,
3228         &mcbsp2_ick,
3229         &mcbsp3_ick,
3230         &mcbsp4_ick,
3231         &mcbsp2_fck,
3232         &mcbsp3_fck,
3233         &mcbsp4_fck,
3234         &emu_src_ck,
3235         &pclk_fck,
3236         &pclkx2_fck,
3237         &atclk_fck,
3238         &traceclk_src_fck,
3239         &traceclk_fck,
3240         &sr1_fck,
3241         &sr2_fck,
3242         &sr_l4_ick,
3243         &secure_32k_fck,
3244         &gpt12_fck,
3245         &wdt1_fck,
3246 };
3247
3248 #endif