2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
38 /* Maximum DPLL multiplier, divider values for OMAP3 */
39 #define OMAP3_MAX_DPLL_MULT 2048
40 #define OMAP3_MAX_DPLL_DIV 128
43 * DPLL1 supplies clock to the MPU.
44 * DPLL2 supplies clock to the IVA2.
45 * DPLL3 supplies CORE domain clocks.
46 * DPLL4 supplies peripheral clocks.
47 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
51 #define DPLL_LOW_POWER_STOP 0x1
52 #define DPLL_LOW_POWER_BYPASS 0x5
53 #define DPLL_LOCKED 0x7
57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
58 static struct clk omap_32k_fck = {
59 .name = "omap_32k_fck",
62 .flags = RATE_FIXED | RATE_PROPAGATES,
65 static struct clk secure_32k_fck = {
66 .name = "secure_32k_fck",
69 .flags = RATE_FIXED | RATE_PROPAGATES,
72 /* Virtual source clocks for osc_sys_ck */
73 static struct clk virt_12m_ck = {
74 .name = "virt_12m_ck",
77 .flags = RATE_FIXED | RATE_PROPAGATES,
80 static struct clk virt_13m_ck = {
81 .name = "virt_13m_ck",
84 .flags = RATE_FIXED | RATE_PROPAGATES,
87 static struct clk virt_16_8m_ck = {
88 .name = "virt_16_8m_ck",
91 .flags = RATE_FIXED | RATE_PROPAGATES,
94 static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
98 .flags = RATE_FIXED | RATE_PROPAGATES,
101 static struct clk virt_26m_ck = {
102 .name = "virt_26m_ck",
105 .flags = RATE_FIXED | RATE_PROPAGATES,
108 static struct clk virt_38_4m_ck = {
109 .name = "virt_38_4m_ck",
112 .flags = RATE_FIXED | RATE_PROPAGATES,
115 static const struct clksel_rate osc_sys_12m_rates[] = {
116 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
120 static const struct clksel_rate osc_sys_13m_rates[] = {
121 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
126 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
131 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
135 static const struct clksel_rate osc_sys_26m_rates[] = {
136 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
141 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
145 static const struct clksel osc_sys_clksel[] = {
146 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
147 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
148 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
149 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
150 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
151 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
155 /* Oscillator clock */
156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
157 static struct clk osc_sys_ck = {
158 .name = "osc_sys_ck",
160 .init = &omap2_init_clksel_parent,
161 .clksel_reg = OMAP3430_PRM_CLKSEL,
162 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
163 .clksel = osc_sys_clksel,
164 /* REVISIT: deal with autoextclkmode? */
165 .flags = RATE_FIXED | RATE_PROPAGATES,
166 .recalc = &omap2_clksel_recalc,
169 static const struct clksel_rate div2_rates[] = {
170 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
171 { .div = 2, .val = 2, .flags = RATE_IN_343X },
175 static const struct clksel sys_clksel[] = {
176 { .parent = &osc_sys_ck, .rates = div2_rates },
180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
182 static struct clk sys_ck = {
185 .parent = &osc_sys_ck,
186 .init = &omap2_init_clksel_parent,
187 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
188 .clksel_mask = OMAP_SYSCLKDIV_MASK,
189 .clksel = sys_clksel,
190 .flags = RATE_PROPAGATES,
191 .recalc = &omap2_clksel_recalc,
194 static struct clk sys_altclk = {
195 .name = "sys_altclk",
197 .flags = RATE_PROPAGATES,
200 /* Optional external clock input for some McBSPs */
201 static struct clk mcbsp_clks = {
202 .name = "mcbsp_clks",
204 .flags = RATE_PROPAGATES,
207 /* PRM EXTERNAL CLOCK OUTPUT */
209 static struct clk sys_clkout1 = {
210 .name = "sys_clkout1",
211 .ops = &clkops_omap2_dflt,
212 .parent = &osc_sys_ck,
213 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
214 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
215 .recalc = &followparent_recalc,
222 static const struct clksel_rate dpll_bypass_rates[] = {
223 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
227 static const struct clksel_rate dpll_locked_rates[] = {
228 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
232 static const struct clksel_rate div16_dpll_rates[] = {
233 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
234 { .div = 2, .val = 2, .flags = RATE_IN_343X },
235 { .div = 3, .val = 3, .flags = RATE_IN_343X },
236 { .div = 4, .val = 4, .flags = RATE_IN_343X },
237 { .div = 5, .val = 5, .flags = RATE_IN_343X },
238 { .div = 6, .val = 6, .flags = RATE_IN_343X },
239 { .div = 7, .val = 7, .flags = RATE_IN_343X },
240 { .div = 8, .val = 8, .flags = RATE_IN_343X },
241 { .div = 9, .val = 9, .flags = RATE_IN_343X },
242 { .div = 10, .val = 10, .flags = RATE_IN_343X },
243 { .div = 11, .val = 11, .flags = RATE_IN_343X },
244 { .div = 12, .val = 12, .flags = RATE_IN_343X },
245 { .div = 13, .val = 13, .flags = RATE_IN_343X },
246 { .div = 14, .val = 14, .flags = RATE_IN_343X },
247 { .div = 15, .val = 15, .flags = RATE_IN_343X },
248 { .div = 16, .val = 16, .flags = RATE_IN_343X },
253 /* MPU clock source */
255 static struct dpll_data dpll1_dd = {
256 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
257 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
258 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
259 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
260 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
261 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
262 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
263 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
264 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
265 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
266 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
267 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
268 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
269 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT,
270 .max_multiplier = OMAP3_MAX_DPLL_MULT,
271 .max_divider = OMAP3_MAX_DPLL_DIV,
272 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
275 static struct clk dpll1_ck = {
279 .dpll_data = &dpll1_dd,
280 .flags = RATE_PROPAGATES,
281 .round_rate = &omap2_dpll_round_rate,
282 .set_rate = &omap3_noncore_dpll_set_rate,
283 .recalc = &omap3_dpll_recalc,
287 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
288 * DPLL isn't bypassed.
290 static struct clk dpll1_x2_ck = {
291 .name = "dpll1_x2_ck",
294 .flags = RATE_PROPAGATES,
295 .recalc = &omap3_clkoutx2_recalc,
298 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
299 static const struct clksel div16_dpll1_x2m2_clksel[] = {
300 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
305 * Does not exist in the TRM - needed to separate the M2 divider from
306 * bypass selection in mpu_ck
308 static struct clk dpll1_x2m2_ck = {
309 .name = "dpll1_x2m2_ck",
311 .parent = &dpll1_x2_ck,
312 .init = &omap2_init_clksel_parent,
313 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
314 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
315 .clksel = div16_dpll1_x2m2_clksel,
316 .flags = RATE_PROPAGATES,
317 .recalc = &omap2_clksel_recalc,
321 /* IVA2 clock source */
324 static struct dpll_data dpll2_dd = {
325 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
326 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
327 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
328 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
329 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
330 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
331 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
332 (1 << DPLL_LOW_POWER_BYPASS),
333 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
334 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
335 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
336 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
337 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
338 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
339 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT,
340 .max_multiplier = OMAP3_MAX_DPLL_MULT,
341 .max_divider = OMAP3_MAX_DPLL_DIV,
342 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
345 static struct clk dpll2_ck = {
347 .ops = &clkops_noncore_dpll_ops,
349 .dpll_data = &dpll2_dd,
350 .flags = RATE_PROPAGATES,
351 .round_rate = &omap2_dpll_round_rate,
352 .set_rate = &omap3_noncore_dpll_set_rate,
353 .recalc = &omap3_dpll_recalc,
356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
357 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
362 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
363 * or CLKOUTX2. CLKOUT seems most plausible.
365 static struct clk dpll2_m2_ck = {
366 .name = "dpll2_m2_ck",
369 .init = &omap2_init_clksel_parent,
370 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
371 OMAP3430_CM_CLKSEL2_PLL),
372 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
373 .clksel = div16_dpll2_m2x2_clksel,
374 .flags = RATE_PROPAGATES,
375 .recalc = &omap2_clksel_recalc,
380 * Source clock for all interfaces and for some device fclks
381 * REVISIT: Also supports fast relock bypass - not included below
383 static struct dpll_data dpll3_dd = {
384 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
385 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
386 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
387 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
388 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
389 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
390 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
391 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
392 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
393 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
394 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
395 .max_multiplier = OMAP3_MAX_DPLL_MULT,
396 .max_divider = OMAP3_MAX_DPLL_DIV,
397 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
400 static struct clk dpll3_ck = {
404 .dpll_data = &dpll3_dd,
405 .flags = RATE_PROPAGATES,
406 .round_rate = &omap2_dpll_round_rate,
407 .recalc = &omap3_dpll_recalc,
411 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
412 * DPLL isn't bypassed
414 static struct clk dpll3_x2_ck = {
415 .name = "dpll3_x2_ck",
418 .flags = RATE_PROPAGATES,
419 .recalc = &omap3_clkoutx2_recalc,
422 static const struct clksel_rate div31_dpll3_rates[] = {
423 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
424 { .div = 2, .val = 2, .flags = RATE_IN_343X },
425 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
426 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
427 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
428 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
429 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
430 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
431 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
432 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
433 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
434 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
435 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
436 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
437 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
438 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
439 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
440 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
441 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
442 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
443 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
444 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
445 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
446 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
447 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
448 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
449 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
450 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
451 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
452 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
453 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
457 static const struct clksel div31_dpll3m2_clksel[] = {
458 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
464 * REVISIT: This DPLL output divider must be changed in SRAM, so until
465 * that code is ready, this should remain a 'read-only' clksel clock.
467 static struct clk dpll3_m2_ck = {
468 .name = "dpll3_m2_ck",
471 .init = &omap2_init_clksel_parent,
472 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
473 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
474 .clksel = div31_dpll3m2_clksel,
475 .flags = RATE_PROPAGATES,
476 .recalc = &omap2_clksel_recalc,
479 static const struct clksel core_ck_clksel[] = {
480 { .parent = &sys_ck, .rates = dpll_bypass_rates },
481 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
485 static struct clk core_ck = {
488 .init = &omap2_init_clksel_parent,
489 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
490 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
491 .clksel = core_ck_clksel,
492 .flags = RATE_PROPAGATES,
493 .recalc = &omap2_clksel_recalc,
496 static const struct clksel dpll3_m2x2_ck_clksel[] = {
497 { .parent = &sys_ck, .rates = dpll_bypass_rates },
498 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
502 static struct clk dpll3_m2x2_ck = {
503 .name = "dpll3_m2x2_ck",
505 .init = &omap2_init_clksel_parent,
506 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
507 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
508 .clksel = dpll3_m2x2_ck_clksel,
509 .flags = RATE_PROPAGATES,
510 .recalc = &omap2_clksel_recalc,
513 /* The PWRDN bit is apparently only available on 3430ES2 and above */
514 static const struct clksel div16_dpll3_clksel[] = {
515 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
519 /* This virtual clock is the source for dpll3_m3x2_ck */
520 static struct clk dpll3_m3_ck = {
521 .name = "dpll3_m3_ck",
524 .init = &omap2_init_clksel_parent,
525 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
526 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
527 .clksel = div16_dpll3_clksel,
528 .flags = RATE_PROPAGATES,
529 .recalc = &omap2_clksel_recalc,
532 /* The PWRDN bit is apparently only available on 3430ES2 and above */
533 static struct clk dpll3_m3x2_ck = {
534 .name = "dpll3_m3x2_ck",
535 .ops = &clkops_omap2_dflt_wait,
536 .parent = &dpll3_m3_ck,
537 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
538 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
539 .flags = RATE_PROPAGATES | INVERT_ENABLE,
540 .recalc = &omap3_clkoutx2_recalc,
543 static const struct clksel emu_core_alwon_ck_clksel[] = {
544 { .parent = &sys_ck, .rates = dpll_bypass_rates },
545 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
549 static struct clk emu_core_alwon_ck = {
550 .name = "emu_core_alwon_ck",
552 .parent = &dpll3_m3x2_ck,
553 .init = &omap2_init_clksel_parent,
554 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
555 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
556 .clksel = emu_core_alwon_ck_clksel,
557 .flags = RATE_PROPAGATES,
558 .recalc = &omap2_clksel_recalc,
562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
564 static struct dpll_data dpll4_dd = {
565 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
566 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
567 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
568 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
569 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
570 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
571 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
572 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
573 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
574 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
575 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
576 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
577 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
578 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT,
579 .max_multiplier = OMAP3_MAX_DPLL_MULT,
580 .max_divider = OMAP3_MAX_DPLL_DIV,
581 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
584 static struct clk dpll4_ck = {
586 .ops = &clkops_noncore_dpll_ops,
588 .dpll_data = &dpll4_dd,
589 .flags = RATE_PROPAGATES,
590 .round_rate = &omap2_dpll_round_rate,
591 .set_rate = &omap3_dpll4_set_rate,
592 .recalc = &omap3_dpll_recalc,
596 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
597 * DPLL isn't bypassed --
598 * XXX does this serve any downstream clocks?
600 static struct clk dpll4_x2_ck = {
601 .name = "dpll4_x2_ck",
604 .flags = RATE_PROPAGATES,
605 .recalc = &omap3_clkoutx2_recalc,
608 static const struct clksel div16_dpll4_clksel[] = {
609 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
613 /* This virtual clock is the source for dpll4_m2x2_ck */
614 static struct clk dpll4_m2_ck = {
615 .name = "dpll4_m2_ck",
618 .init = &omap2_init_clksel_parent,
619 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
620 .clksel_mask = OMAP3430_DIV_96M_MASK,
621 .clksel = div16_dpll4_clksel,
622 .flags = RATE_PROPAGATES,
623 .recalc = &omap2_clksel_recalc,
626 /* The PWRDN bit is apparently only available on 3430ES2 and above */
627 static struct clk dpll4_m2x2_ck = {
628 .name = "dpll4_m2x2_ck",
629 .ops = &clkops_omap2_dflt_wait,
630 .parent = &dpll4_m2_ck,
631 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
632 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
633 .flags = RATE_PROPAGATES | INVERT_ENABLE,
634 .recalc = &omap3_clkoutx2_recalc,
637 static const struct clksel omap_96m_alwon_fck_clksel[] = {
638 { .parent = &sys_ck, .rates = dpll_bypass_rates },
639 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
644 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
645 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
646 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
649 static struct clk omap_96m_alwon_fck = {
650 .name = "omap_96m_alwon_fck",
652 .parent = &dpll4_m2x2_ck,
653 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
656 .clksel = omap_96m_alwon_fck_clksel,
657 .flags = RATE_PROPAGATES,
658 .recalc = &omap2_clksel_recalc,
661 static struct clk cm_96m_fck = {
662 .name = "cm_96m_fck",
664 .parent = &omap_96m_alwon_fck,
665 .flags = RATE_PROPAGATES,
666 .recalc = &followparent_recalc,
669 static const struct clksel_rate omap_96m_dpll_rates[] = {
670 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
674 static const struct clksel_rate omap_96m_sys_rates[] = {
675 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
679 static const struct clksel omap_96m_fck_clksel[] = {
680 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
681 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
685 static struct clk omap_96m_fck = {
686 .name = "omap_96m_fck",
689 .init = &omap2_init_clksel_parent,
690 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
691 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
692 .clksel = omap_96m_fck_clksel,
693 .flags = RATE_PROPAGATES,
694 .recalc = &omap2_clksel_recalc,
697 /* This virtual clock is the source for dpll4_m3x2_ck */
698 static struct clk dpll4_m3_ck = {
699 .name = "dpll4_m3_ck",
702 .init = &omap2_init_clksel_parent,
703 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
704 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
705 .clksel = div16_dpll4_clksel,
706 .flags = RATE_PROPAGATES,
707 .recalc = &omap2_clksel_recalc,
710 /* The PWRDN bit is apparently only available on 3430ES2 and above */
711 static struct clk dpll4_m3x2_ck = {
712 .name = "dpll4_m3x2_ck",
713 .ops = &clkops_omap2_dflt_wait,
714 .parent = &dpll4_m3_ck,
715 .init = &omap2_init_clksel_parent,
716 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
717 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
718 .flags = RATE_PROPAGATES | INVERT_ENABLE,
719 .recalc = &omap3_clkoutx2_recalc,
722 static const struct clksel virt_omap_54m_fck_clksel[] = {
723 { .parent = &sys_ck, .rates = dpll_bypass_rates },
724 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
728 static struct clk virt_omap_54m_fck = {
729 .name = "virt_omap_54m_fck",
731 .parent = &dpll4_m3x2_ck,
732 .init = &omap2_init_clksel_parent,
733 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
734 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
735 .clksel = virt_omap_54m_fck_clksel,
736 .flags = RATE_PROPAGATES,
737 .recalc = &omap2_clksel_recalc,
740 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
741 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
745 static const struct clksel_rate omap_54m_alt_rates[] = {
746 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
750 static const struct clksel omap_54m_clksel[] = {
751 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
752 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
756 static struct clk omap_54m_fck = {
757 .name = "omap_54m_fck",
759 .init = &omap2_init_clksel_parent,
760 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
761 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
762 .clksel = omap_54m_clksel,
763 .flags = RATE_PROPAGATES,
764 .recalc = &omap2_clksel_recalc,
767 static const struct clksel_rate omap_48m_cm96m_rates[] = {
768 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
772 static const struct clksel_rate omap_48m_alt_rates[] = {
773 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
777 static const struct clksel omap_48m_clksel[] = {
778 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
779 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
783 static struct clk omap_48m_fck = {
784 .name = "omap_48m_fck",
786 .init = &omap2_init_clksel_parent,
787 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
788 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
789 .clksel = omap_48m_clksel,
790 .flags = RATE_PROPAGATES,
791 .recalc = &omap2_clksel_recalc,
794 static struct clk omap_12m_fck = {
795 .name = "omap_12m_fck",
797 .parent = &omap_48m_fck,
799 .flags = RATE_PROPAGATES,
800 .recalc = &omap2_fixed_divisor_recalc,
803 /* This virstual clock is the source for dpll4_m4x2_ck */
804 static struct clk dpll4_m4_ck = {
805 .name = "dpll4_m4_ck",
808 .init = &omap2_init_clksel_parent,
809 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
810 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
811 .clksel = div16_dpll4_clksel,
812 .flags = RATE_PROPAGATES,
813 .recalc = &omap2_clksel_recalc,
816 /* The PWRDN bit is apparently only available on 3430ES2 and above */
817 static struct clk dpll4_m4x2_ck = {
818 .name = "dpll4_m4x2_ck",
819 .ops = &clkops_omap2_dflt_wait,
820 .parent = &dpll4_m4_ck,
821 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
822 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
823 .flags = RATE_PROPAGATES | INVERT_ENABLE,
824 .recalc = &omap3_clkoutx2_recalc,
827 /* This virtual clock is the source for dpll4_m5x2_ck */
828 static struct clk dpll4_m5_ck = {
829 .name = "dpll4_m5_ck",
832 .init = &omap2_init_clksel_parent,
833 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
834 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
835 .clksel = div16_dpll4_clksel,
836 .flags = RATE_PROPAGATES,
837 .recalc = &omap2_clksel_recalc,
840 /* The PWRDN bit is apparently only available on 3430ES2 and above */
841 static struct clk dpll4_m5x2_ck = {
842 .name = "dpll4_m5x2_ck",
843 .ops = &clkops_omap2_dflt_wait,
844 .parent = &dpll4_m5_ck,
845 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
846 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
847 .flags = RATE_PROPAGATES | INVERT_ENABLE,
848 .recalc = &omap3_clkoutx2_recalc,
851 /* This virtual clock is the source for dpll4_m6x2_ck */
852 static struct clk dpll4_m6_ck = {
853 .name = "dpll4_m6_ck",
856 .init = &omap2_init_clksel_parent,
857 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
858 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
859 .clksel = div16_dpll4_clksel,
860 .flags = RATE_PROPAGATES,
861 .recalc = &omap2_clksel_recalc,
864 /* The PWRDN bit is apparently only available on 3430ES2 and above */
865 static struct clk dpll4_m6x2_ck = {
866 .name = "dpll4_m6x2_ck",
867 .ops = &clkops_omap2_dflt_wait,
868 .parent = &dpll4_m6_ck,
869 .init = &omap2_init_clksel_parent,
870 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
871 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
872 .flags = RATE_PROPAGATES | INVERT_ENABLE,
873 .recalc = &omap3_clkoutx2_recalc,
876 static struct clk emu_per_alwon_ck = {
877 .name = "emu_per_alwon_ck",
879 .parent = &dpll4_m6x2_ck,
880 .flags = RATE_PROPAGATES,
881 .recalc = &followparent_recalc,
885 /* Supplies 120MHz clock, USIM source clock */
888 static struct dpll_data dpll5_dd = {
889 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
890 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
891 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
892 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
893 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
894 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
895 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
896 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
897 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
898 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
899 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
900 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
901 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
902 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
903 .max_multiplier = OMAP3_MAX_DPLL_MULT,
904 .max_divider = OMAP3_MAX_DPLL_DIV,
905 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
908 static struct clk dpll5_ck = {
910 .ops = &clkops_noncore_dpll_ops,
912 .dpll_data = &dpll5_dd,
913 .flags = RATE_PROPAGATES,
914 .round_rate = &omap2_dpll_round_rate,
915 .set_rate = &omap3_noncore_dpll_set_rate,
916 .recalc = &omap3_dpll_recalc,
919 static const struct clksel div16_dpll5_clksel[] = {
920 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
924 static struct clk dpll5_m2_ck = {
925 .name = "dpll5_m2_ck",
928 .init = &omap2_init_clksel_parent,
929 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
930 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
931 .clksel = div16_dpll5_clksel,
932 .flags = RATE_PROPAGATES,
933 .recalc = &omap2_clksel_recalc,
936 static const struct clksel omap_120m_fck_clksel[] = {
937 { .parent = &sys_ck, .rates = dpll_bypass_rates },
938 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
942 static struct clk omap_120m_fck = {
943 .name = "omap_120m_fck",
945 .parent = &dpll5_m2_ck,
946 .init = &omap2_init_clksel_parent,
947 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
948 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
949 .clksel = omap_120m_fck_clksel,
950 .flags = RATE_PROPAGATES,
951 .recalc = &omap2_clksel_recalc,
954 /* CM EXTERNAL CLOCK OUTPUTS */
956 static const struct clksel_rate clkout2_src_core_rates[] = {
957 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
961 static const struct clksel_rate clkout2_src_sys_rates[] = {
962 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
966 static const struct clksel_rate clkout2_src_96m_rates[] = {
967 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
971 static const struct clksel_rate clkout2_src_54m_rates[] = {
972 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
976 static const struct clksel clkout2_src_clksel[] = {
977 { .parent = &core_ck, .rates = clkout2_src_core_rates },
978 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
979 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
980 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
984 static struct clk clkout2_src_ck = {
985 .name = "clkout2_src_ck",
986 .ops = &clkops_omap2_dflt,
987 .init = &omap2_init_clksel_parent,
988 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
989 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
990 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
991 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
992 .clksel = clkout2_src_clksel,
993 .flags = RATE_PROPAGATES,
994 .recalc = &omap2_clksel_recalc,
997 static const struct clksel_rate sys_clkout2_rates[] = {
998 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
999 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1000 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1001 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1002 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1006 static const struct clksel sys_clkout2_clksel[] = {
1007 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1011 static struct clk sys_clkout2 = {
1012 .name = "sys_clkout2",
1013 .ops = &clkops_null,
1014 .init = &omap2_init_clksel_parent,
1015 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1016 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1017 .clksel = sys_clkout2_clksel,
1018 .recalc = &omap2_clksel_recalc,
1021 /* CM OUTPUT CLOCKS */
1023 static struct clk corex2_fck = {
1024 .name = "corex2_fck",
1025 .ops = &clkops_null,
1026 .parent = &dpll3_m2x2_ck,
1027 .flags = RATE_PROPAGATES,
1028 .recalc = &followparent_recalc,
1031 /* DPLL power domain clock controls */
1033 static const struct clksel div2_core_clksel[] = {
1034 { .parent = &core_ck, .rates = div2_rates },
1039 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1040 * may be inconsistent here?
1042 static struct clk dpll1_fck = {
1043 .name = "dpll1_fck",
1044 .ops = &clkops_null,
1046 .init = &omap2_init_clksel_parent,
1047 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1048 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1049 .clksel = div2_core_clksel,
1050 .flags = RATE_PROPAGATES,
1051 .recalc = &omap2_clksel_recalc,
1056 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1057 * derives from the high-frequency bypass clock originating from DPLL3,
1058 * called 'dpll1_fck'
1060 static const struct clksel mpu_clksel[] = {
1061 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1062 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1066 static struct clk mpu_ck = {
1068 .ops = &clkops_null,
1069 .parent = &dpll1_x2m2_ck,
1070 .init = &omap2_init_clksel_parent,
1071 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1073 .clksel = mpu_clksel,
1074 .flags = RATE_PROPAGATES,
1075 .clkdm_name = "mpu_clkdm",
1076 .recalc = &omap2_clksel_recalc,
1079 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1080 static const struct clksel_rate arm_fck_rates[] = {
1081 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1082 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1086 static const struct clksel arm_fck_clksel[] = {
1087 { .parent = &mpu_ck, .rates = arm_fck_rates },
1091 static struct clk arm_fck = {
1093 .ops = &clkops_null,
1095 .init = &omap2_init_clksel_parent,
1096 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1097 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1098 .clksel = arm_fck_clksel,
1099 .flags = RATE_PROPAGATES,
1100 .recalc = &omap2_clksel_recalc,
1103 /* XXX What about neon_clkdm ? */
1106 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1107 * although it is referenced - so this is a guess
1109 static struct clk emu_mpu_alwon_ck = {
1110 .name = "emu_mpu_alwon_ck",
1111 .ops = &clkops_null,
1113 .flags = RATE_PROPAGATES,
1114 .recalc = &followparent_recalc,
1117 static struct clk dpll2_fck = {
1118 .name = "dpll2_fck",
1119 .ops = &clkops_null,
1121 .init = &omap2_init_clksel_parent,
1122 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1123 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1124 .clksel = div2_core_clksel,
1125 .flags = RATE_PROPAGATES,
1126 .recalc = &omap2_clksel_recalc,
1131 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1132 * derives from the high-frequency bypass clock originating from DPLL3,
1133 * called 'dpll2_fck'
1136 static const struct clksel iva2_clksel[] = {
1137 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1138 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1142 static struct clk iva2_ck = {
1144 .ops = &clkops_omap2_dflt_wait,
1145 .parent = &dpll2_m2_ck,
1146 .init = &omap2_init_clksel_parent,
1147 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1148 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1149 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1150 OMAP3430_CM_IDLEST_PLL),
1151 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1152 .clksel = iva2_clksel,
1153 .flags = RATE_PROPAGATES,
1154 .clkdm_name = "iva2_clkdm",
1155 .recalc = &omap2_clksel_recalc,
1158 /* Common interface clocks */
1160 static struct clk l3_ick = {
1162 .ops = &clkops_null,
1164 .init = &omap2_init_clksel_parent,
1165 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1166 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1167 .clksel = div2_core_clksel,
1168 .flags = RATE_PROPAGATES,
1169 .clkdm_name = "core_l3_clkdm",
1170 .recalc = &omap2_clksel_recalc,
1173 static const struct clksel div2_l3_clksel[] = {
1174 { .parent = &l3_ick, .rates = div2_rates },
1178 static struct clk l4_ick = {
1180 .ops = &clkops_null,
1182 .init = &omap2_init_clksel_parent,
1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1184 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1185 .clksel = div2_l3_clksel,
1186 .flags = RATE_PROPAGATES,
1187 .clkdm_name = "core_l4_clkdm",
1188 .recalc = &omap2_clksel_recalc,
1192 static const struct clksel div2_l4_clksel[] = {
1193 { .parent = &l4_ick, .rates = div2_rates },
1197 static struct clk rm_ick = {
1199 .ops = &clkops_null,
1201 .init = &omap2_init_clksel_parent,
1202 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1203 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1204 .clksel = div2_l4_clksel,
1205 .recalc = &omap2_clksel_recalc,
1208 /* GFX power domain */
1210 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1212 static const struct clksel gfx_l3_clksel[] = {
1213 { .parent = &l3_ick, .rates = gfx_l3_rates },
1217 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1218 static struct clk gfx_l3_ck = {
1219 .name = "gfx_l3_ck",
1220 .ops = &clkops_omap2_dflt_wait,
1222 .init = &omap2_init_clksel_parent,
1223 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1224 .enable_bit = OMAP_EN_GFX_SHIFT,
1225 .recalc = &followparent_recalc,
1228 static struct clk gfx_l3_fck = {
1229 .name = "gfx_l3_fck",
1230 .ops = &clkops_null,
1231 .parent = &gfx_l3_ck,
1232 .init = &omap2_init_clksel_parent,
1233 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1234 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1235 .clksel = gfx_l3_clksel,
1236 .flags = RATE_PROPAGATES,
1237 .clkdm_name = "gfx_3430es1_clkdm",
1238 .recalc = &omap2_clksel_recalc,
1241 static struct clk gfx_l3_ick = {
1242 .name = "gfx_l3_ick",
1243 .ops = &clkops_null,
1244 .parent = &gfx_l3_ck,
1245 .clkdm_name = "gfx_3430es1_clkdm",
1246 .recalc = &followparent_recalc,
1249 static struct clk gfx_cg1_ck = {
1250 .name = "gfx_cg1_ck",
1251 .ops = &clkops_omap2_dflt_wait,
1252 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1253 .init = &omap2_init_clk_clkdm,
1254 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1255 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1256 .clkdm_name = "gfx_3430es1_clkdm",
1257 .recalc = &followparent_recalc,
1260 static struct clk gfx_cg2_ck = {
1261 .name = "gfx_cg2_ck",
1262 .ops = &clkops_omap2_dflt_wait,
1263 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1264 .init = &omap2_init_clk_clkdm,
1265 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1266 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1267 .clkdm_name = "gfx_3430es1_clkdm",
1268 .recalc = &followparent_recalc,
1271 /* SGX power domain - 3430ES2 only */
1273 static const struct clksel_rate sgx_core_rates[] = {
1274 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1275 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1276 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1280 static const struct clksel_rate sgx_96m_rates[] = {
1281 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1285 static const struct clksel sgx_clksel[] = {
1286 { .parent = &core_ck, .rates = sgx_core_rates },
1287 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1291 static struct clk sgx_fck = {
1293 .ops = &clkops_omap2_dflt_wait,
1294 .init = &omap2_init_clksel_parent,
1295 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1296 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1297 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1298 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1299 .clksel = sgx_clksel,
1300 .clkdm_name = "sgx_clkdm",
1301 .recalc = &omap2_clksel_recalc,
1304 static struct clk sgx_ick = {
1306 .ops = &clkops_omap2_dflt_wait,
1308 .init = &omap2_init_clk_clkdm,
1309 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1310 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1311 .clkdm_name = "sgx_clkdm",
1312 .recalc = &followparent_recalc,
1315 /* CORE power domain */
1317 static struct clk d2d_26m_fck = {
1318 .name = "d2d_26m_fck",
1319 .ops = &clkops_omap2_dflt_wait,
1321 .init = &omap2_init_clk_clkdm,
1322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1323 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1324 .clkdm_name = "d2d_clkdm",
1325 .recalc = &followparent_recalc,
1328 static const struct clksel omap343x_gpt_clksel[] = {
1329 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1330 { .parent = &sys_ck, .rates = gpt_sys_rates },
1334 static struct clk gpt10_fck = {
1335 .name = "gpt10_fck",
1336 .ops = &clkops_omap2_dflt_wait,
1338 .init = &omap2_init_clksel_parent,
1339 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1340 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1341 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1342 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1343 .clksel = omap343x_gpt_clksel,
1344 .clkdm_name = "core_l4_clkdm",
1345 .recalc = &omap2_clksel_recalc,
1348 static struct clk gpt11_fck = {
1349 .name = "gpt11_fck",
1350 .ops = &clkops_omap2_dflt_wait,
1352 .init = &omap2_init_clksel_parent,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1354 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1355 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1356 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1357 .clksel = omap343x_gpt_clksel,
1358 .clkdm_name = "core_l4_clkdm",
1359 .recalc = &omap2_clksel_recalc,
1362 static struct clk cpefuse_fck = {
1363 .name = "cpefuse_fck",
1364 .ops = &clkops_omap2_dflt,
1366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1367 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1368 .recalc = &followparent_recalc,
1371 static struct clk ts_fck = {
1373 .ops = &clkops_omap2_dflt,
1374 .parent = &omap_32k_fck,
1375 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1376 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1377 .recalc = &followparent_recalc,
1380 static struct clk usbtll_fck = {
1381 .name = "usbtll_fck",
1382 .ops = &clkops_omap2_dflt,
1383 .parent = &omap_120m_fck,
1384 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1385 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1386 .recalc = &followparent_recalc,
1389 /* CORE 96M FCLK-derived clocks */
1391 static struct clk core_96m_fck = {
1392 .name = "core_96m_fck",
1393 .ops = &clkops_null,
1394 .parent = &omap_96m_fck,
1395 .flags = RATE_PROPAGATES,
1396 .clkdm_name = "core_l4_clkdm",
1397 .recalc = &followparent_recalc,
1400 static struct clk mmchs3_fck = {
1401 .name = "mmchs_fck",
1402 .ops = &clkops_omap2_dflt_wait,
1404 .parent = &core_96m_fck,
1405 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1407 .clkdm_name = "core_l4_clkdm",
1408 .recalc = &followparent_recalc,
1411 static struct clk mmchs2_fck = {
1412 .name = "mmchs_fck",
1413 .ops = &clkops_omap2_dflt_wait,
1415 .parent = &core_96m_fck,
1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1418 .clkdm_name = "core_l4_clkdm",
1419 .recalc = &followparent_recalc,
1422 static struct clk mspro_fck = {
1423 .name = "mspro_fck",
1424 .ops = &clkops_omap2_dflt_wait,
1425 .parent = &core_96m_fck,
1426 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1427 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1428 .clkdm_name = "core_l4_clkdm",
1429 .recalc = &followparent_recalc,
1432 static struct clk mmchs1_fck = {
1433 .name = "mmchs_fck",
1434 .ops = &clkops_omap2_dflt_wait,
1435 .parent = &core_96m_fck,
1436 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1438 .clkdm_name = "core_l4_clkdm",
1439 .recalc = &followparent_recalc,
1442 static struct clk i2c3_fck = {
1444 .ops = &clkops_omap2_dflt_wait,
1446 .parent = &core_96m_fck,
1447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1449 .clkdm_name = "core_l4_clkdm",
1450 .recalc = &followparent_recalc,
1453 static struct clk i2c2_fck = {
1455 .ops = &clkops_omap2_dflt_wait,
1457 .parent = &core_96m_fck,
1458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1459 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1460 .clkdm_name = "core_l4_clkdm",
1461 .recalc = &followparent_recalc,
1464 static struct clk i2c1_fck = {
1466 .ops = &clkops_omap2_dflt_wait,
1468 .parent = &core_96m_fck,
1469 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1470 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1471 .clkdm_name = "core_l4_clkdm",
1472 .recalc = &followparent_recalc,
1476 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1477 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1479 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1480 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1484 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1485 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1489 static const struct clksel mcbsp_15_clksel[] = {
1490 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1491 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1495 static struct clk mcbsp5_fck = {
1496 .name = "mcbsp_fck",
1497 .ops = &clkops_omap2_dflt_wait,
1499 .init = &omap2_init_clksel_parent,
1500 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1501 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1502 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1503 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1504 .clksel = mcbsp_15_clksel,
1505 .clkdm_name = "core_l4_clkdm",
1506 .recalc = &omap2_clksel_recalc,
1509 static struct clk mcbsp1_fck = {
1510 .name = "mcbsp_fck",
1511 .ops = &clkops_omap2_dflt_wait,
1513 .init = &omap2_init_clksel_parent,
1514 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1515 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1516 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1517 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1518 .clksel = mcbsp_15_clksel,
1519 .clkdm_name = "core_l4_clkdm",
1520 .recalc = &omap2_clksel_recalc,
1523 /* CORE_48M_FCK-derived clocks */
1525 static struct clk core_48m_fck = {
1526 .name = "core_48m_fck",
1527 .ops = &clkops_null,
1528 .parent = &omap_48m_fck,
1529 .flags = RATE_PROPAGATES,
1530 .clkdm_name = "core_l4_clkdm",
1531 .recalc = &followparent_recalc,
1534 static struct clk mcspi4_fck = {
1535 .name = "mcspi_fck",
1536 .ops = &clkops_omap2_dflt_wait,
1538 .parent = &core_48m_fck,
1539 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1540 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1541 .recalc = &followparent_recalc,
1544 static struct clk mcspi3_fck = {
1545 .name = "mcspi_fck",
1546 .ops = &clkops_omap2_dflt_wait,
1548 .parent = &core_48m_fck,
1549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1551 .recalc = &followparent_recalc,
1554 static struct clk mcspi2_fck = {
1555 .name = "mcspi_fck",
1556 .ops = &clkops_omap2_dflt_wait,
1558 .parent = &core_48m_fck,
1559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1560 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1561 .recalc = &followparent_recalc,
1564 static struct clk mcspi1_fck = {
1565 .name = "mcspi_fck",
1566 .ops = &clkops_omap2_dflt_wait,
1568 .parent = &core_48m_fck,
1569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1571 .recalc = &followparent_recalc,
1574 static struct clk uart2_fck = {
1575 .name = "uart2_fck",
1576 .ops = &clkops_omap2_dflt_wait,
1577 .parent = &core_48m_fck,
1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1579 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1580 .recalc = &followparent_recalc,
1583 static struct clk uart1_fck = {
1584 .name = "uart1_fck",
1585 .ops = &clkops_omap2_dflt_wait,
1586 .parent = &core_48m_fck,
1587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1588 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1589 .recalc = &followparent_recalc,
1592 static struct clk fshostusb_fck = {
1593 .name = "fshostusb_fck",
1594 .ops = &clkops_omap2_dflt_wait,
1595 .parent = &core_48m_fck,
1596 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1597 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1598 .recalc = &followparent_recalc,
1601 /* CORE_12M_FCK based clocks */
1603 static struct clk core_12m_fck = {
1604 .name = "core_12m_fck",
1605 .ops = &clkops_null,
1606 .parent = &omap_12m_fck,
1607 .flags = RATE_PROPAGATES,
1608 .clkdm_name = "core_l4_clkdm",
1609 .recalc = &followparent_recalc,
1612 static struct clk hdq_fck = {
1614 .ops = &clkops_omap2_dflt_wait,
1615 .parent = &core_12m_fck,
1616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1617 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1618 .recalc = &followparent_recalc,
1621 /* DPLL3-derived clock */
1623 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1624 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1625 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1626 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1627 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1628 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1629 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1633 static const struct clksel ssi_ssr_clksel[] = {
1634 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1638 static struct clk ssi_ssr_fck = {
1639 .name = "ssi_ssr_fck",
1640 .ops = &clkops_omap2_dflt,
1641 .init = &omap2_init_clksel_parent,
1642 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1643 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1644 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1645 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1646 .clksel = ssi_ssr_clksel,
1647 .flags = RATE_PROPAGATES,
1648 .clkdm_name = "core_l4_clkdm",
1649 .recalc = &omap2_clksel_recalc,
1652 static struct clk ssi_sst_fck = {
1653 .name = "ssi_sst_fck",
1654 .ops = &clkops_null,
1655 .parent = &ssi_ssr_fck,
1657 .recalc = &omap2_fixed_divisor_recalc,
1662 /* CORE_L3_ICK based clocks */
1665 * XXX must add clk_enable/clk_disable for these if standard code won't
1668 static struct clk core_l3_ick = {
1669 .name = "core_l3_ick",
1670 .ops = &clkops_null,
1672 .init = &omap2_init_clk_clkdm,
1673 .flags = RATE_PROPAGATES,
1674 .clkdm_name = "core_l3_clkdm",
1675 .recalc = &followparent_recalc,
1678 static struct clk hsotgusb_ick = {
1679 .name = "hsotgusb_ick",
1680 .ops = &clkops_omap2_dflt_wait,
1681 .parent = &core_l3_ick,
1682 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1683 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1684 .clkdm_name = "core_l3_clkdm",
1685 .recalc = &followparent_recalc,
1688 static struct clk sdrc_ick = {
1690 .ops = &clkops_omap2_dflt_wait,
1691 .parent = &core_l3_ick,
1692 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1693 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1694 .flags = ENABLE_ON_INIT,
1695 .clkdm_name = "core_l3_clkdm",
1696 .recalc = &followparent_recalc,
1699 static struct clk gpmc_fck = {
1701 .ops = &clkops_null,
1702 .parent = &core_l3_ick,
1703 .flags = ENABLE_ON_INIT, /* huh? */
1704 .clkdm_name = "core_l3_clkdm",
1705 .recalc = &followparent_recalc,
1708 /* SECURITY_L3_ICK based clocks */
1710 static struct clk security_l3_ick = {
1711 .name = "security_l3_ick",
1712 .ops = &clkops_null,
1714 .flags = RATE_PROPAGATES,
1715 .recalc = &followparent_recalc,
1718 static struct clk pka_ick = {
1720 .ops = &clkops_omap2_dflt_wait,
1721 .parent = &security_l3_ick,
1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1723 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1724 .recalc = &followparent_recalc,
1727 /* CORE_L4_ICK based clocks */
1729 static struct clk core_l4_ick = {
1730 .name = "core_l4_ick",
1731 .ops = &clkops_null,
1733 .init = &omap2_init_clk_clkdm,
1734 .flags = RATE_PROPAGATES,
1735 .clkdm_name = "core_l4_clkdm",
1736 .recalc = &followparent_recalc,
1739 static struct clk usbtll_ick = {
1740 .name = "usbtll_ick",
1741 .ops = &clkops_omap2_dflt_wait,
1742 .parent = &core_l4_ick,
1743 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1744 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1745 .clkdm_name = "core_l4_clkdm",
1746 .recalc = &followparent_recalc,
1749 static struct clk mmchs3_ick = {
1750 .name = "mmchs_ick",
1751 .ops = &clkops_omap2_dflt_wait,
1753 .parent = &core_l4_ick,
1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1755 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1756 .clkdm_name = "core_l4_clkdm",
1757 .recalc = &followparent_recalc,
1760 /* Intersystem Communication Registers - chassis mode only */
1761 static struct clk icr_ick = {
1763 .ops = &clkops_omap2_dflt_wait,
1764 .parent = &core_l4_ick,
1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1767 .clkdm_name = "core_l4_clkdm",
1768 .recalc = &followparent_recalc,
1771 static struct clk aes2_ick = {
1773 .ops = &clkops_omap2_dflt_wait,
1774 .parent = &core_l4_ick,
1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1776 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1777 .clkdm_name = "core_l4_clkdm",
1778 .recalc = &followparent_recalc,
1781 static struct clk sha12_ick = {
1782 .name = "sha12_ick",
1783 .ops = &clkops_omap2_dflt_wait,
1784 .parent = &core_l4_ick,
1785 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1786 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1787 .clkdm_name = "core_l4_clkdm",
1788 .recalc = &followparent_recalc,
1791 static struct clk des2_ick = {
1793 .ops = &clkops_omap2_dflt_wait,
1794 .parent = &core_l4_ick,
1795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1796 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1797 .clkdm_name = "core_l4_clkdm",
1798 .recalc = &followparent_recalc,
1801 static struct clk mmchs2_ick = {
1802 .name = "mmchs_ick",
1803 .ops = &clkops_omap2_dflt_wait,
1805 .parent = &core_l4_ick,
1806 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1807 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1808 .clkdm_name = "core_l4_clkdm",
1809 .recalc = &followparent_recalc,
1812 static struct clk mmchs1_ick = {
1813 .name = "mmchs_ick",
1814 .ops = &clkops_omap2_dflt_wait,
1815 .parent = &core_l4_ick,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1818 .clkdm_name = "core_l4_clkdm",
1819 .recalc = &followparent_recalc,
1822 static struct clk mspro_ick = {
1823 .name = "mspro_ick",
1824 .ops = &clkops_omap2_dflt_wait,
1825 .parent = &core_l4_ick,
1826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1827 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1828 .clkdm_name = "core_l4_clkdm",
1829 .recalc = &followparent_recalc,
1832 static struct clk hdq_ick = {
1834 .ops = &clkops_omap2_dflt_wait,
1835 .parent = &core_l4_ick,
1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1838 .clkdm_name = "core_l4_clkdm",
1839 .recalc = &followparent_recalc,
1842 static struct clk mcspi4_ick = {
1843 .name = "mcspi_ick",
1844 .ops = &clkops_omap2_dflt_wait,
1846 .parent = &core_l4_ick,
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1849 .clkdm_name = "core_l4_clkdm",
1850 .recalc = &followparent_recalc,
1853 static struct clk mcspi3_ick = {
1854 .name = "mcspi_ick",
1855 .ops = &clkops_omap2_dflt_wait,
1857 .parent = &core_l4_ick,
1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1859 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1860 .clkdm_name = "core_l4_clkdm",
1861 .recalc = &followparent_recalc,
1864 static struct clk mcspi2_ick = {
1865 .name = "mcspi_ick",
1866 .ops = &clkops_omap2_dflt_wait,
1868 .parent = &core_l4_ick,
1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1870 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1871 .clkdm_name = "core_l4_clkdm",
1872 .recalc = &followparent_recalc,
1875 static struct clk mcspi1_ick = {
1876 .name = "mcspi_ick",
1877 .ops = &clkops_omap2_dflt_wait,
1879 .parent = &core_l4_ick,
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1882 .clkdm_name = "core_l4_clkdm",
1883 .recalc = &followparent_recalc,
1886 static struct clk i2c3_ick = {
1888 .ops = &clkops_omap2_dflt_wait,
1890 .parent = &core_l4_ick,
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1893 .clkdm_name = "core_l4_clkdm",
1894 .recalc = &followparent_recalc,
1897 static struct clk i2c2_ick = {
1899 .ops = &clkops_omap2_dflt_wait,
1901 .parent = &core_l4_ick,
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1904 .clkdm_name = "core_l4_clkdm",
1905 .recalc = &followparent_recalc,
1908 static struct clk i2c1_ick = {
1910 .ops = &clkops_omap2_dflt_wait,
1912 .parent = &core_l4_ick,
1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1914 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1915 .clkdm_name = "core_l4_clkdm",
1916 .recalc = &followparent_recalc,
1919 static struct clk uart2_ick = {
1920 .name = "uart2_ick",
1921 .ops = &clkops_omap2_dflt_wait,
1922 .parent = &core_l4_ick,
1923 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1924 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1925 .clkdm_name = "core_l4_clkdm",
1926 .recalc = &followparent_recalc,
1929 static struct clk uart1_ick = {
1930 .name = "uart1_ick",
1931 .ops = &clkops_omap2_dflt_wait,
1932 .parent = &core_l4_ick,
1933 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1934 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1935 .clkdm_name = "core_l4_clkdm",
1936 .recalc = &followparent_recalc,
1939 static struct clk gpt11_ick = {
1940 .name = "gpt11_ick",
1941 .ops = &clkops_omap2_dflt_wait,
1942 .parent = &core_l4_ick,
1943 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1944 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1945 .clkdm_name = "core_l4_clkdm",
1946 .recalc = &followparent_recalc,
1949 static struct clk gpt10_ick = {
1950 .name = "gpt10_ick",
1951 .ops = &clkops_omap2_dflt_wait,
1952 .parent = &core_l4_ick,
1953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1954 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1955 .clkdm_name = "core_l4_clkdm",
1956 .recalc = &followparent_recalc,
1959 static struct clk mcbsp5_ick = {
1960 .name = "mcbsp_ick",
1961 .ops = &clkops_omap2_dflt_wait,
1963 .parent = &core_l4_ick,
1964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1966 .clkdm_name = "core_l4_clkdm",
1967 .recalc = &followparent_recalc,
1970 static struct clk mcbsp1_ick = {
1971 .name = "mcbsp_ick",
1972 .ops = &clkops_omap2_dflt_wait,
1974 .parent = &core_l4_ick,
1975 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1976 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1977 .clkdm_name = "core_l4_clkdm",
1978 .recalc = &followparent_recalc,
1981 static struct clk fac_ick = {
1983 .ops = &clkops_omap2_dflt_wait,
1984 .parent = &core_l4_ick,
1985 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1986 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1987 .clkdm_name = "core_l4_clkdm",
1988 .recalc = &followparent_recalc,
1991 static struct clk mailboxes_ick = {
1992 .name = "mailboxes_ick",
1993 .ops = &clkops_omap2_dflt_wait,
1994 .parent = &core_l4_ick,
1995 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1996 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1997 .clkdm_name = "core_l4_clkdm",
1998 .recalc = &followparent_recalc,
2001 static struct clk omapctrl_ick = {
2002 .name = "omapctrl_ick",
2003 .ops = &clkops_omap2_dflt_wait,
2004 .parent = &core_l4_ick,
2005 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2007 .flags = ENABLE_ON_INIT,
2008 .recalc = &followparent_recalc,
2011 /* SSI_L4_ICK based clocks */
2013 static struct clk ssi_l4_ick = {
2014 .name = "ssi_l4_ick",
2015 .ops = &clkops_null,
2017 .flags = RATE_PROPAGATES,
2018 .clkdm_name = "core_l4_clkdm",
2019 .recalc = &followparent_recalc,
2022 static struct clk ssi_ick = {
2024 .ops = &clkops_omap2_dflt,
2025 .parent = &ssi_l4_ick,
2026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2028 .clkdm_name = "core_l4_clkdm",
2029 .recalc = &followparent_recalc,
2032 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2033 * but l4_ick makes more sense to me */
2035 static const struct clksel usb_l4_clksel[] = {
2036 { .parent = &l4_ick, .rates = div2_rates },
2040 static struct clk usb_l4_ick = {
2041 .name = "usb_l4_ick",
2042 .ops = &clkops_omap2_dflt_wait,
2044 .init = &omap2_init_clksel_parent,
2045 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2046 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2047 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2048 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2049 .clksel = usb_l4_clksel,
2050 .recalc = &omap2_clksel_recalc,
2053 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2055 /* SECURITY_L4_ICK2 based clocks */
2057 static struct clk security_l4_ick2 = {
2058 .name = "security_l4_ick2",
2059 .ops = &clkops_null,
2061 .flags = RATE_PROPAGATES,
2062 .recalc = &followparent_recalc,
2065 static struct clk aes1_ick = {
2067 .ops = &clkops_omap2_dflt_wait,
2068 .parent = &security_l4_ick2,
2069 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2070 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2071 .recalc = &followparent_recalc,
2074 static struct clk rng_ick = {
2076 .ops = &clkops_omap2_dflt_wait,
2077 .parent = &security_l4_ick2,
2078 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2079 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2080 .recalc = &followparent_recalc,
2083 static struct clk sha11_ick = {
2084 .name = "sha11_ick",
2085 .ops = &clkops_omap2_dflt_wait,
2086 .parent = &security_l4_ick2,
2087 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2088 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2089 .recalc = &followparent_recalc,
2092 static struct clk des1_ick = {
2094 .ops = &clkops_omap2_dflt_wait,
2095 .parent = &security_l4_ick2,
2096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2097 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2098 .recalc = &followparent_recalc,
2102 static const struct clksel dss1_alwon_fck_clksel[] = {
2103 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2104 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2108 static struct clk dss1_alwon_fck = {
2109 .name = "dss1_alwon_fck",
2110 .ops = &clkops_omap2_dflt,
2111 .parent = &dpll4_m4x2_ck,
2112 .init = &omap2_init_clksel_parent,
2113 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2114 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2115 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2116 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2117 .clksel = dss1_alwon_fck_clksel,
2118 .clkdm_name = "dss_clkdm",
2119 .recalc = &omap2_clksel_recalc,
2122 static struct clk dss_tv_fck = {
2123 .name = "dss_tv_fck",
2124 .ops = &clkops_omap2_dflt,
2125 .parent = &omap_54m_fck,
2126 .init = &omap2_init_clk_clkdm,
2127 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2128 .enable_bit = OMAP3430_EN_TV_SHIFT,
2129 .clkdm_name = "dss_clkdm",
2130 .recalc = &followparent_recalc,
2133 static struct clk dss_96m_fck = {
2134 .name = "dss_96m_fck",
2135 .ops = &clkops_omap2_dflt,
2136 .parent = &omap_96m_fck,
2137 .init = &omap2_init_clk_clkdm,
2138 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2139 .enable_bit = OMAP3430_EN_TV_SHIFT,
2140 .clkdm_name = "dss_clkdm",
2141 .recalc = &followparent_recalc,
2144 static struct clk dss2_alwon_fck = {
2145 .name = "dss2_alwon_fck",
2146 .ops = &clkops_omap2_dflt,
2148 .init = &omap2_init_clk_clkdm,
2149 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2150 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2151 .clkdm_name = "dss_clkdm",
2152 .recalc = &followparent_recalc,
2155 static struct clk dss_ick = {
2156 /* Handles both L3 and L4 clocks */
2158 .ops = &clkops_omap2_dflt,
2160 .init = &omap2_init_clk_clkdm,
2161 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2162 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2163 .clkdm_name = "dss_clkdm",
2164 .recalc = &followparent_recalc,
2169 static const struct clksel cam_mclk_clksel[] = {
2170 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2171 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2175 static struct clk cam_mclk = {
2177 .ops = &clkops_omap2_dflt_wait,
2178 .parent = &dpll4_m5x2_ck,
2179 .init = &omap2_init_clksel_parent,
2180 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2181 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2182 .clksel = cam_mclk_clksel,
2183 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2184 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2185 .clkdm_name = "cam_clkdm",
2186 .recalc = &omap2_clksel_recalc,
2189 static struct clk cam_ick = {
2190 /* Handles both L3 and L4 clocks */
2192 .ops = &clkops_omap2_dflt_wait,
2194 .init = &omap2_init_clk_clkdm,
2195 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2196 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2197 .clkdm_name = "cam_clkdm",
2198 .recalc = &followparent_recalc,
2201 /* USBHOST - 3430ES2 only */
2203 static struct clk usbhost_120m_fck = {
2204 .name = "usbhost_120m_fck",
2205 .ops = &clkops_omap2_dflt_wait,
2206 .parent = &omap_120m_fck,
2207 .init = &omap2_init_clk_clkdm,
2208 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2209 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2210 .clkdm_name = "usbhost_clkdm",
2211 .recalc = &followparent_recalc,
2214 static struct clk usbhost_48m_fck = {
2215 .name = "usbhost_48m_fck",
2216 .ops = &clkops_omap2_dflt_wait,
2217 .parent = &omap_48m_fck,
2218 .init = &omap2_init_clk_clkdm,
2219 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2220 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2221 .clkdm_name = "usbhost_clkdm",
2222 .recalc = &followparent_recalc,
2225 static struct clk usbhost_ick = {
2226 /* Handles both L3 and L4 clocks */
2227 .name = "usbhost_ick",
2228 .ops = &clkops_omap2_dflt_wait,
2230 .init = &omap2_init_clk_clkdm,
2231 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2232 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2233 .clkdm_name = "usbhost_clkdm",
2234 .recalc = &followparent_recalc,
2239 static const struct clksel_rate usim_96m_rates[] = {
2240 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2241 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2242 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2243 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2247 static const struct clksel_rate usim_120m_rates[] = {
2248 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2249 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2250 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2251 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2255 static const struct clksel usim_clksel[] = {
2256 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2257 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2258 { .parent = &sys_ck, .rates = div2_rates },
2263 static struct clk usim_fck = {
2265 .ops = &clkops_omap2_dflt_wait,
2266 .init = &omap2_init_clksel_parent,
2267 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2268 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2269 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2270 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2271 .clksel = usim_clksel,
2272 .recalc = &omap2_clksel_recalc,
2275 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2276 static struct clk gpt1_fck = {
2278 .ops = &clkops_omap2_dflt_wait,
2279 .init = &omap2_init_clksel_parent,
2280 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2281 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2282 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2283 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2284 .clksel = omap343x_gpt_clksel,
2285 .clkdm_name = "wkup_clkdm",
2286 .recalc = &omap2_clksel_recalc,
2289 static struct clk wkup_32k_fck = {
2290 .name = "wkup_32k_fck",
2291 .ops = &clkops_null,
2292 .init = &omap2_init_clk_clkdm,
2293 .parent = &omap_32k_fck,
2294 .flags = RATE_PROPAGATES,
2295 .clkdm_name = "wkup_clkdm",
2296 .recalc = &followparent_recalc,
2299 static struct clk gpio1_dbck = {
2300 .name = "gpio1_dbck",
2301 .ops = &clkops_omap2_dflt_wait,
2302 .parent = &wkup_32k_fck,
2303 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2304 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2305 .clkdm_name = "wkup_clkdm",
2306 .recalc = &followparent_recalc,
2309 static struct clk wdt2_fck = {
2311 .ops = &clkops_omap2_dflt_wait,
2312 .parent = &wkup_32k_fck,
2313 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2314 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2315 .clkdm_name = "wkup_clkdm",
2316 .recalc = &followparent_recalc,
2319 static struct clk wkup_l4_ick = {
2320 .name = "wkup_l4_ick",
2321 .ops = &clkops_null,
2323 .flags = RATE_PROPAGATES,
2324 .clkdm_name = "wkup_clkdm",
2325 .recalc = &followparent_recalc,
2329 /* Never specifically named in the TRM, so we have to infer a likely name */
2330 static struct clk usim_ick = {
2332 .ops = &clkops_omap2_dflt_wait,
2333 .parent = &wkup_l4_ick,
2334 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2335 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2336 .clkdm_name = "wkup_clkdm",
2337 .recalc = &followparent_recalc,
2340 static struct clk wdt2_ick = {
2342 .ops = &clkops_omap2_dflt_wait,
2343 .parent = &wkup_l4_ick,
2344 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2345 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2346 .clkdm_name = "wkup_clkdm",
2347 .recalc = &followparent_recalc,
2350 static struct clk wdt1_ick = {
2352 .ops = &clkops_omap2_dflt_wait,
2353 .parent = &wkup_l4_ick,
2354 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2355 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2356 .clkdm_name = "wkup_clkdm",
2357 .recalc = &followparent_recalc,
2360 static struct clk gpio1_ick = {
2361 .name = "gpio1_ick",
2362 .ops = &clkops_omap2_dflt_wait,
2363 .parent = &wkup_l4_ick,
2364 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2365 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2366 .clkdm_name = "wkup_clkdm",
2367 .recalc = &followparent_recalc,
2370 static struct clk omap_32ksync_ick = {
2371 .name = "omap_32ksync_ick",
2372 .ops = &clkops_omap2_dflt_wait,
2373 .parent = &wkup_l4_ick,
2374 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2375 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2376 .clkdm_name = "wkup_clkdm",
2377 .recalc = &followparent_recalc,
2380 /* XXX This clock no longer exists in 3430 TRM rev F */
2381 static struct clk gpt12_ick = {
2382 .name = "gpt12_ick",
2383 .ops = &clkops_omap2_dflt_wait,
2384 .parent = &wkup_l4_ick,
2385 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2386 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2387 .clkdm_name = "wkup_clkdm",
2388 .recalc = &followparent_recalc,
2391 static struct clk gpt1_ick = {
2393 .ops = &clkops_omap2_dflt_wait,
2394 .parent = &wkup_l4_ick,
2395 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2396 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2397 .clkdm_name = "wkup_clkdm",
2398 .recalc = &followparent_recalc,
2403 /* PER clock domain */
2405 static struct clk per_96m_fck = {
2406 .name = "per_96m_fck",
2407 .ops = &clkops_null,
2408 .parent = &omap_96m_alwon_fck,
2409 .init = &omap2_init_clk_clkdm,
2410 .flags = RATE_PROPAGATES,
2411 .clkdm_name = "per_clkdm",
2412 .recalc = &followparent_recalc,
2415 static struct clk per_48m_fck = {
2416 .name = "per_48m_fck",
2417 .ops = &clkops_null,
2418 .parent = &omap_48m_fck,
2419 .init = &omap2_init_clk_clkdm,
2420 .flags = RATE_PROPAGATES,
2421 .clkdm_name = "per_clkdm",
2422 .recalc = &followparent_recalc,
2425 static struct clk uart3_fck = {
2426 .name = "uart3_fck",
2427 .ops = &clkops_omap2_dflt_wait,
2428 .parent = &per_48m_fck,
2429 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2430 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2431 .clkdm_name = "per_clkdm",
2432 .recalc = &followparent_recalc,
2435 static struct clk gpt2_fck = {
2437 .ops = &clkops_omap2_dflt_wait,
2438 .init = &omap2_init_clksel_parent,
2439 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2440 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2441 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2442 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2443 .clksel = omap343x_gpt_clksel,
2444 .clkdm_name = "per_clkdm",
2445 .recalc = &omap2_clksel_recalc,
2448 static struct clk gpt3_fck = {
2450 .ops = &clkops_omap2_dflt_wait,
2451 .init = &omap2_init_clksel_parent,
2452 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2453 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2454 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2455 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2456 .clksel = omap343x_gpt_clksel,
2457 .clkdm_name = "per_clkdm",
2458 .recalc = &omap2_clksel_recalc,
2461 static struct clk gpt4_fck = {
2463 .ops = &clkops_omap2_dflt_wait,
2464 .init = &omap2_init_clksel_parent,
2465 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2466 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2467 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2468 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2469 .clksel = omap343x_gpt_clksel,
2470 .clkdm_name = "per_clkdm",
2471 .recalc = &omap2_clksel_recalc,
2474 static struct clk gpt5_fck = {
2476 .ops = &clkops_omap2_dflt_wait,
2477 .init = &omap2_init_clksel_parent,
2478 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2479 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2480 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2481 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2482 .clksel = omap343x_gpt_clksel,
2483 .clkdm_name = "per_clkdm",
2484 .recalc = &omap2_clksel_recalc,
2487 static struct clk gpt6_fck = {
2489 .ops = &clkops_omap2_dflt_wait,
2490 .init = &omap2_init_clksel_parent,
2491 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2492 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2493 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2494 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2495 .clksel = omap343x_gpt_clksel,
2496 .clkdm_name = "per_clkdm",
2497 .recalc = &omap2_clksel_recalc,
2500 static struct clk gpt7_fck = {
2502 .ops = &clkops_omap2_dflt_wait,
2503 .init = &omap2_init_clksel_parent,
2504 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2505 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2506 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2507 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2508 .clksel = omap343x_gpt_clksel,
2509 .clkdm_name = "per_clkdm",
2510 .recalc = &omap2_clksel_recalc,
2513 static struct clk gpt8_fck = {
2515 .ops = &clkops_omap2_dflt_wait,
2516 .init = &omap2_init_clksel_parent,
2517 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2518 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2519 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2520 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2521 .clksel = omap343x_gpt_clksel,
2522 .clkdm_name = "per_clkdm",
2523 .recalc = &omap2_clksel_recalc,
2526 static struct clk gpt9_fck = {
2528 .ops = &clkops_omap2_dflt_wait,
2529 .init = &omap2_init_clksel_parent,
2530 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2531 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2532 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2533 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2534 .clksel = omap343x_gpt_clksel,
2535 .clkdm_name = "per_clkdm",
2536 .recalc = &omap2_clksel_recalc,
2539 static struct clk per_32k_alwon_fck = {
2540 .name = "per_32k_alwon_fck",
2541 .ops = &clkops_null,
2542 .parent = &omap_32k_fck,
2543 .clkdm_name = "per_clkdm",
2544 .flags = RATE_PROPAGATES,
2545 .recalc = &followparent_recalc,
2548 static struct clk gpio6_dbck = {
2549 .name = "gpio6_dbck",
2550 .ops = &clkops_omap2_dflt_wait,
2551 .parent = &per_32k_alwon_fck,
2552 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2553 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2554 .clkdm_name = "per_clkdm",
2555 .recalc = &followparent_recalc,
2558 static struct clk gpio5_dbck = {
2559 .name = "gpio5_dbck",
2560 .ops = &clkops_omap2_dflt_wait,
2561 .parent = &per_32k_alwon_fck,
2562 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2563 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2564 .clkdm_name = "per_clkdm",
2565 .recalc = &followparent_recalc,
2568 static struct clk gpio4_dbck = {
2569 .name = "gpio4_dbck",
2570 .ops = &clkops_omap2_dflt_wait,
2571 .parent = &per_32k_alwon_fck,
2572 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2573 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2574 .clkdm_name = "per_clkdm",
2575 .recalc = &followparent_recalc,
2578 static struct clk gpio3_dbck = {
2579 .name = "gpio3_dbck",
2580 .ops = &clkops_omap2_dflt_wait,
2581 .parent = &per_32k_alwon_fck,
2582 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2583 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2584 .clkdm_name = "per_clkdm",
2585 .recalc = &followparent_recalc,
2588 static struct clk gpio2_dbck = {
2589 .name = "gpio2_dbck",
2590 .ops = &clkops_omap2_dflt_wait,
2591 .parent = &per_32k_alwon_fck,
2592 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2593 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2594 .clkdm_name = "per_clkdm",
2595 .recalc = &followparent_recalc,
2598 static struct clk wdt3_fck = {
2600 .ops = &clkops_omap2_dflt_wait,
2601 .parent = &per_32k_alwon_fck,
2602 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2603 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2604 .clkdm_name = "per_clkdm",
2605 .recalc = &followparent_recalc,
2608 static struct clk per_l4_ick = {
2609 .name = "per_l4_ick",
2610 .ops = &clkops_null,
2612 .flags = RATE_PROPAGATES,
2613 .clkdm_name = "per_clkdm",
2614 .recalc = &followparent_recalc,
2617 static struct clk gpio6_ick = {
2618 .name = "gpio6_ick",
2619 .ops = &clkops_omap2_dflt_wait,
2620 .parent = &per_l4_ick,
2621 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2622 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2623 .clkdm_name = "per_clkdm",
2624 .recalc = &followparent_recalc,
2627 static struct clk gpio5_ick = {
2628 .name = "gpio5_ick",
2629 .ops = &clkops_omap2_dflt_wait,
2630 .parent = &per_l4_ick,
2631 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2632 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2633 .clkdm_name = "per_clkdm",
2634 .recalc = &followparent_recalc,
2637 static struct clk gpio4_ick = {
2638 .name = "gpio4_ick",
2639 .ops = &clkops_omap2_dflt_wait,
2640 .parent = &per_l4_ick,
2641 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2642 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2643 .clkdm_name = "per_clkdm",
2644 .recalc = &followparent_recalc,
2647 static struct clk gpio3_ick = {
2648 .name = "gpio3_ick",
2649 .ops = &clkops_omap2_dflt_wait,
2650 .parent = &per_l4_ick,
2651 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2652 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2653 .clkdm_name = "per_clkdm",
2654 .recalc = &followparent_recalc,
2657 static struct clk gpio2_ick = {
2658 .name = "gpio2_ick",
2659 .ops = &clkops_omap2_dflt_wait,
2660 .parent = &per_l4_ick,
2661 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2662 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2663 .clkdm_name = "per_clkdm",
2664 .recalc = &followparent_recalc,
2667 static struct clk wdt3_ick = {
2669 .ops = &clkops_omap2_dflt_wait,
2670 .parent = &per_l4_ick,
2671 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2672 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2673 .clkdm_name = "per_clkdm",
2674 .recalc = &followparent_recalc,
2677 static struct clk uart3_ick = {
2678 .name = "uart3_ick",
2679 .ops = &clkops_omap2_dflt_wait,
2680 .parent = &per_l4_ick,
2681 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2682 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2683 .clkdm_name = "per_clkdm",
2684 .recalc = &followparent_recalc,
2687 static struct clk gpt9_ick = {
2689 .ops = &clkops_omap2_dflt_wait,
2690 .parent = &per_l4_ick,
2691 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2692 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2693 .clkdm_name = "per_clkdm",
2694 .recalc = &followparent_recalc,
2697 static struct clk gpt8_ick = {
2699 .ops = &clkops_omap2_dflt_wait,
2700 .parent = &per_l4_ick,
2701 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2702 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2703 .clkdm_name = "per_clkdm",
2704 .recalc = &followparent_recalc,
2707 static struct clk gpt7_ick = {
2709 .ops = &clkops_omap2_dflt_wait,
2710 .parent = &per_l4_ick,
2711 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2712 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2713 .clkdm_name = "per_clkdm",
2714 .recalc = &followparent_recalc,
2717 static struct clk gpt6_ick = {
2719 .ops = &clkops_omap2_dflt_wait,
2720 .parent = &per_l4_ick,
2721 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2722 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2723 .clkdm_name = "per_clkdm",
2724 .recalc = &followparent_recalc,
2727 static struct clk gpt5_ick = {
2729 .ops = &clkops_omap2_dflt_wait,
2730 .parent = &per_l4_ick,
2731 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2732 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2733 .clkdm_name = "per_clkdm",
2734 .recalc = &followparent_recalc,
2737 static struct clk gpt4_ick = {
2739 .ops = &clkops_omap2_dflt_wait,
2740 .parent = &per_l4_ick,
2741 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2742 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2743 .clkdm_name = "per_clkdm",
2744 .recalc = &followparent_recalc,
2747 static struct clk gpt3_ick = {
2749 .ops = &clkops_omap2_dflt_wait,
2750 .parent = &per_l4_ick,
2751 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2752 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2753 .clkdm_name = "per_clkdm",
2754 .recalc = &followparent_recalc,
2757 static struct clk gpt2_ick = {
2759 .ops = &clkops_omap2_dflt_wait,
2760 .parent = &per_l4_ick,
2761 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2762 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2763 .clkdm_name = "per_clkdm",
2764 .recalc = &followparent_recalc,
2767 static struct clk mcbsp2_ick = {
2768 .name = "mcbsp_ick",
2769 .ops = &clkops_omap2_dflt_wait,
2771 .parent = &per_l4_ick,
2772 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2773 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2774 .clkdm_name = "per_clkdm",
2775 .recalc = &followparent_recalc,
2778 static struct clk mcbsp3_ick = {
2779 .name = "mcbsp_ick",
2780 .ops = &clkops_omap2_dflt_wait,
2782 .parent = &per_l4_ick,
2783 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2784 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2785 .clkdm_name = "per_clkdm",
2786 .recalc = &followparent_recalc,
2789 static struct clk mcbsp4_ick = {
2790 .name = "mcbsp_ick",
2791 .ops = &clkops_omap2_dflt_wait,
2793 .parent = &per_l4_ick,
2794 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2795 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2796 .clkdm_name = "per_clkdm",
2797 .recalc = &followparent_recalc,
2800 static const struct clksel mcbsp_234_clksel[] = {
2801 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2802 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2806 static struct clk mcbsp2_fck = {
2807 .name = "mcbsp_fck",
2808 .ops = &clkops_omap2_dflt_wait,
2810 .init = &omap2_init_clksel_parent,
2811 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2812 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2813 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2814 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2815 .clksel = mcbsp_234_clksel,
2816 .clkdm_name = "per_clkdm",
2817 .recalc = &omap2_clksel_recalc,
2820 static struct clk mcbsp3_fck = {
2821 .name = "mcbsp_fck",
2822 .ops = &clkops_omap2_dflt_wait,
2824 .init = &omap2_init_clksel_parent,
2825 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2826 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2827 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2828 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2829 .clksel = mcbsp_234_clksel,
2830 .clkdm_name = "per_clkdm",
2831 .recalc = &omap2_clksel_recalc,
2834 static struct clk mcbsp4_fck = {
2835 .name = "mcbsp_fck",
2836 .ops = &clkops_omap2_dflt_wait,
2838 .init = &omap2_init_clksel_parent,
2839 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2840 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2841 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2842 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2843 .clksel = mcbsp_234_clksel,
2844 .clkdm_name = "per_clkdm",
2845 .recalc = &omap2_clksel_recalc,
2850 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2852 static const struct clksel_rate emu_src_sys_rates[] = {
2853 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2857 static const struct clksel_rate emu_src_core_rates[] = {
2858 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2862 static const struct clksel_rate emu_src_per_rates[] = {
2863 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2867 static const struct clksel_rate emu_src_mpu_rates[] = {
2868 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2872 static const struct clksel emu_src_clksel[] = {
2873 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2874 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2875 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2876 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2881 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2882 * to switch the source of some of the EMU clocks.
2883 * XXX Are there CLKEN bits for these EMU clks?
2885 static struct clk emu_src_ck = {
2886 .name = "emu_src_ck",
2887 .ops = &clkops_null,
2888 .init = &omap2_init_clksel_parent,
2889 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2890 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2891 .clksel = emu_src_clksel,
2892 .flags = RATE_PROPAGATES,
2893 .clkdm_name = "emu_clkdm",
2894 .recalc = &omap2_clksel_recalc,
2897 static const struct clksel_rate pclk_emu_rates[] = {
2898 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2899 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2900 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2901 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2905 static const struct clksel pclk_emu_clksel[] = {
2906 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2910 static struct clk pclk_fck = {
2912 .ops = &clkops_null,
2913 .init = &omap2_init_clksel_parent,
2914 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2915 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2916 .clksel = pclk_emu_clksel,
2917 .flags = RATE_PROPAGATES,
2918 .clkdm_name = "emu_clkdm",
2919 .recalc = &omap2_clksel_recalc,
2922 static const struct clksel_rate pclkx2_emu_rates[] = {
2923 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2924 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2925 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2929 static const struct clksel pclkx2_emu_clksel[] = {
2930 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2934 static struct clk pclkx2_fck = {
2935 .name = "pclkx2_fck",
2936 .ops = &clkops_null,
2937 .init = &omap2_init_clksel_parent,
2938 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2939 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2940 .clksel = pclkx2_emu_clksel,
2941 .flags = RATE_PROPAGATES,
2942 .clkdm_name = "emu_clkdm",
2943 .recalc = &omap2_clksel_recalc,
2946 static const struct clksel atclk_emu_clksel[] = {
2947 { .parent = &emu_src_ck, .rates = div2_rates },
2951 static struct clk atclk_fck = {
2952 .name = "atclk_fck",
2953 .ops = &clkops_null,
2954 .init = &omap2_init_clksel_parent,
2955 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2956 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2957 .clksel = atclk_emu_clksel,
2958 .flags = RATE_PROPAGATES,
2959 .clkdm_name = "emu_clkdm",
2960 .recalc = &omap2_clksel_recalc,
2963 static struct clk traceclk_src_fck = {
2964 .name = "traceclk_src_fck",
2965 .ops = &clkops_null,
2966 .init = &omap2_init_clksel_parent,
2967 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2968 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2969 .clksel = emu_src_clksel,
2970 .flags = RATE_PROPAGATES,
2971 .clkdm_name = "emu_clkdm",
2972 .recalc = &omap2_clksel_recalc,
2975 static const struct clksel_rate traceclk_rates[] = {
2976 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2977 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2978 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2982 static const struct clksel traceclk_clksel[] = {
2983 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2987 static struct clk traceclk_fck = {
2988 .name = "traceclk_fck",
2989 .ops = &clkops_null,
2990 .init = &omap2_init_clksel_parent,
2991 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2992 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2993 .clksel = traceclk_clksel,
2994 .clkdm_name = "emu_clkdm",
2995 .recalc = &omap2_clksel_recalc,
3000 /* SmartReflex fclk (VDD1) */
3001 static struct clk sr1_fck = {
3003 .ops = &clkops_omap2_dflt_wait,
3005 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3006 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3007 .flags = RATE_PROPAGATES,
3008 .recalc = &followparent_recalc,
3011 /* SmartReflex fclk (VDD2) */
3012 static struct clk sr2_fck = {
3014 .ops = &clkops_omap2_dflt_wait,
3016 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3017 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3018 .flags = RATE_PROPAGATES,
3019 .recalc = &followparent_recalc,
3022 static struct clk sr_l4_ick = {
3023 .name = "sr_l4_ick",
3024 .ops = &clkops_null, /* RMK: missing? */
3026 .clkdm_name = "core_l4_clkdm",
3027 .recalc = &followparent_recalc,
3030 /* SECURE_32K_FCK clocks */
3032 /* XXX This clock no longer exists in 3430 TRM rev F */
3033 static struct clk gpt12_fck = {
3034 .name = "gpt12_fck",
3035 .ops = &clkops_null,
3036 .parent = &secure_32k_fck,
3037 .recalc = &followparent_recalc,
3040 static struct clk wdt1_fck = {
3042 .ops = &clkops_null,
3043 .parent = &secure_32k_fck,
3044 .recalc = &followparent_recalc,