2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_enable(struct clk *clk);
36 static void omap3_noncore_dpll_disable(struct clk *clk);
37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
40 /* Maximum DPLL multiplier, divider values for OMAP3 */
41 #define OMAP3_MAX_DPLL_MULT 2048
42 #define OMAP3_MAX_DPLL_DIV 128
45 * DPLL1 supplies clock to the MPU.
46 * DPLL2 supplies clock to the IVA2.
47 * DPLL3 supplies CORE domain clocks.
48 * DPLL4 supplies peripheral clocks.
49 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
52 /* Forward declarations for DPLL bypass clocks */
53 static struct clk dpll1_fck;
54 static struct clk dpll2_fck;
56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
57 #define DPLL_LOW_POWER_STOP 0x1
58 #define DPLL_LOW_POWER_BYPASS 0x5
59 #define DPLL_LOCKED 0x7
63 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
64 static struct clk omap_32k_fck = {
65 .name = "omap_32k_fck",
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
69 .clkdm = { .name = "prm_clkdm" },
70 .recalc = &propagate_rate,
73 static struct clk secure_32k_fck = {
74 .name = "secure_32k_fck",
76 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
78 .clkdm = { .name = "prm_clkdm" },
79 .recalc = &propagate_rate,
82 /* Virtual source clocks for osc_sys_ck */
83 static struct clk virt_12m_ck = {
84 .name = "virt_12m_ck",
86 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
88 .clkdm = { .name = "prm_clkdm" },
89 .recalc = &propagate_rate,
92 static struct clk virt_13m_ck = {
93 .name = "virt_13m_ck",
95 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
97 .clkdm = { .name = "prm_clkdm" },
98 .recalc = &propagate_rate,
101 static struct clk virt_16_8m_ck = {
102 .name = "virt_16_8m_ck",
104 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
106 .clkdm = { .name = "prm_clkdm" },
107 .recalc = &propagate_rate,
110 static struct clk virt_19_2m_ck = {
111 .name = "virt_19_2m_ck",
113 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
115 .clkdm = { .name = "prm_clkdm" },
116 .recalc = &propagate_rate,
119 static struct clk virt_26m_ck = {
120 .name = "virt_26m_ck",
122 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
124 .clkdm = { .name = "prm_clkdm" },
125 .recalc = &propagate_rate,
128 static struct clk virt_38_4m_ck = {
129 .name = "virt_38_4m_ck",
131 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
133 .clkdm = { .name = "prm_clkdm" },
134 .recalc = &propagate_rate,
137 static const struct clksel_rate osc_sys_12m_rates[] = {
138 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
142 static const struct clksel_rate osc_sys_13m_rates[] = {
143 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
147 static const struct clksel_rate osc_sys_16_8m_rates[] = {
148 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
152 static const struct clksel_rate osc_sys_19_2m_rates[] = {
153 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
157 static const struct clksel_rate osc_sys_26m_rates[] = {
158 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
162 static const struct clksel_rate osc_sys_38_4m_rates[] = {
163 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
167 static const struct clksel osc_sys_clksel[] = {
168 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
169 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
170 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
171 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
172 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
173 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
177 /* Oscillator clock */
178 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
179 static struct clk osc_sys_ck = {
180 .name = "osc_sys_ck",
181 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET,
184 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
185 .clksel = osc_sys_clksel,
186 /* REVISIT: deal with autoextclkmode? */
187 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
189 .clkdm = { .name = "prm_clkdm" },
190 .recalc = &omap2_clksel_recalc,
193 static const struct clksel_rate div2_rates[] = {
194 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
195 { .div = 2, .val = 2, .flags = RATE_IN_343X },
199 static const struct clksel sys_clksel[] = {
200 { .parent = &osc_sys_ck, .rates = div2_rates },
204 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
205 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
206 static struct clk sys_ck = {
208 .parent = &osc_sys_ck,
209 .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
210 .init = &omap2_init_clksel_parent,
211 .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
212 .clksel_mask = OMAP_SYSCLKDIV_MASK,
213 .clksel = sys_clksel,
214 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
215 .clkdm = { .name = "prm_clkdm" },
216 .recalc = &omap2_clksel_recalc,
219 static struct clk sys_altclk = {
220 .name = "sys_altclk",
221 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
222 .clkdm = { .name = "cm_clkdm" },
223 .recalc = &propagate_rate,
227 * Optional external clock input for some McBSPs
228 * Apparently this is not really in prm_clkdm, but rather is fed into
229 * both CORE and PER separately.
231 static struct clk mcbsp_clks = {
232 .name = "mcbsp_clks",
233 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
234 .clkdm = { .name = "prm_clkdm" },
235 .recalc = &propagate_rate,
238 /* PRM EXTERNAL CLOCK OUTPUT */
240 static struct clk sys_clkout1 = {
241 .name = "sys_clkout1",
242 .parent = &osc_sys_ck,
243 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
244 .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
245 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
246 .flags = CLOCK_IN_OMAP343X,
247 .clkdm = { .name = "prm_clkdm" },
248 .recalc = &followparent_recalc,
255 static const struct clksel_rate div16_dpll_rates[] = {
256 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
257 { .div = 2, .val = 2, .flags = RATE_IN_343X },
258 { .div = 3, .val = 3, .flags = RATE_IN_343X },
259 { .div = 4, .val = 4, .flags = RATE_IN_343X },
260 { .div = 5, .val = 5, .flags = RATE_IN_343X },
261 { .div = 6, .val = 6, .flags = RATE_IN_343X },
262 { .div = 7, .val = 7, .flags = RATE_IN_343X },
263 { .div = 8, .val = 8, .flags = RATE_IN_343X },
264 { .div = 9, .val = 9, .flags = RATE_IN_343X },
265 { .div = 10, .val = 10, .flags = RATE_IN_343X },
266 { .div = 11, .val = 11, .flags = RATE_IN_343X },
267 { .div = 12, .val = 12, .flags = RATE_IN_343X },
268 { .div = 13, .val = 13, .flags = RATE_IN_343X },
269 { .div = 14, .val = 14, .flags = RATE_IN_343X },
270 { .div = 15, .val = 15, .flags = RATE_IN_343X },
271 { .div = 16, .val = 16, .flags = RATE_IN_343X },
276 /* MPU clock source */
278 static struct dpll_data dpll1_dd = {
279 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
280 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
281 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
282 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
283 .control_reg = OMAP3430_CM_CLKEN_PLL,
284 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
285 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
286 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
287 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
288 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
289 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
290 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
291 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
292 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
293 .bypass_clk = &dpll1_fck,
294 .max_multiplier = OMAP3_MAX_DPLL_MULT,
296 .max_divider = OMAP3_MAX_DPLL_DIV,
297 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
300 static struct clk dpll1_ck = {
304 .dpll_data = &dpll1_dd,
305 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
306 .round_rate = &omap2_dpll_round_rate,
307 .set_rate = &omap3_noncore_dpll_set_rate,
308 .clkdm = { .name = "dpll1_clkdm" },
309 .recalc = &omap3_dpll_recalc,
313 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
314 * DPLL isn't bypassed.
316 static struct clk dpll1_x2_ck = {
317 .name = "dpll1_x2_ck",
319 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
320 PARENT_CONTROLS_CLOCK,
321 .clkdm = { .name = "dpll1_clkdm" },
322 .recalc = &omap3_clkoutx2_recalc,
325 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
326 static const struct clksel div16_dpll1_x2m2_clksel[] = {
327 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
332 * Does not exist in the TRM - needed to separate the M2 divider from
333 * bypass selection in mpu_ck
335 static struct clk dpll1_x2m2_ck = {
336 .name = "dpll1_x2m2_ck",
337 .parent = &dpll1_x2_ck,
339 .init = &omap2_init_clksel_parent,
340 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
341 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
342 .clksel = div16_dpll1_x2m2_clksel,
343 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
344 PARENT_CONTROLS_CLOCK,
345 .clkdm = { .name = "dpll1_clkdm" },
346 .recalc = &omap2_clksel_recalc,
350 /* IVA2 clock source */
353 static struct dpll_data dpll2_dd = {
354 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
355 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
356 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
357 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
358 .control_reg = OMAP3430_CM_CLKEN_PLL,
359 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
360 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
361 (1 << DPLL_LOW_POWER_BYPASS),
362 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
363 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
364 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
365 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
366 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
367 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
368 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
369 .bypass_clk = &dpll2_fck,
370 .max_multiplier = OMAP3_MAX_DPLL_MULT,
372 .max_divider = OMAP3_MAX_DPLL_DIV,
373 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
376 static struct clk dpll2_ck = {
379 .prcm_mod = OMAP3430_IVA2_MOD,
380 .dpll_data = &dpll2_dd,
381 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
382 .enable = &omap3_noncore_dpll_enable,
383 .disable = &omap3_noncore_dpll_disable,
384 .round_rate = &omap2_dpll_round_rate,
385 .set_rate = &omap3_noncore_dpll_set_rate,
386 .clkdm = { .name = "dpll2_clkdm" },
387 .recalc = &omap3_dpll_recalc,
390 static const struct clksel div16_dpll2_m2x2_clksel[] = {
391 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
396 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
397 * or CLKOUTX2. CLKOUT seems most plausible.
399 static struct clk dpll2_m2_ck = {
400 .name = "dpll2_m2_ck",
402 .prcm_mod = OMAP3430_IVA2_MOD,
403 .init = &omap2_init_clksel_parent,
404 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
405 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
406 .clksel = div16_dpll2_m2x2_clksel,
407 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
408 PARENT_CONTROLS_CLOCK,
409 .clkdm = { .name = "dpll2_clkdm" },
410 .recalc = &omap2_clksel_recalc,
415 * Source clock for all interfaces and for some device fclks
416 * REVISIT: Also supports fast relock bypass - not included below
418 static struct dpll_data dpll3_dd = {
419 .mult_div1_reg = CM_CLKSEL1,
420 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
421 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
422 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
423 .control_reg = CM_CLKEN,
424 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
425 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
426 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
427 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
428 .autoidle_reg = CM_AUTOIDLE,
429 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
430 .idlest_reg = CM_IDLEST,
431 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
432 .bypass_clk = &sys_ck,
433 .max_multiplier = OMAP3_MAX_DPLL_MULT,
435 .max_divider = OMAP3_MAX_DPLL_DIV,
436 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
439 static struct clk dpll3_ck = {
443 .dpll_data = &dpll3_dd,
444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
445 .round_rate = &omap2_dpll_round_rate,
446 .clkdm = { .name = "dpll3_clkdm" },
447 .recalc = &omap3_dpll_recalc,
451 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
452 * DPLL isn't bypassed
454 static struct clk dpll3_x2_ck = {
455 .name = "dpll3_x2_ck",
457 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
458 PARENT_CONTROLS_CLOCK,
459 .clkdm = { .name = "dpll3_clkdm" },
460 .recalc = &omap3_clkoutx2_recalc,
463 static const struct clksel_rate div31_dpll3_rates[] = {
464 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
465 { .div = 2, .val = 2, .flags = RATE_IN_343X },
466 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
467 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
468 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
469 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
470 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
471 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
472 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
473 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
474 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
475 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
476 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
477 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
478 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
479 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
480 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
481 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
482 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
483 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
484 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
485 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
486 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
487 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
488 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
489 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
490 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
491 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
492 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
493 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
494 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
498 static const struct clksel div31_dpll3m2_clksel[] = {
499 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
503 /* DPLL3 output M2 - primary control point for CORE speed */
504 static struct clk dpll3_m2_ck = {
505 .name = "dpll3_m2_ck",
508 .init = &omap2_init_clksel_parent,
509 .clksel_reg = CM_CLKSEL1,
510 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
511 .clksel = div31_dpll3m2_clksel,
512 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
513 PARENT_CONTROLS_CLOCK,
514 .clkdm = { .name = "dpll3_clkdm" },
515 .round_rate = &omap2_clksel_round_rate,
516 .set_rate = &omap3_core_dpll_m2_set_rate,
517 .recalc = &omap2_clksel_recalc,
520 static struct clk core_ck = {
522 .parent = &dpll3_m2_ck,
523 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
524 PARENT_CONTROLS_CLOCK,
525 .clkdm = { .name = "cm_clkdm" },
526 .recalc = &followparent_recalc,
529 static struct clk dpll3_m2x2_ck = {
530 .name = "dpll3_m2x2_ck",
531 .parent = &dpll3_x2_ck,
532 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
533 PARENT_CONTROLS_CLOCK,
534 .clkdm = { .name = "dpll3_clkdm" },
535 .recalc = &followparent_recalc,
538 /* The PWRDN bit is apparently only available on 3430ES2 and above */
539 static const struct clksel div16_dpll3_clksel[] = {
540 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
544 /* This virtual clock is the source for dpll3_m3x2_ck */
545 static struct clk dpll3_m3_ck = {
546 .name = "dpll3_m3_ck",
548 .prcm_mod = OMAP3430_EMU_MOD,
549 .init = &omap2_init_clksel_parent,
550 .clksel_reg = CM_CLKSEL1,
551 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
552 .clksel = div16_dpll3_clksel,
553 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
554 PARENT_CONTROLS_CLOCK,
555 .clkdm = { .name = "dpll3_clkdm" },
556 .recalc = &omap2_clksel_recalc,
559 /* The PWRDN bit is apparently only available on 3430ES2 and above */
560 static struct clk dpll3_m3x2_ck = {
561 .name = "dpll3_m3x2_ck",
562 .parent = &dpll3_m3_ck,
564 .enable_reg = CM_CLKEN,
565 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
566 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
567 .clkdm = { .name = "dpll3_clkdm" },
568 .recalc = &omap3_clkoutx2_recalc,
571 static struct clk emu_core_alwon_ck = {
572 .name = "emu_core_alwon_ck",
573 .parent = &dpll3_m3x2_ck,
574 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
575 PARENT_CONTROLS_CLOCK,
576 .clkdm = { .name = "dpll3_clkdm" },
577 .recalc = &followparent_recalc,
581 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
583 static struct dpll_data dpll4_dd = {
584 .mult_div1_reg = CM_CLKSEL2,
585 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
586 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
587 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
588 .control_reg = CM_CLKEN,
589 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
590 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
591 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
592 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
593 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
594 .autoidle_reg = CM_AUTOIDLE,
595 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
596 .idlest_reg = CM_IDLEST,
597 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
598 .bypass_clk = &sys_ck,
599 .max_multiplier = OMAP3_MAX_DPLL_MULT,
601 .max_divider = OMAP3_MAX_DPLL_DIV,
602 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
605 static struct clk dpll4_ck = {
609 .dpll_data = &dpll4_dd,
610 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
611 .enable = &omap3_noncore_dpll_enable,
612 .disable = &omap3_noncore_dpll_disable,
613 .round_rate = &omap2_dpll_round_rate,
614 .set_rate = &omap3_noncore_dpll_set_rate,
615 .clkdm = { .name = "dpll4_clkdm" },
616 .recalc = &omap3_dpll_recalc,
620 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
621 * DPLL isn't bypassed --
622 * XXX does this serve any downstream clocks?
624 static struct clk dpll4_x2_ck = {
625 .name = "dpll4_x2_ck",
627 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
628 PARENT_CONTROLS_CLOCK,
629 .clkdm = { .name = "dpll4_clkdm" },
630 .recalc = &omap3_clkoutx2_recalc,
633 static const struct clksel div16_dpll4_clksel[] = {
634 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
638 /* This virtual clock is the source for dpll4_m2x2_ck */
639 static struct clk dpll4_m2_ck = {
640 .name = "dpll4_m2_ck",
643 .init = &omap2_init_clksel_parent,
644 .clksel_reg = OMAP3430_CM_CLKSEL3,
645 .clksel_mask = OMAP3430_DIV_96M_MASK,
646 .clksel = div16_dpll4_clksel,
647 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
648 PARENT_CONTROLS_CLOCK,
649 .clkdm = { .name = "dpll4_clkdm" },
650 .recalc = &omap2_clksel_recalc,
653 /* The PWRDN bit is apparently only available on 3430ES2 and above */
654 static struct clk dpll4_m2x2_ck = {
655 .name = "dpll4_m2x2_ck",
656 .parent = &dpll4_m2_ck,
658 .enable_reg = CM_CLKEN,
659 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
660 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
661 .clkdm = { .name = "dpll4_clkdm" },
662 .recalc = &omap3_clkoutx2_recalc,
666 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
667 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
668 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
671 static struct clk omap_96m_alwon_fck = {
672 .name = "omap_96m_alwon_fck",
673 .parent = &dpll4_m2x2_ck,
674 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
675 PARENT_CONTROLS_CLOCK,
676 .clkdm = { .name = "prm_clkdm" },
677 .recalc = &followparent_recalc,
680 static struct clk cm_96m_fck = {
681 .name = "cm_96m_fck",
682 .parent = &omap_96m_alwon_fck,
683 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
684 PARENT_CONTROLS_CLOCK,
685 .clkdm = { .name = "cm_clkdm" },
686 .recalc = &followparent_recalc,
689 static const struct clksel_rate omap_96m_dpll_rates[] = {
690 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
694 static const struct clksel_rate omap_96m_sys_rates[] = {
695 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
699 static const struct clksel omap_96m_fck_clksel[] = {
700 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
701 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
705 static struct clk omap_96m_fck = {
706 .name = "omap_96m_fck",
709 .init = &omap2_init_clksel_parent,
710 .clksel_reg = CM_CLKSEL1,
711 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
712 .clksel = omap_96m_fck_clksel,
713 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
714 PARENT_CONTROLS_CLOCK,
715 .clkdm = { .name = "cm_clkdm" },
716 .recalc = &omap2_clksel_recalc,
719 /* This virtual clock is the source for dpll4_m3x2_ck */
720 static struct clk dpll4_m3_ck = {
721 .name = "dpll4_m3_ck",
723 .prcm_mod = OMAP3430_DSS_MOD,
724 .init = &omap2_init_clksel_parent,
725 .clksel_reg = CM_CLKSEL,
726 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
727 .clksel = div16_dpll4_clksel,
728 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
729 PARENT_CONTROLS_CLOCK,
730 .clkdm = { .name = "dpll4_clkdm" },
731 .recalc = &omap2_clksel_recalc,
734 /* The PWRDN bit is apparently only available on 3430ES2 and above */
735 static struct clk dpll4_m3x2_ck = {
736 .name = "dpll4_m3x2_ck",
737 .parent = &dpll4_m3_ck,
739 .init = &omap2_init_clksel_parent,
740 .enable_reg = CM_CLKEN,
741 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
742 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
743 .clkdm = { .name = "dpll4_clkdm" },
744 .recalc = &omap3_clkoutx2_recalc,
747 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
748 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
752 static const struct clksel_rate omap_54m_alt_rates[] = {
753 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
757 static const struct clksel omap_54m_clksel[] = {
758 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
759 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
763 static struct clk omap_54m_fck = {
764 .name = "omap_54m_fck",
766 .init = &omap2_init_clksel_parent,
767 .clksel_reg = CM_CLKSEL1,
768 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
769 .clksel = omap_54m_clksel,
770 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
771 PARENT_CONTROLS_CLOCK,
772 .clkdm = { .name = "cm_clkdm" },
773 .recalc = &omap2_clksel_recalc,
776 static const struct clksel_rate omap_48m_cm96m_rates[] = {
777 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
781 static const struct clksel_rate omap_48m_alt_rates[] = {
782 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
786 static const struct clksel omap_48m_clksel[] = {
787 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
788 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
792 static struct clk omap_48m_fck = {
793 .name = "omap_48m_fck",
795 .init = &omap2_init_clksel_parent,
796 .clksel_reg = CM_CLKSEL1,
797 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
798 .clksel = omap_48m_clksel,
799 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
800 PARENT_CONTROLS_CLOCK,
801 .clkdm = { .name = "cm_clkdm" },
802 .recalc = &omap2_clksel_recalc,
805 static struct clk omap_12m_fck = {
806 .name = "omap_12m_fck",
807 .parent = &omap_48m_fck,
809 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
810 PARENT_CONTROLS_CLOCK,
811 .clkdm = { .name = "cm_clkdm" },
812 .recalc = &omap2_fixed_divisor_recalc,
815 /* This virstual clock is the source for dpll4_m4x2_ck */
816 static struct clk dpll4_m4_ck = {
817 .name = "dpll4_m4_ck",
819 .prcm_mod = OMAP3430_DSS_MOD,
820 .init = &omap2_init_clksel_parent,
821 .clksel_reg = CM_CLKSEL,
822 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
823 .clksel = div16_dpll4_clksel,
824 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
825 PARENT_CONTROLS_CLOCK,
826 .clkdm = { .name = "dpll4_clkdm" },
827 .recalc = &omap2_clksel_recalc,
828 .set_rate = &omap2_clksel_set_rate,
829 .round_rate = &omap2_clksel_round_rate,
832 /* The PWRDN bit is apparently only available on 3430ES2 and above */
833 static struct clk dpll4_m4x2_ck = {
834 .name = "dpll4_m4x2_ck",
835 .parent = &dpll4_m4_ck,
837 .enable_reg = CM_CLKEN,
838 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
839 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
840 .clkdm = { .name = "dpll4_clkdm" },
841 .recalc = &omap3_clkoutx2_recalc,
844 /* This virtual clock is the source for dpll4_m5x2_ck */
845 static struct clk dpll4_m5_ck = {
846 .name = "dpll4_m5_ck",
848 .prcm_mod = OMAP3430_CAM_MOD,
849 .init = &omap2_init_clksel_parent,
850 .clksel_reg = CM_CLKSEL,
851 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
852 .clksel = div16_dpll4_clksel,
853 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
854 PARENT_CONTROLS_CLOCK,
855 .clkdm = { .name = "dpll4_clkdm" },
856 .recalc = &omap2_clksel_recalc,
859 /* The PWRDN bit is apparently only available on 3430ES2 and above */
860 static struct clk dpll4_m5x2_ck = {
861 .name = "dpll4_m5x2_ck",
862 .parent = &dpll4_m5_ck,
864 .enable_reg = CM_CLKEN,
865 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
866 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
867 .clkdm = { .name = "dpll4_clkdm" },
868 .recalc = &omap3_clkoutx2_recalc,
871 /* This virtual clock is the source for dpll4_m6x2_ck */
872 static struct clk dpll4_m6_ck = {
873 .name = "dpll4_m6_ck",
875 .prcm_mod = OMAP3430_EMU_MOD,
876 .init = &omap2_init_clksel_parent,
877 .clksel_reg = CM_CLKSEL1,
878 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
879 .clksel = div16_dpll4_clksel,
880 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
881 PARENT_CONTROLS_CLOCK,
882 .clkdm = { .name = "dpll4_clkdm" },
883 .recalc = &omap2_clksel_recalc,
886 /* The PWRDN bit is apparently only available on 3430ES2 and above */
887 static struct clk dpll4_m6x2_ck = {
888 .name = "dpll4_m6x2_ck",
889 .parent = &dpll4_m6_ck,
891 .init = &omap2_init_clksel_parent,
892 .enable_reg = CM_CLKEN,
893 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
894 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
895 .clkdm = { .name = "dpll4_clkdm" },
896 .recalc = &omap3_clkoutx2_recalc,
899 static struct clk emu_per_alwon_ck = {
900 .name = "emu_per_alwon_ck",
901 .parent = &dpll4_m6x2_ck,
902 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
903 PARENT_CONTROLS_CLOCK,
904 .clkdm = { .name = "dpll4_clkdm" },
905 .recalc = &followparent_recalc,
909 /* Supplies 120MHz clock, USIM source clock */
912 static struct dpll_data dpll5_dd = {
913 .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4,
914 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
915 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
916 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
917 .control_reg = OMAP3430ES2_CM_CLKEN2,
918 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
919 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
920 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
921 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
922 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
923 .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL,
924 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
925 .idlest_reg = CM_IDLEST2,
926 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
927 .bypass_clk = &sys_ck,
928 .max_multiplier = OMAP3_MAX_DPLL_MULT,
930 .max_divider = OMAP3_MAX_DPLL_DIV,
931 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
934 static struct clk dpll5_ck = {
938 .dpll_data = &dpll5_dd,
939 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
940 .enable = &omap3_noncore_dpll_enable,
941 .disable = &omap3_noncore_dpll_disable,
942 .round_rate = &omap2_dpll_round_rate,
943 .set_rate = &omap3_noncore_dpll_set_rate,
944 .clkdm = { .name = "dpll5_clkdm" },
945 .recalc = &omap3_dpll_recalc,
948 static const struct clksel div16_dpll5_clksel[] = {
949 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
953 static struct clk dpll5_m2_ck = {
954 .name = "dpll5_m2_ck",
957 .init = &omap2_init_clksel_parent,
958 .clksel_reg = OMAP3430ES2_CM_CLKSEL5,
959 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
960 .clksel = div16_dpll5_clksel,
961 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
962 PARENT_CONTROLS_CLOCK,
963 .clkdm = { .name = "dpll5_clkdm" },
964 .recalc = &omap2_clksel_recalc,
967 /* CM EXTERNAL CLOCK OUTPUTS */
969 static const struct clksel_rate clkout2_src_core_rates[] = {
970 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
974 static const struct clksel_rate clkout2_src_sys_rates[] = {
975 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
979 static const struct clksel_rate clkout2_src_96m_rates[] = {
980 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
984 static const struct clksel_rate clkout2_src_54m_rates[] = {
985 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
989 static const struct clksel clkout2_src_clksel[] = {
990 { .parent = &core_ck, .rates = clkout2_src_core_rates },
991 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
992 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
993 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
997 static struct clk clkout2_src_ck = {
998 .name = "clkout2_src_ck",
999 .prcm_mod = OMAP3430_CCR_MOD,
1000 .init = &omap2_init_clksel_parent,
1001 .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1002 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1003 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1004 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1005 .clksel = clkout2_src_clksel,
1006 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1007 .clkdm = { .name = "cm_clkdm" },
1008 .recalc = &omap2_clksel_recalc,
1011 static const struct clksel_rate sys_clkout2_rates[] = {
1012 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1013 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1014 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1015 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1016 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1020 static const struct clksel sys_clkout2_clksel[] = {
1021 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1025 static struct clk sys_clkout2 = {
1026 .name = "sys_clkout2",
1027 .prcm_mod = OMAP3430_CCR_MOD,
1028 .init = &omap2_init_clksel_parent,
1029 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1030 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1031 .clksel = sys_clkout2_clksel,
1032 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1033 .clkdm = { .name = "cm_clkdm" },
1034 .recalc = &omap2_clksel_recalc,
1037 /* CM OUTPUT CLOCKS */
1039 static struct clk corex2_fck = {
1040 .name = "corex2_fck",
1041 .parent = &dpll3_m2x2_ck,
1042 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1043 PARENT_CONTROLS_CLOCK,
1044 .clkdm = { .name = "cm_clkdm" },
1045 .recalc = &followparent_recalc,
1048 /* DPLL power domain clock controls */
1050 static const struct clksel_rate div4_rates[] = {
1051 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1052 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1053 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1057 static const struct clksel div4_core_clksel[] = {
1058 { .parent = &core_ck, .rates = div4_rates },
1062 static struct clk dpll1_fck = {
1063 .name = "dpll1_fck",
1065 .prcm_mod = MPU_MOD,
1066 .init = &omap2_init_clksel_parent,
1067 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1068 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1069 .clksel = div4_core_clksel,
1070 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1071 PARENT_CONTROLS_CLOCK,
1072 .clkdm = { .name = "cm_clkdm" },
1073 .recalc = &omap2_clksel_recalc,
1076 static struct clk mpu_ck = {
1078 .parent = &dpll1_x2m2_ck,
1079 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1080 PARENT_CONTROLS_CLOCK,
1081 .clkdm = { .name = "mpu_clkdm" },
1082 .recalc = &followparent_recalc,
1085 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1086 static const struct clksel_rate arm_fck_rates[] = {
1087 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1088 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1092 static const struct clksel arm_fck_clksel[] = {
1093 { .parent = &mpu_ck, .rates = arm_fck_rates },
1097 static struct clk arm_fck = {
1100 .prcm_mod = MPU_MOD,
1101 .init = &omap2_init_clksel_parent,
1102 .clksel_reg = OMAP3430_CM_IDLEST_PLL,
1103 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1104 .clksel = arm_fck_clksel,
1105 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1106 PARENT_CONTROLS_CLOCK,
1107 .clkdm = { .name = "mpu_clkdm" },
1108 .recalc = &omap2_clksel_recalc,
1111 /* XXX What about neon_clkdm ? */
1114 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1115 * although it is referenced - so this is a guess
1117 static struct clk emu_mpu_alwon_ck = {
1118 .name = "emu_mpu_alwon_ck",
1120 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1121 PARENT_CONTROLS_CLOCK,
1122 .clkdm = { .name = "mpu_clkdm" },
1123 .recalc = &followparent_recalc,
1126 static struct clk dpll2_fck = {
1127 .name = "dpll2_fck",
1129 .prcm_mod = OMAP3430_IVA2_MOD,
1130 .init = &omap2_init_clksel_parent,
1131 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1132 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1133 .clksel = div4_core_clksel,
1134 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1135 PARENT_CONTROLS_CLOCK,
1136 .clkdm = { .name = "cm_clkdm" },
1137 .recalc = &omap2_clksel_recalc,
1140 static struct clk iva2_ck = {
1142 .parent = &dpll2_m2_ck,
1143 .prcm_mod = OMAP3430_IVA2_MOD,
1144 .init = &omap2_init_clksel_parent,
1145 .enable_reg = CM_FCLKEN,
1146 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1147 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1148 .clkdm = { .name = "iva2_clkdm" },
1149 .recalc = &followparent_recalc,
1152 /* Common interface clocks */
1154 static const struct clksel div2_core_clksel[] = {
1155 { .parent = &core_ck, .rates = div2_rates },
1159 static struct clk l3_ick = {
1162 .prcm_mod = CORE_MOD,
1163 .init = &omap2_init_clksel_parent,
1164 .clksel_reg = CM_CLKSEL,
1165 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1166 .clksel = div2_core_clksel,
1167 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1168 PARENT_CONTROLS_CLOCK,
1169 .clkdm = { .name = "core_l3_clkdm" },
1170 .recalc = &omap2_clksel_recalc,
1173 static const struct clksel div2_l3_clksel[] = {
1174 { .parent = &l3_ick, .rates = div2_rates },
1178 static struct clk l4_ick = {
1181 .prcm_mod = CORE_MOD,
1182 .init = &omap2_init_clksel_parent,
1183 .clksel_reg = CM_CLKSEL,
1184 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1185 .clksel = div2_l3_clksel,
1186 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1187 PARENT_CONTROLS_CLOCK,
1188 .clkdm = { .name = "core_l4_clkdm" },
1189 .recalc = &omap2_clksel_recalc,
1193 static const struct clksel div2_l4_clksel[] = {
1194 { .parent = &l4_ick, .rates = div2_rates },
1198 static struct clk rm_ick = {
1201 .prcm_mod = WKUP_MOD,
1202 .init = &omap2_init_clksel_parent,
1203 .clksel_reg = CM_CLKSEL,
1204 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1205 .clksel = div2_l4_clksel,
1206 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1207 .clkdm = { .name = "cm_clkdm" },
1208 .recalc = &omap2_clksel_recalc,
1211 /* GFX power domain */
1213 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1215 static const struct clksel gfx_l3_clksel[] = {
1216 { .parent = &l3_ick, .rates = gfx_l3_rates },
1220 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1221 static struct clk gfx_l3_ck = {
1222 .name = "gfx_l3_ck",
1224 .prcm_mod = GFX_MOD,
1225 .init = &omap2_init_clksel_parent,
1226 .enable_reg = CM_ICLKEN,
1227 .enable_bit = OMAP_EN_GFX_SHIFT,
1228 .flags = CLOCK_IN_OMAP3430ES1,
1229 .clkdm = { .name = "gfx_3430es1_clkdm" },
1230 .recalc = &followparent_recalc,
1233 static struct clk gfx_l3_fck = {
1234 .name = "gfx_l3_fck",
1235 .parent = &gfx_l3_ck,
1236 .prcm_mod = GFX_MOD,
1237 .init = &omap2_init_clksel_parent,
1238 .clksel_reg = CM_CLKSEL,
1239 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1240 .clksel = gfx_l3_clksel,
1241 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1242 PARENT_CONTROLS_CLOCK,
1243 .clkdm = { .name = "gfx_3430es1_clkdm" },
1244 .recalc = &omap2_clksel_recalc,
1247 static struct clk gfx_l3_ick = {
1248 .name = "gfx_l3_ick",
1249 .parent = &gfx_l3_ck,
1250 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1251 .clkdm = { .name = "gfx_3430es1_clkdm" },
1252 .recalc = &followparent_recalc,
1255 static struct clk gfx_cg1_ck = {
1256 .name = "gfx_cg1_ck",
1257 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1258 .prcm_mod = GFX_MOD,
1259 .enable_reg = CM_FCLKEN,
1260 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1261 .flags = CLOCK_IN_OMAP3430ES1,
1262 .clkdm = { .name = "gfx_3430es1_clkdm" },
1263 .recalc = &followparent_recalc,
1266 static struct clk gfx_cg2_ck = {
1267 .name = "gfx_cg2_ck",
1268 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1269 .prcm_mod = GFX_MOD,
1270 .enable_reg = CM_FCLKEN,
1271 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1272 .flags = CLOCK_IN_OMAP3430ES1,
1273 .clkdm = { .name = "gfx_3430es1_clkdm" },
1274 .recalc = &followparent_recalc,
1277 /* SGX power domain - 3430ES2 only */
1279 static const struct clksel_rate sgx_core_rates[] = {
1280 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1281 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1282 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1286 static const struct clksel_rate sgx_96m_rates[] = {
1287 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1291 static const struct clksel sgx_clksel[] = {
1292 { .parent = &core_ck, .rates = sgx_core_rates },
1293 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1297 static struct clk sgx_fck = {
1299 .init = &omap2_init_clksel_parent,
1300 .prcm_mod = OMAP3430ES2_SGX_MOD,
1301 .enable_reg = CM_FCLKEN,
1302 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1303 .clksel_reg = CM_CLKSEL,
1304 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1305 .clksel = sgx_clksel,
1306 .flags = CLOCK_IN_OMAP3430ES2,
1307 .clkdm = { .name = "sgx_clkdm" },
1308 .recalc = &omap2_clksel_recalc,
1311 static struct clk sgx_ick = {
1314 .prcm_mod = OMAP3430ES2_SGX_MOD,
1315 .enable_reg = CM_ICLKEN,
1316 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1317 .flags = CLOCK_IN_OMAP3430ES2,
1318 .clkdm = { .name = "sgx_clkdm" },
1319 .recalc = &followparent_recalc,
1322 /* CORE power domain */
1324 static struct clk d2d_26m_fck = {
1325 .name = "d2d_26m_fck",
1327 .prcm_mod = CORE_MOD,
1328 .enable_reg = CM_FCLKEN1,
1329 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1330 .flags = CLOCK_IN_OMAP3430ES1,
1331 .clkdm = { .name = "d2d_clkdm" },
1332 .recalc = &followparent_recalc,
1335 static const struct clksel omap343x_gpt_clksel[] = {
1336 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1337 { .parent = &sys_ck, .rates = gpt_sys_rates },
1341 static struct clk gpt10_fck = {
1342 .name = "gpt10_fck",
1344 .prcm_mod = CORE_MOD,
1345 .init = &omap2_init_clksel_parent,
1346 .enable_reg = CM_FCLKEN1,
1347 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1348 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
1349 .clksel_reg = CM_CLKSEL,
1350 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1351 .clksel = omap343x_gpt_clksel,
1352 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1353 .clkdm = { .name = "core_l4_clkdm" },
1354 .recalc = &omap2_clksel_recalc,
1357 static struct clk gpt11_fck = {
1358 .name = "gpt11_fck",
1360 .prcm_mod = CORE_MOD,
1361 .init = &omap2_init_clksel_parent,
1362 .enable_reg = CM_FCLKEN1,
1363 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1364 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
1365 .clksel_reg = CM_CLKSEL,
1366 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1367 .clksel = omap343x_gpt_clksel,
1368 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1369 .clkdm = { .name = "core_l4_clkdm" },
1370 .recalc = &omap2_clksel_recalc,
1373 static struct clk cpefuse_fck = {
1374 .name = "cpefuse_fck",
1376 .prcm_mod = CORE_MOD,
1377 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1378 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1379 .idlest_bit = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1380 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1381 .clkdm = { .name = "cm_clkdm" },
1382 .recalc = &followparent_recalc,
1385 static struct clk ts_fck = {
1387 .parent = &omap_32k_fck,
1388 .prcm_mod = CORE_MOD,
1389 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1390 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1391 .flags = CLOCK_IN_OMAP3430ES2,
1392 .clkdm = { .name = "core_l4_clkdm" },
1393 .recalc = &followparent_recalc,
1396 static struct clk usbtll_fck = {
1397 .name = "usbtll_fck",
1398 .parent = &dpll5_m2_ck,
1399 .prcm_mod = CORE_MOD,
1400 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1401 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1402 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1403 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1404 .clkdm = { .name = "core_l4_clkdm" },
1405 .recalc = &followparent_recalc,
1408 /* CORE 96M FCLK-derived clocks */
1410 static struct clk core_96m_fck = {
1411 .name = "core_96m_fck",
1412 .parent = &omap_96m_fck,
1413 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1414 PARENT_CONTROLS_CLOCK,
1415 .clkdm = { .name = "core_l4_clkdm" },
1416 .recalc = &followparent_recalc,
1419 static struct clk mmchs3_fck = {
1420 .name = "mmchs_fck",
1422 .parent = &core_96m_fck,
1423 .prcm_mod = CORE_MOD,
1424 .enable_reg = CM_FCLKEN1,
1425 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1426 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1427 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1428 .clkdm = { .name = "core_l4_clkdm" },
1429 .recalc = &followparent_recalc,
1432 static struct clk mmchs2_fck = {
1433 .name = "mmchs_fck",
1435 .parent = &core_96m_fck,
1436 .prcm_mod = CORE_MOD,
1437 .enable_reg = CM_FCLKEN1,
1438 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1439 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1440 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1441 .clkdm = { .name = "core_l4_clkdm" },
1442 .recalc = &followparent_recalc,
1445 static struct clk mspro_fck = {
1446 .name = "mspro_fck",
1447 .parent = &core_96m_fck,
1448 .prcm_mod = CORE_MOD,
1449 .enable_reg = CM_FCLKEN1,
1450 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1451 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1452 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1453 .clkdm = { .name = "core_l4_clkdm" },
1454 .recalc = &followparent_recalc,
1457 static struct clk mmchs1_fck = {
1458 .name = "mmchs_fck",
1459 .parent = &core_96m_fck,
1460 .prcm_mod = CORE_MOD,
1461 .enable_reg = CM_FCLKEN1,
1462 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1463 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1464 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1465 .clkdm = { .name = "core_l4_clkdm" },
1466 .recalc = &followparent_recalc,
1469 static struct clk i2c3_fck = {
1472 .parent = &core_96m_fck,
1473 .prcm_mod = CORE_MOD,
1474 .enable_reg = CM_FCLKEN1,
1475 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1476 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
1477 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1478 .clkdm = { .name = "core_l4_clkdm" },
1479 .recalc = &followparent_recalc,
1482 static struct clk i2c2_fck = {
1485 .parent = &core_96m_fck,
1486 .prcm_mod = CORE_MOD,
1487 .enable_reg = CM_FCLKEN1,
1488 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1489 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
1490 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1491 .clkdm = { .name = "core_l4_clkdm" },
1492 .recalc = &followparent_recalc,
1495 static struct clk i2c1_fck = {
1498 .parent = &core_96m_fck,
1499 .prcm_mod = CORE_MOD,
1500 .enable_reg = CM_FCLKEN1,
1501 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1502 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
1503 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1504 .clkdm = { .name = "core_l4_clkdm" },
1505 .recalc = &followparent_recalc,
1509 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1510 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1512 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1513 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1517 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1518 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1522 static const struct clksel mcbsp_15_clksel[] = {
1523 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1524 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1528 static struct clk mcbsp5_src_fck = {
1529 .name = "mcbsp_src_fck",
1531 .prcm_mod = CLK_REG_IN_SCM,
1532 .init = &omap2_init_clksel_parent,
1533 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
1534 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1535 .clksel = mcbsp_15_clksel,
1536 .flags = CLOCK_IN_OMAP343X,
1537 .clkdm = { .name = "core_l4_clkdm" },
1538 .recalc = &omap2_clksel_recalc,
1541 static struct clk mcbsp5_fck = {
1542 .name = "mcbsp_fck",
1544 .parent = &mcbsp5_src_fck,
1545 .prcm_mod = CORE_MOD,
1546 .enable_reg = CM_FCLKEN1,
1547 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1548 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
1549 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1550 .clkdm = { .name = "core_l4_clkdm" },
1551 .recalc = &followparent_recalc,
1554 static struct clk mcbsp1_src_fck = {
1555 .name = "mcbsp_src_fck",
1557 .prcm_mod = CLK_REG_IN_SCM,
1558 .init = &omap2_init_clksel_parent,
1559 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
1560 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1561 .clksel = mcbsp_15_clksel,
1562 .flags = CLOCK_IN_OMAP343X,
1563 .clkdm = { .name = "core_l4_clkdm" },
1564 .recalc = &omap2_clksel_recalc,
1567 static struct clk mcbsp1_fck = {
1568 .name = "mcbsp_fck",
1570 .parent = &mcbsp1_src_fck,
1571 .prcm_mod = CORE_MOD,
1572 .enable_reg = CM_FCLKEN1,
1573 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1574 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
1575 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1576 .clkdm = { .name = "core_l4_clkdm" },
1577 .recalc = &followparent_recalc,
1580 /* CORE_48M_FCK-derived clocks */
1582 static struct clk core_48m_fck = {
1583 .name = "core_48m_fck",
1584 .parent = &omap_48m_fck,
1585 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1586 PARENT_CONTROLS_CLOCK,
1587 .clkdm = { .name = "core_l4_clkdm" },
1588 .recalc = &followparent_recalc,
1591 static struct clk mcspi4_fck = {
1592 .name = "mcspi_fck",
1594 .parent = &core_48m_fck,
1595 .prcm_mod = CORE_MOD,
1596 .enable_reg = CM_FCLKEN1,
1597 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1598 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1599 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1600 .clkdm = { .name = "core_l4_clkdm" },
1601 .recalc = &followparent_recalc,
1604 static struct clk mcspi3_fck = {
1605 .name = "mcspi_fck",
1607 .parent = &core_48m_fck,
1608 .prcm_mod = CORE_MOD,
1609 .enable_reg = CM_FCLKEN1,
1610 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1611 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
1612 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1613 .clkdm = { .name = "core_l4_clkdm" },
1614 .recalc = &followparent_recalc,
1617 static struct clk mcspi2_fck = {
1618 .name = "mcspi_fck",
1620 .parent = &core_48m_fck,
1621 .prcm_mod = CORE_MOD,
1622 .enable_reg = CM_FCLKEN1,
1623 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1624 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
1625 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1626 .clkdm = { .name = "core_l4_clkdm" },
1627 .recalc = &followparent_recalc,
1630 static struct clk mcspi1_fck = {
1631 .name = "mcspi_fck",
1633 .parent = &core_48m_fck,
1634 .prcm_mod = CORE_MOD,
1635 .enable_reg = CM_FCLKEN1,
1636 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1637 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
1638 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1639 .clkdm = { .name = "core_l4_clkdm" },
1640 .recalc = &followparent_recalc,
1643 static struct clk uart2_fck = {
1644 .name = "uart2_fck",
1645 .parent = &core_48m_fck,
1646 .prcm_mod = CORE_MOD,
1647 .enable_reg = CM_FCLKEN1,
1648 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1649 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
1650 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1651 .clkdm = { .name = "core_l4_clkdm" },
1652 .recalc = &followparent_recalc,
1655 static struct clk uart1_fck = {
1656 .name = "uart1_fck",
1657 .parent = &core_48m_fck,
1658 .prcm_mod = CORE_MOD,
1659 .enable_reg = CM_FCLKEN1,
1660 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1661 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
1662 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1663 .clkdm = { .name = "core_l4_clkdm" },
1664 .recalc = &followparent_recalc,
1667 /* XXX doublecheck: is this idle or standby? */
1668 static struct clk fshostusb_fck = {
1669 .name = "fshostusb_fck",
1670 .parent = &core_48m_fck,
1671 .prcm_mod = CORE_MOD,
1672 .enable_reg = CM_FCLKEN1,
1673 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1674 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1675 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1676 .clkdm = { .name = "core_l4_clkdm" },
1677 .recalc = &followparent_recalc,
1680 /* CORE_12M_FCK based clocks */
1682 static struct clk core_12m_fck = {
1683 .name = "core_12m_fck",
1684 .parent = &omap_12m_fck,
1685 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1686 PARENT_CONTROLS_CLOCK,
1687 .clkdm = { .name = "core_l4_clkdm" },
1688 .recalc = &followparent_recalc,
1691 static struct clk hdq_fck = {
1693 .parent = &core_12m_fck,
1694 .prcm_mod = CORE_MOD,
1695 .enable_reg = CM_FCLKEN1,
1696 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1697 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1698 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1699 .clkdm = { .name = "core_l4_clkdm" },
1700 .recalc = &followparent_recalc,
1703 /* DPLL3-derived clock */
1705 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1706 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1707 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1708 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1709 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1710 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1711 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1715 static const struct clksel ssi_ssr_clksel[] = {
1716 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1720 static struct clk ssi_ssr_fck_3430es1 = {
1721 .name = "ssi_ssr_fck",
1722 .init = &omap2_init_clksel_parent,
1723 .prcm_mod = CORE_MOD,
1724 .enable_reg = CM_FCLKEN1,
1725 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1726 .clksel_reg = CM_CLKSEL,
1727 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1728 .clksel = ssi_ssr_clksel,
1729 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1730 .clkdm = { .name = "core_l4_clkdm" },
1731 .recalc = &omap2_clksel_recalc,
1734 static struct clk ssi_ssr_fck_3430es2 = {
1735 .name = "ssi_ssr_fck",
1736 .init = &omap2_init_clksel_parent,
1737 .prcm_mod = CORE_MOD,
1738 .enable_reg = CM_FCLKEN1,
1739 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1740 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1741 .clksel_reg = CM_CLKSEL,
1742 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1743 .clksel = ssi_ssr_clksel,
1744 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | WAIT_READY,
1745 .clkdm = { .name = "core_l4_clkdm" },
1746 .recalc = &omap2_clksel_recalc,
1749 /* It's unfortunate that we need to duplicate this clock. */
1750 static struct clk ssi_sst_fck_3430es1 = {
1751 .name = "ssi_sst_fck",
1752 .parent = &ssi_ssr_fck_3430es1,
1754 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1755 .clkdm = { .name = "core_l4_clkdm" },
1756 .recalc = &omap2_fixed_divisor_recalc,
1759 static struct clk ssi_sst_fck_3430es2 = {
1760 .name = "ssi_sst_fck",
1761 .parent = &ssi_ssr_fck_3430es2,
1763 .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1764 .clkdm = { .name = "core_l4_clkdm" },
1765 .recalc = &omap2_fixed_divisor_recalc,
1770 /* CORE_L3_ICK based clocks */
1773 * XXX must add clk_enable/clk_disable for these if standard code won't
1776 static struct clk core_l3_ick = {
1777 .name = "core_l3_ick",
1779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1780 PARENT_CONTROLS_CLOCK,
1781 .clkdm = { .name = "core_l3_clkdm" },
1782 .recalc = &followparent_recalc,
1785 static struct clk hsotgusb_ick_3430es1 = {
1786 .name = "hsotgusb_ick",
1787 .parent = &core_l3_ick,
1788 .prcm_mod = CORE_MOD,
1789 .enable_reg = CM_ICLKEN1,
1790 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1791 .flags = CLOCK_IN_OMAP3430ES1,
1792 .clkdm = { .name = "core_l3_clkdm" },
1793 .recalc = &followparent_recalc,
1796 static struct clk hsotgusb_ick_3430es2 = {
1797 .name = "hsotgusb_ick",
1798 .parent = &core_l3_ick,
1799 .prcm_mod = CORE_MOD,
1800 .enable_reg = CM_ICLKEN1,
1801 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1802 .idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1803 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1804 .clkdm = { .name = "core_l3_clkdm" },
1805 .recalc = &followparent_recalc,
1808 static struct clk sdrc_ick = {
1810 .parent = &core_l3_ick,
1811 .prcm_mod = CORE_MOD,
1812 .enable_reg = CM_ICLKEN1,
1813 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1814 .idlest_bit = OMAP3430_ST_SDRC_SHIFT,
1815 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1816 .clkdm = { .name = "core_l3_clkdm" },
1817 .recalc = &followparent_recalc,
1820 static struct clk gpmc_fck = {
1822 .parent = &core_l3_ick,
1823 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1825 .clkdm = { .name = "core_l3_clkdm" },
1826 .recalc = &followparent_recalc,
1829 /* SECURITY_L3_ICK based clocks */
1831 static struct clk security_l3_ick = {
1832 .name = "security_l3_ick",
1834 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1835 PARENT_CONTROLS_CLOCK,
1836 .clkdm = { .name = "core_l3_clkdm" },
1837 .recalc = &followparent_recalc,
1840 static struct clk pka_ick = {
1842 .parent = &security_l3_ick,
1843 .prcm_mod = CORE_MOD,
1844 .enable_reg = CM_ICLKEN2,
1845 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1846 .idlest_bit = OMAP3430_ST_PKA_SHIFT,
1847 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1848 .clkdm = { .name = "core_l3_clkdm" },
1849 .recalc = &followparent_recalc,
1852 /* CORE_L4_ICK based clocks */
1854 static struct clk core_l4_ick = {
1855 .name = "core_l4_ick",
1857 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1858 PARENT_CONTROLS_CLOCK,
1859 .clkdm = { .name = "core_l4_clkdm" },
1860 .recalc = &followparent_recalc,
1863 static struct clk usbtll_ick = {
1864 .name = "usbtll_ick",
1865 .parent = &core_l4_ick,
1866 .prcm_mod = CORE_MOD,
1867 .enable_reg = CM_ICLKEN3,
1868 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1869 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1870 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1871 .clkdm = { .name = "core_l4_clkdm" },
1872 .recalc = &followparent_recalc,
1875 static struct clk mmchs3_ick = {
1876 .name = "mmchs_ick",
1878 .parent = &core_l4_ick,
1879 .prcm_mod = CORE_MOD,
1880 .enable_reg = CM_ICLKEN1,
1881 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1882 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1883 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1884 .clkdm = { .name = "core_l4_clkdm" },
1885 .recalc = &followparent_recalc,
1888 /* Intersystem Communication Registers - chassis mode only */
1889 static struct clk icr_ick = {
1891 .parent = &core_l4_ick,
1892 .prcm_mod = CORE_MOD,
1893 .enable_reg = CM_ICLKEN1,
1894 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1895 .idlest_bit = OMAP3430_ST_ICR_SHIFT,
1896 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1897 .clkdm = { .name = "core_l4_clkdm" },
1898 .recalc = &followparent_recalc,
1901 static struct clk aes2_ick = {
1903 .parent = &core_l4_ick,
1904 .prcm_mod = CORE_MOD,
1905 .enable_reg = CM_ICLKEN1,
1906 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1907 .idlest_bit = OMAP3430_ST_AES2_SHIFT,
1908 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1909 .clkdm = { .name = "core_l4_clkdm" },
1910 .recalc = &followparent_recalc,
1913 static struct clk sha12_ick = {
1914 .name = "sha12_ick",
1915 .parent = &core_l4_ick,
1916 .prcm_mod = CORE_MOD,
1917 .enable_reg = CM_ICLKEN1,
1918 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1919 .idlest_bit = OMAP3430_ST_SHA12_SHIFT,
1920 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1921 .clkdm = { .name = "core_l4_clkdm" },
1922 .recalc = &followparent_recalc,
1925 static struct clk des2_ick = {
1927 .parent = &core_l4_ick,
1928 .prcm_mod = CORE_MOD,
1929 .enable_reg = CM_ICLKEN1,
1930 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1931 .idlest_bit = OMAP3430_ST_DES2_SHIFT,
1932 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1933 .clkdm = { .name = "core_l4_clkdm" },
1934 .recalc = &followparent_recalc,
1937 static struct clk mmchs2_ick = {
1938 .name = "mmchs_ick",
1940 .parent = &core_l4_ick,
1941 .prcm_mod = CORE_MOD,
1942 .enable_reg = CM_ICLKEN1,
1943 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1944 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1945 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1946 .clkdm = { .name = "core_l4_clkdm" },
1947 .recalc = &followparent_recalc,
1950 static struct clk mmchs1_ick = {
1951 .name = "mmchs_ick",
1952 .parent = &core_l4_ick,
1953 .prcm_mod = CORE_MOD,
1954 .enable_reg = CM_ICLKEN1,
1955 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1956 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1957 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1958 .clkdm = { .name = "core_l4_clkdm" },
1959 .recalc = &followparent_recalc,
1962 static struct clk mspro_ick = {
1963 .name = "mspro_ick",
1964 .parent = &core_l4_ick,
1965 .prcm_mod = CORE_MOD,
1966 .enable_reg = CM_ICLKEN1,
1967 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1968 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1969 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1970 .clkdm = { .name = "core_l4_clkdm" },
1971 .recalc = &followparent_recalc,
1974 static struct clk hdq_ick = {
1976 .parent = &core_l4_ick,
1977 .prcm_mod = CORE_MOD,
1978 .enable_reg = CM_ICLKEN1,
1979 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1980 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1981 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1982 .clkdm = { .name = "core_l4_clkdm" },
1983 .recalc = &followparent_recalc,
1986 static struct clk mcspi4_ick = {
1987 .name = "mcspi_ick",
1989 .parent = &core_l4_ick,
1990 .prcm_mod = CORE_MOD,
1991 .enable_reg = CM_ICLKEN1,
1992 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1993 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1994 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1995 .clkdm = { .name = "core_l4_clkdm" },
1996 .recalc = &followparent_recalc,
1999 static struct clk mcspi3_ick = {
2000 .name = "mcspi_ick",
2002 .parent = &core_l4_ick,
2003 .prcm_mod = CORE_MOD,
2004 .enable_reg = CM_ICLKEN1,
2005 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2006 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
2007 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2008 .clkdm = { .name = "core_l4_clkdm" },
2009 .recalc = &followparent_recalc,
2012 static struct clk mcspi2_ick = {
2013 .name = "mcspi_ick",
2015 .parent = &core_l4_ick,
2016 .prcm_mod = CORE_MOD,
2017 .enable_reg = CM_ICLKEN1,
2018 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2019 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
2020 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2021 .clkdm = { .name = "core_l4_clkdm" },
2022 .recalc = &followparent_recalc,
2025 static struct clk mcspi1_ick = {
2026 .name = "mcspi_ick",
2028 .parent = &core_l4_ick,
2029 .prcm_mod = CORE_MOD,
2030 .enable_reg = CM_ICLKEN1,
2031 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2032 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
2033 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2034 .clkdm = { .name = "core_l4_clkdm" },
2035 .recalc = &followparent_recalc,
2038 static struct clk i2c3_ick = {
2041 .parent = &core_l4_ick,
2042 .prcm_mod = CORE_MOD,
2043 .enable_reg = CM_ICLKEN1,
2044 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2045 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
2046 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2047 .clkdm = { .name = "core_l4_clkdm" },
2048 .recalc = &followparent_recalc,
2051 static struct clk i2c2_ick = {
2054 .parent = &core_l4_ick,
2055 .prcm_mod = CORE_MOD,
2056 .enable_reg = CM_ICLKEN1,
2057 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2058 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
2059 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2060 .clkdm = { .name = "core_l4_clkdm" },
2061 .recalc = &followparent_recalc,
2064 static struct clk i2c1_ick = {
2067 .parent = &core_l4_ick,
2068 .prcm_mod = CORE_MOD,
2069 .enable_reg = CM_ICLKEN1,
2070 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
2071 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
2072 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2073 .clkdm = { .name = "core_l4_clkdm" },
2074 .recalc = &followparent_recalc,
2077 static struct clk uart2_ick = {
2078 .name = "uart2_ick",
2079 .parent = &core_l4_ick,
2080 .prcm_mod = CORE_MOD,
2081 .enable_reg = CM_ICLKEN1,
2082 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2083 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
2084 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2085 .clkdm = { .name = "core_l4_clkdm" },
2086 .recalc = &followparent_recalc,
2089 static struct clk uart1_ick = {
2090 .name = "uart1_ick",
2091 .parent = &core_l4_ick,
2092 .prcm_mod = CORE_MOD,
2093 .enable_reg = CM_ICLKEN1,
2094 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2095 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
2096 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2097 .clkdm = { .name = "core_l4_clkdm" },
2098 .recalc = &followparent_recalc,
2101 static struct clk gpt11_ick = {
2102 .name = "gpt11_ick",
2103 .parent = &core_l4_ick,
2104 .prcm_mod = CORE_MOD,
2105 .enable_reg = CM_ICLKEN1,
2106 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2107 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
2108 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2109 .clkdm = { .name = "core_l4_clkdm" },
2110 .recalc = &followparent_recalc,
2113 static struct clk gpt10_ick = {
2114 .name = "gpt10_ick",
2115 .parent = &core_l4_ick,
2116 .prcm_mod = CORE_MOD,
2117 .enable_reg = CM_ICLKEN1,
2118 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2119 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
2120 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2121 .clkdm = { .name = "core_l4_clkdm" },
2122 .recalc = &followparent_recalc,
2125 static struct clk mcbsp5_ick = {
2126 .name = "mcbsp_ick",
2128 .parent = &core_l4_ick,
2129 .prcm_mod = CORE_MOD,
2130 .enable_reg = CM_ICLKEN1,
2131 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2132 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
2133 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2134 .clkdm = { .name = "core_l4_clkdm" },
2135 .recalc = &followparent_recalc,
2138 static struct clk mcbsp1_ick = {
2139 .name = "mcbsp_ick",
2141 .parent = &core_l4_ick,
2142 .prcm_mod = CORE_MOD,
2143 .enable_reg = CM_ICLKEN1,
2144 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2145 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
2146 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2147 .clkdm = { .name = "core_l4_clkdm" },
2148 .recalc = &followparent_recalc,
2151 static struct clk fac_ick = {
2153 .parent = &core_l4_ick,
2154 .prcm_mod = CORE_MOD,
2155 .enable_reg = CM_ICLKEN1,
2156 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2157 .idlest_bit = OMAP3430ES1_ST_FAC_SHIFT,
2158 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2159 .clkdm = { .name = "core_l4_clkdm" },
2160 .recalc = &followparent_recalc,
2163 static struct clk mailboxes_ick = {
2164 .name = "mailboxes_ick",
2165 .parent = &core_l4_ick,
2166 .prcm_mod = CORE_MOD,
2167 .enable_reg = CM_ICLKEN1,
2168 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2169 .idlest_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2170 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2171 .clkdm = { .name = "core_l4_clkdm" },
2172 .recalc = &followparent_recalc,
2175 static struct clk omapctrl_ick = {
2176 .name = "omapctrl_ick",
2177 .parent = &core_l4_ick,
2178 .prcm_mod = CORE_MOD,
2179 .enable_reg = CM_ICLKEN1,
2180 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2181 .idlest_bit = OMAP3430_ST_OMAPCTRL_SHIFT,
2182 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2183 .clkdm = { .name = "core_l4_clkdm" },
2184 .recalc = &followparent_recalc,
2187 /* SSI_L4_ICK based clocks */
2189 static struct clk ssi_l4_ick = {
2190 .name = "ssi_l4_ick",
2192 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2193 PARENT_CONTROLS_CLOCK,
2194 .clkdm = { .name = "core_l4_clkdm" },
2195 .recalc = &followparent_recalc,
2198 static struct clk ssi_ick_3430es1 = {
2200 .parent = &ssi_l4_ick,
2201 .prcm_mod = CORE_MOD,
2202 .enable_reg = CM_ICLKEN1,
2203 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2204 .flags = CLOCK_IN_OMAP3430ES1,
2205 .clkdm = { .name = "core_l4_clkdm" },
2206 .recalc = &followparent_recalc,
2209 static struct clk ssi_ick_3430es2 = {
2211 .parent = &ssi_l4_ick,
2212 .prcm_mod = CORE_MOD,
2213 .enable_reg = CM_ICLKEN1,
2214 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2215 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2216 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2217 .clkdm = { .name = "core_l4_clkdm" },
2218 .recalc = &followparent_recalc,
2222 * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2223 * but l4_ick makes more sense to me
2225 static const struct clksel usb_l4_clksel[] = {
2226 { .parent = &l4_ick, .rates = div2_rates },
2230 static struct clk usb_l4_ick = {
2231 .name = "usb_l4_ick",
2233 .prcm_mod = CORE_MOD,
2234 .init = &omap2_init_clksel_parent,
2235 .enable_reg = CM_ICLKEN1,
2236 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2237 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2238 .clksel_reg = CM_CLKSEL,
2239 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2240 .clksel = usb_l4_clksel,
2241 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2242 .clkdm = { .name = "core_l4_clkdm" },
2243 .recalc = &omap2_clksel_recalc,
2246 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2248 /* SECURITY_L4_ICK2 based clocks */
2250 static struct clk security_l4_ick2 = {
2251 .name = "security_l4_ick2",
2253 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2254 PARENT_CONTROLS_CLOCK,
2255 .clkdm = { .name = "core_l4_clkdm" },
2256 .recalc = &followparent_recalc,
2259 static struct clk aes1_ick = {
2261 .parent = &security_l4_ick2,
2262 .prcm_mod = CORE_MOD,
2263 .enable_reg = CM_ICLKEN2,
2264 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2265 .idlest_bit = OMAP3430_ST_AES1_SHIFT,
2266 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2267 .clkdm = { .name = "core_l4_clkdm" },
2268 .recalc = &followparent_recalc,
2271 static struct clk rng_ick = {
2273 .parent = &security_l4_ick2,
2274 .prcm_mod = CORE_MOD,
2275 .enable_reg = CM_ICLKEN2,
2276 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2277 .idlest_bit = OMAP3430_ST_RNG_SHIFT,
2278 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2279 .clkdm = { .name = "core_l4_clkdm" },
2280 .recalc = &followparent_recalc,
2283 static struct clk sha11_ick = {
2284 .name = "sha11_ick",
2285 .parent = &security_l4_ick2,
2286 .prcm_mod = CORE_MOD,
2287 .enable_reg = CM_ICLKEN2,
2288 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2289 .idlest_bit = OMAP3430_ST_SHA11_SHIFT,
2290 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2291 .clkdm = { .name = "core_l4_clkdm" },
2292 .recalc = &followparent_recalc,
2295 static struct clk des1_ick = {
2297 .parent = &security_l4_ick2,
2298 .prcm_mod = CORE_MOD,
2299 .enable_reg = CM_ICLKEN2,
2300 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2301 .idlest_bit = OMAP3430_ST_DES1_SHIFT,
2302 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2303 .clkdm = { .name = "core_l4_clkdm" },
2304 .recalc = &followparent_recalc,
2308 static struct clk dss1_alwon_fck_3430es1 = {
2309 .name = "dss1_alwon_fck",
2310 .parent = &dpll4_m4x2_ck,
2311 .prcm_mod = OMAP3430_DSS_MOD,
2312 .enable_reg = CM_FCLKEN,
2313 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2314 .flags = CLOCK_IN_OMAP3430ES1,
2315 .clkdm = { .name = "dss_clkdm" },
2316 .recalc = &followparent_recalc,
2319 static struct clk dss1_alwon_fck_3430es2 = {
2320 .name = "dss1_alwon_fck",
2321 .parent = &dpll4_m4x2_ck,
2322 .init = &omap2_init_clksel_parent,
2323 .prcm_mod = OMAP3430_DSS_MOD,
2324 .enable_reg = CM_FCLKEN,
2325 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2326 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2327 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2328 .clkdm = { .name = "dss_clkdm" },
2329 .recalc = &followparent_recalc,
2332 static struct clk dss_tv_fck = {
2333 .name = "dss_tv_fck",
2334 .parent = &omap_54m_fck,
2335 .prcm_mod = OMAP3430_DSS_MOD,
2336 .enable_reg = CM_FCLKEN,
2337 .enable_bit = OMAP3430_EN_TV_SHIFT,
2338 .flags = CLOCK_IN_OMAP343X,
2339 .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2340 .recalc = &followparent_recalc,
2343 static struct clk dss_96m_fck = {
2344 .name = "dss_96m_fck",
2345 .parent = &omap_96m_fck,
2346 .prcm_mod = OMAP3430_DSS_MOD,
2347 .enable_reg = CM_FCLKEN,
2348 .enable_bit = OMAP3430_EN_TV_SHIFT,
2349 .flags = CLOCK_IN_OMAP343X,
2350 .clkdm = { .name = "dss_clkdm" },
2351 .recalc = &followparent_recalc,
2354 static struct clk dss2_alwon_fck = {
2355 .name = "dss2_alwon_fck",
2357 .prcm_mod = OMAP3430_DSS_MOD,
2358 .enable_reg = CM_FCLKEN,
2359 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2360 .flags = CLOCK_IN_OMAP343X,
2361 .clkdm = { .name = "dss_clkdm" },
2362 .recalc = &followparent_recalc,
2365 static struct clk dss_ick_3430es1 = {
2366 /* Handles both L3 and L4 clocks */
2369 .prcm_mod = OMAP3430_DSS_MOD,
2370 .enable_reg = CM_ICLKEN,
2371 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2372 .flags = CLOCK_IN_OMAP3430ES1,
2373 .clkdm = { .name = "dss_clkdm" },
2374 .recalc = &followparent_recalc,
2377 static struct clk dss_ick_3430es2 = {
2378 /* Handles both L3 and L4 clocks */
2381 .prcm_mod = OMAP3430_DSS_MOD,
2382 .enable_reg = CM_ICLKEN,
2383 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2384 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2385 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2386 .clkdm = { .name = "dss_clkdm" },
2387 .recalc = &followparent_recalc,
2392 static struct clk cam_mclk = {
2394 .parent = &dpll4_m5x2_ck,
2395 .prcm_mod = OMAP3430_CAM_MOD,
2396 .enable_reg = CM_FCLKEN,
2397 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2398 .flags = CLOCK_IN_OMAP343X,
2399 .clkdm = { .name = "cam_clkdm" },
2400 .recalc = &followparent_recalc,
2403 static struct clk cam_ick = {
2404 /* Handles both L3 and L4 clocks */
2407 .prcm_mod = OMAP3430_CAM_MOD,
2408 .enable_reg = CM_ICLKEN,
2409 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2410 .flags = CLOCK_IN_OMAP343X,
2411 .clkdm = { .name = "cam_clkdm" },
2412 .recalc = &followparent_recalc,
2415 static struct clk csi2_96m_fck = {
2416 .name = "csi2_96m_fck",
2417 .parent = &core_96m_fck,
2418 .prcm_mod = OMAP3430_CAM_MOD,
2419 .enable_reg = CM_FCLKEN,
2420 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2421 .flags = CLOCK_IN_OMAP343X,
2422 .clkdm = { .name = "cam_clkdm" },
2423 .recalc = &followparent_recalc,
2426 /* USBHOST - 3430ES2 only */
2428 static struct clk usbhost_120m_fck = {
2429 .name = "usbhost_120m_fck",
2430 .parent = &dpll5_m2_ck,
2431 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2432 .enable_reg = CM_FCLKEN,
2433 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2434 .flags = CLOCK_IN_OMAP3430ES2,
2435 .clkdm = { .name = "usbhost_clkdm" },
2436 .recalc = &followparent_recalc,
2439 static struct clk usbhost_48m_fck = {
2440 .name = "usbhost_48m_fck",
2441 .parent = &omap_48m_fck,
2442 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2443 .enable_reg = CM_FCLKEN,
2444 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2445 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2446 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2447 .clkdm = { .name = "usbhost_clkdm" },
2448 .recalc = &followparent_recalc,
2451 static struct clk usbhost_ick = {
2452 /* Handles both L3 and L4 clocks */
2453 .name = "usbhost_ick",
2455 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2456 .enable_reg = CM_ICLKEN,
2457 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2458 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2459 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2460 .clkdm = { .name = "usbhost_clkdm" },
2461 .recalc = &followparent_recalc,
2466 static const struct clksel_rate usim_96m_rates[] = {
2467 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2468 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2469 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2470 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2474 static const struct clksel_rate usim_120m_rates[] = {
2475 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2476 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2477 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2478 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2482 static const struct clksel usim_clksel[] = {
2483 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2484 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2485 { .parent = &sys_ck, .rates = div2_rates },
2490 static struct clk usim_fck = {
2492 .prcm_mod = WKUP_MOD,
2493 .init = &omap2_init_clksel_parent,
2494 .enable_reg = CM_FCLKEN,
2495 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2496 .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
2497 .clksel_reg = CM_CLKSEL,
2498 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2499 .clksel = usim_clksel,
2500 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2501 .clkdm = { .name = "prm_clkdm" },
2502 .recalc = &omap2_clksel_recalc,
2505 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2506 static struct clk gpt1_fck = {
2508 .prcm_mod = WKUP_MOD,
2509 .init = &omap2_init_clksel_parent,
2510 .enable_reg = CM_FCLKEN,
2511 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2512 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2513 .clksel_reg = CM_CLKSEL,
2514 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2515 .clksel = omap343x_gpt_clksel,
2516 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2517 .clkdm = { .name = "prm_clkdm" },
2518 .recalc = &omap2_clksel_recalc,
2521 static struct clk wkup_32k_fck = {
2522 .name = "wkup_32k_fck",
2523 .parent = &omap_32k_fck,
2524 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2525 .clkdm = { .name = "prm_clkdm" },
2526 .recalc = &followparent_recalc,
2529 static struct clk gpio1_dbck = {
2530 .name = "gpio1_dbck",
2531 .parent = &wkup_32k_fck,
2532 .prcm_mod = WKUP_MOD,
2533 .enable_reg = CM_FCLKEN,
2534 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2535 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2536 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2537 .clkdm = { .name = "prm_clkdm" },
2538 .recalc = &followparent_recalc,
2541 static struct clk wdt2_fck = {
2543 .parent = &wkup_32k_fck,
2544 .prcm_mod = WKUP_MOD,
2545 .enable_reg = CM_FCLKEN,
2546 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2547 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2548 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2549 .clkdm = { .name = "prm_clkdm" },
2550 .recalc = &followparent_recalc,
2553 static struct clk wkup_l4_ick = {
2554 .name = "wkup_l4_ick",
2556 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2557 .clkdm = { .name = "prm_clkdm" },
2558 .recalc = &followparent_recalc,
2561 static struct clk usim_ick = {
2563 .parent = &wkup_l4_ick,
2564 .prcm_mod = WKUP_MOD,
2565 .enable_reg = CM_ICLKEN,
2566 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2567 .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
2568 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2569 .clkdm = { .name = "prm_clkdm" },
2570 .recalc = &followparent_recalc,
2573 static struct clk wdt2_ick = {
2575 .parent = &wkup_l4_ick,
2576 .prcm_mod = WKUP_MOD,
2577 .enable_reg = CM_ICLKEN,
2578 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2579 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2580 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2581 .clkdm = { .name = "prm_clkdm" },
2582 .recalc = &followparent_recalc,
2585 static struct clk wdt1_ick = {
2587 .parent = &wkup_l4_ick,
2588 .prcm_mod = WKUP_MOD,
2589 .enable_reg = CM_ICLKEN,
2590 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2591 .idlest_bit = OMAP3430_ST_WDT1_SHIFT,
2592 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2593 .clkdm = { .name = "prm_clkdm" },
2594 .recalc = &followparent_recalc,
2597 static struct clk gpio1_ick = {
2598 .name = "gpio1_ick",
2599 .parent = &wkup_l4_ick,
2600 .prcm_mod = WKUP_MOD,
2601 .enable_reg = CM_ICLKEN,
2602 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2603 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2604 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2605 .clkdm = { .name = "prm_clkdm" },
2606 .recalc = &followparent_recalc,
2609 static struct clk omap_32ksync_ick = {
2610 .name = "omap_32ksync_ick",
2611 .parent = &wkup_l4_ick,
2612 .prcm_mod = WKUP_MOD,
2613 .enable_reg = CM_ICLKEN,
2614 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2615 .idlest_bit = OMAP3430_ST_32KSYNC_SHIFT,
2616 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2617 .clkdm = { .name = "prm_clkdm" },
2618 .recalc = &followparent_recalc,
2621 static struct clk gpt12_ick = {
2622 .name = "gpt12_ick",
2623 .parent = &wkup_l4_ick,
2624 .prcm_mod = WKUP_MOD,
2625 .enable_reg = CM_ICLKEN,
2626 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2627 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
2628 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2629 .clkdm = { .name = "prm_clkdm" },
2630 .recalc = &followparent_recalc,
2633 static struct clk gpt1_ick = {
2635 .parent = &wkup_l4_ick,
2636 .prcm_mod = WKUP_MOD,
2637 .enable_reg = CM_ICLKEN,
2638 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2639 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2640 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2641 .clkdm = { .name = "prm_clkdm" },
2642 .recalc = &followparent_recalc,
2647 /* PER clock domain */
2649 static struct clk per_96m_fck = {
2650 .name = "per_96m_fck",
2651 .parent = &omap_96m_alwon_fck,
2652 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2653 PARENT_CONTROLS_CLOCK,
2654 .clkdm = { .name = "per_clkdm" },
2655 .recalc = &followparent_recalc,
2658 static struct clk per_48m_fck = {
2659 .name = "per_48m_fck",
2660 .parent = &omap_48m_fck,
2661 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2662 PARENT_CONTROLS_CLOCK,
2663 .clkdm = { .name = "per_clkdm" },
2664 .recalc = &followparent_recalc,
2667 static struct clk uart3_fck = {
2668 .name = "uart3_fck",
2669 .parent = &per_48m_fck,
2670 .prcm_mod = OMAP3430_PER_MOD,
2671 .enable_reg = CM_FCLKEN,
2672 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2673 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2674 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2675 .clkdm = { .name = "per_clkdm" },
2676 .recalc = &followparent_recalc,
2679 static struct clk gpt2_fck = {
2681 .prcm_mod = OMAP3430_PER_MOD,
2682 .init = &omap2_init_clksel_parent,
2683 .enable_reg = CM_FCLKEN,
2684 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2685 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
2686 .clksel_reg = CM_CLKSEL,
2687 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2688 .clksel = omap343x_gpt_clksel,
2689 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2690 .clkdm = { .name = "per_clkdm" },
2691 .recalc = &omap2_clksel_recalc,
2694 static struct clk gpt3_fck = {
2696 .prcm_mod = OMAP3430_PER_MOD,
2697 .init = &omap2_init_clksel_parent,
2698 .enable_reg = CM_FCLKEN,
2699 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2700 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
2701 .clksel_reg = CM_CLKSEL,
2702 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2703 .clksel = omap343x_gpt_clksel,
2704 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2705 .clkdm = { .name = "per_clkdm" },
2706 .recalc = &omap2_clksel_recalc,
2709 static struct clk gpt4_fck = {
2711 .prcm_mod = OMAP3430_PER_MOD,
2712 .init = &omap2_init_clksel_parent,
2713 .enable_reg = CM_FCLKEN,
2714 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2715 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
2716 .clksel_reg = CM_CLKSEL,
2717 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2718 .clksel = omap343x_gpt_clksel,
2719 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2720 .clkdm = { .name = "per_clkdm" },
2721 .recalc = &omap2_clksel_recalc,
2724 static struct clk gpt5_fck = {
2726 .prcm_mod = OMAP3430_PER_MOD,
2727 .init = &omap2_init_clksel_parent,
2728 .enable_reg = CM_FCLKEN,
2729 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2730 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
2731 .clksel_reg = CM_CLKSEL,
2732 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2733 .clksel = omap343x_gpt_clksel,
2734 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2735 .clkdm = { .name = "per_clkdm" },
2736 .recalc = &omap2_clksel_recalc,
2739 static struct clk gpt6_fck = {
2741 .prcm_mod = OMAP3430_PER_MOD,
2742 .init = &omap2_init_clksel_parent,
2743 .enable_reg = CM_FCLKEN,
2744 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2745 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
2746 .clksel_reg = CM_CLKSEL,
2747 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2748 .clksel = omap343x_gpt_clksel,
2749 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2750 .clkdm = { .name = "per_clkdm" },
2751 .recalc = &omap2_clksel_recalc,
2754 static struct clk gpt7_fck = {
2756 .prcm_mod = OMAP3430_PER_MOD,
2757 .init = &omap2_init_clksel_parent,
2758 .enable_reg = CM_FCLKEN,
2759 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2760 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2761 .clksel_reg = CM_CLKSEL,
2762 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2763 .clksel = omap343x_gpt_clksel,
2764 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2765 .clkdm = { .name = "per_clkdm" },
2766 .recalc = &omap2_clksel_recalc,
2769 static struct clk gpt8_fck = {
2771 .prcm_mod = OMAP3430_PER_MOD,
2772 .init = &omap2_init_clksel_parent,
2773 .enable_reg = CM_FCLKEN,
2774 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2775 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2776 .clksel_reg = CM_CLKSEL,
2777 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2778 .clksel = omap343x_gpt_clksel,
2779 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2780 .clkdm = { .name = "per_clkdm" },
2781 .recalc = &omap2_clksel_recalc,
2784 static struct clk gpt9_fck = {
2786 .prcm_mod = OMAP3430_PER_MOD,
2787 .init = &omap2_init_clksel_parent,
2788 .enable_reg = CM_FCLKEN,
2789 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2790 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2791 .clksel_reg = CM_CLKSEL,
2792 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2793 .clksel = omap343x_gpt_clksel,
2794 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2795 .clkdm = { .name = "per_clkdm" },
2796 .recalc = &omap2_clksel_recalc,
2799 static struct clk per_32k_alwon_fck = {
2800 .name = "per_32k_alwon_fck",
2801 .parent = &omap_32k_fck,
2802 .clkdm = { .name = "per_clkdm" },
2803 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2804 .recalc = &followparent_recalc,
2807 static struct clk gpio6_dbck = {
2808 .name = "gpio6_dbck",
2809 .parent = &per_32k_alwon_fck,
2810 .prcm_mod = OMAP3430_PER_MOD,
2811 .enable_reg = CM_FCLKEN,
2812 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2813 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2814 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2815 .clkdm = { .name = "per_clkdm" },
2816 .recalc = &followparent_recalc,
2819 static struct clk gpio5_dbck = {
2820 .name = "gpio5_dbck",
2821 .parent = &per_32k_alwon_fck,
2822 .prcm_mod = OMAP3430_PER_MOD,
2823 .enable_reg = CM_FCLKEN,
2824 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2825 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2826 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2827 .clkdm = { .name = "per_clkdm" },
2828 .recalc = &followparent_recalc,
2831 static struct clk gpio4_dbck = {
2832 .name = "gpio4_dbck",
2833 .parent = &per_32k_alwon_fck,
2834 .prcm_mod = OMAP3430_PER_MOD,
2835 .enable_reg = CM_FCLKEN,
2836 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2837 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2838 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2839 .clkdm = { .name = "per_clkdm" },
2840 .recalc = &followparent_recalc,
2843 static struct clk gpio3_dbck = {
2844 .name = "gpio3_dbck",
2845 .parent = &per_32k_alwon_fck,
2846 .prcm_mod = OMAP3430_PER_MOD,
2847 .enable_reg = CM_FCLKEN,
2848 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2849 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2850 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2851 .clkdm = { .name = "per_clkdm" },
2852 .recalc = &followparent_recalc,
2855 static struct clk gpio2_dbck = {
2856 .name = "gpio2_dbck",
2857 .parent = &per_32k_alwon_fck,
2858 .prcm_mod = OMAP3430_PER_MOD,
2859 .enable_reg = CM_FCLKEN,
2860 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2861 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2862 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2863 .clkdm = { .name = "per_clkdm" },
2864 .recalc = &followparent_recalc,
2867 static struct clk wdt3_fck = {
2869 .parent = &per_32k_alwon_fck,
2870 .prcm_mod = OMAP3430_PER_MOD,
2871 .enable_reg = CM_FCLKEN,
2872 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2873 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2874 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2875 .clkdm = { .name = "per_clkdm" },
2876 .recalc = &followparent_recalc,
2879 static struct clk per_l4_ick = {
2880 .name = "per_l4_ick",
2882 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2883 PARENT_CONTROLS_CLOCK,
2884 .clkdm = { .name = "per_clkdm" },
2885 .recalc = &followparent_recalc,
2888 static struct clk gpio6_ick = {
2889 .name = "gpio6_ick",
2890 .parent = &per_l4_ick,
2891 .prcm_mod = OMAP3430_PER_MOD,
2892 .enable_reg = CM_ICLKEN,
2893 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2894 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2895 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2896 .clkdm = { .name = "per_clkdm" },
2897 .recalc = &followparent_recalc,
2900 static struct clk gpio5_ick = {
2901 .name = "gpio5_ick",
2902 .parent = &per_l4_ick,
2903 .prcm_mod = OMAP3430_PER_MOD,
2904 .enable_reg = CM_ICLKEN,
2905 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2906 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2907 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2908 .clkdm = { .name = "per_clkdm" },
2909 .recalc = &followparent_recalc,
2912 static struct clk gpio4_ick = {
2913 .name = "gpio4_ick",
2914 .parent = &per_l4_ick,
2915 .prcm_mod = OMAP3430_PER_MOD,
2916 .enable_reg = CM_ICLKEN,
2917 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2918 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2919 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2920 .clkdm = { .name = "per_clkdm" },
2921 .recalc = &followparent_recalc,
2924 static struct clk gpio3_ick = {
2925 .name = "gpio3_ick",
2926 .parent = &per_l4_ick,
2927 .prcm_mod = OMAP3430_PER_MOD,
2928 .enable_reg = CM_ICLKEN,
2929 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2930 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2931 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2932 .clkdm = { .name = "per_clkdm" },
2933 .recalc = &followparent_recalc,
2936 static struct clk gpio2_ick = {
2937 .name = "gpio2_ick",
2938 .parent = &per_l4_ick,
2939 .prcm_mod = OMAP3430_PER_MOD,
2940 .enable_reg = CM_ICLKEN,
2941 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2942 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2943 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2944 .clkdm = { .name = "per_clkdm" },
2945 .recalc = &followparent_recalc,
2948 static struct clk wdt3_ick = {
2950 .parent = &per_l4_ick,
2951 .prcm_mod = OMAP3430_PER_MOD,
2952 .enable_reg = CM_ICLKEN,
2953 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2954 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2955 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2956 .clkdm = { .name = "per_clkdm" },
2957 .recalc = &followparent_recalc,
2960 static struct clk uart3_ick = {
2961 .name = "uart3_ick",
2962 .parent = &per_l4_ick,
2963 .prcm_mod = OMAP3430_PER_MOD,
2964 .enable_reg = CM_ICLKEN,
2965 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2966 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2967 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2968 .clkdm = { .name = "per_clkdm" },
2969 .recalc = &followparent_recalc,
2972 static struct clk gpt9_ick = {
2974 .parent = &per_l4_ick,
2975 .prcm_mod = OMAP3430_PER_MOD,
2976 .enable_reg = CM_ICLKEN,
2977 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2978 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2979 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2980 .clkdm = { .name = "per_clkdm" },
2981 .recalc = &followparent_recalc,
2984 static struct clk gpt8_ick = {
2986 .parent = &per_l4_ick,
2987 .prcm_mod = OMAP3430_PER_MOD,
2988 .enable_reg = CM_ICLKEN,
2989 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2990 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2991 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2992 .clkdm = { .name = "per_clkdm" },
2993 .recalc = &followparent_recalc,
2996 static struct clk gpt7_ick = {
2998 .parent = &per_l4_ick,
2999 .prcm_mod = OMAP3430_PER_MOD,
3000 .enable_reg = CM_ICLKEN,
3001 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
3002 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
3003 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3004 .clkdm = { .name = "per_clkdm" },
3005 .recalc = &followparent_recalc,
3008 static struct clk gpt6_ick = {
3010 .parent = &per_l4_ick,
3011 .prcm_mod = OMAP3430_PER_MOD,
3012 .enable_reg = CM_ICLKEN,
3013 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
3014 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
3015 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3016 .clkdm = { .name = "per_clkdm" },
3017 .recalc = &followparent_recalc,
3020 static struct clk gpt5_ick = {
3022 .parent = &per_l4_ick,
3023 .prcm_mod = OMAP3430_PER_MOD,
3024 .enable_reg = CM_ICLKEN,
3025 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
3026 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
3027 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3028 .clkdm = { .name = "per_clkdm" },
3029 .recalc = &followparent_recalc,
3032 static struct clk gpt4_ick = {
3034 .parent = &per_l4_ick,
3035 .prcm_mod = OMAP3430_PER_MOD,
3036 .enable_reg = CM_ICLKEN,
3037 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
3038 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
3039 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3040 .clkdm = { .name = "per_clkdm" },
3041 .recalc = &followparent_recalc,
3044 static struct clk gpt3_ick = {
3046 .parent = &per_l4_ick,
3047 .prcm_mod = OMAP3430_PER_MOD,
3048 .enable_reg = CM_ICLKEN,
3049 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
3050 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
3051 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3052 .clkdm = { .name = "per_clkdm" },
3053 .recalc = &followparent_recalc,
3056 static struct clk gpt2_ick = {
3058 .parent = &per_l4_ick,
3059 .prcm_mod = OMAP3430_PER_MOD,
3060 .enable_reg = CM_ICLKEN,
3061 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
3062 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
3063 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3064 .clkdm = { .name = "per_clkdm" },
3065 .recalc = &followparent_recalc,
3068 static struct clk mcbsp2_ick = {
3069 .name = "mcbsp_ick",
3071 .parent = &per_l4_ick,
3072 .prcm_mod = OMAP3430_PER_MOD,
3073 .enable_reg = CM_ICLKEN,
3074 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3075 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3076 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3077 .clkdm = { .name = "per_clkdm" },
3078 .recalc = &followparent_recalc,
3081 static struct clk mcbsp3_ick = {
3082 .name = "mcbsp_ick",
3084 .parent = &per_l4_ick,
3085 .prcm_mod = OMAP3430_PER_MOD,
3086 .enable_reg = CM_ICLKEN,
3087 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3088 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3089 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3090 .clkdm = { .name = "per_clkdm" },
3091 .recalc = &followparent_recalc,
3094 static struct clk mcbsp4_ick = {
3095 .name = "mcbsp_ick",
3097 .parent = &per_l4_ick,
3098 .prcm_mod = OMAP3430_PER_MOD,
3099 .enable_reg = CM_ICLKEN,
3100 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3101 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3102 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3103 .clkdm = { .name = "per_clkdm" },
3104 .recalc = &followparent_recalc,
3107 static const struct clksel mcbsp_234_clksel[] = {
3108 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3109 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
3113 static struct clk mcbsp2_src_fck = {
3114 .name = "mcbsp_src_fck",
3116 .prcm_mod = CLK_REG_IN_SCM,
3117 .init = &omap2_init_clksel_parent,
3118 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
3119 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
3120 .clksel = mcbsp_234_clksel,
3121 .flags = CLOCK_IN_OMAP343X,
3122 .clkdm = { .name = "per_clkdm" },
3123 .recalc = &omap2_clksel_recalc,
3126 static struct clk mcbsp2_fck = {
3127 .name = "mcbsp_fck",
3129 .parent = &mcbsp2_src_fck,
3130 .prcm_mod = OMAP3430_PER_MOD,
3131 .enable_reg = CM_FCLKEN,
3132 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3133 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3134 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3135 .clkdm = { .name = "per_clkdm" },
3136 .recalc = &omap2_clksel_recalc,
3139 static struct clk mcbsp3_src_fck = {
3140 .name = "mcbsp_src_fck",
3142 .prcm_mod = CLK_REG_IN_SCM,
3143 .init = &omap2_init_clksel_parent,
3144 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3145 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
3146 .clksel = mcbsp_234_clksel,
3147 .flags = CLOCK_IN_OMAP343X,
3148 .clkdm = { .name = "per_clkdm" },
3149 .recalc = &omap2_clksel_recalc,
3152 static struct clk mcbsp3_fck = {
3153 .name = "mcbsp_fck",
3155 .parent = &mcbsp3_src_fck,
3156 .prcm_mod = OMAP3430_PER_MOD,
3157 .enable_reg = CM_FCLKEN,
3158 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3159 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3160 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3161 .clkdm = { .name = "per_clkdm" },
3162 .recalc = &omap2_clksel_recalc,
3165 static struct clk mcbsp4_src_fck = {
3166 .name = "mcbsp_src_fck",
3168 .prcm_mod = CLK_REG_IN_SCM,
3169 .init = &omap2_init_clksel_parent,
3170 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3171 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
3172 .clksel = mcbsp_234_clksel,
3173 .flags = CLOCK_IN_OMAP343X,
3174 .clkdm = { .name = "per_clkdm" },
3175 .recalc = &omap2_clksel_recalc,
3178 static struct clk mcbsp4_fck = {
3179 .name = "mcbsp_fck",
3181 .parent = &mcbsp4_src_fck,
3182 .prcm_mod = OMAP3430_PER_MOD,
3183 .enable_reg = CM_FCLKEN,
3184 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3185 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3186 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3187 .clkdm = { .name = "per_clkdm" },
3188 .recalc = &omap2_clksel_recalc,
3193 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3195 static const struct clksel_rate emu_src_sys_rates[] = {
3196 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3200 static const struct clksel_rate emu_src_core_rates[] = {
3201 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3205 static const struct clksel_rate emu_src_per_rates[] = {
3206 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3210 static const struct clksel_rate emu_src_mpu_rates[] = {
3211 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3215 static const struct clksel emu_src_clksel[] = {
3216 { .parent = &sys_ck, .rates = emu_src_sys_rates },
3217 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3218 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
3219 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
3224 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3225 * to switch the source of some of the EMU clocks.
3226 * XXX Are there CLKEN bits for these EMU clks?
3228 static struct clk emu_src_ck = {
3229 .name = "emu_src_ck",
3230 .prcm_mod = OMAP3430_EMU_MOD,
3231 .init = &omap2_init_clksel_parent,
3232 .clksel_reg = CM_CLKSEL1,
3233 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
3234 .clksel = emu_src_clksel,
3235 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3236 .clkdm = { .name = "emu_clkdm" },
3237 .recalc = &omap2_clksel_recalc,
3240 static const struct clksel_rate pclk_emu_rates[] = {
3241 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3242 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3243 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3244 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3248 static const struct clksel pclk_emu_clksel[] = {
3249 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3253 static struct clk pclk_fck = {
3255 .prcm_mod = OMAP3430_EMU_MOD,
3256 .init = &omap2_init_clksel_parent,
3257 .clksel_reg = CM_CLKSEL1,
3258 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3259 .clksel = pclk_emu_clksel,
3260 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3261 .clkdm = { .name = "emu_clkdm" },
3262 .recalc = &omap2_clksel_recalc,
3265 static const struct clksel_rate pclkx2_emu_rates[] = {
3266 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3267 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3268 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3272 static const struct clksel pclkx2_emu_clksel[] = {
3273 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3277 static struct clk pclkx2_fck = {
3278 .name = "pclkx2_fck",
3279 .prcm_mod = OMAP3430_EMU_MOD,
3280 .init = &omap2_init_clksel_parent,
3281 .clksel_reg = CM_CLKSEL1,
3282 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3283 .clksel = pclkx2_emu_clksel,
3284 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3285 .clkdm = { .name = "emu_clkdm" },
3286 .recalc = &omap2_clksel_recalc,
3289 static const struct clksel atclk_emu_clksel[] = {
3290 { .parent = &emu_src_ck, .rates = div2_rates },
3294 static struct clk atclk_fck = {
3295 .name = "atclk_fck",
3296 .prcm_mod = OMAP3430_EMU_MOD,
3297 .init = &omap2_init_clksel_parent,
3298 .clksel_reg = CM_CLKSEL1,
3299 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3300 .clksel = atclk_emu_clksel,
3301 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3302 .clkdm = { .name = "emu_clkdm" },
3303 .recalc = &omap2_clksel_recalc,
3306 static struct clk traceclk_src_fck = {
3307 .name = "traceclk_src_fck",
3308 .prcm_mod = OMAP3430_EMU_MOD,
3309 .init = &omap2_init_clksel_parent,
3310 .clksel_reg = CM_CLKSEL1,
3311 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3312 .clksel = emu_src_clksel,
3313 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3314 .clkdm = { .name = "emu_clkdm" },
3315 .recalc = &omap2_clksel_recalc,
3318 static const struct clksel_rate traceclk_rates[] = {
3319 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3320 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3321 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3325 static const struct clksel traceclk_clksel[] = {
3326 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3330 static struct clk traceclk_fck = {
3331 .name = "traceclk_fck",
3332 .prcm_mod = OMAP3430_EMU_MOD,
3333 .init = &omap2_init_clksel_parent,
3334 .clksel_reg = CM_CLKSEL1,
3335 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3336 .clksel = traceclk_clksel,
3337 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3338 .clkdm = { .name = "emu_clkdm" },
3339 .recalc = &omap2_clksel_recalc,
3344 /* SmartReflex fclk (VDD1) */
3345 static struct clk sr1_fck = {
3348 .prcm_mod = WKUP_MOD,
3349 .enable_reg = CM_FCLKEN,
3350 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3351 .idlest_bit = OMAP3430_ST_SR1_SHIFT,
3352 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3353 .clkdm = { .name = "prm_clkdm" },
3354 .recalc = &followparent_recalc,
3357 /* SmartReflex fclk (VDD2) */
3358 static struct clk sr2_fck = {
3361 .prcm_mod = WKUP_MOD,
3362 .enable_reg = CM_FCLKEN,
3363 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3364 .idlest_bit = OMAP3430_ST_SR2_SHIFT,
3365 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3366 .clkdm = { .name = "prm_clkdm" },
3367 .recalc = &followparent_recalc,
3370 static struct clk sr_l4_ick = {
3371 .name = "sr_l4_ick",
3373 .flags = CLOCK_IN_OMAP343X,
3374 .clkdm = { .name = "core_l4_clkdm" },
3375 .recalc = &followparent_recalc,
3378 /* SECURE_32K_FCK clocks */
3380 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3381 static struct clk gpt12_fck = {
3382 .name = "gpt12_fck",
3383 .parent = &secure_32k_fck,
3384 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
3385 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3386 .clkdm = { .name = "prm_clkdm" },
3387 .recalc = &followparent_recalc,
3390 static struct clk wdt1_fck = {
3392 .parent = &secure_32k_fck,
3393 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3394 .clkdm = { .name = "prm_clkdm" },
3395 .recalc = &followparent_recalc,
3398 static struct clk *onchip_34xx_clks[] __initdata = {
3426 &omap_96m_alwon_fck,
3492 &ssi_ssr_fck_3430es1,
3493 &ssi_ssr_fck_3430es2,
3494 &ssi_sst_fck_3430es1,
3495 &ssi_sst_fck_3430es2,
3497 &hsotgusb_ick_3430es1,
3498 &hsotgusb_ick_3430es2,
3539 &dss1_alwon_fck_3430es1,
3540 &dss1_alwon_fck_3430es2,