2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
32 static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
34 static void omap3_dpll_allow_idle(struct clk *clk);
35 static void omap3_dpll_deny_idle(struct clk *clk);
36 static u32 omap3_dpll_autoidle_read(struct clk *clk);
37 static int omap3_noncore_dpll_enable(struct clk *clk);
38 static void omap3_noncore_dpll_disable(struct clk *clk);
39 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
40 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
42 /* Maximum DPLL multiplier, divider values for OMAP3 */
43 #define OMAP3_MAX_DPLL_MULT 2048
44 #define OMAP3_MAX_DPLL_DIV 128
47 * DPLL1 supplies clock to the MPU.
48 * DPLL2 supplies clock to the IVA2.
49 * DPLL3 supplies CORE domain clocks.
50 * DPLL4 supplies peripheral clocks.
51 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 /* Forward declarations for DPLL bypass clocks */
55 static struct clk dpll1_fck;
56 static struct clk dpll2_fck;
58 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
59 #define DPLL_LOW_POWER_STOP 0x1
60 #define DPLL_LOW_POWER_BYPASS 0x5
61 #define DPLL_LOCKED 0x7
65 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
66 static struct clk omap_32k_fck = {
67 .name = "omap_32k_fck",
69 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
70 .clkdm = { .name = "prm_clkdm" },
73 static struct clk secure_32k_fck = {
74 .name = "secure_32k_fck",
76 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
77 .clkdm = { .name = "prm_clkdm" },
80 /* Virtual source clocks for osc_sys_ck */
81 static struct clk virt_12m_ck = {
82 .name = "virt_12m_ck",
84 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
85 .clkdm = { .name = "prm_clkdm" },
88 static struct clk virt_13m_ck = {
89 .name = "virt_13m_ck",
91 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
92 .clkdm = { .name = "prm_clkdm" },
95 static struct clk virt_16_8m_ck = {
96 .name = "virt_16_8m_ck",
98 .flags = CLOCK_IN_OMAP3430ES2 | ALWAYS_ENABLED,
99 .clkdm = { .name = "prm_clkdm" },
102 static struct clk virt_19_2m_ck = {
103 .name = "virt_19_2m_ck",
105 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
106 .clkdm = { .name = "prm_clkdm" },
109 static struct clk virt_26m_ck = {
110 .name = "virt_26m_ck",
112 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
113 .clkdm = { .name = "prm_clkdm" },
116 static struct clk virt_38_4m_ck = {
117 .name = "virt_38_4m_ck",
119 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
120 .clkdm = { .name = "prm_clkdm" },
123 static const struct clksel_rate osc_sys_12m_rates[] = {
124 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
128 static const struct clksel_rate osc_sys_13m_rates[] = {
129 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
133 static const struct clksel_rate osc_sys_16_8m_rates[] = {
134 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
138 static const struct clksel_rate osc_sys_19_2m_rates[] = {
139 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
143 static const struct clksel_rate osc_sys_26m_rates[] = {
144 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
148 static const struct clksel_rate osc_sys_38_4m_rates[] = {
149 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
153 static const struct clksel osc_sys_clksel[] = {
154 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
155 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
156 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
157 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
158 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
159 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
163 /* Oscillator clock */
164 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
165 static struct clk osc_sys_ck = {
166 .name = "osc_sys_ck",
167 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
168 .init = &omap2_init_clksel_parent,
169 .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET,
170 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
171 .clksel = osc_sys_clksel,
172 /* REVISIT: deal with autoextclkmode? */
173 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
174 .clkdm = { .name = "prm_clkdm" },
175 .recalc = &omap2_clksel_recalc,
178 static const struct clksel_rate div2_rates[] = {
179 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
180 { .div = 2, .val = 2, .flags = RATE_IN_343X },
184 static const struct clksel sys_clksel[] = {
185 { .parent = &osc_sys_ck, .rates = div2_rates },
189 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
190 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
191 static struct clk sys_ck = {
193 .parent = &osc_sys_ck,
194 .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
195 .init = &omap2_init_clksel_parent,
196 .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
197 .clksel_mask = OMAP_SYSCLKDIV_MASK,
198 .clksel = sys_clksel,
199 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
200 .clkdm = { .name = "prm_clkdm" },
201 .recalc = &omap2_clksel_recalc,
204 static struct clk sys_altclk = {
205 .name = "sys_altclk",
206 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
207 .clkdm = { .name = "cm_clkdm" },
211 * Optional external clock input for some McBSPs
212 * Apparently this is not really in prm_clkdm, but rather is fed into
213 * both CORE and PER separately.
215 static struct clk mcbsp_clks = {
216 .name = "mcbsp_clks",
217 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
218 .clkdm = { .name = "prm_clkdm" },
221 /* PRM EXTERNAL CLOCK OUTPUT */
223 static struct clk sys_clkout1 = {
224 .name = "sys_clkout1",
225 .parent = &osc_sys_ck,
226 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
227 .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
228 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
229 .flags = CLOCK_IN_OMAP343X,
230 .clkdm = { .name = "prm_clkdm" },
231 .recalc = &followparent_recalc,
238 static const struct clksel_rate div16_dpll_rates[] = {
239 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
240 { .div = 2, .val = 2, .flags = RATE_IN_343X },
241 { .div = 3, .val = 3, .flags = RATE_IN_343X },
242 { .div = 4, .val = 4, .flags = RATE_IN_343X },
243 { .div = 5, .val = 5, .flags = RATE_IN_343X },
244 { .div = 6, .val = 6, .flags = RATE_IN_343X },
245 { .div = 7, .val = 7, .flags = RATE_IN_343X },
246 { .div = 8, .val = 8, .flags = RATE_IN_343X },
247 { .div = 9, .val = 9, .flags = RATE_IN_343X },
248 { .div = 10, .val = 10, .flags = RATE_IN_343X },
249 { .div = 11, .val = 11, .flags = RATE_IN_343X },
250 { .div = 12, .val = 12, .flags = RATE_IN_343X },
251 { .div = 13, .val = 13, .flags = RATE_IN_343X },
252 { .div = 14, .val = 14, .flags = RATE_IN_343X },
253 { .div = 15, .val = 15, .flags = RATE_IN_343X },
254 { .div = 16, .val = 16, .flags = RATE_IN_343X },
259 /* MPU clock source */
261 static struct dpll_data dpll1_dd = {
262 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
263 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
264 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
265 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
266 .control_reg = OMAP3430_CM_CLKEN_PLL,
267 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
268 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
269 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
270 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
271 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
272 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
273 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
274 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
275 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
276 .bypass_clk = &dpll1_fck,
277 .max_multiplier = OMAP3_MAX_DPLL_MULT,
279 .max_divider = OMAP3_MAX_DPLL_DIV,
280 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
283 static struct clk dpll1_ck = {
287 .dpll_data = &dpll1_dd,
288 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
289 .round_rate = &omap2_dpll_round_rate,
290 .set_rate = &omap3_noncore_dpll_set_rate,
291 .clkdm = { .name = "dpll1_clkdm" },
292 .recalc = &omap3_dpll_recalc,
296 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
297 * DPLL isn't bypassed.
299 static struct clk dpll1_x2_ck = {
300 .name = "dpll1_x2_ck",
302 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
303 .clkdm = { .name = "dpll1_clkdm" },
304 .recalc = &omap3_clkoutx2_recalc,
307 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
308 static const struct clksel div16_dpll1_x2m2_clksel[] = {
309 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
314 * Does not exist in the TRM - needed to separate the M2 divider from
315 * bypass selection in mpu_ck
317 static struct clk dpll1_x2m2_ck = {
318 .name = "dpll1_x2m2_ck",
319 .parent = &dpll1_x2_ck,
321 .init = &omap2_init_clksel_parent,
322 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
323 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
324 .clksel = div16_dpll1_x2m2_clksel,
325 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
326 .clkdm = { .name = "dpll1_clkdm" },
327 .recalc = &omap2_clksel_recalc,
331 /* IVA2 clock source */
334 static struct dpll_data dpll2_dd = {
335 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
336 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
337 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
338 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
339 .control_reg = OMAP3430_CM_CLKEN_PLL,
340 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
341 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
342 (1 << DPLL_LOW_POWER_BYPASS),
343 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
344 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
345 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
346 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
347 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
348 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
349 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
350 .bypass_clk = &dpll2_fck,
351 .max_multiplier = OMAP3_MAX_DPLL_MULT,
353 .max_divider = OMAP3_MAX_DPLL_DIV,
354 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
357 static struct clk dpll2_ck = {
360 .prcm_mod = OMAP3430_IVA2_MOD,
361 .dpll_data = &dpll2_dd,
362 .flags = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
363 .enable = &omap3_noncore_dpll_enable,
364 .disable = &omap3_noncore_dpll_disable,
365 .round_rate = &omap2_dpll_round_rate,
366 .set_rate = &omap3_noncore_dpll_set_rate,
367 .clkdm = { .name = "dpll2_clkdm" },
368 .recalc = &omap3_dpll_recalc,
371 static const struct clksel div16_dpll2_m2x2_clksel[] = {
372 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
377 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
378 * or CLKOUTX2. CLKOUT seems most plausible.
380 static struct clk dpll2_m2_ck = {
381 .name = "dpll2_m2_ck",
383 .prcm_mod = OMAP3430_IVA2_MOD,
384 .init = &omap2_init_clksel_parent,
385 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
386 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
387 .clksel = div16_dpll2_m2x2_clksel,
388 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
389 .clkdm = { .name = "dpll2_clkdm" },
390 .recalc = &omap2_clksel_recalc,
395 * Source clock for all interfaces and for some device fclks
396 * REVISIT: Also supports fast relock bypass - not included below
398 static struct dpll_data dpll3_dd = {
399 .mult_div1_reg = CM_CLKSEL1,
400 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
401 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
402 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
403 .control_reg = CM_CLKEN,
404 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
405 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
406 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
407 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
408 .autoidle_reg = CM_AUTOIDLE,
409 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
410 .idlest_reg = CM_IDLEST,
411 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
412 .bypass_clk = &sys_ck,
413 .max_multiplier = OMAP3_MAX_DPLL_MULT,
415 .max_divider = OMAP3_MAX_DPLL_DIV,
416 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
419 static struct clk dpll3_ck = {
423 .dpll_data = &dpll3_dd,
424 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
425 .round_rate = &omap2_dpll_round_rate,
426 .clkdm = { .name = "dpll3_clkdm" },
427 .recalc = &omap3_dpll_recalc,
430 static const struct clksel_rate div31_dpll3_rates[] = {
431 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
432 { .div = 2, .val = 2, .flags = RATE_IN_343X },
433 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
434 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
435 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
436 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
437 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
438 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
439 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
440 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
441 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
442 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
443 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
444 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
445 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
446 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
447 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
448 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
449 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
450 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
451 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
452 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
453 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
454 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
455 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
456 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
457 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
458 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
459 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
460 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
461 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
465 static const struct clksel div31_dpll3m2_clksel[] = {
466 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
470 /* DPLL3 output M2 - primary control point for CORE speed */
471 static struct clk dpll3_m2_ck = {
472 .name = "dpll3_m2_ck",
475 .init = &omap2_init_clksel_parent,
476 .clksel_reg = CM_CLKSEL1,
477 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
478 .clksel = div31_dpll3m2_clksel,
479 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
480 .clkdm = { .name = "dpll3_clkdm" },
481 .round_rate = &omap2_clksel_round_rate,
482 .set_rate = &omap3_core_dpll_m2_set_rate,
483 .recalc = &omap2_clksel_recalc,
486 static struct clk core_ck = {
488 .parent = &dpll3_m2_ck,
489 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
490 .clkdm = { .name = "cm_clkdm" },
491 .recalc = &followparent_recalc,
494 static struct clk dpll3_m2x2_ck = {
495 .name = "dpll3_m2x2_ck",
496 .parent = &dpll3_m2_ck,
497 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
498 .clkdm = { .name = "dpll3_clkdm" },
499 .recalc = &omap3_clkoutx2_recalc,
502 /* The PWRDN bit is apparently only available on 3430ES2 and above */
503 static const struct clksel div16_dpll3_clksel[] = {
504 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
508 /* This virtual clock is the source for dpll3_m3x2_ck */
509 static struct clk dpll3_m3_ck = {
510 .name = "dpll3_m3_ck",
512 .prcm_mod = OMAP3430_EMU_MOD,
513 .init = &omap2_init_clksel_parent,
514 .clksel_reg = CM_CLKSEL1,
515 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
516 .clksel = div16_dpll3_clksel,
517 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
518 .clkdm = { .name = "dpll3_clkdm" },
519 .recalc = &omap2_clksel_recalc,
522 /* The PWRDN bit is apparently only available on 3430ES2 and above */
523 static struct clk dpll3_m3x2_ck = {
524 .name = "dpll3_m3x2_ck",
525 .parent = &dpll3_m3_ck,
527 .enable_reg = CM_CLKEN,
528 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
529 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
530 .clkdm = { .name = "dpll3_clkdm" },
531 .recalc = &omap3_clkoutx2_recalc,
534 static struct clk emu_core_alwon_ck = {
535 .name = "emu_core_alwon_ck",
536 .parent = &dpll3_m3x2_ck,
537 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
538 .clkdm = { .name = "dpll3_clkdm" },
539 .recalc = &followparent_recalc,
543 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
545 static struct dpll_data dpll4_dd = {
546 .mult_div1_reg = CM_CLKSEL2,
547 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
548 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
549 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
550 .control_reg = CM_CLKEN,
551 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
552 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
553 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
554 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
555 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
556 .autoidle_reg = CM_AUTOIDLE,
557 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
558 .idlest_reg = CM_IDLEST,
559 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
560 .bypass_clk = &sys_ck,
561 .max_multiplier = OMAP3_MAX_DPLL_MULT,
563 .max_divider = OMAP3_MAX_DPLL_DIV,
564 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
567 static struct clk dpll4_ck = {
571 .dpll_data = &dpll4_dd,
572 .flags = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
573 .enable = &omap3_noncore_dpll_enable,
574 .disable = &omap3_noncore_dpll_disable,
575 .round_rate = &omap2_dpll_round_rate,
576 .set_rate = &omap3_noncore_dpll_set_rate,
577 .clkdm = { .name = "dpll4_clkdm" },
578 .recalc = &omap3_dpll_recalc,
581 static const struct clksel div16_dpll4_clksel[] = {
582 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
586 /* This virtual clock is the source for dpll4_m2x2_ck */
587 static struct clk dpll4_m2_ck = {
588 .name = "dpll4_m2_ck",
591 .init = &omap2_init_clksel_parent,
592 .clksel_reg = OMAP3430_CM_CLKSEL3,
593 .clksel_mask = OMAP3430_DIV_96M_MASK,
594 .clksel = div16_dpll4_clksel,
595 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
596 .clkdm = { .name = "dpll4_clkdm" },
597 .recalc = &omap2_clksel_recalc,
600 /* The PWRDN bit is apparently only available on 3430ES2 and above */
601 static struct clk dpll4_m2x2_ck = {
602 .name = "dpll4_m2x2_ck",
603 .parent = &dpll4_m2_ck,
605 .enable_reg = CM_CLKEN,
606 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
607 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
608 .clkdm = { .name = "dpll4_clkdm" },
609 .recalc = &omap3_clkoutx2_recalc,
613 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
614 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
615 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
618 static struct clk omap_96m_alwon_fck = {
619 .name = "omap_96m_alwon_fck",
620 .parent = &dpll4_m2x2_ck,
621 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
622 .clkdm = { .name = "prm_clkdm" },
623 .recalc = &followparent_recalc,
626 static struct clk cm_96m_fck = {
627 .name = "cm_96m_fck",
628 .parent = &omap_96m_alwon_fck,
629 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
630 .clkdm = { .name = "cm_clkdm" },
631 .recalc = &followparent_recalc,
634 static const struct clksel_rate omap_96m_dpll_rates[] = {
635 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
639 static const struct clksel_rate omap_96m_sys_rates[] = {
640 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
644 static const struct clksel omap_96m_fck_clksel[] = {
645 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
646 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
650 static struct clk omap_96m_fck = {
651 .name = "omap_96m_fck",
654 .init = &omap2_init_clksel_parent,
655 .clksel_reg = CM_CLKSEL1,
656 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
657 .clksel = omap_96m_fck_clksel,
658 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
659 .clkdm = { .name = "cm_clkdm" },
660 .recalc = &omap2_clksel_recalc,
663 /* This virtual clock is the source for dpll4_m3x2_ck */
664 static struct clk dpll4_m3_ck = {
665 .name = "dpll4_m3_ck",
667 .prcm_mod = OMAP3430_DSS_MOD,
668 .init = &omap2_init_clksel_parent,
669 .clksel_reg = CM_CLKSEL,
670 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
671 .clksel = div16_dpll4_clksel,
672 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
673 .clkdm = { .name = "dpll4_clkdm" },
674 .recalc = &omap2_clksel_recalc,
677 /* The PWRDN bit is apparently only available on 3430ES2 and above */
678 static struct clk dpll4_m3x2_ck = {
679 .name = "dpll4_m3x2_ck",
680 .parent = &dpll4_m3_ck,
682 .init = &omap2_init_clksel_parent,
683 .enable_reg = CM_CLKEN,
684 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
685 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
686 .clkdm = { .name = "dpll4_clkdm" },
687 .recalc = &omap3_clkoutx2_recalc,
690 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
691 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
695 static const struct clksel_rate omap_54m_alt_rates[] = {
696 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
700 static const struct clksel omap_54m_clksel[] = {
701 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
702 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
706 static struct clk omap_54m_fck = {
707 .name = "omap_54m_fck",
709 .init = &omap2_init_clksel_parent,
710 .clksel_reg = CM_CLKSEL1,
711 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
712 .clksel = omap_54m_clksel,
713 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
714 .clkdm = { .name = "cm_clkdm" },
715 .recalc = &omap2_clksel_recalc,
718 static const struct clksel_rate omap_48m_cm96m_rates[] = {
719 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
723 static const struct clksel_rate omap_48m_alt_rates[] = {
724 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
728 static const struct clksel omap_48m_clksel[] = {
729 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
730 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
734 static struct clk omap_48m_fck = {
735 .name = "omap_48m_fck",
737 .init = &omap2_init_clksel_parent,
738 .clksel_reg = CM_CLKSEL1,
739 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
740 .clksel = omap_48m_clksel,
741 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
742 .clkdm = { .name = "cm_clkdm" },
743 .recalc = &omap2_clksel_recalc,
746 static struct clk omap_12m_fck = {
747 .name = "omap_12m_fck",
748 .parent = &omap_48m_fck,
750 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
751 .clkdm = { .name = "cm_clkdm" },
752 .recalc = &omap2_fixed_divisor_recalc,
755 /* This virstual clock is the source for dpll4_m4x2_ck */
756 static struct clk dpll4_m4_ck = {
757 .name = "dpll4_m4_ck",
759 .prcm_mod = OMAP3430_DSS_MOD,
760 .init = &omap2_init_clksel_parent,
761 .clksel_reg = CM_CLKSEL,
762 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
763 .clksel = div16_dpll4_clksel,
764 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
765 .clkdm = { .name = "dpll4_clkdm" },
766 .recalc = &omap2_clksel_recalc,
767 .set_rate = &omap2_clksel_set_rate,
768 .round_rate = &omap2_clksel_round_rate,
771 /* The PWRDN bit is apparently only available on 3430ES2 and above */
772 static struct clk dpll4_m4x2_ck = {
773 .name = "dpll4_m4x2_ck",
774 .parent = &dpll4_m4_ck,
776 .enable_reg = CM_CLKEN,
777 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
778 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
779 .clkdm = { .name = "dpll4_clkdm" },
780 .recalc = &omap3_clkoutx2_recalc,
783 /* This virtual clock is the source for dpll4_m5x2_ck */
784 static struct clk dpll4_m5_ck = {
785 .name = "dpll4_m5_ck",
787 .prcm_mod = OMAP3430_CAM_MOD,
788 .init = &omap2_init_clksel_parent,
789 .clksel_reg = CM_CLKSEL,
790 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
791 .clksel = div16_dpll4_clksel,
792 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
793 .clkdm = { .name = "dpll4_clkdm" },
794 .recalc = &omap2_clksel_recalc,
797 /* The PWRDN bit is apparently only available on 3430ES2 and above */
798 static struct clk dpll4_m5x2_ck = {
799 .name = "dpll4_m5x2_ck",
800 .parent = &dpll4_m5_ck,
802 .enable_reg = CM_CLKEN,
803 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
804 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
805 .clkdm = { .name = "dpll4_clkdm" },
806 .recalc = &omap3_clkoutx2_recalc,
809 /* This virtual clock is the source for dpll4_m6x2_ck */
810 static struct clk dpll4_m6_ck = {
811 .name = "dpll4_m6_ck",
813 .prcm_mod = OMAP3430_EMU_MOD,
814 .init = &omap2_init_clksel_parent,
815 .clksel_reg = CM_CLKSEL1,
816 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
817 .clksel = div16_dpll4_clksel,
818 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
819 .clkdm = { .name = "dpll4_clkdm" },
820 .recalc = &omap2_clksel_recalc,
823 /* The PWRDN bit is apparently only available on 3430ES2 and above */
824 static struct clk dpll4_m6x2_ck = {
825 .name = "dpll4_m6x2_ck",
826 .parent = &dpll4_m6_ck,
828 .init = &omap2_init_clksel_parent,
829 .enable_reg = CM_CLKEN,
830 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
831 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
832 .clkdm = { .name = "dpll4_clkdm" },
833 .recalc = &omap3_clkoutx2_recalc,
836 static struct clk emu_per_alwon_ck = {
837 .name = "emu_per_alwon_ck",
838 .parent = &dpll4_m6x2_ck,
839 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
840 .clkdm = { .name = "dpll4_clkdm" },
841 .recalc = &followparent_recalc,
845 /* Supplies 120MHz clock, USIM source clock */
848 static struct dpll_data dpll5_dd = {
849 .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4,
850 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
851 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
852 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
853 .control_reg = OMAP3430ES2_CM_CLKEN2,
854 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
855 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
856 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
857 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
858 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
859 .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL,
860 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
861 .idlest_reg = CM_IDLEST2,
862 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
863 .bypass_clk = &sys_ck,
864 .max_multiplier = OMAP3_MAX_DPLL_MULT,
866 .max_divider = OMAP3_MAX_DPLL_DIV,
867 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
870 static struct clk dpll5_ck = {
874 .dpll_data = &dpll5_dd,
875 .flags = CLOCK_IN_OMAP3430ES2 | RECALC_ON_ENABLE,
876 .enable = &omap3_noncore_dpll_enable,
877 .disable = &omap3_noncore_dpll_disable,
878 .round_rate = &omap2_dpll_round_rate,
879 .set_rate = &omap3_noncore_dpll_set_rate,
880 .clkdm = { .name = "dpll5_clkdm" },
881 .recalc = &omap3_dpll_recalc,
884 static const struct clksel div16_dpll5_clksel[] = {
885 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
889 static struct clk dpll5_m2_ck = {
890 .name = "dpll5_m2_ck",
893 .init = &omap2_init_clksel_parent,
894 .clksel_reg = OMAP3430ES2_CM_CLKSEL5,
895 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
896 .clksel = div16_dpll5_clksel,
897 .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
898 .clkdm = { .name = "dpll5_clkdm" },
899 .recalc = &omap2_clksel_recalc,
902 /* CM EXTERNAL CLOCK OUTPUTS */
904 static const struct clksel_rate clkout2_src_core_rates[] = {
905 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
909 static const struct clksel_rate clkout2_src_sys_rates[] = {
910 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
914 static const struct clksel_rate clkout2_src_96m_rates[] = {
915 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
919 static const struct clksel_rate clkout2_src_54m_rates[] = {
920 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
924 static const struct clksel clkout2_src_clksel[] = {
925 { .parent = &core_ck, .rates = clkout2_src_core_rates },
926 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
927 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
928 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
932 static struct clk clkout2_src_ck = {
933 .name = "clkout2_src_ck",
934 .prcm_mod = OMAP3430_CCR_MOD,
935 .init = &omap2_init_clksel_parent,
936 .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
937 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
938 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
939 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
940 .clksel = clkout2_src_clksel,
941 .flags = CLOCK_IN_OMAP343X,
942 .clkdm = { .name = "cm_clkdm" },
943 .recalc = &omap2_clksel_recalc,
946 static const struct clksel_rate sys_clkout2_rates[] = {
947 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
948 { .div = 2, .val = 1, .flags = RATE_IN_343X },
949 { .div = 4, .val = 2, .flags = RATE_IN_343X },
950 { .div = 8, .val = 3, .flags = RATE_IN_343X },
951 { .div = 16, .val = 4, .flags = RATE_IN_343X },
955 static const struct clksel sys_clkout2_clksel[] = {
956 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
960 static struct clk sys_clkout2 = {
961 .name = "sys_clkout2",
962 .prcm_mod = OMAP3430_CCR_MOD,
963 .init = &omap2_init_clksel_parent,
964 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
965 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
966 .clksel = sys_clkout2_clksel,
967 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
968 .clkdm = { .name = "cm_clkdm" },
969 .recalc = &omap2_clksel_recalc,
972 /* CM OUTPUT CLOCKS */
974 static struct clk corex2_fck = {
975 .name = "corex2_fck",
976 .parent = &dpll3_m2x2_ck,
977 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
978 .clkdm = { .name = "cm_clkdm" },
979 .recalc = &followparent_recalc,
982 /* DPLL power domain clock controls */
984 static const struct clksel_rate div4_rates[] = {
985 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
986 { .div = 2, .val = 2, .flags = RATE_IN_343X },
987 { .div = 4, .val = 4, .flags = RATE_IN_343X },
991 static const struct clksel div4_core_clksel[] = {
992 { .parent = &core_ck, .rates = div4_rates },
996 static struct clk dpll1_fck = {
1000 .init = &omap2_init_clksel_parent,
1001 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1002 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1003 .clksel = div4_core_clksel,
1004 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1005 .clkdm = { .name = "cm_clkdm" },
1006 .recalc = &omap2_clksel_recalc,
1009 static struct clk mpu_ck = {
1011 .parent = &dpll1_x2m2_ck,
1012 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1013 .clkdm = { .name = "mpu_clkdm" },
1014 .recalc = &followparent_recalc,
1017 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1018 static const struct clksel_rate arm_fck_rates[] = {
1019 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1020 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1024 static const struct clksel arm_fck_clksel[] = {
1025 { .parent = &mpu_ck, .rates = arm_fck_rates },
1029 static struct clk arm_fck = {
1032 .prcm_mod = MPU_MOD,
1033 .init = &omap2_init_clksel_parent,
1034 .clksel_reg = OMAP3430_CM_IDLEST_PLL,
1035 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1036 .clksel = arm_fck_clksel,
1037 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1038 .clkdm = { .name = "mpu_clkdm" },
1039 .recalc = &omap2_clksel_recalc,
1042 /* XXX What about neon_clkdm ? */
1045 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1046 * although it is referenced - so this is a guess
1048 static struct clk emu_mpu_alwon_ck = {
1049 .name = "emu_mpu_alwon_ck",
1051 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1052 .clkdm = { .name = "mpu_clkdm" },
1053 .recalc = &followparent_recalc,
1056 static struct clk dpll2_fck = {
1057 .name = "dpll2_fck",
1059 .prcm_mod = OMAP3430_IVA2_MOD,
1060 .init = &omap2_init_clksel_parent,
1061 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1062 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1063 .clksel = div4_core_clksel,
1064 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1065 .clkdm = { .name = "cm_clkdm" },
1066 .recalc = &omap2_clksel_recalc,
1069 static struct clk iva2_ck = {
1071 .parent = &dpll2_m2_ck,
1072 .prcm_mod = OMAP3430_IVA2_MOD,
1073 .init = &omap2_init_clksel_parent,
1074 .enable_reg = CM_FCLKEN,
1075 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1076 .flags = CLOCK_IN_OMAP343X,
1077 .clkdm = { .name = "iva2_clkdm" },
1078 .recalc = &followparent_recalc,
1081 /* Common interface clocks */
1083 static const struct clksel div2_core_clksel[] = {
1084 { .parent = &core_ck, .rates = div2_rates },
1088 static struct clk l3_ick = {
1091 .prcm_mod = CORE_MOD,
1092 .init = &omap2_init_clksel_parent,
1093 .clksel_reg = CM_CLKSEL,
1094 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1095 .clksel = div2_core_clksel,
1096 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1097 .clkdm = { .name = "core_l3_clkdm" },
1098 .recalc = &omap2_clksel_recalc,
1101 static const struct clksel div2_l3_clksel[] = {
1102 { .parent = &l3_ick, .rates = div2_rates },
1106 static struct clk l4_ick = {
1109 .prcm_mod = CORE_MOD,
1110 .init = &omap2_init_clksel_parent,
1111 .clksel_reg = CM_CLKSEL,
1112 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1113 .clksel = div2_l3_clksel,
1114 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1115 .clkdm = { .name = "core_l4_clkdm" },
1116 .recalc = &omap2_clksel_recalc,
1120 static const struct clksel div2_l4_clksel[] = {
1121 { .parent = &l4_ick, .rates = div2_rates },
1125 static struct clk rm_ick = {
1128 .prcm_mod = WKUP_MOD,
1129 .init = &omap2_init_clksel_parent,
1130 .clksel_reg = CM_CLKSEL,
1131 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1132 .clksel = div2_l4_clksel,
1133 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1134 .clkdm = { .name = "cm_clkdm" },
1135 .recalc = &omap2_clksel_recalc,
1138 /* GFX power domain */
1140 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1142 static const struct clksel gfx_l3_clksel[] = {
1143 { .parent = &l3_ick, .rates = gfx_l3_rates },
1147 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1148 static struct clk gfx_l3_ck = {
1149 .name = "gfx_l3_ck",
1151 .prcm_mod = GFX_MOD,
1152 .init = &omap2_init_clksel_parent,
1153 .enable_reg = CM_ICLKEN,
1154 .enable_bit = OMAP_EN_GFX_SHIFT,
1155 .flags = CLOCK_IN_OMAP3430ES1,
1156 .clkdm = { .name = "gfx_3430es1_clkdm" },
1157 .recalc = &followparent_recalc,
1160 static struct clk gfx_l3_fck = {
1161 .name = "gfx_l3_fck",
1162 .parent = &gfx_l3_ck,
1163 .prcm_mod = GFX_MOD,
1164 .init = &omap2_init_clksel_parent,
1165 .clksel_reg = CM_CLKSEL,
1166 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1167 .clksel = gfx_l3_clksel,
1168 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1169 .clkdm = { .name = "gfx_3430es1_clkdm" },
1170 .recalc = &omap2_clksel_recalc,
1173 static struct clk gfx_l3_ick = {
1174 .name = "gfx_l3_ick",
1175 .parent = &gfx_l3_ck,
1176 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1177 .clkdm = { .name = "gfx_3430es1_clkdm" },
1178 .recalc = &followparent_recalc,
1181 static struct clk gfx_cg1_ck = {
1182 .name = "gfx_cg1_ck",
1183 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1184 .prcm_mod = GFX_MOD,
1185 .enable_reg = CM_FCLKEN,
1186 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1187 .flags = CLOCK_IN_OMAP3430ES1,
1188 .clkdm = { .name = "gfx_3430es1_clkdm" },
1189 .recalc = &followparent_recalc,
1192 static struct clk gfx_cg2_ck = {
1193 .name = "gfx_cg2_ck",
1194 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1195 .prcm_mod = GFX_MOD,
1196 .enable_reg = CM_FCLKEN,
1197 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1198 .flags = CLOCK_IN_OMAP3430ES1,
1199 .clkdm = { .name = "gfx_3430es1_clkdm" },
1200 .recalc = &followparent_recalc,
1203 /* SGX power domain - 3430ES2 only */
1205 static const struct clksel_rate sgx_core_rates[] = {
1206 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1207 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1208 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1212 static const struct clksel_rate sgx_96m_rates[] = {
1213 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1217 static const struct clksel sgx_clksel[] = {
1218 { .parent = &core_ck, .rates = sgx_core_rates },
1219 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1223 static struct clk sgx_fck = {
1225 .init = &omap2_init_clksel_parent,
1226 .prcm_mod = OMAP3430ES2_SGX_MOD,
1227 .enable_reg = CM_FCLKEN,
1228 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1229 .clksel_reg = CM_CLKSEL,
1230 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1231 .clksel = sgx_clksel,
1232 .flags = CLOCK_IN_OMAP3430ES2,
1233 .clkdm = { .name = "sgx_clkdm" },
1234 .recalc = &omap2_clksel_recalc,
1237 static struct clk sgx_ick = {
1240 .prcm_mod = OMAP3430ES2_SGX_MOD,
1241 .enable_reg = CM_ICLKEN,
1242 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1243 .flags = CLOCK_IN_OMAP3430ES2,
1244 .clkdm = { .name = "sgx_clkdm" },
1245 .recalc = &followparent_recalc,
1248 /* CORE power domain */
1250 static struct clk d2d_26m_fck = {
1251 .name = "d2d_26m_fck",
1253 .prcm_mod = CORE_MOD,
1254 .enable_reg = CM_FCLKEN1,
1255 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1256 .flags = CLOCK_IN_OMAP3430ES1,
1257 .clkdm = { .name = "d2d_clkdm" },
1258 .recalc = &followparent_recalc,
1261 static const struct clksel omap343x_gpt_clksel[] = {
1262 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1263 { .parent = &sys_ck, .rates = gpt_sys_rates },
1267 static struct clk gpt10_fck = {
1268 .name = "gpt10_fck",
1270 .prcm_mod = CORE_MOD,
1271 .init = &omap2_init_clksel_parent,
1272 .enable_reg = CM_FCLKEN1,
1273 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1274 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
1275 .clksel_reg = CM_CLKSEL,
1276 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1277 .clksel = omap343x_gpt_clksel,
1278 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1279 .clkdm = { .name = "core_l4_clkdm" },
1280 .recalc = &omap2_clksel_recalc,
1283 static struct clk gpt11_fck = {
1284 .name = "gpt11_fck",
1286 .prcm_mod = CORE_MOD,
1287 .init = &omap2_init_clksel_parent,
1288 .enable_reg = CM_FCLKEN1,
1289 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1290 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
1291 .clksel_reg = CM_CLKSEL,
1292 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1293 .clksel = omap343x_gpt_clksel,
1294 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1295 .clkdm = { .name = "core_l4_clkdm" },
1296 .recalc = &omap2_clksel_recalc,
1299 static struct clk cpefuse_fck = {
1300 .name = "cpefuse_fck",
1302 .prcm_mod = CORE_MOD,
1303 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1304 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1305 .idlest_bit = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1306 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1307 .clkdm = { .name = "cm_clkdm" },
1308 .recalc = &followparent_recalc,
1311 static struct clk ts_fck = {
1313 .parent = &omap_32k_fck,
1314 .prcm_mod = CORE_MOD,
1315 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1316 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1317 .flags = CLOCK_IN_OMAP3430ES2,
1318 .clkdm = { .name = "core_l4_clkdm" },
1319 .recalc = &followparent_recalc,
1322 static struct clk usbtll_fck = {
1323 .name = "usbtll_fck",
1324 .parent = &dpll5_m2_ck,
1325 .prcm_mod = CORE_MOD,
1326 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1327 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1328 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1329 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1330 .clkdm = { .name = "core_l4_clkdm" },
1331 .recalc = &followparent_recalc,
1334 /* CORE 96M FCLK-derived clocks */
1336 static struct clk core_96m_fck = {
1337 .name = "core_96m_fck",
1338 .parent = &omap_96m_fck,
1339 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1340 .clkdm = { .name = "core_l4_clkdm" },
1341 .recalc = &followparent_recalc,
1344 static struct clk mmchs3_fck = {
1345 .name = "mmchs_fck",
1347 .parent = &core_96m_fck,
1348 .prcm_mod = CORE_MOD,
1349 .enable_reg = CM_FCLKEN1,
1350 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1351 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1352 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1353 .clkdm = { .name = "core_l4_clkdm" },
1354 .recalc = &followparent_recalc,
1357 static struct clk mmchs2_fck = {
1358 .name = "mmchs_fck",
1360 .parent = &core_96m_fck,
1361 .prcm_mod = CORE_MOD,
1362 .enable_reg = CM_FCLKEN1,
1363 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1364 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1365 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1366 .clkdm = { .name = "core_l4_clkdm" },
1367 .recalc = &followparent_recalc,
1370 static struct clk mspro_fck = {
1371 .name = "mspro_fck",
1372 .parent = &core_96m_fck,
1373 .prcm_mod = CORE_MOD,
1374 .enable_reg = CM_FCLKEN1,
1375 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1376 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1377 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1378 .clkdm = { .name = "core_l4_clkdm" },
1379 .recalc = &followparent_recalc,
1382 static struct clk mmchs1_fck = {
1383 .name = "mmchs_fck",
1384 .parent = &core_96m_fck,
1385 .prcm_mod = CORE_MOD,
1386 .enable_reg = CM_FCLKEN1,
1387 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1388 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1389 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1390 .clkdm = { .name = "core_l4_clkdm" },
1391 .recalc = &followparent_recalc,
1394 static struct clk i2c3_fck = {
1397 .parent = &core_96m_fck,
1398 .prcm_mod = CORE_MOD,
1399 .enable_reg = CM_FCLKEN1,
1400 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1401 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
1402 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1403 .clkdm = { .name = "core_l4_clkdm" },
1404 .recalc = &followparent_recalc,
1407 static struct clk i2c2_fck = {
1410 .parent = &core_96m_fck,
1411 .prcm_mod = CORE_MOD,
1412 .enable_reg = CM_FCLKEN1,
1413 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1414 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
1415 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1416 .clkdm = { .name = "core_l4_clkdm" },
1417 .recalc = &followparent_recalc,
1420 static struct clk i2c1_fck = {
1423 .parent = &core_96m_fck,
1424 .prcm_mod = CORE_MOD,
1425 .enable_reg = CM_FCLKEN1,
1426 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1427 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
1428 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1429 .clkdm = { .name = "core_l4_clkdm" },
1430 .recalc = &followparent_recalc,
1434 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1435 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1437 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1438 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1442 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1443 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1447 static const struct clksel mcbsp_15_clksel[] = {
1448 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1449 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1453 static struct clk mcbsp5_src_fck = {
1454 .name = "mcbsp_src_fck",
1456 .prcm_mod = CLK_REG_IN_SCM,
1457 .init = &omap2_init_clksel_parent,
1458 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
1459 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1460 .clksel = mcbsp_15_clksel,
1461 .flags = CLOCK_IN_OMAP343X,
1462 .clkdm = { .name = "core_l4_clkdm" },
1463 .recalc = &omap2_clksel_recalc,
1466 static struct clk mcbsp5_fck = {
1467 .name = "mcbsp_fck",
1469 .parent = &mcbsp5_src_fck,
1470 .prcm_mod = CORE_MOD,
1471 .enable_reg = CM_FCLKEN1,
1472 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1473 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
1474 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1475 .clkdm = { .name = "core_l4_clkdm" },
1476 .recalc = &followparent_recalc,
1479 static struct clk mcbsp1_src_fck = {
1480 .name = "mcbsp_src_fck",
1482 .prcm_mod = CLK_REG_IN_SCM,
1483 .init = &omap2_init_clksel_parent,
1484 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
1485 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1486 .clksel = mcbsp_15_clksel,
1487 .flags = CLOCK_IN_OMAP343X,
1488 .clkdm = { .name = "core_l4_clkdm" },
1489 .recalc = &omap2_clksel_recalc,
1492 static struct clk mcbsp1_fck = {
1493 .name = "mcbsp_fck",
1495 .parent = &mcbsp1_src_fck,
1496 .prcm_mod = CORE_MOD,
1497 .enable_reg = CM_FCLKEN1,
1498 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1499 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
1500 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1501 .clkdm = { .name = "core_l4_clkdm" },
1502 .recalc = &followparent_recalc,
1505 /* CORE_48M_FCK-derived clocks */
1507 static struct clk core_48m_fck = {
1508 .name = "core_48m_fck",
1509 .parent = &omap_48m_fck,
1510 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1511 .clkdm = { .name = "core_l4_clkdm" },
1512 .recalc = &followparent_recalc,
1515 static struct clk mcspi4_fck = {
1516 .name = "mcspi_fck",
1518 .parent = &core_48m_fck,
1519 .prcm_mod = CORE_MOD,
1520 .enable_reg = CM_FCLKEN1,
1521 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1522 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1523 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1524 .clkdm = { .name = "core_l4_clkdm" },
1525 .recalc = &followparent_recalc,
1528 static struct clk mcspi3_fck = {
1529 .name = "mcspi_fck",
1531 .parent = &core_48m_fck,
1532 .prcm_mod = CORE_MOD,
1533 .enable_reg = CM_FCLKEN1,
1534 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1535 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
1536 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1537 .clkdm = { .name = "core_l4_clkdm" },
1538 .recalc = &followparent_recalc,
1541 static struct clk mcspi2_fck = {
1542 .name = "mcspi_fck",
1544 .parent = &core_48m_fck,
1545 .prcm_mod = CORE_MOD,
1546 .enable_reg = CM_FCLKEN1,
1547 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1548 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
1549 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1550 .clkdm = { .name = "core_l4_clkdm" },
1551 .recalc = &followparent_recalc,
1554 static struct clk mcspi1_fck = {
1555 .name = "mcspi_fck",
1557 .parent = &core_48m_fck,
1558 .prcm_mod = CORE_MOD,
1559 .enable_reg = CM_FCLKEN1,
1560 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1561 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
1562 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1563 .clkdm = { .name = "core_l4_clkdm" },
1564 .recalc = &followparent_recalc,
1567 static struct clk uart2_fck = {
1568 .name = "uart2_fck",
1569 .parent = &core_48m_fck,
1570 .prcm_mod = CORE_MOD,
1571 .enable_reg = CM_FCLKEN1,
1572 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1573 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
1574 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1575 .clkdm = { .name = "core_l4_clkdm" },
1576 .recalc = &followparent_recalc,
1579 static struct clk uart1_fck = {
1580 .name = "uart1_fck",
1581 .parent = &core_48m_fck,
1582 .prcm_mod = CORE_MOD,
1583 .enable_reg = CM_FCLKEN1,
1584 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1585 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
1586 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1587 .clkdm = { .name = "core_l4_clkdm" },
1588 .recalc = &followparent_recalc,
1591 /* XXX doublecheck: is this idle or standby? */
1592 static struct clk fshostusb_fck = {
1593 .name = "fshostusb_fck",
1594 .parent = &core_48m_fck,
1595 .prcm_mod = CORE_MOD,
1596 .enable_reg = CM_FCLKEN1,
1597 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1598 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1599 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1600 .clkdm = { .name = "core_l4_clkdm" },
1601 .recalc = &followparent_recalc,
1604 /* CORE_12M_FCK based clocks */
1606 static struct clk core_12m_fck = {
1607 .name = "core_12m_fck",
1608 .parent = &omap_12m_fck,
1609 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1610 .clkdm = { .name = "core_l4_clkdm" },
1611 .recalc = &followparent_recalc,
1614 static struct clk hdq_fck = {
1616 .parent = &core_12m_fck,
1617 .prcm_mod = CORE_MOD,
1618 .enable_reg = CM_FCLKEN1,
1619 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1620 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1621 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1622 .clkdm = { .name = "core_l4_clkdm" },
1623 .recalc = &followparent_recalc,
1626 /* DPLL3-derived clock */
1628 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1629 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1630 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1631 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1632 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1633 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1634 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1638 static const struct clksel ssi_ssr_clksel[] = {
1639 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1643 static struct clk ssi_ssr_fck_3430es1 = {
1644 .name = "ssi_ssr_fck",
1645 .init = &omap2_init_clksel_parent,
1646 .prcm_mod = CORE_MOD,
1647 .enable_reg = CM_FCLKEN1,
1648 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1649 .clksel_reg = CM_CLKSEL,
1650 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1651 .clksel = ssi_ssr_clksel,
1652 .flags = CLOCK_IN_OMAP3430ES1,
1653 .clkdm = { .name = "core_l4_clkdm" },
1654 .recalc = &omap2_clksel_recalc,
1657 static struct clk ssi_ssr_fck_3430es2 = {
1658 .name = "ssi_ssr_fck",
1659 .init = &omap2_init_clksel_parent,
1660 .prcm_mod = CORE_MOD,
1661 .enable_reg = CM_FCLKEN1,
1662 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1663 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1664 .clksel_reg = CM_CLKSEL,
1665 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1666 .clksel = ssi_ssr_clksel,
1667 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1668 .clkdm = { .name = "core_l4_clkdm" },
1669 .recalc = &omap2_clksel_recalc,
1672 /* It's unfortunate that we need to duplicate this clock. */
1673 static struct clk ssi_sst_fck_3430es1 = {
1674 .name = "ssi_sst_fck",
1675 .parent = &ssi_ssr_fck_3430es1,
1677 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1678 .clkdm = { .name = "core_l4_clkdm" },
1679 .recalc = &omap2_fixed_divisor_recalc,
1682 static struct clk ssi_sst_fck_3430es2 = {
1683 .name = "ssi_sst_fck",
1684 .parent = &ssi_ssr_fck_3430es2,
1686 .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1687 .clkdm = { .name = "core_l4_clkdm" },
1688 .recalc = &omap2_fixed_divisor_recalc,
1693 /* CORE_L3_ICK based clocks */
1696 * XXX must add clk_enable/clk_disable for these if standard code won't
1699 static struct clk core_l3_ick = {
1700 .name = "core_l3_ick",
1702 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1703 .clkdm = { .name = "core_l3_clkdm" },
1704 .recalc = &followparent_recalc,
1707 static struct clk hsotgusb_ick_3430es1 = {
1708 .name = "hsotgusb_ick",
1709 .parent = &core_l3_ick,
1710 .prcm_mod = CORE_MOD,
1711 .enable_reg = CM_ICLKEN1,
1712 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1713 .flags = CLOCK_IN_OMAP3430ES1,
1714 .clkdm = { .name = "core_l3_clkdm" },
1715 .recalc = &followparent_recalc,
1718 static struct clk hsotgusb_ick_3430es2 = {
1719 .name = "hsotgusb_ick",
1720 .parent = &core_l3_ick,
1721 .prcm_mod = CORE_MOD,
1722 .enable_reg = CM_ICLKEN1,
1723 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1724 .idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1725 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1726 .clkdm = { .name = "core_l3_clkdm" },
1727 .recalc = &followparent_recalc,
1730 static struct clk sdrc_ick = {
1732 .parent = &core_l3_ick,
1733 .prcm_mod = CORE_MOD,
1734 .enable_reg = CM_ICLKEN1,
1735 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1736 .idlest_bit = OMAP3430_ST_SDRC_SHIFT,
1737 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1738 .clkdm = { .name = "core_l3_clkdm" },
1739 .recalc = &followparent_recalc,
1742 static struct clk gpmc_fck = {
1744 .parent = &core_l3_ick,
1745 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1747 .clkdm = { .name = "core_l3_clkdm" },
1748 .recalc = &followparent_recalc,
1751 /* SECURITY_L3_ICK based clocks */
1753 static struct clk security_l3_ick = {
1754 .name = "security_l3_ick",
1756 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1757 .clkdm = { .name = "core_l3_clkdm" },
1758 .recalc = &followparent_recalc,
1761 static struct clk pka_ick = {
1763 .parent = &security_l3_ick,
1764 .prcm_mod = CORE_MOD,
1765 .enable_reg = CM_ICLKEN2,
1766 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1767 .idlest_bit = OMAP3430_ST_PKA_SHIFT,
1768 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1769 .clkdm = { .name = "core_l3_clkdm" },
1770 .recalc = &followparent_recalc,
1773 /* CORE_L4_ICK based clocks */
1775 static struct clk core_l4_ick = {
1776 .name = "core_l4_ick",
1778 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1779 .clkdm = { .name = "core_l4_clkdm" },
1780 .recalc = &followparent_recalc,
1783 static struct clk usbtll_ick = {
1784 .name = "usbtll_ick",
1785 .parent = &core_l4_ick,
1786 .prcm_mod = CORE_MOD,
1787 .enable_reg = CM_ICLKEN3,
1788 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1789 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1790 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1791 .clkdm = { .name = "core_l4_clkdm" },
1792 .recalc = &followparent_recalc,
1795 static struct clk mmchs3_ick = {
1796 .name = "mmchs_ick",
1798 .parent = &core_l4_ick,
1799 .prcm_mod = CORE_MOD,
1800 .enable_reg = CM_ICLKEN1,
1801 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1802 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1803 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1804 .clkdm = { .name = "core_l4_clkdm" },
1805 .recalc = &followparent_recalc,
1808 /* Intersystem Communication Registers - chassis mode only */
1809 static struct clk icr_ick = {
1811 .parent = &core_l4_ick,
1812 .prcm_mod = CORE_MOD,
1813 .enable_reg = CM_ICLKEN1,
1814 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1815 .idlest_bit = OMAP3430_ST_ICR_SHIFT,
1816 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1817 .clkdm = { .name = "core_l4_clkdm" },
1818 .recalc = &followparent_recalc,
1821 static struct clk aes2_ick = {
1823 .parent = &core_l4_ick,
1824 .prcm_mod = CORE_MOD,
1825 .enable_reg = CM_ICLKEN1,
1826 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1827 .idlest_bit = OMAP3430_ST_AES2_SHIFT,
1828 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1829 .clkdm = { .name = "core_l4_clkdm" },
1830 .recalc = &followparent_recalc,
1833 static struct clk sha12_ick = {
1834 .name = "sha12_ick",
1835 .parent = &core_l4_ick,
1836 .prcm_mod = CORE_MOD,
1837 .enable_reg = CM_ICLKEN1,
1838 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1839 .idlest_bit = OMAP3430_ST_SHA12_SHIFT,
1840 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1841 .clkdm = { .name = "core_l4_clkdm" },
1842 .recalc = &followparent_recalc,
1845 static struct clk des2_ick = {
1847 .parent = &core_l4_ick,
1848 .prcm_mod = CORE_MOD,
1849 .enable_reg = CM_ICLKEN1,
1850 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1851 .idlest_bit = OMAP3430_ST_DES2_SHIFT,
1852 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1853 .clkdm = { .name = "core_l4_clkdm" },
1854 .recalc = &followparent_recalc,
1857 static struct clk mmchs2_ick = {
1858 .name = "mmchs_ick",
1860 .parent = &core_l4_ick,
1861 .prcm_mod = CORE_MOD,
1862 .enable_reg = CM_ICLKEN1,
1863 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1864 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1865 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1866 .clkdm = { .name = "core_l4_clkdm" },
1867 .recalc = &followparent_recalc,
1870 static struct clk mmchs1_ick = {
1871 .name = "mmchs_ick",
1872 .parent = &core_l4_ick,
1873 .prcm_mod = CORE_MOD,
1874 .enable_reg = CM_ICLKEN1,
1875 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1876 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1877 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1878 .clkdm = { .name = "core_l4_clkdm" },
1879 .recalc = &followparent_recalc,
1882 static struct clk mspro_ick = {
1883 .name = "mspro_ick",
1884 .parent = &core_l4_ick,
1885 .prcm_mod = CORE_MOD,
1886 .enable_reg = CM_ICLKEN1,
1887 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1888 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1889 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1890 .clkdm = { .name = "core_l4_clkdm" },
1891 .recalc = &followparent_recalc,
1894 static struct clk hdq_ick = {
1896 .parent = &core_l4_ick,
1897 .prcm_mod = CORE_MOD,
1898 .enable_reg = CM_ICLKEN1,
1899 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1900 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1901 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1902 .clkdm = { .name = "core_l4_clkdm" },
1903 .recalc = &followparent_recalc,
1906 static struct clk mcspi4_ick = {
1907 .name = "mcspi_ick",
1909 .parent = &core_l4_ick,
1910 .prcm_mod = CORE_MOD,
1911 .enable_reg = CM_ICLKEN1,
1912 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1913 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1914 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1915 .clkdm = { .name = "core_l4_clkdm" },
1916 .recalc = &followparent_recalc,
1919 static struct clk mcspi3_ick = {
1920 .name = "mcspi_ick",
1922 .parent = &core_l4_ick,
1923 .prcm_mod = CORE_MOD,
1924 .enable_reg = CM_ICLKEN1,
1925 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1926 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
1927 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1928 .clkdm = { .name = "core_l4_clkdm" },
1929 .recalc = &followparent_recalc,
1932 static struct clk mcspi2_ick = {
1933 .name = "mcspi_ick",
1935 .parent = &core_l4_ick,
1936 .prcm_mod = CORE_MOD,
1937 .enable_reg = CM_ICLKEN1,
1938 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1939 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
1940 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1941 .clkdm = { .name = "core_l4_clkdm" },
1942 .recalc = &followparent_recalc,
1945 static struct clk mcspi1_ick = {
1946 .name = "mcspi_ick",
1948 .parent = &core_l4_ick,
1949 .prcm_mod = CORE_MOD,
1950 .enable_reg = CM_ICLKEN1,
1951 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1952 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
1953 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1954 .clkdm = { .name = "core_l4_clkdm" },
1955 .recalc = &followparent_recalc,
1958 static struct clk i2c3_ick = {
1961 .parent = &core_l4_ick,
1962 .prcm_mod = CORE_MOD,
1963 .enable_reg = CM_ICLKEN1,
1964 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1965 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
1966 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1967 .clkdm = { .name = "core_l4_clkdm" },
1968 .recalc = &followparent_recalc,
1971 static struct clk i2c2_ick = {
1974 .parent = &core_l4_ick,
1975 .prcm_mod = CORE_MOD,
1976 .enable_reg = CM_ICLKEN1,
1977 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1978 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
1979 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1980 .clkdm = { .name = "core_l4_clkdm" },
1981 .recalc = &followparent_recalc,
1984 static struct clk i2c1_ick = {
1987 .parent = &core_l4_ick,
1988 .prcm_mod = CORE_MOD,
1989 .enable_reg = CM_ICLKEN1,
1990 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1991 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
1992 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1993 .clkdm = { .name = "core_l4_clkdm" },
1994 .recalc = &followparent_recalc,
1997 static struct clk uart2_ick = {
1998 .name = "uart2_ick",
1999 .parent = &core_l4_ick,
2000 .prcm_mod = CORE_MOD,
2001 .enable_reg = CM_ICLKEN1,
2002 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2003 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
2004 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2005 .clkdm = { .name = "core_l4_clkdm" },
2006 .recalc = &followparent_recalc,
2009 static struct clk uart1_ick = {
2010 .name = "uart1_ick",
2011 .parent = &core_l4_ick,
2012 .prcm_mod = CORE_MOD,
2013 .enable_reg = CM_ICLKEN1,
2014 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2015 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
2016 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2017 .clkdm = { .name = "core_l4_clkdm" },
2018 .recalc = &followparent_recalc,
2021 static struct clk gpt11_ick = {
2022 .name = "gpt11_ick",
2023 .parent = &core_l4_ick,
2024 .prcm_mod = CORE_MOD,
2025 .enable_reg = CM_ICLKEN1,
2026 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2027 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
2028 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2029 .clkdm = { .name = "core_l4_clkdm" },
2030 .recalc = &followparent_recalc,
2033 static struct clk gpt10_ick = {
2034 .name = "gpt10_ick",
2035 .parent = &core_l4_ick,
2036 .prcm_mod = CORE_MOD,
2037 .enable_reg = CM_ICLKEN1,
2038 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2039 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
2040 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2041 .clkdm = { .name = "core_l4_clkdm" },
2042 .recalc = &followparent_recalc,
2045 static struct clk mcbsp5_ick = {
2046 .name = "mcbsp_ick",
2048 .parent = &core_l4_ick,
2049 .prcm_mod = CORE_MOD,
2050 .enable_reg = CM_ICLKEN1,
2051 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2052 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
2053 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2054 .clkdm = { .name = "core_l4_clkdm" },
2055 .recalc = &followparent_recalc,
2058 static struct clk mcbsp1_ick = {
2059 .name = "mcbsp_ick",
2061 .parent = &core_l4_ick,
2062 .prcm_mod = CORE_MOD,
2063 .enable_reg = CM_ICLKEN1,
2064 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2065 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
2066 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2067 .clkdm = { .name = "core_l4_clkdm" },
2068 .recalc = &followparent_recalc,
2071 static struct clk fac_ick = {
2073 .parent = &core_l4_ick,
2074 .prcm_mod = CORE_MOD,
2075 .enable_reg = CM_ICLKEN1,
2076 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2077 .idlest_bit = OMAP3430ES1_ST_FAC_SHIFT,
2078 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2079 .clkdm = { .name = "core_l4_clkdm" },
2080 .recalc = &followparent_recalc,
2083 static struct clk mailboxes_ick = {
2084 .name = "mailboxes_ick",
2085 .parent = &core_l4_ick,
2086 .prcm_mod = CORE_MOD,
2087 .enable_reg = CM_ICLKEN1,
2088 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2089 .idlest_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2090 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2091 .clkdm = { .name = "core_l4_clkdm" },
2092 .recalc = &followparent_recalc,
2095 static struct clk omapctrl_ick = {
2096 .name = "omapctrl_ick",
2097 .parent = &core_l4_ick,
2098 .prcm_mod = CORE_MOD,
2099 .enable_reg = CM_ICLKEN1,
2100 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2101 .idlest_bit = OMAP3430_ST_OMAPCTRL_SHIFT,
2102 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2103 .clkdm = { .name = "core_l4_clkdm" },
2104 .recalc = &followparent_recalc,
2107 /* SSI_L4_ICK based clocks */
2109 static struct clk ssi_l4_ick = {
2110 .name = "ssi_l4_ick",
2112 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2113 .clkdm = { .name = "core_l4_clkdm" },
2114 .recalc = &followparent_recalc,
2117 static struct clk ssi_ick_3430es1 = {
2119 .parent = &ssi_l4_ick,
2120 .prcm_mod = CORE_MOD,
2121 .enable_reg = CM_ICLKEN1,
2122 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2123 .flags = CLOCK_IN_OMAP3430ES1,
2124 .clkdm = { .name = "core_l4_clkdm" },
2125 .recalc = &followparent_recalc,
2128 static struct clk ssi_ick_3430es2 = {
2130 .parent = &ssi_l4_ick,
2131 .prcm_mod = CORE_MOD,
2132 .enable_reg = CM_ICLKEN1,
2133 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2134 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2135 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2136 .clkdm = { .name = "core_l4_clkdm" },
2137 .recalc = &followparent_recalc,
2141 * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2142 * but l4_ick makes more sense to me
2144 static const struct clksel usb_l4_clksel[] = {
2145 { .parent = &l4_ick, .rates = div2_rates },
2149 static struct clk usb_l4_ick = {
2150 .name = "usb_l4_ick",
2152 .prcm_mod = CORE_MOD,
2153 .init = &omap2_init_clksel_parent,
2154 .enable_reg = CM_ICLKEN1,
2155 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2156 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2157 .clksel_reg = CM_CLKSEL,
2158 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2159 .clksel = usb_l4_clksel,
2160 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2161 .clkdm = { .name = "core_l4_clkdm" },
2162 .recalc = &omap2_clksel_recalc,
2165 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2167 /* SECURITY_L4_ICK2 based clocks */
2169 static struct clk security_l4_ick2 = {
2170 .name = "security_l4_ick2",
2172 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2173 .clkdm = { .name = "core_l4_clkdm" },
2174 .recalc = &followparent_recalc,
2177 static struct clk aes1_ick = {
2179 .parent = &security_l4_ick2,
2180 .prcm_mod = CORE_MOD,
2181 .enable_reg = CM_ICLKEN2,
2182 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2183 .idlest_bit = OMAP3430_ST_AES1_SHIFT,
2184 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2185 .clkdm = { .name = "core_l4_clkdm" },
2186 .recalc = &followparent_recalc,
2189 static struct clk rng_ick = {
2191 .parent = &security_l4_ick2,
2192 .prcm_mod = CORE_MOD,
2193 .enable_reg = CM_ICLKEN2,
2194 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2195 .idlest_bit = OMAP3430_ST_RNG_SHIFT,
2196 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2197 .clkdm = { .name = "core_l4_clkdm" },
2198 .recalc = &followparent_recalc,
2201 static struct clk sha11_ick = {
2202 .name = "sha11_ick",
2203 .parent = &security_l4_ick2,
2204 .prcm_mod = CORE_MOD,
2205 .enable_reg = CM_ICLKEN2,
2206 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2207 .idlest_bit = OMAP3430_ST_SHA11_SHIFT,
2208 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2209 .clkdm = { .name = "core_l4_clkdm" },
2210 .recalc = &followparent_recalc,
2213 static struct clk des1_ick = {
2215 .parent = &security_l4_ick2,
2216 .prcm_mod = CORE_MOD,
2217 .enable_reg = CM_ICLKEN2,
2218 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2219 .idlest_bit = OMAP3430_ST_DES1_SHIFT,
2220 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2221 .clkdm = { .name = "core_l4_clkdm" },
2222 .recalc = &followparent_recalc,
2226 static struct clk dss1_alwon_fck_3430es1 = {
2227 .name = "dss1_alwon_fck",
2228 .parent = &dpll4_m4x2_ck,
2229 .prcm_mod = OMAP3430_DSS_MOD,
2230 .enable_reg = CM_FCLKEN,
2231 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2232 .flags = CLOCK_IN_OMAP3430ES1,
2233 .clkdm = { .name = "dss_clkdm" },
2234 .recalc = &followparent_recalc,
2237 static struct clk dss1_alwon_fck_3430es2 = {
2238 .name = "dss1_alwon_fck",
2239 .parent = &dpll4_m4x2_ck,
2240 .init = &omap2_init_clksel_parent,
2241 .prcm_mod = OMAP3430_DSS_MOD,
2242 .enable_reg = CM_FCLKEN,
2243 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2244 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2245 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2246 .clkdm = { .name = "dss_clkdm" },
2247 .recalc = &followparent_recalc,
2250 static struct clk dss_tv_fck = {
2251 .name = "dss_tv_fck",
2252 .parent = &omap_54m_fck,
2253 .prcm_mod = OMAP3430_DSS_MOD,
2254 .enable_reg = CM_FCLKEN,
2255 .enable_bit = OMAP3430_EN_TV_SHIFT,
2256 .flags = CLOCK_IN_OMAP343X,
2257 .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2258 .recalc = &followparent_recalc,
2261 static struct clk dss_96m_fck = {
2262 .name = "dss_96m_fck",
2263 .parent = &omap_96m_fck,
2264 .prcm_mod = OMAP3430_DSS_MOD,
2265 .enable_reg = CM_FCLKEN,
2266 .enable_bit = OMAP3430_EN_TV_SHIFT,
2267 .flags = CLOCK_IN_OMAP343X,
2268 .clkdm = { .name = "dss_clkdm" },
2269 .recalc = &followparent_recalc,
2272 static struct clk dss2_alwon_fck = {
2273 .name = "dss2_alwon_fck",
2275 .prcm_mod = OMAP3430_DSS_MOD,
2276 .enable_reg = CM_FCLKEN,
2277 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2278 .flags = CLOCK_IN_OMAP343X,
2279 .clkdm = { .name = "dss_clkdm" },
2280 .recalc = &followparent_recalc,
2283 static struct clk dss_ick_3430es1 = {
2284 /* Handles both L3 and L4 clocks */
2287 .prcm_mod = OMAP3430_DSS_MOD,
2288 .enable_reg = CM_ICLKEN,
2289 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2290 .flags = CLOCK_IN_OMAP3430ES1,
2291 .clkdm = { .name = "dss_clkdm" },
2292 .recalc = &followparent_recalc,
2295 static struct clk dss_ick_3430es2 = {
2296 /* Handles both L3 and L4 clocks */
2299 .prcm_mod = OMAP3430_DSS_MOD,
2300 .enable_reg = CM_ICLKEN,
2301 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2302 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2303 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2304 .clkdm = { .name = "dss_clkdm" },
2305 .recalc = &followparent_recalc,
2310 static struct clk cam_mclk = {
2312 .parent = &dpll4_m5x2_ck,
2313 .prcm_mod = OMAP3430_CAM_MOD,
2314 .enable_reg = CM_FCLKEN,
2315 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2316 .flags = CLOCK_IN_OMAP343X,
2317 .clkdm = { .name = "cam_clkdm" },
2318 .recalc = &followparent_recalc,
2321 static struct clk cam_ick = {
2322 /* Handles both L3 and L4 clocks */
2325 .prcm_mod = OMAP3430_CAM_MOD,
2326 .enable_reg = CM_ICLKEN,
2327 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2328 .flags = CLOCK_IN_OMAP343X,
2329 .clkdm = { .name = "cam_clkdm" },
2330 .recalc = &followparent_recalc,
2333 static struct clk csi2_96m_fck = {
2334 .name = "csi2_96m_fck",
2335 .parent = &core_96m_fck,
2336 .prcm_mod = OMAP3430_CAM_MOD,
2337 .enable_reg = CM_FCLKEN,
2338 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2339 .flags = CLOCK_IN_OMAP343X,
2340 .clkdm = { .name = "cam_clkdm" },
2341 .recalc = &followparent_recalc,
2344 /* USBHOST - 3430ES2 only */
2346 static struct clk usbhost_120m_fck = {
2347 .name = "usbhost_120m_fck",
2348 .parent = &dpll5_m2_ck,
2349 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2350 .enable_reg = CM_FCLKEN,
2351 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2352 .flags = CLOCK_IN_OMAP3430ES2,
2353 .clkdm = { .name = "usbhost_clkdm" },
2354 .recalc = &followparent_recalc,
2357 static struct clk usbhost_48m_fck = {
2358 .name = "usbhost_48m_fck",
2359 .parent = &omap_48m_fck,
2360 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2361 .enable_reg = CM_FCLKEN,
2362 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2363 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2364 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2365 .clkdm = { .name = "usbhost_clkdm" },
2366 .recalc = &followparent_recalc,
2369 static struct clk usbhost_ick = {
2370 /* Handles both L3 and L4 clocks */
2371 .name = "usbhost_ick",
2373 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2374 .enable_reg = CM_ICLKEN,
2375 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2376 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2377 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2378 .clkdm = { .name = "usbhost_clkdm" },
2379 .recalc = &followparent_recalc,
2384 static const struct clksel_rate usim_96m_rates[] = {
2385 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2386 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2387 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2388 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2392 static const struct clksel_rate usim_120m_rates[] = {
2393 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2394 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2395 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2396 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2400 static const struct clksel usim_clksel[] = {
2401 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2402 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2403 { .parent = &sys_ck, .rates = div2_rates },
2408 static struct clk usim_fck = {
2410 .prcm_mod = WKUP_MOD,
2411 .init = &omap2_init_clksel_parent,
2412 .enable_reg = CM_FCLKEN,
2413 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2414 .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
2415 .clksel_reg = CM_CLKSEL,
2416 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2417 .clksel = usim_clksel,
2418 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2419 .clkdm = { .name = "prm_clkdm" },
2420 .recalc = &omap2_clksel_recalc,
2423 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2424 static struct clk gpt1_fck = {
2426 .prcm_mod = WKUP_MOD,
2427 .init = &omap2_init_clksel_parent,
2428 .enable_reg = CM_FCLKEN,
2429 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2430 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2431 .clksel_reg = CM_CLKSEL,
2432 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2433 .clksel = omap343x_gpt_clksel,
2434 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2435 .clkdm = { .name = "prm_clkdm" },
2436 .recalc = &omap2_clksel_recalc,
2439 static struct clk wkup_32k_fck = {
2440 .name = "wkup_32k_fck",
2441 .parent = &omap_32k_fck,
2442 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2443 .clkdm = { .name = "prm_clkdm" },
2444 .recalc = &followparent_recalc,
2447 static struct clk gpio1_dbck = {
2448 .name = "gpio1_dbck",
2449 .parent = &wkup_32k_fck,
2450 .prcm_mod = WKUP_MOD,
2451 .enable_reg = CM_FCLKEN,
2452 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2453 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2454 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2455 .clkdm = { .name = "prm_clkdm" },
2456 .recalc = &followparent_recalc,
2459 static struct clk wdt2_fck = {
2461 .parent = &wkup_32k_fck,
2462 .prcm_mod = WKUP_MOD,
2463 .enable_reg = CM_FCLKEN,
2464 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2465 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2466 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2467 .clkdm = { .name = "prm_clkdm" },
2468 .recalc = &followparent_recalc,
2471 static struct clk wkup_l4_ick = {
2472 .name = "wkup_l4_ick",
2474 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2475 .clkdm = { .name = "prm_clkdm" },
2476 .recalc = &followparent_recalc,
2479 static struct clk usim_ick = {
2481 .parent = &wkup_l4_ick,
2482 .prcm_mod = WKUP_MOD,
2483 .enable_reg = CM_ICLKEN,
2484 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2485 .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
2486 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2487 .clkdm = { .name = "prm_clkdm" },
2488 .recalc = &followparent_recalc,
2491 static struct clk wdt2_ick = {
2493 .parent = &wkup_l4_ick,
2494 .prcm_mod = WKUP_MOD,
2495 .enable_reg = CM_ICLKEN,
2496 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2497 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2498 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2499 .clkdm = { .name = "prm_clkdm" },
2500 .recalc = &followparent_recalc,
2503 static struct clk wdt1_ick = {
2505 .parent = &wkup_l4_ick,
2506 .prcm_mod = WKUP_MOD,
2507 .enable_reg = CM_ICLKEN,
2508 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2509 .idlest_bit = OMAP3430_ST_WDT1_SHIFT,
2510 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2511 .clkdm = { .name = "prm_clkdm" },
2512 .recalc = &followparent_recalc,
2515 static struct clk gpio1_ick = {
2516 .name = "gpio1_ick",
2517 .parent = &wkup_l4_ick,
2518 .prcm_mod = WKUP_MOD,
2519 .enable_reg = CM_ICLKEN,
2520 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2521 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2522 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2523 .clkdm = { .name = "prm_clkdm" },
2524 .recalc = &followparent_recalc,
2527 static struct clk omap_32ksync_ick = {
2528 .name = "omap_32ksync_ick",
2529 .parent = &wkup_l4_ick,
2530 .prcm_mod = WKUP_MOD,
2531 .enable_reg = CM_ICLKEN,
2532 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2533 .idlest_bit = OMAP3430_ST_32KSYNC_SHIFT,
2534 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2535 .clkdm = { .name = "prm_clkdm" },
2536 .recalc = &followparent_recalc,
2539 static struct clk gpt12_ick = {
2540 .name = "gpt12_ick",
2541 .parent = &wkup_l4_ick,
2542 .prcm_mod = WKUP_MOD,
2543 .enable_reg = CM_ICLKEN,
2544 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2545 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
2546 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2547 .clkdm = { .name = "prm_clkdm" },
2548 .recalc = &followparent_recalc,
2551 static struct clk gpt1_ick = {
2553 .parent = &wkup_l4_ick,
2554 .prcm_mod = WKUP_MOD,
2555 .enable_reg = CM_ICLKEN,
2556 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2557 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2558 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2559 .clkdm = { .name = "prm_clkdm" },
2560 .recalc = &followparent_recalc,
2565 /* PER clock domain */
2567 static struct clk per_96m_fck = {
2568 .name = "per_96m_fck",
2569 .parent = &omap_96m_alwon_fck,
2570 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2571 .clkdm = { .name = "per_clkdm" },
2572 .recalc = &followparent_recalc,
2575 static struct clk per_48m_fck = {
2576 .name = "per_48m_fck",
2577 .parent = &omap_48m_fck,
2578 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2579 .clkdm = { .name = "per_clkdm" },
2580 .recalc = &followparent_recalc,
2583 static struct clk uart3_fck = {
2584 .name = "uart3_fck",
2585 .parent = &per_48m_fck,
2586 .prcm_mod = OMAP3430_PER_MOD,
2587 .enable_reg = CM_FCLKEN,
2588 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2589 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2590 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2591 .clkdm = { .name = "per_clkdm" },
2592 .recalc = &followparent_recalc,
2595 static struct clk gpt2_fck = {
2597 .prcm_mod = OMAP3430_PER_MOD,
2598 .init = &omap2_init_clksel_parent,
2599 .enable_reg = CM_FCLKEN,
2600 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2601 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
2602 .clksel_reg = CM_CLKSEL,
2603 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2604 .clksel = omap343x_gpt_clksel,
2605 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2606 .clkdm = { .name = "per_clkdm" },
2607 .recalc = &omap2_clksel_recalc,
2610 static struct clk gpt3_fck = {
2612 .prcm_mod = OMAP3430_PER_MOD,
2613 .init = &omap2_init_clksel_parent,
2614 .enable_reg = CM_FCLKEN,
2615 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2616 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
2617 .clksel_reg = CM_CLKSEL,
2618 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2619 .clksel = omap343x_gpt_clksel,
2620 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2621 .clkdm = { .name = "per_clkdm" },
2622 .recalc = &omap2_clksel_recalc,
2625 static struct clk gpt4_fck = {
2627 .prcm_mod = OMAP3430_PER_MOD,
2628 .init = &omap2_init_clksel_parent,
2629 .enable_reg = CM_FCLKEN,
2630 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2631 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
2632 .clksel_reg = CM_CLKSEL,
2633 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2634 .clksel = omap343x_gpt_clksel,
2635 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2636 .clkdm = { .name = "per_clkdm" },
2637 .recalc = &omap2_clksel_recalc,
2640 static struct clk gpt5_fck = {
2642 .prcm_mod = OMAP3430_PER_MOD,
2643 .init = &omap2_init_clksel_parent,
2644 .enable_reg = CM_FCLKEN,
2645 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2646 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
2647 .clksel_reg = CM_CLKSEL,
2648 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2649 .clksel = omap343x_gpt_clksel,
2650 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2651 .clkdm = { .name = "per_clkdm" },
2652 .recalc = &omap2_clksel_recalc,
2655 static struct clk gpt6_fck = {
2657 .prcm_mod = OMAP3430_PER_MOD,
2658 .init = &omap2_init_clksel_parent,
2659 .enable_reg = CM_FCLKEN,
2660 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2661 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
2662 .clksel_reg = CM_CLKSEL,
2663 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2664 .clksel = omap343x_gpt_clksel,
2665 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2666 .clkdm = { .name = "per_clkdm" },
2667 .recalc = &omap2_clksel_recalc,
2670 static struct clk gpt7_fck = {
2672 .prcm_mod = OMAP3430_PER_MOD,
2673 .init = &omap2_init_clksel_parent,
2674 .enable_reg = CM_FCLKEN,
2675 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2676 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2677 .clksel_reg = CM_CLKSEL,
2678 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2679 .clksel = omap343x_gpt_clksel,
2680 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2681 .clkdm = { .name = "per_clkdm" },
2682 .recalc = &omap2_clksel_recalc,
2685 static struct clk gpt8_fck = {
2687 .prcm_mod = OMAP3430_PER_MOD,
2688 .init = &omap2_init_clksel_parent,
2689 .enable_reg = CM_FCLKEN,
2690 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2691 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2692 .clksel_reg = CM_CLKSEL,
2693 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2694 .clksel = omap343x_gpt_clksel,
2695 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2696 .clkdm = { .name = "per_clkdm" },
2697 .recalc = &omap2_clksel_recalc,
2700 static struct clk gpt9_fck = {
2702 .prcm_mod = OMAP3430_PER_MOD,
2703 .init = &omap2_init_clksel_parent,
2704 .enable_reg = CM_FCLKEN,
2705 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2706 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2707 .clksel_reg = CM_CLKSEL,
2708 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2709 .clksel = omap343x_gpt_clksel,
2710 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2711 .clkdm = { .name = "per_clkdm" },
2712 .recalc = &omap2_clksel_recalc,
2715 static struct clk per_32k_alwon_fck = {
2716 .name = "per_32k_alwon_fck",
2717 .parent = &omap_32k_fck,
2718 .clkdm = { .name = "per_clkdm" },
2719 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2720 .recalc = &followparent_recalc,
2723 static struct clk gpio6_dbck = {
2724 .name = "gpio6_dbck",
2725 .parent = &per_32k_alwon_fck,
2726 .prcm_mod = OMAP3430_PER_MOD,
2727 .enable_reg = CM_FCLKEN,
2728 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2729 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2730 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2731 .clkdm = { .name = "per_clkdm" },
2732 .recalc = &followparent_recalc,
2735 static struct clk gpio5_dbck = {
2736 .name = "gpio5_dbck",
2737 .parent = &per_32k_alwon_fck,
2738 .prcm_mod = OMAP3430_PER_MOD,
2739 .enable_reg = CM_FCLKEN,
2740 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2741 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2742 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2743 .clkdm = { .name = "per_clkdm" },
2744 .recalc = &followparent_recalc,
2747 static struct clk gpio4_dbck = {
2748 .name = "gpio4_dbck",
2749 .parent = &per_32k_alwon_fck,
2750 .prcm_mod = OMAP3430_PER_MOD,
2751 .enable_reg = CM_FCLKEN,
2752 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2753 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2754 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2755 .clkdm = { .name = "per_clkdm" },
2756 .recalc = &followparent_recalc,
2759 static struct clk gpio3_dbck = {
2760 .name = "gpio3_dbck",
2761 .parent = &per_32k_alwon_fck,
2762 .prcm_mod = OMAP3430_PER_MOD,
2763 .enable_reg = CM_FCLKEN,
2764 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2765 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2766 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2767 .clkdm = { .name = "per_clkdm" },
2768 .recalc = &followparent_recalc,
2771 static struct clk gpio2_dbck = {
2772 .name = "gpio2_dbck",
2773 .parent = &per_32k_alwon_fck,
2774 .prcm_mod = OMAP3430_PER_MOD,
2775 .enable_reg = CM_FCLKEN,
2776 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2777 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2778 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2779 .clkdm = { .name = "per_clkdm" },
2780 .recalc = &followparent_recalc,
2783 static struct clk wdt3_fck = {
2785 .parent = &per_32k_alwon_fck,
2786 .prcm_mod = OMAP3430_PER_MOD,
2787 .enable_reg = CM_FCLKEN,
2788 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2789 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2790 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2791 .clkdm = { .name = "per_clkdm" },
2792 .recalc = &followparent_recalc,
2795 static struct clk per_l4_ick = {
2796 .name = "per_l4_ick",
2798 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2799 .clkdm = { .name = "per_clkdm" },
2800 .recalc = &followparent_recalc,
2803 static struct clk gpio6_ick = {
2804 .name = "gpio6_ick",
2805 .parent = &per_l4_ick,
2806 .prcm_mod = OMAP3430_PER_MOD,
2807 .enable_reg = CM_ICLKEN,
2808 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2809 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2810 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2811 .clkdm = { .name = "per_clkdm" },
2812 .recalc = &followparent_recalc,
2815 static struct clk gpio5_ick = {
2816 .name = "gpio5_ick",
2817 .parent = &per_l4_ick,
2818 .prcm_mod = OMAP3430_PER_MOD,
2819 .enable_reg = CM_ICLKEN,
2820 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2821 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2822 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2823 .clkdm = { .name = "per_clkdm" },
2824 .recalc = &followparent_recalc,
2827 static struct clk gpio4_ick = {
2828 .name = "gpio4_ick",
2829 .parent = &per_l4_ick,
2830 .prcm_mod = OMAP3430_PER_MOD,
2831 .enable_reg = CM_ICLKEN,
2832 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2833 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2834 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2835 .clkdm = { .name = "per_clkdm" },
2836 .recalc = &followparent_recalc,
2839 static struct clk gpio3_ick = {
2840 .name = "gpio3_ick",
2841 .parent = &per_l4_ick,
2842 .prcm_mod = OMAP3430_PER_MOD,
2843 .enable_reg = CM_ICLKEN,
2844 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2845 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2846 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2847 .clkdm = { .name = "per_clkdm" },
2848 .recalc = &followparent_recalc,
2851 static struct clk gpio2_ick = {
2852 .name = "gpio2_ick",
2853 .parent = &per_l4_ick,
2854 .prcm_mod = OMAP3430_PER_MOD,
2855 .enable_reg = CM_ICLKEN,
2856 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2857 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2858 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2859 .clkdm = { .name = "per_clkdm" },
2860 .recalc = &followparent_recalc,
2863 static struct clk wdt3_ick = {
2865 .parent = &per_l4_ick,
2866 .prcm_mod = OMAP3430_PER_MOD,
2867 .enable_reg = CM_ICLKEN,
2868 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2869 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2870 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2871 .clkdm = { .name = "per_clkdm" },
2872 .recalc = &followparent_recalc,
2875 static struct clk uart3_ick = {
2876 .name = "uart3_ick",
2877 .parent = &per_l4_ick,
2878 .prcm_mod = OMAP3430_PER_MOD,
2879 .enable_reg = CM_ICLKEN,
2880 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2881 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2882 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2883 .clkdm = { .name = "per_clkdm" },
2884 .recalc = &followparent_recalc,
2887 static struct clk gpt9_ick = {
2889 .parent = &per_l4_ick,
2890 .prcm_mod = OMAP3430_PER_MOD,
2891 .enable_reg = CM_ICLKEN,
2892 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2893 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2894 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2895 .clkdm = { .name = "per_clkdm" },
2896 .recalc = &followparent_recalc,
2899 static struct clk gpt8_ick = {
2901 .parent = &per_l4_ick,
2902 .prcm_mod = OMAP3430_PER_MOD,
2903 .enable_reg = CM_ICLKEN,
2904 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2905 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2906 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2907 .clkdm = { .name = "per_clkdm" },
2908 .recalc = &followparent_recalc,
2911 static struct clk gpt7_ick = {
2913 .parent = &per_l4_ick,
2914 .prcm_mod = OMAP3430_PER_MOD,
2915 .enable_reg = CM_ICLKEN,
2916 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2917 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2918 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2919 .clkdm = { .name = "per_clkdm" },
2920 .recalc = &followparent_recalc,
2923 static struct clk gpt6_ick = {
2925 .parent = &per_l4_ick,
2926 .prcm_mod = OMAP3430_PER_MOD,
2927 .enable_reg = CM_ICLKEN,
2928 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2929 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
2930 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2931 .clkdm = { .name = "per_clkdm" },
2932 .recalc = &followparent_recalc,
2935 static struct clk gpt5_ick = {
2937 .parent = &per_l4_ick,
2938 .prcm_mod = OMAP3430_PER_MOD,
2939 .enable_reg = CM_ICLKEN,
2940 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2941 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
2942 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2943 .clkdm = { .name = "per_clkdm" },
2944 .recalc = &followparent_recalc,
2947 static struct clk gpt4_ick = {
2949 .parent = &per_l4_ick,
2950 .prcm_mod = OMAP3430_PER_MOD,
2951 .enable_reg = CM_ICLKEN,
2952 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2953 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
2954 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2955 .clkdm = { .name = "per_clkdm" },
2956 .recalc = &followparent_recalc,
2959 static struct clk gpt3_ick = {
2961 .parent = &per_l4_ick,
2962 .prcm_mod = OMAP3430_PER_MOD,
2963 .enable_reg = CM_ICLKEN,
2964 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2965 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
2966 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2967 .clkdm = { .name = "per_clkdm" },
2968 .recalc = &followparent_recalc,
2971 static struct clk gpt2_ick = {
2973 .parent = &per_l4_ick,
2974 .prcm_mod = OMAP3430_PER_MOD,
2975 .enable_reg = CM_ICLKEN,
2976 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2977 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
2978 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2979 .clkdm = { .name = "per_clkdm" },
2980 .recalc = &followparent_recalc,
2983 static struct clk mcbsp2_ick = {
2984 .name = "mcbsp_ick",
2986 .parent = &per_l4_ick,
2987 .prcm_mod = OMAP3430_PER_MOD,
2988 .enable_reg = CM_ICLKEN,
2989 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2990 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
2991 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2992 .clkdm = { .name = "per_clkdm" },
2993 .recalc = &followparent_recalc,
2996 static struct clk mcbsp3_ick = {
2997 .name = "mcbsp_ick",
2999 .parent = &per_l4_ick,
3000 .prcm_mod = OMAP3430_PER_MOD,
3001 .enable_reg = CM_ICLKEN,
3002 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3003 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3004 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3005 .clkdm = { .name = "per_clkdm" },
3006 .recalc = &followparent_recalc,
3009 static struct clk mcbsp4_ick = {
3010 .name = "mcbsp_ick",
3012 .parent = &per_l4_ick,
3013 .prcm_mod = OMAP3430_PER_MOD,
3014 .enable_reg = CM_ICLKEN,
3015 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3016 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3017 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3018 .clkdm = { .name = "per_clkdm" },
3019 .recalc = &followparent_recalc,
3022 static const struct clksel mcbsp_234_clksel[] = {
3023 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3024 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
3028 static struct clk mcbsp2_src_fck = {
3029 .name = "mcbsp_src_fck",
3031 .prcm_mod = CLK_REG_IN_SCM,
3032 .init = &omap2_init_clksel_parent,
3033 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
3034 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
3035 .clksel = mcbsp_234_clksel,
3036 .flags = CLOCK_IN_OMAP343X,
3037 .clkdm = { .name = "per_clkdm" },
3038 .recalc = &omap2_clksel_recalc,
3041 static struct clk mcbsp2_fck = {
3042 .name = "mcbsp_fck",
3044 .parent = &mcbsp2_src_fck,
3045 .prcm_mod = OMAP3430_PER_MOD,
3046 .enable_reg = CM_FCLKEN,
3047 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3048 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3049 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3050 .clkdm = { .name = "per_clkdm" },
3051 .recalc = &omap2_clksel_recalc,
3054 static struct clk mcbsp3_src_fck = {
3055 .name = "mcbsp_src_fck",
3057 .prcm_mod = CLK_REG_IN_SCM,
3058 .init = &omap2_init_clksel_parent,
3059 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3060 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
3061 .clksel = mcbsp_234_clksel,
3062 .flags = CLOCK_IN_OMAP343X,
3063 .clkdm = { .name = "per_clkdm" },
3064 .recalc = &omap2_clksel_recalc,
3067 static struct clk mcbsp3_fck = {
3068 .name = "mcbsp_fck",
3070 .parent = &mcbsp3_src_fck,
3071 .prcm_mod = OMAP3430_PER_MOD,
3072 .enable_reg = CM_FCLKEN,
3073 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3074 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3075 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3076 .clkdm = { .name = "per_clkdm" },
3077 .recalc = &omap2_clksel_recalc,
3080 static struct clk mcbsp4_src_fck = {
3081 .name = "mcbsp_src_fck",
3083 .prcm_mod = CLK_REG_IN_SCM,
3084 .init = &omap2_init_clksel_parent,
3085 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3086 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
3087 .clksel = mcbsp_234_clksel,
3088 .flags = CLOCK_IN_OMAP343X,
3089 .clkdm = { .name = "per_clkdm" },
3090 .recalc = &omap2_clksel_recalc,
3093 static struct clk mcbsp4_fck = {
3094 .name = "mcbsp_fck",
3096 .parent = &mcbsp4_src_fck,
3097 .prcm_mod = OMAP3430_PER_MOD,
3098 .enable_reg = CM_FCLKEN,
3099 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3100 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3101 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3102 .clkdm = { .name = "per_clkdm" },
3103 .recalc = &omap2_clksel_recalc,
3108 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3110 static const struct clksel_rate emu_src_sys_rates[] = {
3111 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3115 static const struct clksel_rate emu_src_core_rates[] = {
3116 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3120 static const struct clksel_rate emu_src_per_rates[] = {
3121 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3125 static const struct clksel_rate emu_src_mpu_rates[] = {
3126 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3130 static const struct clksel emu_src_clksel[] = {
3131 { .parent = &sys_ck, .rates = emu_src_sys_rates },
3132 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3133 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
3134 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
3139 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3140 * to switch the source of some of the EMU clocks.
3141 * XXX Are there CLKEN bits for these EMU clks?
3143 static struct clk emu_src_ck = {
3144 .name = "emu_src_ck",
3145 .prcm_mod = OMAP3430_EMU_MOD,
3146 .init = &omap2_init_clksel_parent,
3147 .clksel_reg = CM_CLKSEL1,
3148 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
3149 .clksel = emu_src_clksel,
3150 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3151 .clkdm = { .name = "emu_clkdm" },
3152 .recalc = &omap2_clksel_recalc,
3155 static const struct clksel_rate pclk_emu_rates[] = {
3156 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3157 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3158 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3159 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3163 static const struct clksel pclk_emu_clksel[] = {
3164 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3168 static struct clk pclk_fck = {
3170 .prcm_mod = OMAP3430_EMU_MOD,
3171 .init = &omap2_init_clksel_parent,
3172 .clksel_reg = CM_CLKSEL1,
3173 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3174 .clksel = pclk_emu_clksel,
3175 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3176 .clkdm = { .name = "emu_clkdm" },
3177 .recalc = &omap2_clksel_recalc,
3180 static const struct clksel_rate pclkx2_emu_rates[] = {
3181 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3182 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3183 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3187 static const struct clksel pclkx2_emu_clksel[] = {
3188 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3192 static struct clk pclkx2_fck = {
3193 .name = "pclkx2_fck",
3194 .prcm_mod = OMAP3430_EMU_MOD,
3195 .init = &omap2_init_clksel_parent,
3196 .clksel_reg = CM_CLKSEL1,
3197 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3198 .clksel = pclkx2_emu_clksel,
3199 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3200 .clkdm = { .name = "emu_clkdm" },
3201 .recalc = &omap2_clksel_recalc,
3204 static const struct clksel atclk_emu_clksel[] = {
3205 { .parent = &emu_src_ck, .rates = div2_rates },
3209 static struct clk atclk_fck = {
3210 .name = "atclk_fck",
3211 .prcm_mod = OMAP3430_EMU_MOD,
3212 .init = &omap2_init_clksel_parent,
3213 .clksel_reg = CM_CLKSEL1,
3214 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3215 .clksel = atclk_emu_clksel,
3216 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3217 .clkdm = { .name = "emu_clkdm" },
3218 .recalc = &omap2_clksel_recalc,
3221 static struct clk traceclk_src_fck = {
3222 .name = "traceclk_src_fck",
3223 .prcm_mod = OMAP3430_EMU_MOD,
3224 .init = &omap2_init_clksel_parent,
3225 .clksel_reg = CM_CLKSEL1,
3226 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3227 .clksel = emu_src_clksel,
3228 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3229 .clkdm = { .name = "emu_clkdm" },
3230 .recalc = &omap2_clksel_recalc,
3233 static const struct clksel_rate traceclk_rates[] = {
3234 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3235 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3236 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3240 static const struct clksel traceclk_clksel[] = {
3241 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3245 static struct clk traceclk_fck = {
3246 .name = "traceclk_fck",
3247 .prcm_mod = OMAP3430_EMU_MOD,
3248 .init = &omap2_init_clksel_parent,
3249 .clksel_reg = CM_CLKSEL1,
3250 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3251 .clksel = traceclk_clksel,
3252 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3253 .clkdm = { .name = "emu_clkdm" },
3254 .recalc = &omap2_clksel_recalc,
3259 /* SmartReflex fclk (VDD1) */
3260 static struct clk sr1_fck = {
3263 .prcm_mod = WKUP_MOD,
3264 .enable_reg = CM_FCLKEN,
3265 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3266 .idlest_bit = OMAP3430_ST_SR1_SHIFT,
3267 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3268 .clkdm = { .name = "prm_clkdm" },
3269 .recalc = &followparent_recalc,
3272 /* SmartReflex fclk (VDD2) */
3273 static struct clk sr2_fck = {
3276 .prcm_mod = WKUP_MOD,
3277 .enable_reg = CM_FCLKEN,
3278 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3279 .idlest_bit = OMAP3430_ST_SR2_SHIFT,
3280 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3281 .clkdm = { .name = "prm_clkdm" },
3282 .recalc = &followparent_recalc,
3285 static struct clk sr_l4_ick = {
3286 .name = "sr_l4_ick",
3288 .flags = CLOCK_IN_OMAP343X,
3289 .clkdm = { .name = "core_l4_clkdm" },
3290 .recalc = &followparent_recalc,
3293 /* SECURE_32K_FCK clocks */
3295 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3296 static struct clk gpt12_fck = {
3297 .name = "gpt12_fck",
3298 .parent = &secure_32k_fck,
3299 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
3300 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3301 .clkdm = { .name = "prm_clkdm" },
3302 .recalc = &followparent_recalc,
3305 static struct clk wdt1_fck = {
3307 .parent = &secure_32k_fck,
3308 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3309 .clkdm = { .name = "prm_clkdm" },
3310 .recalc = &followparent_recalc,
3313 static struct clk *onchip_34xx_clks[] __initdata = {
3339 &omap_96m_alwon_fck,
3405 &ssi_ssr_fck_3430es1,
3406 &ssi_ssr_fck_3430es2,
3407 &ssi_sst_fck_3430es1,
3408 &ssi_sst_fck_3430es2,
3410 &hsotgusb_ick_3430es1,
3411 &hsotgusb_ick_3430es2,
3452 &dss1_alwon_fck_3430es1,
3453 &dss1_alwon_fck_3430es2,