arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <asm/arch/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  52 #define DPLL_LOW_POWER_STOP             0x1
  53 #define DPLL_LOW_POWER_BYPASS           0x5
  54 #define DPLL_LOCKED                     0x7
  55
  56 /* PRM CLOCKS */
  57
  58 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  59 static struct clk omap_32k_fck = {
  60         .name           = "omap_32k_fck",
  61         .rate           = 32768,
  62         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  63                                 ALWAYS_ENABLED,
  64         .recalc         = &propagate_rate,
  65 };
  66
  67 static struct clk secure_32k_fck = {
  68         .name           = "secure_32k_fck",
  69         .rate           = 32768,
  70         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  71                                 ALWAYS_ENABLED,
  72         .recalc         = &propagate_rate,
  73 };
  74
  75 /* Virtual source clocks for osc_sys_ck */
  76 static struct clk virt_12m_ck = {
  77         .name           = "virt_12m_ck",
  78         .rate           = 12000000,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .recalc         = &propagate_rate,
  82 };
  83
  84 static struct clk virt_13m_ck = {
  85         .name           = "virt_13m_ck",
  86         .rate           = 13000000,
  87         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  88                                 ALWAYS_ENABLED,
  89         .recalc         = &propagate_rate,
  90 };
  91
  92 static struct clk virt_16_8m_ck = {
  93         .name           = "virt_16_8m_ck",
  94         .rate           = 16800000,
  95         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  96                                 ALWAYS_ENABLED,
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_19_2m_ck = {
 101         .name           = "virt_19_2m_ck",
 102         .rate           = 19200000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .recalc         = &propagate_rate,
 106 };
 107
 108 static struct clk virt_26m_ck = {
 109         .name           = "virt_26m_ck",
 110         .rate           = 26000000,
 111         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 112                                 ALWAYS_ENABLED,
 113         .recalc         = &propagate_rate,
 114 };
 115
 116 static struct clk virt_38_4m_ck = {
 117         .name           = "virt_38_4m_ck",
 118         .rate           = 38400000,
 119         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 120                                 ALWAYS_ENABLED,
 121         .recalc         = &propagate_rate,
 122 };
 123
 124 static const struct clksel_rate osc_sys_12m_rates[] = {
 125         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 126         { .div = 0 }
 127 };
 128
 129 static const struct clksel_rate osc_sys_13m_rates[] = {
 130         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 131         { .div = 0 }
 132 };
 133
 134 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 135         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 136         { .div = 0 }
 137 };
 138
 139 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 141         { .div = 0 }
 142 };
 143
 144 static const struct clksel_rate osc_sys_26m_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 146         { .div = 0 }
 147 };
 148
 149 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 151         { .div = 0 }
 152 };
 153
 154 static const struct clksel osc_sys_clksel[] = {
 155         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 156         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 157         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 158         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 159         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 160         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 161         { .parent = NULL },
 162 };
 163
 164 /* Oscillator clock */
 165 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 166 static struct clk osc_sys_ck = {
 167         .name           = "osc_sys_ck",
 168         .init           = &omap2_init_clksel_parent,
 169         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 170         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 171         .clksel         = osc_sys_clksel,
 172         /* REVISIT: deal with autoextclkmode? */
 173         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 174                                 ALWAYS_ENABLED,
 175         .recalc         = &omap2_clksel_recalc,
 176 };
 177
 178 static const struct clksel_rate div2_rates[] = {
 179         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 180         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 181         { .div = 0 }
 182 };
 183
 184 static const struct clksel sys_clksel[] = {
 185         { .parent = &osc_sys_ck, .rates = div2_rates },
 186         { .parent = NULL }
 187 };
 188
 189 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 190 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 191 static struct clk sys_ck = {
 192         .name           = "sys_ck",
 193         .parent         = &osc_sys_ck,
 194         .init           = &omap2_init_clksel_parent,
 195         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 196         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 197         .clksel         = sys_clksel,
 198         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 199         .recalc         = &omap2_clksel_recalc,
 200 };
 201
 202 static struct clk sys_altclk = {
 203         .name           = "sys_altclk",
 204         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 205         .recalc         = &propagate_rate,
 206 };
 207
 208 /* Optional external clock input for some McBSPs */
 209 static struct clk mcbsp_clks = {
 210         .name           = "mcbsp_clks",
 211         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 212         .recalc         = &propagate_rate,
 213 };
 214
 215 /* PRM EXTERNAL CLOCK OUTPUT */
 216
 217 static struct clk sys_clkout1 = {
 218         .name           = "sys_clkout1",
 219         .parent         = &osc_sys_ck,
 220         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 221         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 222         .flags          = CLOCK_IN_OMAP343X,
 223         .recalc         = &followparent_recalc,
 224 };
 225
 226 /* DPLLS */
 227
 228 /* CM CLOCKS */
 229
 230 static const struct clksel_rate dpll_bypass_rates[] = {
 231         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 232         { .div = 0 }
 233 };
 234
 235 static const struct clksel_rate dpll_locked_rates[] = {
 236         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 237         { .div = 0 }
 238 };
 239
 240 static const struct clksel_rate div16_dpll_rates[] = {
 241         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 242         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 243         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 244         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 245         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 246         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 247         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 248         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 249         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 250         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 251         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 252         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 253         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 254         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 255         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 256         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 257         { .div = 0 }
 258 };
 259
 260 /* DPLL1 */
 261 /* MPU clock source */
 262 /* Type: DPLL */
 263 static struct dpll_data dpll1_dd = {
 264         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 265         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 266         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 267         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 268         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 269         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 270         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 271         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 272         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 273         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 274         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 275         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 276         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 277         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 278         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 279         .max_divider    = OMAP3_MAX_DPLL_DIV,
 280         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 281 };
 282
 283 static struct clk dpll1_ck = {
 284         .name           = "dpll1_ck",
 285         .parent         = &sys_ck,
 286         .dpll_data      = &dpll1_dd,
 287         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 288         .round_rate     = &omap2_dpll_round_rate,
 289         .set_rate       = &omap3_noncore_dpll_set_rate,
 290         .recalc         = &omap3_dpll_recalc,
 291 };
 292
 293 /*
 294  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 295  * DPLL isn't bypassed.
 296  */
 297 static struct clk dpll1_x2_ck = {
 298         .name           = "dpll1_x2_ck",
 299         .parent         = &dpll1_ck,
 300         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 301                                 PARENT_CONTROLS_CLOCK,
 302         .recalc         = &omap3_clkoutx2_recalc,
 303 };
 304
 305 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 306 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 307         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 308         { .parent = NULL }
 309 };
 310
 311 /*
 312  * Does not exist in the TRM - needed to separate the M2 divider from
 313  * bypass selection in mpu_ck
 314  */
 315 static struct clk dpll1_x2m2_ck = {
 316         .name           = "dpll1_x2m2_ck",
 317         .parent         = &dpll1_x2_ck,
 318         .init           = &omap2_init_clksel_parent,
 319         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 320         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 321         .clksel         = div16_dpll1_x2m2_clksel,
 322         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 323                                 PARENT_CONTROLS_CLOCK,
 324         .recalc         = &omap2_clksel_recalc,
 325 };
 326
 327 /* DPLL2 */
 328 /* IVA2 clock source */
 329 /* Type: DPLL */
 330
 331 static struct dpll_data dpll2_dd = {
 332         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 333         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 334         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 335         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 336         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 337         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 338         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 339                                 (1 << DPLL_LOW_POWER_BYPASS),
 340         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 341         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 342         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 343         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 344         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 345         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 346         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 347         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 348         .max_divider    = OMAP3_MAX_DPLL_DIV,
 349         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 350 };
 351
 352 static struct clk dpll2_ck = {
 353         .name           = "dpll2_ck",
 354         .parent         = &sys_ck,
 355         .dpll_data      = &dpll2_dd,
 356         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 357         .enable         = &omap3_noncore_dpll_enable,
 358         .disable        = &omap3_noncore_dpll_disable,
 359         .round_rate     = &omap2_dpll_round_rate,
 360         .set_rate       = &omap3_noncore_dpll_set_rate,
 361         .recalc         = &omap3_dpll_recalc,
 362 };
 363
 364 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 365         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 366         { .parent = NULL }
 367 };
 368
 369 /*
 370  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 371  * or CLKOUTX2. CLKOUT seems most plausible.
 372  */
 373 static struct clk dpll2_m2_ck = {
 374         .name           = "dpll2_m2_ck",
 375         .parent         = &dpll2_ck,
 376         .init           = &omap2_init_clksel_parent,
 377         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 378                                           OMAP3430_CM_CLKSEL2_PLL),
 379         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 380         .clksel         = div16_dpll2_m2x2_clksel,
 381         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 382                                 PARENT_CONTROLS_CLOCK,
 383         .recalc         = &omap2_clksel_recalc,
 384 };
 385
 386 /*
 387  * DPLL3
 388  * Source clock for all interfaces and for some device fclks
 389  * REVISIT: Also supports fast relock bypass - not included below
 390  */
 391 static struct dpll_data dpll3_dd = {
 392         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 393         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 394         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 395         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 396         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 397         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 398         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 399         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 400         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 401         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 402         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 403         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 404         .max_divider    = OMAP3_MAX_DPLL_DIV,
 405         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 406 };
 407
 408 static struct clk dpll3_ck = {
 409         .name           = "dpll3_ck",
 410         .parent         = &sys_ck,
 411         .dpll_data      = &dpll3_dd,
 412         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 413         .round_rate     = &omap2_dpll_round_rate,
 414         .set_rate       = &omap3_noncore_dpll_set_rate,
 415         .recalc         = &omap3_dpll_recalc,
 416 };
 417
 418 /*
 419  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 420  * DPLL isn't bypassed
 421  */
 422 static struct clk dpll3_x2_ck = {
 423         .name           = "dpll3_x2_ck",
 424         .parent         = &dpll3_ck,
 425         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 426                                 PARENT_CONTROLS_CLOCK,
 427         .recalc         = &omap3_clkoutx2_recalc,
 428 };
 429
 430 static const struct clksel_rate div31_dpll3_rates[] = {
 431         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 432         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 433         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 434         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 435         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 436         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 437         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 438         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 439         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 440         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 441         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 442         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 443         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 444         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 445         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 446         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 447         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 448         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 449         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 450         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 451         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 452         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 453         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 454         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 455         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 456         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 457         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 458         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 459         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 460         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 461         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 462         { .div = 0 },
 463 };
 464
 465 static const struct clksel div31_dpll3m2_clksel[] = {
 466         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 467         { .parent = NULL }
 468 };
 469
 470 /*
 471  * DPLL3 output M2
 472  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 473  * that code is ready, this should remain a 'read-only' clksel clock.
 474  */
 475 static struct clk dpll3_m2_ck = {
 476         .name           = "dpll3_m2_ck",
 477         .parent         = &dpll3_ck,
 478         .init           = &omap2_init_clksel_parent,
 479         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 480         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 481         .clksel         = div31_dpll3m2_clksel,
 482         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 483                                 PARENT_CONTROLS_CLOCK,
 484         .recalc         = &omap2_clksel_recalc,
 485 };
 486
 487 static const struct clksel core_ck_clksel[] = {
 488         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 489         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 490         { .parent = NULL }
 491 };
 492
 493 static struct clk core_ck = {
 494         .name           = "core_ck",
 495         .init           = &omap2_init_clksel_parent,
 496         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 497         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 498         .clksel         = core_ck_clksel,
 499         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 500                                 PARENT_CONTROLS_CLOCK,
 501         .recalc         = &omap2_clksel_recalc,
 502 };
 503
 504 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 505         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 506         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 507         { .parent = NULL }
 508 };
 509
 510 static struct clk dpll3_m2x2_ck = {
 511         .name           = "dpll3_m2x2_ck",
 512         .init           = &omap2_init_clksel_parent,
 513         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 514         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 515         .clksel         = dpll3_m2x2_ck_clksel,
 516         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 517                                 PARENT_CONTROLS_CLOCK,
 518         .recalc         = &omap2_clksel_recalc,
 519 };
 520
 521 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 522 static const struct clksel div16_dpll3_clksel[] = {
 523         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 524         { .parent = NULL }
 525 };
 526
 527 /* This virtual clock is the source for dpll3_m3x2_ck */
 528 static struct clk dpll3_m3_ck = {
 529         .name           = "dpll3_m3_ck",
 530         .parent         = &dpll3_ck,
 531         .init           = &omap2_init_clksel_parent,
 532         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 533         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 534         .clksel         = div16_dpll3_clksel,
 535         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 536                                 PARENT_CONTROLS_CLOCK,
 537         .recalc         = &omap2_clksel_recalc,
 538 };
 539
 540 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 541 static struct clk dpll3_m3x2_ck = {
 542         .name           = "dpll3_m3x2_ck",
 543         .parent         = &dpll3_m3_ck,
 544         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 545         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 546         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 547         .recalc         = &omap3_clkoutx2_recalc,
 548 };
 549
 550 static const struct clksel emu_core_alwon_ck_clksel[] = {
 551         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 552         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 553         { .parent = NULL }
 554 };
 555
 556 static struct clk emu_core_alwon_ck = {
 557         .name           = "emu_core_alwon_ck",
 558         .parent         = &dpll3_m3x2_ck,
 559         .init           = &omap2_init_clksel_parent,
 560         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 561         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 562         .clksel         = emu_core_alwon_ck_clksel,
 563         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 564                                 PARENT_CONTROLS_CLOCK,
 565         .recalc         = &omap2_clksel_recalc,
 566 };
 567
 568 /* DPLL4 */
 569 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 570 /* Type: DPLL */
 571 static struct dpll_data dpll4_dd = {
 572         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 573         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 574         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 575         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 576         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 577         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 578         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 579         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 580         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 581         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 582         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 583         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 584         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 585         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 586         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 587         .max_divider    = OMAP3_MAX_DPLL_DIV,
 588         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 589 };
 590
 591 static struct clk dpll4_ck = {
 592         .name           = "dpll4_ck",
 593         .parent         = &sys_ck,
 594         .dpll_data      = &dpll4_dd,
 595         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 596         .enable         = &omap3_noncore_dpll_enable,
 597         .disable        = &omap3_noncore_dpll_disable,
 598         .round_rate     = &omap2_dpll_round_rate,
 599         .set_rate       = &omap3_noncore_dpll_set_rate,
 600         .recalc         = &omap3_dpll_recalc,
 601 };
 602
 603 /*
 604  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 605  * DPLL isn't bypassed --
 606  * XXX does this serve any downstream clocks?
 607  */
 608 static struct clk dpll4_x2_ck = {
 609         .name           = "dpll4_x2_ck",
 610         .parent         = &dpll4_ck,
 611         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 612                                 PARENT_CONTROLS_CLOCK,
 613         .recalc         = &omap3_clkoutx2_recalc,
 614 };
 615
 616 static const struct clksel div16_dpll4_clksel[] = {
 617         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 618         { .parent = NULL }
 619 };
 620
 621 /* This virtual clock is the source for dpll4_m2x2_ck */
 622 static struct clk dpll4_m2_ck = {
 623         .name           = "dpll4_m2_ck",
 624         .parent         = &dpll4_ck,
 625         .init           = &omap2_init_clksel_parent,
 626         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 627         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 628         .clksel         = div16_dpll4_clksel,
 629         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 630                                 PARENT_CONTROLS_CLOCK,
 631         .recalc         = &omap2_clksel_recalc,
 632 };
 633
 634 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 635 static struct clk dpll4_m2x2_ck = {
 636         .name           = "dpll4_m2x2_ck",
 637         .parent         = &dpll4_m2_ck,
 638         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 639         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 640         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 641         .recalc         = &omap3_clkoutx2_recalc,
 642 };
 643
 644 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 645         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 646         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 647         { .parent = NULL }
 648 };
 649
 650 static struct clk omap_96m_alwon_fck = {
 651         .name           = "omap_96m_alwon_fck",
 652         .parent         = &dpll4_m2x2_ck,
 653         .init           = &omap2_init_clksel_parent,
 654         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 655         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 656         .clksel         = omap_96m_alwon_fck_clksel,
 657         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 658                                  PARENT_CONTROLS_CLOCK,
 659         .recalc         = &omap2_clksel_recalc,
 660 };
 661
 662 static struct clk omap_96m_fck = {
 663         .name           = "omap_96m_fck",
 664         .parent         = &omap_96m_alwon_fck,
 665         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 666                                 PARENT_CONTROLS_CLOCK,
 667         .recalc         = &followparent_recalc,
 668 };
 669
 670 static const struct clksel cm_96m_fck_clksel[] = {
 671         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 672         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 673         { .parent = NULL }
 674 };
 675
 676 static struct clk cm_96m_fck = {
 677         .name           = "cm_96m_fck",
 678         .parent         = &dpll4_m2x2_ck,
 679         .init           = &omap2_init_clksel_parent,
 680         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 681         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 682         .clksel         = cm_96m_fck_clksel,
 683         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 684                                 PARENT_CONTROLS_CLOCK,
 685         .recalc         = &omap2_clksel_recalc,
 686 };
 687
 688 /* This virtual clock is the source for dpll4_m3x2_ck */
 689 static struct clk dpll4_m3_ck = {
 690         .name           = "dpll4_m3_ck",
 691         .parent         = &dpll4_ck,
 692         .init           = &omap2_init_clksel_parent,
 693         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 694         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 695         .clksel         = div16_dpll4_clksel,
 696         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 697                                 PARENT_CONTROLS_CLOCK,
 698         .recalc         = &omap2_clksel_recalc,
 699 };
 700
 701 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 702 static struct clk dpll4_m3x2_ck = {
 703         .name           = "dpll4_m3x2_ck",
 704         .parent         = &dpll4_m3_ck,
 705         .init           = &omap2_init_clksel_parent,
 706         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 707         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 708         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 709         .recalc         = &omap3_clkoutx2_recalc,
 710 };
 711
 712 static const struct clksel virt_omap_54m_fck_clksel[] = {
 713         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 714         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 715         { .parent = NULL }
 716 };
 717
 718 static struct clk virt_omap_54m_fck = {
 719         .name           = "virt_omap_54m_fck",
 720         .parent         = &dpll4_m3x2_ck,
 721         .init           = &omap2_init_clksel_parent,
 722         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 723         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 724         .clksel         = virt_omap_54m_fck_clksel,
 725         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 726                                 PARENT_CONTROLS_CLOCK,
 727         .recalc         = &omap2_clksel_recalc,
 728 };
 729
 730 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 731         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 732         { .div = 0 }
 733 };
 734
 735 static const struct clksel_rate omap_54m_alt_rates[] = {
 736         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 737         { .div = 0 }
 738 };
 739
 740 static const struct clksel omap_54m_clksel[] = {
 741         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 742         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 743         { .parent = NULL }
 744 };
 745
 746 static struct clk omap_54m_fck = {
 747         .name           = "omap_54m_fck",
 748         .init           = &omap2_init_clksel_parent,
 749         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 750         .clksel_mask    = OMAP3430_SOURCE_54M,
 751         .clksel         = omap_54m_clksel,
 752         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 753                                 PARENT_CONTROLS_CLOCK,
 754         .recalc         = &omap2_clksel_recalc,
 755 };
 756
 757 static const struct clksel_rate omap_48m_96md2_rates[] = {
 758         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 759         { .div = 0 }
 760 };
 761
 762 static const struct clksel_rate omap_48m_alt_rates[] = {
 763         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 764         { .div = 0 }
 765 };
 766
 767 static const struct clksel omap_48m_clksel[] = {
 768         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 769         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 770         { .parent = NULL }
 771 };
 772
 773 static struct clk omap_48m_fck = {
 774         .name           = "omap_48m_fck",
 775         .init           = &omap2_init_clksel_parent,
 776         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 777         .clksel_mask    = OMAP3430_SOURCE_48M,
 778         .clksel         = omap_48m_clksel,
 779         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 780                                 PARENT_CONTROLS_CLOCK,
 781         .recalc         = &omap2_clksel_recalc,
 782 };
 783
 784 static struct clk omap_12m_fck = {
 785         .name           = "omap_12m_fck",
 786         .parent         = &omap_48m_fck,
 787         .fixed_div      = 4,
 788         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 789                                 PARENT_CONTROLS_CLOCK,
 790         .recalc         = &omap2_fixed_divisor_recalc,
 791 };
 792
 793 /* This virstual clock is the source for dpll4_m4x2_ck */
 794 static struct clk dpll4_m4_ck = {
 795         .name           = "dpll4_m4_ck",
 796         .parent         = &dpll4_ck,
 797         .init           = &omap2_init_clksel_parent,
 798         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 799         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 800         .clksel         = div16_dpll4_clksel,
 801         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 802                                 PARENT_CONTROLS_CLOCK,
 803         .recalc         = &omap2_clksel_recalc,
 804 };
 805
 806 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 807 static struct clk dpll4_m4x2_ck = {
 808         .name           = "dpll4_m4x2_ck",
 809         .parent         = &dpll4_m4_ck,
 810         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 811         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 812         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 813         .recalc         = &omap3_clkoutx2_recalc,
 814 };
 815
 816 /* This virtual clock is the source for dpll4_m5x2_ck */
 817 static struct clk dpll4_m5_ck = {
 818         .name           = "dpll4_m5_ck",
 819         .parent         = &dpll4_ck,
 820         .init           = &omap2_init_clksel_parent,
 821         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 822         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 823         .clksel         = div16_dpll4_clksel,
 824         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 825                                 PARENT_CONTROLS_CLOCK,
 826         .recalc         = &omap2_clksel_recalc,
 827 };
 828
 829 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 830 static struct clk dpll4_m5x2_ck = {
 831         .name           = "dpll4_m5x2_ck",
 832         .parent         = &dpll4_m5_ck,
 833         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 834         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 835         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 836         .recalc         = &omap3_clkoutx2_recalc,
 837 };
 838
 839 /* This virtual clock is the source for dpll4_m6x2_ck */
 840 static struct clk dpll4_m6_ck = {
 841         .name           = "dpll4_m6_ck",
 842         .parent         = &dpll4_ck,
 843         .init           = &omap2_init_clksel_parent,
 844         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 845         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 846         .clksel         = div16_dpll4_clksel,
 847         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 848                                 PARENT_CONTROLS_CLOCK,
 849         .recalc         = &omap2_clksel_recalc,
 850 };
 851
 852 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 853 static struct clk dpll4_m6x2_ck = {
 854         .name           = "dpll4_m6x2_ck",
 855         .parent         = &dpll4_m6_ck,
 856         .init           = &omap2_init_clksel_parent,
 857         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 858         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 859         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 860         .recalc         = &omap3_clkoutx2_recalc,
 861 };
 862
 863 static struct clk emu_per_alwon_ck = {
 864         .name           = "emu_per_alwon_ck",
 865         .parent         = &dpll4_m6x2_ck,
 866         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 867                                 PARENT_CONTROLS_CLOCK,
 868         .recalc         = &followparent_recalc,
 869 };
 870
 871 /* DPLL5 */
 872 /* Supplies 120MHz clock, USIM source clock */
 873 /* Type: DPLL */
 874 /* 3430ES2 only */
 875 static struct dpll_data dpll5_dd = {
 876         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 877         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 878         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 879         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 880         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 881         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 882         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 883         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 884         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 885         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 886         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 887         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 888         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 889         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 890         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 891         .max_divider    = OMAP3_MAX_DPLL_DIV,
 892         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 893 };
 894
 895 static struct clk dpll5_ck = {
 896         .name           = "dpll5_ck",
 897         .parent         = &sys_ck,
 898         .dpll_data      = &dpll5_dd,
 899         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 900         .enable         = &omap3_noncore_dpll_enable,
 901         .disable        = &omap3_noncore_dpll_disable,
 902         .round_rate     = &omap2_dpll_round_rate,
 903         .set_rate       = &omap3_noncore_dpll_set_rate,
 904         .recalc         = &omap3_dpll_recalc,
 905 };
 906
 907 static const struct clksel div16_dpll5_clksel[] = {
 908         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 909         { .parent = NULL }
 910 };
 911
 912 static struct clk dpll5_m2_ck = {
 913         .name           = "dpll5_m2_ck",
 914         .parent         = &dpll5_ck,
 915         .init           = &omap2_init_clksel_parent,
 916         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 917         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 918         .clksel         = div16_dpll5_clksel,
 919         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 920                                 PARENT_CONTROLS_CLOCK,
 921         .recalc         = &omap2_clksel_recalc,
 922 };
 923
 924 static const struct clksel omap_120m_fck_clksel[] = {
 925         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 926         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 927         { .parent = NULL }
 928 };
 929
 930 static struct clk omap_120m_fck = {
 931         .name           = "omap_120m_fck",
 932         .parent         = &dpll5_m2_ck,
 933         .init           = &omap2_init_clksel_parent,
 934         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 935         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 936         .clksel         = omap_120m_fck_clksel,
 937         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 938                                 PARENT_CONTROLS_CLOCK,
 939         .recalc         = &omap2_clksel_recalc,
 940 };
 941
 942 /* CM EXTERNAL CLOCK OUTPUTS */
 943
 944 static const struct clksel_rate clkout2_src_core_rates[] = {
 945         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 946         { .div = 0 }
 947 };
 948
 949 static const struct clksel_rate clkout2_src_sys_rates[] = {
 950         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 951         { .div = 0 }
 952 };
 953
 954 static const struct clksel_rate clkout2_src_96m_rates[] = {
 955         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 956         { .div = 0 }
 957 };
 958
 959 static const struct clksel_rate clkout2_src_54m_rates[] = {
 960         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 961         { .div = 0 }
 962 };
 963
 964 static const struct clksel clkout2_src_clksel[] = {
 965         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 966         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 967         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 968         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 969         { .parent = NULL }
 970 };
 971
 972 static struct clk clkout2_src_ck = {
 973         .name           = "clkout2_src_ck",
 974         .init           = &omap2_init_clksel_parent,
 975         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 976         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 977         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 978         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 979         .clksel         = clkout2_src_clksel,
 980         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 981         .recalc         = &omap2_clksel_recalc,
 982 };
 983
 984 static const struct clksel_rate sys_clkout2_rates[] = {
 985         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 986         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 987         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 988         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 989         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 990         { .div = 0 },
 991 };
 992
 993 static const struct clksel sys_clkout2_clksel[] = {
 994         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 995         { .parent = NULL },
 996 };
 997
 998 static struct clk sys_clkout2 = {
 999         .name           = "sys_clkout2",
1000         .init           = &omap2_init_clksel_parent,
1001         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1002         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1003         .clksel         = sys_clkout2_clksel,
1004         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1005         .recalc         = &omap2_clksel_recalc,
1006 };
1007
1008 /* CM OUTPUT CLOCKS */
1009
1010 static struct clk corex2_fck = {
1011         .name           = "corex2_fck",
1012         .parent         = &dpll3_m2x2_ck,
1013         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1014                                 PARENT_CONTROLS_CLOCK,
1015         .recalc         = &followparent_recalc,
1016 };
1017
1018 /* DPLL power domain clock controls */
1019
1020 static const struct clksel div2_core_clksel[] = {
1021         { .parent = &core_ck, .rates = div2_rates },
1022         { .parent = NULL }
1023 };
1024
1025 /*
1026  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1027  * may be inconsistent here?
1028  */
1029 static struct clk dpll1_fck = {
1030         .name           = "dpll1_fck",
1031         .parent         = &core_ck,
1032         .init           = &omap2_init_clksel_parent,
1033         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1034         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1035         .clksel         = div2_core_clksel,
1036         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1037                                 PARENT_CONTROLS_CLOCK,
1038         .recalc         = &omap2_clksel_recalc,
1039 };
1040
1041 /*
1042  * MPU clksel:
1043  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1044  * derives from the high-frequency bypass clock originating from DPLL3,
1045  * called 'dpll1_fck'
1046  */
1047 static const struct clksel mpu_clksel[] = {
1048         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1049         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1050         { .parent = NULL }
1051 };
1052
1053 static struct clk mpu_ck = {
1054         .name           = "mpu_ck",
1055         .parent         = &dpll1_x2m2_ck,
1056         .init           = &omap2_init_clksel_parent,
1057         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1058         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1059         .clksel         = mpu_clksel,
1060         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1061                                 PARENT_CONTROLS_CLOCK,
1062         .clkdm_name     = "mpu_clkdm",
1063         .recalc         = &omap2_clksel_recalc,
1064 };
1065
1066 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1067 static const struct clksel_rate arm_fck_rates[] = {
1068         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1069         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1070         { .div = 0 },
1071 };
1072
1073 static const struct clksel arm_fck_clksel[] = {
1074         { .parent = &mpu_ck, .rates = arm_fck_rates },
1075         { .parent = NULL }
1076 };
1077
1078 static struct clk arm_fck = {
1079         .name           = "arm_fck",
1080         .parent         = &mpu_ck,
1081         .init           = &omap2_init_clksel_parent,
1082         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1083         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1084         .clksel         = arm_fck_clksel,
1085         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1086                                 PARENT_CONTROLS_CLOCK,
1087         .recalc         = &omap2_clksel_recalc,
1088 };
1089
1090 /* XXX What about neon_clkdm ? */
1091
1092 /*
1093  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1094  * although it is referenced - so this is a guess
1095  */
1096 static struct clk emu_mpu_alwon_ck = {
1097         .name           = "emu_mpu_alwon_ck",
1098         .parent         = &mpu_ck,
1099         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1100                                 PARENT_CONTROLS_CLOCK,
1101         .recalc         = &followparent_recalc,
1102 };
1103
1104 static struct clk dpll2_fck = {
1105         .name           = "dpll2_fck",
1106         .parent         = &core_ck,
1107         .init           = &omap2_init_clksel_parent,
1108         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1109         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1110         .clksel         = div2_core_clksel,
1111         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1112                                 PARENT_CONTROLS_CLOCK,
1113         .recalc         = &omap2_clksel_recalc,
1114 };
1115
1116 /*
1117  * IVA2 clksel:
1118  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1119  * derives from the high-frequency bypass clock originating from DPLL3,
1120  * called 'dpll2_fck'
1121  */
1122
1123 static const struct clksel iva2_clksel[] = {
1124         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1125         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1126         { .parent = NULL }
1127 };
1128
1129 static struct clk iva2_ck = {
1130         .name           = "iva2_ck",
1131         .parent         = &dpll2_m2_ck,
1132         .init           = &omap2_init_clksel_parent,
1133         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1134         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1135         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1136                                           OMAP3430_CM_IDLEST_PLL),
1137         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1138         .clksel         = iva2_clksel,
1139         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1140         .clkdm_name     = "iva2_clkdm",
1141         .recalc         = &omap2_clksel_recalc,
1142 };
1143
1144 /* Common interface clocks */
1145
1146 static struct clk l3_ick = {
1147         .name           = "l3_ick",
1148         .parent         = &core_ck,
1149         .init           = &omap2_init_clksel_parent,
1150         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1151         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1152         .clksel         = div2_core_clksel,
1153         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1154                                 PARENT_CONTROLS_CLOCK,
1155         .clkdm_name     = "core_l3_clkdm",
1156         .recalc         = &omap2_clksel_recalc,
1157 };
1158
1159 static const struct clksel div2_l3_clksel[] = {
1160         { .parent = &l3_ick, .rates = div2_rates },
1161         { .parent = NULL }
1162 };
1163
1164 static struct clk l4_ick = {
1165         .name           = "l4_ick",
1166         .parent         = &l3_ick,
1167         .init           = &omap2_init_clksel_parent,
1168         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1169         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1170         .clksel         = div2_l3_clksel,
1171         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1172                                 PARENT_CONTROLS_CLOCK,
1173         .clkdm_name     = "core_l4_clkdm",
1174         .recalc         = &omap2_clksel_recalc,
1175
1176 };
1177
1178 static const struct clksel div2_l4_clksel[] = {
1179         { .parent = &l4_ick, .rates = div2_rates },
1180         { .parent = NULL }
1181 };
1182
1183 static struct clk rm_ick = {
1184         .name           = "rm_ick",
1185         .parent         = &l4_ick,
1186         .init           = &omap2_init_clksel_parent,
1187         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1188         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1189         .clksel         = div2_l4_clksel,
1190         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1191         .recalc         = &omap2_clksel_recalc,
1192 };
1193
1194 /* GFX power domain */
1195
1196 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1197
1198 static const struct clksel gfx_l3_clksel[] = {
1199         { .parent = &l3_ick, .rates = gfx_l3_rates },
1200         { .parent = NULL }
1201 };
1202
1203 static struct clk gfx_l3_fck = {
1204         .name           = "gfx_l3_fck",
1205         .parent         = &l3_ick,
1206         .init           = &omap2_init_clksel_parent,
1207         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1208         .enable_bit     = OMAP_EN_GFX_SHIFT,
1209         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1210         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1211         .clksel         = gfx_l3_clksel,
1212         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1213         .clkdm_name     = "gfx_3430es1_clkdm",
1214         .recalc         = &omap2_clksel_recalc,
1215 };
1216
1217 static struct clk gfx_l3_ick = {
1218         .name           = "gfx_l3_ick",
1219         .parent         = &l3_ick,
1220         .init           = &omap2_init_clk_clkdm,
1221         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1222         .enable_bit     = OMAP_EN_GFX_SHIFT,
1223         .flags          = CLOCK_IN_OMAP3430ES1,
1224         .clkdm_name     = "gfx_3430es1_clkdm",
1225         .recalc         = &followparent_recalc,
1226 };
1227
1228 static struct clk gfx_cg1_ck = {
1229         .name           = "gfx_cg1_ck",
1230         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1231         .init           = &omap2_init_clk_clkdm,
1232         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1233         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1234         .flags          = CLOCK_IN_OMAP3430ES1,
1235         .clkdm_name     = "gfx_3430es1_clkdm",
1236         .recalc         = &followparent_recalc,
1237 };
1238
1239 static struct clk gfx_cg2_ck = {
1240         .name           = "gfx_cg2_ck",
1241         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1242         .init           = &omap2_init_clk_clkdm,
1243         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1244         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1245         .flags          = CLOCK_IN_OMAP3430ES1,
1246         .clkdm_name     = "gfx_3430es1_clkdm",
1247         .recalc         = &followparent_recalc,
1248 };
1249
1250 /* SGX power domain - 3430ES2 only */
1251
1252 static const struct clksel_rate sgx_core_rates[] = {
1253         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1254         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1255         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1256         { .div = 0 },
1257 };
1258
1259 static const struct clksel_rate sgx_96m_rates[] = {
1260         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1261         { .div = 0 },
1262 };
1263
1264 static const struct clksel sgx_clksel[] = {
1265         { .parent = &core_ck,    .rates = sgx_core_rates },
1266         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1267         { .parent = NULL },
1268 };
1269
1270 static struct clk sgx_fck = {
1271         .name           = "sgx_fck",
1272         .init           = &omap2_init_clksel_parent,
1273         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1274         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1275         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1276         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1277         .clksel         = sgx_clksel,
1278         .flags          = CLOCK_IN_OMAP3430ES2,
1279         .clkdm_name     = "sgx_clkdm",
1280         .recalc         = &omap2_clksel_recalc,
1281 };
1282
1283 static struct clk sgx_ick = {
1284         .name           = "sgx_ick",
1285         .parent         = &l3_ick,
1286         .init           = &omap2_init_clk_clkdm,
1287         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1288         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1289         .flags          = CLOCK_IN_OMAP3430ES2,
1290         .clkdm_name     = "sgx_clkdm",
1291         .recalc         = &followparent_recalc,
1292 };
1293
1294 /* CORE power domain */
1295
1296 static struct clk d2d_26m_fck = {
1297         .name           = "d2d_26m_fck",
1298         .parent         = &sys_ck,
1299         .init           = &omap2_init_clk_clkdm,
1300         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1301         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1302         .flags          = CLOCK_IN_OMAP3430ES1,
1303         .clkdm_name     = "d2d_clkdm",
1304         .recalc         = &followparent_recalc,
1305 };
1306
1307 static const struct clksel omap343x_gpt_clksel[] = {
1308         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1309         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1310         { .parent = NULL}
1311 };
1312
1313 static struct clk gpt10_fck = {
1314         .name           = "gpt10_fck",
1315         .parent         = &sys_ck,
1316         .init           = &omap2_init_clksel_parent,
1317         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1318         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1319         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1320         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1321         .clksel         = omap343x_gpt_clksel,
1322         .flags          = CLOCK_IN_OMAP343X,
1323         .clkdm_name     = "core_l4_clkdm",
1324         .recalc         = &omap2_clksel_recalc,
1325 };
1326
1327 static struct clk gpt11_fck = {
1328         .name           = "gpt11_fck",
1329         .parent         = &sys_ck,
1330         .init           = &omap2_init_clksel_parent,
1331         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1333         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1334         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1335         .clksel         = omap343x_gpt_clksel,
1336         .flags          = CLOCK_IN_OMAP343X,
1337         .clkdm_name     = "core_l4_clkdm",
1338         .recalc         = &omap2_clksel_recalc,
1339 };
1340
1341 static struct clk cpefuse_fck = {
1342         .name           = "cpefuse_fck",
1343         .parent         = &sys_ck,
1344         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1345         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1346         .flags          = CLOCK_IN_OMAP3430ES2,
1347         .recalc         = &followparent_recalc,
1348 };
1349
1350 static struct clk ts_fck = {
1351         .name           = "ts_fck",
1352         .parent         = &omap_32k_fck,
1353         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1354         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1355         .flags          = CLOCK_IN_OMAP3430ES2,
1356         .recalc         = &followparent_recalc,
1357 };
1358
1359 static struct clk usbtll_fck = {
1360         .name           = "usbtll_fck",
1361         .parent         = &omap_120m_fck,
1362         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1363         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1364         .flags          = CLOCK_IN_OMAP3430ES2,
1365         .recalc         = &followparent_recalc,
1366 };
1367
1368 /* CORE 96M FCLK-derived clocks */
1369
1370 static struct clk core_96m_fck = {
1371         .name           = "core_96m_fck",
1372         .parent         = &omap_96m_fck,
1373         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1374                                 PARENT_CONTROLS_CLOCK,
1375         .clkdm_name     = "core_l4_clkdm",
1376         .recalc         = &followparent_recalc,
1377 };
1378
1379 static struct clk mmchs3_fck = {
1380         .name           = "mmchs_fck",
1381         .id             = 3,
1382         .parent         = &core_96m_fck,
1383         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1385         .flags          = CLOCK_IN_OMAP3430ES2,
1386         .clkdm_name     = "core_l4_clkdm",
1387         .recalc         = &followparent_recalc,
1388 };
1389
1390 static struct clk mmchs2_fck = {
1391         .name           = "mmchs_fck",
1392         .id             = 2,
1393         .parent         = &core_96m_fck,
1394         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1395         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1396         .flags          = CLOCK_IN_OMAP343X,
1397         .clkdm_name     = "core_l4_clkdm",
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 static struct clk mspro_fck = {
1402         .name           = "mspro_fck",
1403         .parent         = &core_96m_fck,
1404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1405         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1406         .flags          = CLOCK_IN_OMAP343X,
1407         .clkdm_name     = "core_l4_clkdm",
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk mmchs1_fck = {
1412         .name           = "mmchs_fck",
1413         .id             = 1,
1414         .parent         = &core_96m_fck,
1415         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1416         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1417         .flags          = CLOCK_IN_OMAP343X,
1418         .clkdm_name     = "core_l4_clkdm",
1419         .recalc         = &followparent_recalc,
1420 };
1421
1422 static struct clk i2c3_fck = {
1423         .name           = "i2c_fck",
1424         .id             = 3,
1425         .parent         = &core_96m_fck,
1426         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1427         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1428         .flags          = CLOCK_IN_OMAP343X,
1429         .clkdm_name     = "core_l4_clkdm",
1430         .recalc         = &followparent_recalc,
1431 };
1432
1433 static struct clk i2c2_fck = {
1434         .name           = "i2c_fck",
1435         .id             = 2,
1436         .parent         = &core_96m_fck,
1437         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1438         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1439         .flags          = CLOCK_IN_OMAP343X,
1440         .clkdm_name     = "core_l4_clkdm",
1441         .recalc         = &followparent_recalc,
1442 };
1443
1444 static struct clk i2c1_fck = {
1445         .name           = "i2c_fck",
1446         .id             = 1,
1447         .parent         = &core_96m_fck,
1448         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1449         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1450         .flags          = CLOCK_IN_OMAP343X,
1451         .clkdm_name     = "core_l4_clkdm",
1452         .recalc         = &followparent_recalc,
1453 };
1454
1455 /*
1456  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1457  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1458  */
1459 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1460         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1461         { .div = 0 }
1462 };
1463
1464 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1465         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1466         { .div = 0 }
1467 };
1468
1469 static const struct clksel mcbsp_15_clksel[] = {
1470         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1471         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1472         { .parent = NULL }
1473 };
1474
1475 static struct clk mcbsp5_fck = {
1476         .name           = "mcbsp5_fck",
1477         .init           = &omap2_init_clksel_parent,
1478         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1479         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1480         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1481         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1482         .clksel         = mcbsp_15_clksel,
1483         .flags          = CLOCK_IN_OMAP343X,
1484         .clkdm_name     = "core_l4_clkdm",
1485         .recalc         = &omap2_clksel_recalc,
1486 };
1487
1488 static struct clk mcbsp1_fck = {
1489         .name           = "mcbsp1_fck",
1490         .init           = &omap2_init_clksel_parent,
1491         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1492         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1493         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1494         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1495         .clksel         = mcbsp_15_clksel,
1496         .flags          = CLOCK_IN_OMAP343X,
1497         .clkdm_name     = "core_l4_clkdm",
1498         .recalc         = &omap2_clksel_recalc,
1499 };
1500
1501 /* CORE_48M_FCK-derived clocks */
1502
1503 static struct clk core_48m_fck = {
1504         .name           = "core_48m_fck",
1505         .parent         = &omap_48m_fck,
1506         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1507                                 PARENT_CONTROLS_CLOCK,
1508         .clkdm_name     = "core_l4_clkdm",
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static struct clk mcspi4_fck = {
1513         .name           = "mcspi_fck",
1514         .id             = 4,
1515         .parent         = &core_48m_fck,
1516         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1517         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1518         .flags          = CLOCK_IN_OMAP343X,
1519         .recalc         = &followparent_recalc,
1520 };
1521
1522 static struct clk mcspi3_fck = {
1523         .name           = "mcspi_fck",
1524         .id             = 3,
1525         .parent         = &core_48m_fck,
1526         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1527         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1528         .flags          = CLOCK_IN_OMAP343X,
1529         .recalc         = &followparent_recalc,
1530 };
1531
1532 static struct clk mcspi2_fck = {
1533         .name           = "mcspi_fck",
1534         .id             = 2,
1535         .parent         = &core_48m_fck,
1536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1538         .flags          = CLOCK_IN_OMAP343X,
1539         .recalc         = &followparent_recalc,
1540 };
1541
1542 static struct clk mcspi1_fck = {
1543         .name           = "mcspi_fck",
1544         .id             = 1,
1545         .parent         = &core_48m_fck,
1546         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1547         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1548         .flags          = CLOCK_IN_OMAP343X,
1549         .recalc         = &followparent_recalc,
1550 };
1551
1552 static struct clk uart2_fck = {
1553         .name           = "uart2_fck",
1554         .parent         = &core_48m_fck,
1555         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1556         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1557         .flags          = CLOCK_IN_OMAP343X,
1558         .recalc         = &followparent_recalc,
1559 };
1560
1561 static struct clk uart1_fck = {
1562         .name           = "uart1_fck",
1563         .parent         = &core_48m_fck,
1564         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1565         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1566         .flags          = CLOCK_IN_OMAP343X,
1567         .recalc         = &followparent_recalc,
1568 };
1569
1570 static struct clk fshostusb_fck = {
1571         .name           = "fshostusb_fck",
1572         .parent         = &core_48m_fck,
1573         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1574         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1575         .flags          = CLOCK_IN_OMAP3430ES1,
1576         .recalc         = &followparent_recalc,
1577 };
1578
1579 /* CORE_12M_FCK based clocks */
1580
1581 static struct clk core_12m_fck = {
1582         .name           = "core_12m_fck",
1583         .parent         = &omap_12m_fck,
1584         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1585                                 PARENT_CONTROLS_CLOCK,
1586         .clkdm_name     = "core_l4_clkdm",
1587         .recalc         = &followparent_recalc,
1588 };
1589
1590 static struct clk hdq_fck = {
1591         .name           = "hdq_fck",
1592         .parent         = &core_12m_fck,
1593         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1595         .flags          = CLOCK_IN_OMAP343X,
1596         .recalc         = &followparent_recalc,
1597 };
1598
1599 /* DPLL3-derived clock */
1600
1601 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1602         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1603         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1604         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1605         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1606         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1607         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1608         { .div = 0 }
1609 };
1610
1611 static const struct clksel ssi_ssr_clksel[] = {
1612         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1613         { .parent = NULL }
1614 };
1615
1616 static struct clk ssi_ssr_fck = {
1617         .name           = "ssi_ssr_fck",
1618         .init           = &omap2_init_clksel_parent,
1619         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1620         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1621         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1622         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1623         .clksel         = ssi_ssr_clksel,
1624         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1625         .clkdm_name     = "core_l4_clkdm",
1626         .recalc         = &omap2_clksel_recalc,
1627 };
1628
1629 static struct clk ssi_sst_fck = {
1630         .name           = "ssi_sst_fck",
1631         .parent         = &ssi_ssr_fck,
1632         .fixed_div      = 2,
1633         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1634         .recalc         = &omap2_fixed_divisor_recalc,
1635 };
1636
1637
1638
1639 /* CORE_L3_ICK based clocks */
1640
1641 /*
1642  * XXX must add clk_enable/clk_disable for these if standard code won't
1643  * handle it
1644  */
1645 static struct clk core_l3_ick = {
1646         .name           = "core_l3_ick",
1647         .parent         = &l3_ick,
1648         .init           = &omap2_init_clk_clkdm,
1649         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1650                                 PARENT_CONTROLS_CLOCK,
1651         .clkdm_name     = "core_l3_clkdm",
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk hsotgusb_ick = {
1656         .name           = "hsotgusb_ick",
1657         .parent         = &core_l3_ick,
1658         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1659         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1660         .flags          = CLOCK_IN_OMAP343X,
1661         .clkdm_name     = "core_l3_clkdm",
1662         .recalc         = &followparent_recalc,
1663 };
1664
1665 static struct clk sdrc_ick = {
1666         .name           = "sdrc_ick",
1667         .parent         = &core_l3_ick,
1668         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1669         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1670         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1671         .clkdm_name     = "core_l3_clkdm",
1672         .recalc         = &followparent_recalc,
1673 };
1674
1675 static struct clk gpmc_fck = {
1676         .name           = "gpmc_fck",
1677         .parent         = &core_l3_ick,
1678         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1679                                 ENABLE_ON_INIT,
1680         .clkdm_name     = "core_l3_clkdm",
1681         .recalc         = &followparent_recalc,
1682 };
1683
1684 /* SECURITY_L3_ICK based clocks */
1685
1686 static struct clk security_l3_ick = {
1687         .name           = "security_l3_ick",
1688         .parent         = &l3_ick,
1689         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1690                                 PARENT_CONTROLS_CLOCK,
1691         .recalc         = &followparent_recalc,
1692 };
1693
1694 static struct clk pka_ick = {
1695         .name           = "pka_ick",
1696         .parent         = &security_l3_ick,
1697         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1698         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1699         .flags          = CLOCK_IN_OMAP343X,
1700         .recalc         = &followparent_recalc,
1701 };
1702
1703 /* CORE_L4_ICK based clocks */
1704
1705 static struct clk core_l4_ick = {
1706         .name           = "core_l4_ick",
1707         .parent         = &l4_ick,
1708         .init           = &omap2_init_clk_clkdm,
1709         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1710                                 PARENT_CONTROLS_CLOCK,
1711         .clkdm_name     = "core_l4_clkdm",
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 static struct clk usbtll_ick = {
1716         .name           = "usbtll_ick",
1717         .parent         = &core_l4_ick,
1718         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1719         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1720         .flags          = CLOCK_IN_OMAP3430ES2,
1721         .clkdm_name     = "core_l4_clkdm",
1722         .recalc         = &followparent_recalc,
1723 };
1724
1725 static struct clk mmchs3_ick = {
1726         .name           = "mmchs_ick",
1727         .id             = 3,
1728         .parent         = &core_l4_ick,
1729         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1730         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1731         .flags          = CLOCK_IN_OMAP3430ES2,
1732         .clkdm_name     = "core_l4_clkdm",
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 /* Intersystem Communication Registers - chassis mode only */
1737 static struct clk icr_ick = {
1738         .name           = "icr_ick",
1739         .parent         = &core_l4_ick,
1740         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1741         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1742         .flags          = CLOCK_IN_OMAP343X,
1743         .clkdm_name     = "core_l4_clkdm",
1744         .recalc         = &followparent_recalc,
1745 };
1746
1747 static struct clk aes2_ick = {
1748         .name           = "aes2_ick",
1749         .parent         = &core_l4_ick,
1750         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1751         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1752         .flags          = CLOCK_IN_OMAP343X,
1753         .clkdm_name     = "core_l4_clkdm",
1754         .recalc         = &followparent_recalc,
1755 };
1756
1757 static struct clk sha12_ick = {
1758         .name           = "sha12_ick",
1759         .parent         = &core_l4_ick,
1760         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1761         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1762         .flags          = CLOCK_IN_OMAP343X,
1763         .clkdm_name     = "core_l4_clkdm",
1764         .recalc         = &followparent_recalc,
1765 };
1766
1767 static struct clk des2_ick = {
1768         .name           = "des2_ick",
1769         .parent         = &core_l4_ick,
1770         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1771         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1772         .flags          = CLOCK_IN_OMAP343X,
1773         .clkdm_name     = "core_l4_clkdm",
1774         .recalc         = &followparent_recalc,
1775 };
1776
1777 static struct clk mmchs2_ick = {
1778         .name           = "mmchs_ick",
1779         .id             = 2,
1780         .parent         = &core_l4_ick,
1781         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1782         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1783         .flags          = CLOCK_IN_OMAP343X,
1784         .clkdm_name     = "core_l4_clkdm",
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk mmchs1_ick = {
1789         .name           = "mmchs_ick",
1790         .id             = 1,
1791         .parent         = &core_l4_ick,
1792         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1793         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1794         .flags          = CLOCK_IN_OMAP343X,
1795         .clkdm_name     = "core_l4_clkdm",
1796         .recalc         = &followparent_recalc,
1797 };
1798
1799 static struct clk mspro_ick = {
1800         .name           = "mspro_ick",
1801         .parent         = &core_l4_ick,
1802         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1803         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1804         .flags          = CLOCK_IN_OMAP343X,
1805         .clkdm_name     = "core_l4_clkdm",
1806         .recalc         = &followparent_recalc,
1807 };
1808
1809 static struct clk hdq_ick = {
1810         .name           = "hdq_ick",
1811         .parent         = &core_l4_ick,
1812         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1813         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1814         .flags          = CLOCK_IN_OMAP343X,
1815         .clkdm_name     = "core_l4_clkdm",
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 static struct clk mcspi4_ick = {
1820         .name           = "mcspi_ick",
1821         .id             = 4,
1822         .parent         = &core_l4_ick,
1823         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1824         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1825         .flags          = CLOCK_IN_OMAP343X,
1826         .clkdm_name     = "core_l4_clkdm",
1827         .recalc         = &followparent_recalc,
1828 };
1829
1830 static struct clk mcspi3_ick = {
1831         .name           = "mcspi_ick",
1832         .id             = 3,
1833         .parent         = &core_l4_ick,
1834         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1835         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1836         .flags          = CLOCK_IN_OMAP343X,
1837         .clkdm_name     = "core_l4_clkdm",
1838         .recalc         = &followparent_recalc,
1839 };
1840
1841 static struct clk mcspi2_ick = {
1842         .name           = "mcspi_ick",
1843         .id             = 2,
1844         .parent         = &core_l4_ick,
1845         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1846         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1847         .flags          = CLOCK_IN_OMAP343X,
1848         .clkdm_name     = "core_l4_clkdm",
1849         .recalc         = &followparent_recalc,
1850 };
1851
1852 static struct clk mcspi1_ick = {
1853         .name           = "mcspi_ick",
1854         .id             = 1,
1855         .parent         = &core_l4_ick,
1856         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1857         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1858         .flags          = CLOCK_IN_OMAP343X,
1859         .clkdm_name     = "core_l4_clkdm",
1860         .recalc         = &followparent_recalc,
1861 };
1862
1863 static struct clk i2c3_ick = {
1864         .name           = "i2c_ick",
1865         .id             = 3,
1866         .parent         = &core_l4_ick,
1867         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1868         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1869         .flags          = CLOCK_IN_OMAP343X,
1870         .clkdm_name     = "core_l4_clkdm",
1871         .recalc         = &followparent_recalc,
1872 };
1873
1874 static struct clk i2c2_ick = {
1875         .name           = "i2c_ick",
1876         .id             = 2,
1877         .parent         = &core_l4_ick,
1878         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1879         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1880         .flags          = CLOCK_IN_OMAP343X,
1881         .clkdm_name     = "core_l4_clkdm",
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk i2c1_ick = {
1886         .name           = "i2c_ick",
1887         .id             = 1,
1888         .parent         = &core_l4_ick,
1889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1891         .flags          = CLOCK_IN_OMAP343X,
1892         .clkdm_name     = "core_l4_clkdm",
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk uart2_ick = {
1897         .name           = "uart2_ick",
1898         .parent         = &core_l4_ick,
1899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1900         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1901         .flags          = CLOCK_IN_OMAP343X,
1902         .clkdm_name     = "core_l4_clkdm",
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk uart1_ick = {
1907         .name           = "uart1_ick",
1908         .parent         = &core_l4_ick,
1909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1910         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1911         .flags          = CLOCK_IN_OMAP343X,
1912         .clkdm_name     = "core_l4_clkdm",
1913         .recalc         = &followparent_recalc,
1914 };
1915
1916 static struct clk gpt11_ick = {
1917         .name           = "gpt11_ick",
1918         .parent         = &core_l4_ick,
1919         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1920         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1921         .flags          = CLOCK_IN_OMAP343X,
1922         .clkdm_name     = "core_l4_clkdm",
1923         .recalc         = &followparent_recalc,
1924 };
1925
1926 static struct clk gpt10_ick = {
1927         .name           = "gpt10_ick",
1928         .parent         = &core_l4_ick,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1930         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1931         .flags          = CLOCK_IN_OMAP343X,
1932         .clkdm_name     = "core_l4_clkdm",
1933         .recalc         = &followparent_recalc,
1934 };
1935
1936 static struct clk mcbsp5_ick = {
1937         .name           = "mcbsp5_ick",
1938         .parent         = &core_l4_ick,
1939         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1940         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1941         .flags          = CLOCK_IN_OMAP343X,
1942         .clkdm_name     = "core_l4_clkdm",
1943         .recalc         = &followparent_recalc,
1944 };
1945
1946 static struct clk mcbsp1_ick = {
1947         .name           = "mcbsp1_ick",
1948         .parent         = &core_l4_ick,
1949         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1950         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1951         .flags          = CLOCK_IN_OMAP343X,
1952         .clkdm_name     = "core_l4_clkdm",
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk fac_ick = {
1957         .name           = "fac_ick",
1958         .parent         = &core_l4_ick,
1959         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1960         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1961         .flags          = CLOCK_IN_OMAP3430ES1,
1962         .clkdm_name     = "core_l4_clkdm",
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk mailboxes_ick = {
1967         .name           = "mailboxes_ick",
1968         .parent         = &core_l4_ick,
1969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1970         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1971         .flags          = CLOCK_IN_OMAP343X,
1972         .clkdm_name     = "core_l4_clkdm",
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk omapctrl_ick = {
1977         .name           = "omapctrl_ick",
1978         .parent         = &core_l4_ick,
1979         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1980         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1981         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1982         .recalc         = &followparent_recalc,
1983 };
1984
1985 /* SSI_L4_ICK based clocks */
1986
1987 static struct clk ssi_l4_ick = {
1988         .name           = "ssi_l4_ick",
1989         .parent         = &l4_ick,
1990         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1991                                 PARENT_CONTROLS_CLOCK,
1992         .clkdm_name     = "core_l4_clkdm",
1993         .recalc         = &followparent_recalc,
1994 };
1995
1996 static struct clk ssi_ick = {
1997         .name           = "ssi_ick",
1998         .parent         = &ssi_l4_ick,
1999         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2000         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2001         .flags          = CLOCK_IN_OMAP343X,
2002         .clkdm_name     = "core_l4_clkdm",
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2007  * but l4_ick makes more sense to me */
2008
2009 static const struct clksel usb_l4_clksel[] = {
2010         { .parent = &l4_ick, .rates = div2_rates },
2011         { .parent = NULL },
2012 };
2013
2014 static struct clk usb_l4_ick = {
2015         .name           = "usb_l4_ick",
2016         .parent         = &l4_ick,
2017         .init           = &omap2_init_clksel_parent,
2018         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2020         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2021         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2022         .clksel         = usb_l4_clksel,
2023         .flags          = CLOCK_IN_OMAP3430ES1,
2024         .recalc         = &omap2_clksel_recalc,
2025 };
2026
2027 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2028
2029 /* SECURITY_L4_ICK2 based clocks */
2030
2031 static struct clk security_l4_ick2 = {
2032         .name           = "security_l4_ick2",
2033         .parent         = &l4_ick,
2034         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2035                                 PARENT_CONTROLS_CLOCK,
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk aes1_ick = {
2040         .name           = "aes1_ick",
2041         .parent         = &security_l4_ick2,
2042         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2043         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2044         .flags          = CLOCK_IN_OMAP343X,
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk rng_ick = {
2049         .name           = "rng_ick",
2050         .parent         = &security_l4_ick2,
2051         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2052         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2053         .flags          = CLOCK_IN_OMAP343X,
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk sha11_ick = {
2058         .name           = "sha11_ick",
2059         .parent         = &security_l4_ick2,
2060         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2061         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2062         .flags          = CLOCK_IN_OMAP343X,
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk des1_ick = {
2067         .name           = "des1_ick",
2068         .parent         = &security_l4_ick2,
2069         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2070         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2071         .flags          = CLOCK_IN_OMAP343X,
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 /* DSS */
2076 static const struct clksel dss1_alwon_fck_clksel[] = {
2077         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2078         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2079         { .parent = NULL }
2080 };
2081
2082 static struct clk dss1_alwon_fck = {
2083         .name           = "dss1_alwon_fck",
2084         .parent         = &dpll4_m4x2_ck,
2085         .init           = &omap2_init_clksel_parent,
2086         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2087         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2088         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2089         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2090         .clksel         = dss1_alwon_fck_clksel,
2091         .flags          = CLOCK_IN_OMAP343X,
2092         .clkdm_name     = "dss_clkdm",
2093         .recalc         = &omap2_clksel_recalc,
2094 };
2095
2096 static struct clk dss_tv_fck = {
2097         .name           = "dss_tv_fck",
2098         .parent         = &omap_54m_fck,
2099         .init           = &omap2_init_clk_clkdm,
2100         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2101         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2102         .flags          = CLOCK_IN_OMAP343X,
2103         .clkdm_name     = "dss_clkdm",
2104         .recalc         = &followparent_recalc,
2105 };
2106
2107 static struct clk dss_96m_fck = {
2108         .name           = "dss_96m_fck",
2109         .parent         = &omap_96m_fck,
2110         .init           = &omap2_init_clk_clkdm,
2111         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2112         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2113         .flags          = CLOCK_IN_OMAP343X,
2114         .clkdm_name     = "dss_clkdm",
2115         .recalc         = &followparent_recalc,
2116 };
2117
2118 static struct clk dss2_alwon_fck = {
2119         .name           = "dss2_alwon_fck",
2120         .parent         = &sys_ck,
2121         .init           = &omap2_init_clk_clkdm,
2122         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2123         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2124         .flags          = CLOCK_IN_OMAP343X,
2125         .clkdm_name     = "dss_clkdm",
2126         .recalc         = &followparent_recalc,
2127 };
2128
2129 static struct clk dss_ick = {
2130         /* Handles both L3 and L4 clocks */
2131         .name           = "dss_ick",
2132         .parent         = &l4_ick,
2133         .init           = &omap2_init_clk_clkdm,
2134         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2135         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2136         .flags          = CLOCK_IN_OMAP343X,
2137         .clkdm_name     = "dss_clkdm",
2138         .recalc         = &followparent_recalc,
2139 };
2140
2141 /* CAM */
2142
2143 static const struct clksel cam_mclk_clksel[] = {
2144         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2145         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2146         { .parent = NULL }
2147 };
2148
2149 static struct clk cam_mclk = {
2150         .name           = "cam_mclk",
2151         .parent         = &dpll4_m5x2_ck,
2152         .init           = &omap2_init_clksel_parent,
2153         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2154         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2155         .clksel         = cam_mclk_clksel,
2156         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2157         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2158         .flags          = CLOCK_IN_OMAP343X,
2159         .clkdm_name     = "cam_clkdm",
2160         .recalc         = &omap2_clksel_recalc,
2161 };
2162
2163 static struct clk cam_l3_ick = {
2164         .name           = "cam_l3_ick",
2165         .parent         = &l3_ick,
2166         .init           = &omap2_init_clk_clkdm,
2167         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2168         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2169         .flags          = CLOCK_IN_OMAP343X,
2170         .clkdm_name     = "cam_clkdm",
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk cam_l4_ick = {
2175         .name           = "cam_l4_ick",
2176         .parent         = &l4_ick,
2177         .init           = &omap2_init_clk_clkdm,
2178         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2179         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2180         .flags          = CLOCK_IN_OMAP343X,
2181         .clkdm_name     = "cam_clkdm",
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 /* USBHOST - 3430ES2 only */
2186
2187 static struct clk usbhost_120m_fck = {
2188         .name           = "usbhost_120m_fck",
2189         .parent         = &omap_120m_fck,
2190         .init           = &omap2_init_clk_clkdm,
2191         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2192         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2193         .flags          = CLOCK_IN_OMAP3430ES2,
2194         .clkdm_name     = "usbhost_clkdm",
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk usbhost_48m_fck = {
2199         .name           = "usbhost_48m_fck",
2200         .parent         = &omap_48m_fck,
2201         .init           = &omap2_init_clk_clkdm,
2202         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2203         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2204         .flags          = CLOCK_IN_OMAP3430ES2,
2205         .clkdm_name     = "usbhost_clkdm",
2206         .recalc         = &followparent_recalc,
2207 };
2208
2209 static struct clk usbhost_l3_ick = {
2210         .name           = "usbhost_l3_ick",
2211         .parent         = &l3_ick,
2212         .init           = &omap2_init_clk_clkdm,
2213         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2214         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2215         .flags          = CLOCK_IN_OMAP3430ES2,
2216         .clkdm_name     = "usbhost_clkdm",
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 static struct clk usbhost_l4_ick = {
2221         .name           = "usbhost_l4_ick",
2222         .parent         = &l4_ick,
2223         .init           = &omap2_init_clk_clkdm,
2224         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2225         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2226         .flags          = CLOCK_IN_OMAP3430ES2,
2227         .clkdm_name     = "usbhost_clkdm",
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 static struct clk usbhost_sar_fck = {
2232         .name           = "usbhost_sar_fck",
2233         .parent         = &osc_sys_ck,
2234         .init           = &omap2_init_clk_clkdm,
2235         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2236         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2237         .flags          = CLOCK_IN_OMAP3430ES2,
2238         .clkdm_name     = "usbhost_clkdm",
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 /* WKUP */
2243
2244 static const struct clksel_rate usim_96m_rates[] = {
2245         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2246         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2247         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2248         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2249         { .div = 0 },
2250 };
2251
2252 static const struct clksel_rate usim_120m_rates[] = {
2253         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2254         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2255         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2256         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2257         { .div = 0 },
2258 };
2259
2260 static const struct clksel usim_clksel[] = {
2261         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2262         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2263         { .parent = &sys_ck,            .rates = div2_rates },
2264         { .parent = NULL },
2265 };
2266
2267 /* 3430ES2 only */
2268 static struct clk usim_fck = {
2269         .name           = "usim_fck",
2270         .init           = &omap2_init_clksel_parent,
2271         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2272         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2273         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2274         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2275         .clksel         = usim_clksel,
2276         .flags          = CLOCK_IN_OMAP3430ES2,
2277         .recalc         = &omap2_clksel_recalc,
2278 };
2279
2280 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2281 static struct clk gpt1_fck = {
2282         .name           = "gpt1_fck",
2283         .init           = &omap2_init_clksel_parent,
2284         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2285         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2286         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2287         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2288         .clksel         = omap343x_gpt_clksel,
2289         .flags          = CLOCK_IN_OMAP343X,
2290         .clkdm_name     = "wkup_clkdm",
2291         .recalc         = &omap2_clksel_recalc,
2292 };
2293
2294 static struct clk wkup_32k_fck = {
2295         .name           = "wkup_32k_fck",
2296         .init           = &omap2_init_clk_clkdm,
2297         .parent         = &omap_32k_fck,
2298         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2299         .clkdm_name     = "wkup_clkdm",
2300         .recalc         = &followparent_recalc,
2301 };
2302
2303 static struct clk gpio1_fck = {
2304         .name           = "gpio1_fck",
2305         .parent         = &wkup_32k_fck,
2306         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2307         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2308         .flags          = CLOCK_IN_OMAP343X,
2309         .clkdm_name     = "wkup_clkdm",
2310         .recalc         = &followparent_recalc,
2311 };
2312
2313 static struct clk wdt2_fck = {
2314         .name           = "wdt2_fck",
2315         .parent         = &wkup_32k_fck,
2316         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2317         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2318         .flags          = CLOCK_IN_OMAP343X,
2319         .clkdm_name     = "wkup_clkdm",
2320         .recalc         = &followparent_recalc,
2321 };
2322
2323 static struct clk wkup_l4_ick = {
2324         .name           = "wkup_l4_ick",
2325         .parent         = &sys_ck,
2326         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2327         .clkdm_name     = "wkup_clkdm",
2328         .recalc         = &followparent_recalc,
2329 };
2330
2331 /* 3430ES2 only */
2332 /* Never specifically named in the TRM, so we have to infer a likely name */
2333 static struct clk usim_ick = {
2334         .name           = "usim_ick",
2335         .parent         = &wkup_l4_ick,
2336         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2337         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2338         .flags          = CLOCK_IN_OMAP3430ES2,
2339         .clkdm_name     = "wkup_clkdm",
2340         .recalc         = &followparent_recalc,
2341 };
2342
2343 static struct clk wdt2_ick = {
2344         .name           = "wdt2_ick",
2345         .parent         = &wkup_l4_ick,
2346         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2347         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2348         .flags          = CLOCK_IN_OMAP343X,
2349         .clkdm_name     = "wkup_clkdm",
2350         .recalc         = &followparent_recalc,
2351 };
2352
2353 static struct clk wdt1_ick = {
2354         .name           = "wdt1_ick",
2355         .parent         = &wkup_l4_ick,
2356         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2357         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2358         .flags          = CLOCK_IN_OMAP343X,
2359         .clkdm_name     = "wkup_clkdm",
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 static struct clk gpio1_ick = {
2364         .name           = "gpio1_ick",
2365         .parent         = &wkup_l4_ick,
2366         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2367         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2368         .flags          = CLOCK_IN_OMAP343X,
2369         .clkdm_name     = "wkup_clkdm",
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk omap_32ksync_ick = {
2374         .name           = "omap_32ksync_ick",
2375         .parent         = &wkup_l4_ick,
2376         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2377         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2378         .flags          = CLOCK_IN_OMAP343X,
2379         .clkdm_name     = "wkup_clkdm",
2380         .recalc         = &followparent_recalc,
2381 };
2382
2383 /* XXX This clock no longer exists in 3430 TRM rev F */
2384 static struct clk gpt12_ick = {
2385         .name           = "gpt12_ick",
2386         .parent         = &wkup_l4_ick,
2387         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2388         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2389         .flags          = CLOCK_IN_OMAP343X,
2390         .clkdm_name     = "wkup_clkdm",
2391         .recalc         = &followparent_recalc,
2392 };
2393
2394 static struct clk gpt1_ick = {
2395         .name           = "gpt1_ick",
2396         .parent         = &wkup_l4_ick,
2397         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2398         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2399         .flags          = CLOCK_IN_OMAP343X,
2400         .clkdm_name     = "wkup_clkdm",
2401         .recalc         = &followparent_recalc,
2402 };
2403
2404
2405
2406 /* PER clock domain */
2407
2408 static struct clk per_96m_fck = {
2409         .name           = "per_96m_fck",
2410         .parent         = &omap_96m_alwon_fck,
2411         .init           = &omap2_init_clk_clkdm,
2412         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2413                                 PARENT_CONTROLS_CLOCK,
2414         .clkdm_name     = "per_clkdm",
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk per_48m_fck = {
2419         .name           = "per_48m_fck",
2420         .parent         = &omap_48m_fck,
2421         .init           = &omap2_init_clk_clkdm,
2422         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2423                                 PARENT_CONTROLS_CLOCK,
2424         .clkdm_name     = "per_clkdm",
2425         .recalc         = &followparent_recalc,
2426 };
2427
2428 static struct clk uart3_fck = {
2429         .name           = "uart3_fck",
2430         .parent         = &per_48m_fck,
2431         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2432         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2433         .flags          = CLOCK_IN_OMAP343X,
2434         .clkdm_name     = "per_clkdm",
2435         .recalc         = &followparent_recalc,
2436 };
2437
2438 static struct clk gpt2_fck = {
2439         .name           = "gpt2_fck",
2440         .init           = &omap2_init_clksel_parent,
2441         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2442         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2443         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2444         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2445         .clksel         = omap343x_gpt_clksel,
2446         .flags          = CLOCK_IN_OMAP343X,
2447         .clkdm_name     = "per_clkdm",
2448         .recalc         = &omap2_clksel_recalc,
2449 };
2450
2451 static struct clk gpt3_fck = {
2452         .name           = "gpt3_fck",
2453         .init           = &omap2_init_clksel_parent,
2454         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2455         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2456         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2457         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2458         .clksel         = omap343x_gpt_clksel,
2459         .flags          = CLOCK_IN_OMAP343X,
2460         .clkdm_name     = "per_clkdm",
2461         .recalc         = &omap2_clksel_recalc,
2462 };
2463
2464 static struct clk gpt4_fck = {
2465         .name           = "gpt4_fck",
2466         .init           = &omap2_init_clksel_parent,
2467         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2469         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2470         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2471         .clksel         = omap343x_gpt_clksel,
2472         .flags          = CLOCK_IN_OMAP343X,
2473         .clkdm_name     = "per_clkdm",
2474         .recalc         = &omap2_clksel_recalc,
2475 };
2476
2477 static struct clk gpt5_fck = {
2478         .name           = "gpt5_fck",
2479         .init           = &omap2_init_clksel_parent,
2480         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2481         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2482         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2483         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2484         .clksel         = omap343x_gpt_clksel,
2485         .flags          = CLOCK_IN_OMAP343X,
2486         .clkdm_name     = "per_clkdm",
2487         .recalc         = &omap2_clksel_recalc,
2488 };
2489
2490 static struct clk gpt6_fck = {
2491         .name           = "gpt6_fck",
2492         .init           = &omap2_init_clksel_parent,
2493         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2494         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2495         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2496         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2497         .clksel         = omap343x_gpt_clksel,
2498         .flags          = CLOCK_IN_OMAP343X,
2499         .clkdm_name     = "per_clkdm",
2500         .recalc         = &omap2_clksel_recalc,
2501 };
2502
2503 static struct clk gpt7_fck = {
2504         .name           = "gpt7_fck",
2505         .init           = &omap2_init_clksel_parent,
2506         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2507         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2508         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2509         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2510         .clksel         = omap343x_gpt_clksel,
2511         .flags          = CLOCK_IN_OMAP343X,
2512         .clkdm_name     = "per_clkdm",
2513         .recalc         = &omap2_clksel_recalc,
2514 };
2515
2516 static struct clk gpt8_fck = {
2517         .name           = "gpt8_fck",
2518         .init           = &omap2_init_clksel_parent,
2519         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2520         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2521         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2522         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2523         .clksel         = omap343x_gpt_clksel,
2524         .flags          = CLOCK_IN_OMAP343X,
2525         .clkdm_name     = "per_clkdm",
2526         .recalc         = &omap2_clksel_recalc,
2527 };
2528
2529 static struct clk gpt9_fck = {
2530         .name           = "gpt9_fck",
2531         .init           = &omap2_init_clksel_parent,
2532         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2533         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2534         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2535         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2536         .clksel         = omap343x_gpt_clksel,
2537         .flags          = CLOCK_IN_OMAP343X,
2538         .clkdm_name     = "per_clkdm",
2539         .recalc         = &omap2_clksel_recalc,
2540 };
2541
2542 static struct clk per_32k_alwon_fck = {
2543         .name           = "per_32k_alwon_fck",
2544         .parent         = &omap_32k_fck,
2545         .clkdm_name     = "per_clkdm",
2546         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2547         .recalc         = &followparent_recalc,
2548 };
2549
2550 static struct clk gpio6_fck = {
2551         .name           = "gpio6_fck",
2552         .parent         = &per_32k_alwon_fck,
2553         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2554         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2555         .flags          = CLOCK_IN_OMAP343X,
2556         .clkdm_name     = "per_clkdm",
2557         .recalc         = &followparent_recalc,
2558 };
2559
2560 static struct clk gpio5_fck = {
2561         .name           = "gpio5_fck",
2562         .parent         = &per_32k_alwon_fck,
2563         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2565         .flags          = CLOCK_IN_OMAP343X,
2566         .clkdm_name     = "per_clkdm",
2567         .recalc         = &followparent_recalc,
2568 };
2569
2570 static struct clk gpio4_fck = {
2571         .name           = "gpio4_fck",
2572         .parent         = &per_32k_alwon_fck,
2573         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2574         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2575         .flags          = CLOCK_IN_OMAP343X,
2576         .clkdm_name     = "per_clkdm",
2577         .recalc         = &followparent_recalc,
2578 };
2579
2580 static struct clk gpio3_fck = {
2581         .name           = "gpio3_fck",
2582         .parent         = &per_32k_alwon_fck,
2583         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2584         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2585         .flags          = CLOCK_IN_OMAP343X,
2586         .clkdm_name     = "per_clkdm",
2587         .recalc         = &followparent_recalc,
2588 };
2589
2590 static struct clk gpio2_fck = {
2591         .name           = "gpio2_fck",
2592         .parent         = &per_32k_alwon_fck,
2593         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2594         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2595         .flags          = CLOCK_IN_OMAP343X,
2596         .clkdm_name     = "per_clkdm",
2597         .recalc         = &followparent_recalc,
2598 };
2599
2600 static struct clk wdt3_fck = {
2601         .name           = "wdt3_fck",
2602         .parent         = &per_32k_alwon_fck,
2603         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2604         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2605         .flags          = CLOCK_IN_OMAP343X,
2606         .clkdm_name     = "per_clkdm",
2607         .recalc         = &followparent_recalc,
2608 };
2609
2610 static struct clk per_l4_ick = {
2611         .name           = "per_l4_ick",
2612         .parent         = &l4_ick,
2613         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2614                                 PARENT_CONTROLS_CLOCK,
2615         .clkdm_name     = "per_clkdm",
2616         .recalc         = &followparent_recalc,
2617 };
2618
2619 static struct clk gpio6_ick = {
2620         .name           = "gpio6_ick",
2621         .parent         = &per_l4_ick,
2622         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2623         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2624         .flags          = CLOCK_IN_OMAP343X,
2625         .clkdm_name     = "per_clkdm",
2626         .recalc         = &followparent_recalc,
2627 };
2628
2629 static struct clk gpio5_ick = {
2630         .name           = "gpio5_ick",
2631         .parent         = &per_l4_ick,
2632         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2633         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2634         .flags          = CLOCK_IN_OMAP343X,
2635         .clkdm_name     = "per_clkdm",
2636         .recalc         = &followparent_recalc,
2637 };
2638
2639 static struct clk gpio4_ick = {
2640         .name           = "gpio4_ick",
2641         .parent         = &per_l4_ick,
2642         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2643         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2644         .flags          = CLOCK_IN_OMAP343X,
2645         .clkdm_name     = "per_clkdm",
2646         .recalc         = &followparent_recalc,
2647 };
2648
2649 static struct clk gpio3_ick = {
2650         .name           = "gpio3_ick",
2651         .parent         = &per_l4_ick,
2652         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2653         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2654         .flags          = CLOCK_IN_OMAP343X,
2655         .clkdm_name     = "per_clkdm",
2656         .recalc         = &followparent_recalc,
2657 };
2658
2659 static struct clk gpio2_ick = {
2660         .name           = "gpio2_ick",
2661         .parent         = &per_l4_ick,
2662         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2663         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2664         .flags          = CLOCK_IN_OMAP343X,
2665         .clkdm_name     = "per_clkdm",
2666         .recalc         = &followparent_recalc,
2667 };
2668
2669 static struct clk wdt3_ick = {
2670         .name           = "wdt3_ick",
2671         .parent         = &per_l4_ick,
2672         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2673         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2674         .flags          = CLOCK_IN_OMAP343X,
2675         .clkdm_name     = "per_clkdm",
2676         .recalc         = &followparent_recalc,
2677 };
2678
2679 static struct clk uart3_ick = {
2680         .name           = "uart3_ick",
2681         .parent         = &per_l4_ick,
2682         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2683         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2684         .flags          = CLOCK_IN_OMAP343X,
2685         .clkdm_name     = "per_clkdm",
2686         .recalc         = &followparent_recalc,
2687 };
2688
2689 static struct clk gpt9_ick = {
2690         .name           = "gpt9_ick",
2691         .parent         = &per_l4_ick,
2692         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2693         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2694         .flags          = CLOCK_IN_OMAP343X,
2695         .clkdm_name     = "per_clkdm",
2696         .recalc         = &followparent_recalc,
2697 };
2698
2699 static struct clk gpt8_ick = {
2700         .name           = "gpt8_ick",
2701         .parent         = &per_l4_ick,
2702         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2703         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2704         .flags          = CLOCK_IN_OMAP343X,
2705         .clkdm_name     = "per_clkdm",
2706         .recalc         = &followparent_recalc,
2707 };
2708
2709 static struct clk gpt7_ick = {
2710         .name           = "gpt7_ick",
2711         .parent         = &per_l4_ick,
2712         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2713         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2714         .flags          = CLOCK_IN_OMAP343X,
2715         .clkdm_name     = "per_clkdm",
2716         .recalc         = &followparent_recalc,
2717 };
2718
2719 static struct clk gpt6_ick = {
2720         .name           = "gpt6_ick",
2721         .parent         = &per_l4_ick,
2722         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2723         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2724         .flags          = CLOCK_IN_OMAP343X,
2725         .clkdm_name     = "per_clkdm",
2726         .recalc         = &followparent_recalc,
2727 };
2728
2729 static struct clk gpt5_ick = {
2730         .name           = "gpt5_ick",
2731         .parent         = &per_l4_ick,
2732         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2733         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2734         .flags          = CLOCK_IN_OMAP343X,
2735         .clkdm_name     = "per_clkdm",
2736         .recalc         = &followparent_recalc,
2737 };
2738
2739 static struct clk gpt4_ick = {
2740         .name           = "gpt4_ick",
2741         .parent         = &per_l4_ick,
2742         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2743         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2744         .flags          = CLOCK_IN_OMAP343X,
2745         .clkdm_name     = "per_clkdm",
2746         .recalc         = &followparent_recalc,
2747 };
2748
2749 static struct clk gpt3_ick = {
2750         .name           = "gpt3_ick",
2751         .parent         = &per_l4_ick,
2752         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2753         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2754         .flags          = CLOCK_IN_OMAP343X,
2755         .clkdm_name     = "per_clkdm",
2756         .recalc         = &followparent_recalc,
2757 };
2758
2759 static struct clk gpt2_ick = {
2760         .name           = "gpt2_ick",
2761         .parent         = &per_l4_ick,
2762         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2763         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2764         .flags          = CLOCK_IN_OMAP343X,
2765         .clkdm_name     = "per_clkdm",
2766         .recalc         = &followparent_recalc,
2767 };
2768
2769 static struct clk mcbsp2_ick = {
2770         .name           = "mcbsp2_ick",
2771         .parent         = &per_l4_ick,
2772         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2773         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2774         .flags          = CLOCK_IN_OMAP343X,
2775         .clkdm_name     = "per_clkdm",
2776         .recalc         = &followparent_recalc,
2777 };
2778
2779 static struct clk mcbsp3_ick = {
2780         .name           = "mcbsp3_ick",
2781         .parent         = &per_l4_ick,
2782         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2783         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2784         .flags          = CLOCK_IN_OMAP343X,
2785         .clkdm_name     = "per_clkdm",
2786         .recalc         = &followparent_recalc,
2787 };
2788
2789 static struct clk mcbsp4_ick = {
2790         .name           = "mcbsp4_ick",
2791         .parent         = &per_l4_ick,
2792         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2793         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2794         .flags          = CLOCK_IN_OMAP343X,
2795         .clkdm_name     = "per_clkdm",
2796         .recalc         = &followparent_recalc,
2797 };
2798
2799 static const struct clksel mcbsp_234_clksel[] = {
2800         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2801         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2802         { .parent = NULL }
2803 };
2804
2805 static struct clk mcbsp2_fck = {
2806         .name           = "mcbsp2_fck",
2807         .init           = &omap2_init_clksel_parent,
2808         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2809         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2810         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2811         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2812         .clksel         = mcbsp_234_clksel,
2813         .flags          = CLOCK_IN_OMAP343X,
2814         .clkdm_name     = "per_clkdm",
2815         .recalc         = &omap2_clksel_recalc,
2816 };
2817
2818 static struct clk mcbsp3_fck = {
2819         .name           = "mcbsp3_fck",
2820         .init           = &omap2_init_clksel_parent,
2821         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2822         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2823         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2824         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2825         .clksel         = mcbsp_234_clksel,
2826         .flags          = CLOCK_IN_OMAP343X,
2827         .clkdm_name     = "per_clkdm",
2828         .recalc         = &omap2_clksel_recalc,
2829 };
2830
2831 static struct clk mcbsp4_fck = {
2832         .name           = "mcbsp4_fck",
2833         .init           = &omap2_init_clksel_parent,
2834         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2835         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2836         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2837         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2838         .clksel         = mcbsp_234_clksel,
2839         .flags          = CLOCK_IN_OMAP343X,
2840         .clkdm_name     = "per_clkdm",
2841         .recalc         = &omap2_clksel_recalc,
2842 };
2843
2844 /* EMU clocks */
2845
2846 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2847
2848 static const struct clksel_rate emu_src_sys_rates[] = {
2849         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2850         { .div = 0 },
2851 };
2852
2853 static const struct clksel_rate emu_src_core_rates[] = {
2854         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2855         { .div = 0 },
2856 };
2857
2858 static const struct clksel_rate emu_src_per_rates[] = {
2859         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2860         { .div = 0 },
2861 };
2862
2863 static const struct clksel_rate emu_src_mpu_rates[] = {
2864         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2865         { .div = 0 },
2866 };
2867
2868 static const struct clksel emu_src_clksel[] = {
2869         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2870         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2871         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2872         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2873         { .parent = NULL },
2874 };
2875
2876 /*
2877  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2878  * to switch the source of some of the EMU clocks.
2879  * XXX Are there CLKEN bits for these EMU clks?
2880  */
2881 static struct clk emu_src_ck = {
2882         .name           = "emu_src_ck",
2883         .init           = &omap2_init_clksel_parent,
2884         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2885         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2886         .clksel         = emu_src_clksel,
2887         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2888         .clkdm_name     = "emu_clkdm",
2889         .recalc         = &omap2_clksel_recalc,
2890 };
2891
2892 static const struct clksel_rate pclk_emu_rates[] = {
2893         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2894         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2895         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2896         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2897         { .div = 0 },
2898 };
2899
2900 static const struct clksel pclk_emu_clksel[] = {
2901         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2902         { .parent = NULL },
2903 };
2904
2905 static struct clk pclk_fck = {
2906         .name           = "pclk_fck",
2907         .init           = &omap2_init_clksel_parent,
2908         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2909         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2910         .clksel         = pclk_emu_clksel,
2911         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2912         .clkdm_name     = "emu_clkdm",
2913         .recalc         = &omap2_clksel_recalc,
2914 };
2915
2916 static const struct clksel_rate pclkx2_emu_rates[] = {
2917         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2918         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2919         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2920         { .div = 0 },
2921 };
2922
2923 static const struct clksel pclkx2_emu_clksel[] = {
2924         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2925         { .parent = NULL },
2926 };
2927
2928 static struct clk pclkx2_fck = {
2929         .name           = "pclkx2_fck",
2930         .init           = &omap2_init_clksel_parent,
2931         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2932         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2933         .clksel         = pclkx2_emu_clksel,
2934         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2935         .clkdm_name     = "emu_clkdm",
2936         .recalc         = &omap2_clksel_recalc,
2937 };
2938
2939 static const struct clksel atclk_emu_clksel[] = {
2940         { .parent = &emu_src_ck, .rates = div2_rates },
2941         { .parent = NULL },
2942 };
2943
2944 static struct clk atclk_fck = {
2945         .name           = "atclk_fck",
2946         .init           = &omap2_init_clksel_parent,
2947         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2948         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2949         .clksel         = atclk_emu_clksel,
2950         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2951         .clkdm_name     = "emu_clkdm",
2952         .recalc         = &omap2_clksel_recalc,
2953 };
2954
2955 static struct clk traceclk_src_fck = {
2956         .name           = "traceclk_src_fck",
2957         .init           = &omap2_init_clksel_parent,
2958         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2959         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2960         .clksel         = emu_src_clksel,
2961         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2962         .clkdm_name     = "emu_clkdm",
2963         .recalc         = &omap2_clksel_recalc,
2964 };
2965
2966 static const struct clksel_rate traceclk_rates[] = {
2967         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2968         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2969         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2970         { .div = 0 },
2971 };
2972
2973 static const struct clksel traceclk_clksel[] = {
2974         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2975         { .parent = NULL },
2976 };
2977
2978 static struct clk traceclk_fck = {
2979         .name           = "traceclk_fck",
2980         .init           = &omap2_init_clksel_parent,
2981         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2982         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2983         .clksel         = traceclk_clksel,
2984         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2985         .clkdm_name     = "emu_clkdm",
2986         .recalc         = &omap2_clksel_recalc,
2987 };
2988
2989 /* SR clocks */
2990
2991 /* SmartReflex fclk (VDD1) */
2992 static struct clk sr1_fck = {
2993         .name           = "sr1_fck",
2994         .parent         = &sys_ck,
2995         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2996         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2997         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2998         .recalc         = &followparent_recalc,
2999 };
3000
3001 /* SmartReflex fclk (VDD2) */
3002 static struct clk sr2_fck = {
3003         .name           = "sr2_fck",
3004         .parent         = &sys_ck,
3005         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3006         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3007         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3008         .recalc         = &followparent_recalc,
3009 };
3010
3011 static struct clk sr_l4_ick = {
3012         .name           = "sr_l4_ick",
3013         .parent         = &l4_ick,
3014         .flags          = CLOCK_IN_OMAP343X,
3015         .clkdm_name     = "core_l4_clkdm",
3016         .recalc         = &followparent_recalc,
3017 };
3018
3019 /* SECURE_32K_FCK clocks */
3020
3021 /* XXX This clock no longer exists in 3430 TRM rev F */
3022 static struct clk gpt12_fck = {
3023         .name           = "gpt12_fck",
3024         .parent         = &secure_32k_fck,
3025         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3026         .recalc         = &followparent_recalc,
3027 };
3028
3029 static struct clk wdt1_fck = {
3030         .name           = "wdt1_fck",
3031         .parent         = &secure_32k_fck,
3032         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3033         .recalc         = &followparent_recalc,
3034 };
3035
3036 static struct clk *onchip_34xx_clks[] __initdata = {
3037         &omap_32k_fck,
3038         &virt_12m_ck,
3039         &virt_13m_ck,
3040         &virt_16_8m_ck,
3041         &virt_19_2m_ck,
3042         &virt_26m_ck,
3043         &virt_38_4m_ck,
3044         &osc_sys_ck,
3045         &sys_ck,
3046         &sys_altclk,
3047         &mcbsp_clks,
3048         &sys_clkout1,
3049         &dpll1_ck,
3050         &dpll1_x2_ck,
3051         &dpll1_x2m2_ck,
3052         &dpll2_ck,
3053         &dpll2_m2_ck,
3054         &dpll3_ck,
3055         &core_ck,
3056         &dpll3_x2_ck,
3057         &dpll3_m2_ck,
3058         &dpll3_m2x2_ck,
3059         &dpll3_m3_ck,
3060         &dpll3_m3x2_ck,
3061         &emu_core_alwon_ck,
3062         &dpll4_ck,
3063         &dpll4_x2_ck,
3064         &omap_96m_alwon_fck,
3065         &omap_96m_fck,
3066         &cm_96m_fck,
3067         &virt_omap_54m_fck,
3068         &omap_54m_fck,
3069         &omap_48m_fck,
3070         &omap_12m_fck,
3071         &dpll4_m2_ck,
3072         &dpll4_m2x2_ck,
3073         &dpll4_m3_ck,
3074         &dpll4_m3x2_ck,
3075         &dpll4_m4_ck,
3076         &dpll4_m4x2_ck,
3077         &dpll4_m5_ck,
3078         &dpll4_m5x2_ck,
3079         &dpll4_m6_ck,
3080         &dpll4_m6x2_ck,
3081         &emu_per_alwon_ck,
3082         &dpll5_ck,
3083         &dpll5_m2_ck,
3084         &omap_120m_fck,
3085         &clkout2_src_ck,
3086         &sys_clkout2,
3087         &corex2_fck,
3088         &dpll1_fck,
3089         &mpu_ck,
3090         &arm_fck,
3091         &emu_mpu_alwon_ck,
3092         &dpll2_fck,
3093         &iva2_ck,
3094         &l3_ick,
3095         &l4_ick,
3096         &rm_ick,
3097         &gfx_l3_fck,
3098         &gfx_l3_ick,
3099         &gfx_cg1_ck,
3100         &gfx_cg2_ck,
3101         &sgx_fck,
3102         &sgx_ick,
3103         &d2d_26m_fck,
3104         &gpt10_fck,
3105         &gpt11_fck,
3106         &cpefuse_fck,
3107         &ts_fck,
3108         &usbtll_fck,
3109         &core_96m_fck,
3110         &mmchs3_fck,
3111         &mmchs2_fck,
3112         &mspro_fck,
3113         &mmchs1_fck,
3114         &i2c3_fck,
3115         &i2c2_fck,
3116         &i2c1_fck,
3117         &mcbsp5_fck,
3118         &mcbsp1_fck,
3119         &core_48m_fck,
3120         &mcspi4_fck,
3121         &mcspi3_fck,
3122         &mcspi2_fck,
3123         &mcspi1_fck,
3124         &uart2_fck,
3125         &uart1_fck,
3126         &fshostusb_fck,
3127         &core_12m_fck,
3128         &hdq_fck,
3129         &ssi_ssr_fck,
3130         &ssi_sst_fck,
3131         &core_l3_ick,
3132         &hsotgusb_ick,
3133         &sdrc_ick,
3134         &gpmc_fck,
3135         &security_l3_ick,
3136         &pka_ick,
3137         &core_l4_ick,
3138         &usbtll_ick,
3139         &mmchs3_ick,
3140         &icr_ick,
3141         &aes2_ick,
3142         &sha12_ick,
3143         &des2_ick,
3144         &mmchs2_ick,
3145         &mmchs1_ick,
3146         &mspro_ick,
3147         &hdq_ick,
3148         &mcspi4_ick,
3149         &mcspi3_ick,
3150         &mcspi2_ick,
3151         &mcspi1_ick,
3152         &i2c3_ick,
3153         &i2c2_ick,
3154         &i2c1_ick,
3155         &uart2_ick,
3156         &uart1_ick,
3157         &gpt11_ick,
3158         &gpt10_ick,
3159         &mcbsp5_ick,
3160         &mcbsp1_ick,
3161         &fac_ick,
3162         &mailboxes_ick,
3163         &omapctrl_ick,
3164         &ssi_l4_ick,
3165         &ssi_ick,
3166         &usb_l4_ick,
3167         &security_l4_ick2,
3168         &aes1_ick,
3169         &rng_ick,
3170         &sha11_ick,
3171         &des1_ick,
3172         &dss1_alwon_fck,
3173         &dss_tv_fck,
3174         &dss_96m_fck,
3175         &dss2_alwon_fck,
3176         &dss_ick,
3177         &cam_mclk,
3178         &cam_l3_ick,
3179         &cam_l4_ick,
3180         &usbhost_120m_fck,
3181         &usbhost_48m_fck,
3182         &usbhost_l3_ick,
3183         &usbhost_l4_ick,
3184         &usbhost_sar_fck,
3185         &usim_fck,
3186         &gpt1_fck,
3187         &wkup_32k_fck,
3188         &gpio1_fck,
3189         &wdt2_fck,
3190         &wkup_l4_ick,
3191         &usim_ick,
3192         &wdt2_ick,
3193         &wdt1_ick,
3194         &gpio1_ick,
3195         &omap_32ksync_ick,
3196         &gpt12_ick,
3197         &gpt1_ick,
3198         &per_96m_fck,
3199         &per_48m_fck,
3200         &uart3_fck,
3201         &gpt2_fck,
3202         &gpt3_fck,
3203         &gpt4_fck,
3204         &gpt5_fck,
3205         &gpt6_fck,
3206         &gpt7_fck,
3207         &gpt8_fck,
3208         &gpt9_fck,
3209         &per_32k_alwon_fck,
3210         &gpio6_fck,
3211         &gpio5_fck,
3212         &gpio4_fck,
3213         &gpio3_fck,
3214         &gpio2_fck,
3215         &wdt3_fck,
3216         &per_l4_ick,
3217         &gpio6_ick,
3218         &gpio5_ick,
3219         &gpio4_ick,
3220         &gpio3_ick,
3221         &gpio2_ick,
3222         &wdt3_ick,
3223         &uart3_ick,
3224         &gpt9_ick,
3225         &gpt8_ick,
3226         &gpt7_ick,
3227         &gpt6_ick,
3228         &gpt5_ick,
3229         &gpt4_ick,
3230         &gpt3_ick,
3231         &gpt2_ick,
3232         &mcbsp2_ick,
3233         &mcbsp3_ick,
3234         &mcbsp4_ick,
3235         &mcbsp2_fck,
3236         &mcbsp3_fck,
3237         &mcbsp4_fck,
3238         &emu_src_ck,
3239         &pclk_fck,
3240         &pclkx2_fck,
3241         &atclk_fck,
3242         &traceclk_src_fck,
3243         &traceclk_fck,
3244         &sr1_fck,
3245         &sr2_fck,
3246         &sr_l4_ick,
3247         &secure_32k_fck,
3248         &gpt12_fck,
3249         &wdt1_fck,
3250 };
3251
3252 #endif