arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <asm/arch/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  52 #define DPLL_LOW_POWER_STOP             0x1
  53 #define DPLL_LOW_POWER_BYPASS           0x5
  54 #define DPLL_LOCKED                     0x7
  55
  56 /* PRM CLOCKS */
  57
  58 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  59 static struct clk omap_32k_fck = {
  60         .name           = "omap_32k_fck",
  61         .rate           = 32768,
  62         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  63                                 ALWAYS_ENABLED,
  64         .recalc         = &propagate_rate,
  65 };
  66
  67 static struct clk secure_32k_fck = {
  68         .name           = "secure_32k_fck",
  69         .rate           = 32768,
  70         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  71                                 ALWAYS_ENABLED,
  72         .recalc         = &propagate_rate,
  73 };
  74
  75 /* Virtual source clocks for osc_sys_ck */
  76 static struct clk virt_12m_ck = {
  77         .name           = "virt_12m_ck",
  78         .rate           = 12000000,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .recalc         = &propagate_rate,
  82 };
  83
  84 static struct clk virt_13m_ck = {
  85         .name           = "virt_13m_ck",
  86         .rate           = 13000000,
  87         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  88                                 ALWAYS_ENABLED,
  89         .recalc         = &propagate_rate,
  90 };
  91
  92 static struct clk virt_16_8m_ck = {
  93         .name           = "virt_16_8m_ck",
  94         .rate           = 16800000,
  95         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  96                                 ALWAYS_ENABLED,
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_19_2m_ck = {
 101         .name           = "virt_19_2m_ck",
 102         .rate           = 19200000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .recalc         = &propagate_rate,
 106 };
 107
 108 static struct clk virt_26m_ck = {
 109         .name           = "virt_26m_ck",
 110         .rate           = 26000000,
 111         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 112                                 ALWAYS_ENABLED,
 113         .recalc         = &propagate_rate,
 114 };
 115
 116 static struct clk virt_38_4m_ck = {
 117         .name           = "virt_38_4m_ck",
 118         .rate           = 38400000,
 119         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 120                                 ALWAYS_ENABLED,
 121         .recalc         = &propagate_rate,
 122 };
 123
 124 static const struct clksel_rate osc_sys_12m_rates[] = {
 125         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 126         { .div = 0 }
 127 };
 128
 129 static const struct clksel_rate osc_sys_13m_rates[] = {
 130         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 131         { .div = 0 }
 132 };
 133
 134 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 135         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 136         { .div = 0 }
 137 };
 138
 139 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 141         { .div = 0 }
 142 };
 143
 144 static const struct clksel_rate osc_sys_26m_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 146         { .div = 0 }
 147 };
 148
 149 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 151         { .div = 0 }
 152 };
 153
 154 static const struct clksel osc_sys_clksel[] = {
 155         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 156         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 157         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 158         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 159         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 160         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 161         { .parent = NULL },
 162 };
 163
 164 /* Oscillator clock */
 165 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 166 static struct clk osc_sys_ck = {
 167         .name           = "osc_sys_ck",
 168         .init           = &omap2_init_clksel_parent,
 169         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 170         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 171         .clksel         = osc_sys_clksel,
 172         /* REVISIT: deal with autoextclkmode? */
 173         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 174                                 ALWAYS_ENABLED,
 175         .recalc         = &omap2_clksel_recalc,
 176 };
 177
 178 static const struct clksel_rate div2_rates[] = {
 179         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 180         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 181         { .div = 0 }
 182 };
 183
 184 static const struct clksel sys_clksel[] = {
 185         { .parent = &osc_sys_ck, .rates = div2_rates },
 186         { .parent = NULL }
 187 };
 188
 189 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 190 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 191 static struct clk sys_ck = {
 192         .name           = "sys_ck",
 193         .parent         = &osc_sys_ck,
 194         .init           = &omap2_init_clksel_parent,
 195         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 196         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 197         .clksel         = sys_clksel,
 198         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 199         .recalc         = &omap2_clksel_recalc,
 200 };
 201
 202 static struct clk sys_altclk = {
 203         .name           = "sys_altclk",
 204         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 205         .recalc         = &propagate_rate,
 206 };
 207
 208 /* Optional external clock input for some McBSPs */
 209 static struct clk mcbsp_clks = {
 210         .name           = "mcbsp_clks",
 211         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 212         .recalc         = &propagate_rate,
 213 };
 214
 215 /* PRM EXTERNAL CLOCK OUTPUT */
 216
 217 static struct clk sys_clkout1 = {
 218         .name           = "sys_clkout1",
 219         .parent         = &osc_sys_ck,
 220         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 221         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 222         .flags          = CLOCK_IN_OMAP343X,
 223         .recalc         = &followparent_recalc,
 224 };
 225
 226 /* DPLLS */
 227
 228 /* CM CLOCKS */
 229
 230 static const struct clksel_rate dpll_bypass_rates[] = {
 231         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 232         { .div = 0 }
 233 };
 234
 235 static const struct clksel_rate dpll_locked_rates[] = {
 236         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 237         { .div = 0 }
 238 };
 239
 240 static const struct clksel_rate div16_dpll_rates[] = {
 241         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 242         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 243         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 244         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 245         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 246         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 247         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 248         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 249         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 250         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 251         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 252         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 253         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 254         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 255         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 256         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 257         { .div = 0 }
 258 };
 259
 260 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 261         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 262
 263 /* DPLL1 */
 264 /* MPU clock source */
 265 /* Type: DPLL */
 266 static struct dpll_data dpll1_dd = {
 267         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 268         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 269         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 270         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 271         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 272         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 273         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 274         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 275         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 276         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 277         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 278         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 279         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 280         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 281         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 282         .max_divider    = OMAP3_MAX_DPLL_DIV,
 283         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 284 };
 285
 286 static struct clk dpll1_ck = {
 287         .name           = "dpll1_ck",
 288         .parent         = &sys_ck,
 289         .dpll_data      = &dpll1_dd,
 290         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 291         .round_rate     = &omap2_dpll_round_rate,
 292         .set_rate       = &omap3_noncore_dpll_set_rate,
 293         .recalc         = &omap3_dpll_recalc,
 294 };
 295
 296 /*
 297  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 298  * DPLL isn't bypassed.
 299  */
 300 static struct clk dpll1_x2_ck = {
 301         .name           = "dpll1_x2_ck",
 302         .parent         = &dpll1_ck,
 303         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 304                                 PARENT_CONTROLS_CLOCK,
 305         .recalc         = &omap3_clkoutx2_recalc,
 306 };
 307
 308 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 309 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 310         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 311         { .parent = NULL }
 312 };
 313
 314 /*
 315  * Does not exist in the TRM - needed to separate the M2 divider from
 316  * bypass selection in mpu_ck
 317  */
 318 static struct clk dpll1_x2m2_ck = {
 319         .name           = "dpll1_x2m2_ck",
 320         .parent         = &dpll1_x2_ck,
 321         .init           = &omap2_init_clksel_parent,
 322         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 323         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 324         .clksel         = div16_dpll1_x2m2_clksel,
 325         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 326                                 PARENT_CONTROLS_CLOCK,
 327         .recalc         = &omap2_clksel_recalc,
 328 };
 329
 330 /* DPLL2 */
 331 /* IVA2 clock source */
 332 /* Type: DPLL */
 333
 334 static struct dpll_data dpll2_dd = {
 335         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 336         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 337         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 338         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 339         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 340         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 341         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 342                                 (1 << DPLL_LOW_POWER_BYPASS),
 343         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 344         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 345         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 346         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 347         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 348         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 349         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 350         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 351         .max_divider    = OMAP3_MAX_DPLL_DIV,
 352         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 353 };
 354
 355 static struct clk dpll2_ck = {
 356         .name           = "dpll2_ck",
 357         .parent         = &sys_ck,
 358         .dpll_data      = &dpll2_dd,
 359         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 360         .enable         = &omap3_noncore_dpll_enable,
 361         .disable        = &omap3_noncore_dpll_disable,
 362         .round_rate     = &omap2_dpll_round_rate,
 363         .set_rate       = &omap3_noncore_dpll_set_rate,
 364         .recalc         = &omap3_dpll_recalc,
 365 };
 366
 367 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 368         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 369         { .parent = NULL }
 370 };
 371
 372 /*
 373  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 374  * or CLKOUTX2. CLKOUT seems most plausible.
 375  */
 376 static struct clk dpll2_m2_ck = {
 377         .name           = "dpll2_m2_ck",
 378         .parent         = &dpll2_ck,
 379         .init           = &omap2_init_clksel_parent,
 380         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 381                                           OMAP3430_CM_CLKSEL2_PLL),
 382         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 383         .clksel         = div16_dpll2_m2x2_clksel,
 384         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 385                                 PARENT_CONTROLS_CLOCK,
 386         .recalc         = &omap2_clksel_recalc,
 387 };
 388
 389 /*
 390  * DPLL3
 391  * Source clock for all interfaces and for some device fclks
 392  * REVISIT: Also supports fast relock bypass - not included below
 393  */
 394 static struct dpll_data dpll3_dd = {
 395         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 396         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 397         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 398         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 399         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 400         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 401         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 402         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 403         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 404         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 405         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 406         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 407         .max_divider    = OMAP3_MAX_DPLL_DIV,
 408         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 409 };
 410
 411 static struct clk dpll3_ck = {
 412         .name           = "dpll3_ck",
 413         .parent         = &sys_ck,
 414         .dpll_data      = &dpll3_dd,
 415         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 416         .round_rate     = &omap2_dpll_round_rate,
 417         .recalc         = &omap3_dpll_recalc,
 418 };
 419
 420 /*
 421  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 422  * DPLL isn't bypassed
 423  */
 424 static struct clk dpll3_x2_ck = {
 425         .name           = "dpll3_x2_ck",
 426         .parent         = &dpll3_ck,
 427         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 428                                 PARENT_CONTROLS_CLOCK,
 429         .recalc         = &omap3_clkoutx2_recalc,
 430 };
 431
 432 static const struct clksel_rate div31_dpll3_rates[] = {
 433         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 434         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 435         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 436         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 437         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 438         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 439         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 440         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 441         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 442         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 443         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 444         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 445         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 446         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 447         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 448         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 449         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 450         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 451         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 452         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 453         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 454         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 455         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 456         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 457         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 458         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 459         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 460         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 461         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 462         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 463         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 464         { .div = 0 },
 465 };
 466
 467 static const struct clksel div31_dpll3m2_clksel[] = {
 468         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 469         { .parent = NULL }
 470 };
 471
 472 /*
 473  * DPLL3 output M2
 474  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 475  * that code is ready, this should remain a 'read-only' clksel clock.
 476  */
 477 static struct clk dpll3_m2_ck = {
 478         .name           = "dpll3_m2_ck",
 479         .parent         = &dpll3_ck,
 480         .init           = &omap2_init_clksel_parent,
 481         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 482         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 483         .clksel         = div31_dpll3m2_clksel,
 484         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 485                                 PARENT_CONTROLS_CLOCK,
 486         .recalc         = &omap2_clksel_recalc,
 487 };
 488
 489 static const struct clksel core_ck_clksel[] = {
 490         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 491         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 492         { .parent = NULL }
 493 };
 494
 495 static struct clk core_ck = {
 496         .name           = "core_ck",
 497         .init           = &omap2_init_clksel_parent,
 498         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 499         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 500         .clksel         = core_ck_clksel,
 501         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 502                                 PARENT_CONTROLS_CLOCK,
 503         .recalc         = &omap2_clksel_recalc,
 504 };
 505
 506 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 507         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 508         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 509         { .parent = NULL }
 510 };
 511
 512 static struct clk dpll3_m2x2_ck = {
 513         .name           = "dpll3_m2x2_ck",
 514         .init           = &omap2_init_clksel_parent,
 515         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 516         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 517         .clksel         = dpll3_m2x2_ck_clksel,
 518         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 519                                 PARENT_CONTROLS_CLOCK,
 520         .recalc         = &omap2_clksel_recalc,
 521 };
 522
 523 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 524 static const struct clksel div16_dpll3_clksel[] = {
 525         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 526         { .parent = NULL }
 527 };
 528
 529 /* This virtual clock is the source for dpll3_m3x2_ck */
 530 static struct clk dpll3_m3_ck = {
 531         .name           = "dpll3_m3_ck",
 532         .parent         = &dpll3_ck,
 533         .init           = &omap2_init_clksel_parent,
 534         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 535         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 536         .clksel         = div16_dpll3_clksel,
 537         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 538                                 PARENT_CONTROLS_CLOCK,
 539         .recalc         = &omap2_clksel_recalc,
 540 };
 541
 542 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 543 static struct clk dpll3_m3x2_ck = {
 544         .name           = "dpll3_m3x2_ck",
 545         .parent         = &dpll3_m3_ck,
 546         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 547         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 548         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 549         .recalc         = &omap3_clkoutx2_recalc,
 550 };
 551
 552 static const struct clksel emu_core_alwon_ck_clksel[] = {
 553         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 554         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 555         { .parent = NULL }
 556 };
 557
 558 static struct clk emu_core_alwon_ck = {
 559         .name           = "emu_core_alwon_ck",
 560         .parent         = &dpll3_m3x2_ck,
 561         .init           = &omap2_init_clksel_parent,
 562         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 563         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 564         .clksel         = emu_core_alwon_ck_clksel,
 565         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 566                                 PARENT_CONTROLS_CLOCK,
 567         .recalc         = &omap2_clksel_recalc,
 568 };
 569
 570 /* DPLL4 */
 571 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 572 /* Type: DPLL */
 573 static struct dpll_data dpll4_dd = {
 574         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 575         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 576         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 577         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 578         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 579         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 580         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 581         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 582         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 583         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 584         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 585         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 586         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 587         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 588         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 589         .max_divider    = OMAP3_MAX_DPLL_DIV,
 590         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 591 };
 592
 593 static struct clk dpll4_ck = {
 594         .name           = "dpll4_ck",
 595         .parent         = &sys_ck,
 596         .dpll_data      = &dpll4_dd,
 597         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 598         .enable         = &omap3_noncore_dpll_enable,
 599         .disable        = &omap3_noncore_dpll_disable,
 600         .round_rate     = &omap2_dpll_round_rate,
 601         .set_rate       = &omap3_noncore_dpll_set_rate,
 602         .recalc         = &omap3_dpll_recalc,
 603 };
 604
 605 /*
 606  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 607  * DPLL isn't bypassed --
 608  * XXX does this serve any downstream clocks?
 609  */
 610 static struct clk dpll4_x2_ck = {
 611         .name           = "dpll4_x2_ck",
 612         .parent         = &dpll4_ck,
 613         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 614                                 PARENT_CONTROLS_CLOCK,
 615         .recalc         = &omap3_clkoutx2_recalc,
 616 };
 617
 618 static const struct clksel div16_dpll4_clksel[] = {
 619         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 620         { .parent = NULL }
 621 };
 622
 623 /* This virtual clock is the source for dpll4_m2x2_ck */
 624 static struct clk dpll4_m2_ck = {
 625         .name           = "dpll4_m2_ck",
 626         .parent         = &dpll4_ck,
 627         .init           = &omap2_init_clksel_parent,
 628         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 629         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 630         .clksel         = div16_dpll4_clksel,
 631         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 632                                 PARENT_CONTROLS_CLOCK,
 633         .recalc         = &omap2_clksel_recalc,
 634 };
 635
 636 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 637 static struct clk dpll4_m2x2_ck = {
 638         .name           = "dpll4_m2x2_ck",
 639         .parent         = &dpll4_m2_ck,
 640         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 641         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 642         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 643         .recalc         = &omap3_clkoutx2_recalc,
 644 };
 645
 646 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 647         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 648         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 649         { .parent = NULL }
 650 };
 651
 652 static struct clk omap_96m_alwon_fck = {
 653         .name           = "omap_96m_alwon_fck",
 654         .parent         = &dpll4_m2x2_ck,
 655         .init           = &omap2_init_clksel_parent,
 656         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 657         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 658         .clksel         = omap_96m_alwon_fck_clksel,
 659         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 660                                  PARENT_CONTROLS_CLOCK,
 661         .recalc         = &omap2_clksel_recalc,
 662 };
 663
 664 static struct clk omap_96m_fck = {
 665         .name           = "omap_96m_fck",
 666         .parent         = &omap_96m_alwon_fck,
 667         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 668                                 PARENT_CONTROLS_CLOCK,
 669         .recalc         = &followparent_recalc,
 670 };
 671
 672 static const struct clksel cm_96m_fck_clksel[] = {
 673         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 674         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 675         { .parent = NULL }
 676 };
 677
 678 static struct clk cm_96m_fck = {
 679         .name           = "cm_96m_fck",
 680         .parent         = &dpll4_m2x2_ck,
 681         .init           = &omap2_init_clksel_parent,
 682         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 683         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 684         .clksel         = cm_96m_fck_clksel,
 685         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 686                                 PARENT_CONTROLS_CLOCK,
 687         .recalc         = &omap2_clksel_recalc,
 688 };
 689
 690 /* This virtual clock is the source for dpll4_m3x2_ck */
 691 static struct clk dpll4_m3_ck = {
 692         .name           = "dpll4_m3_ck",
 693         .parent         = &dpll4_ck,
 694         .init           = &omap2_init_clksel_parent,
 695         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 696         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 697         .clksel         = div16_dpll4_clksel,
 698         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 699                                 PARENT_CONTROLS_CLOCK,
 700         .recalc         = &omap2_clksel_recalc,
 701 };
 702
 703 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 704 static struct clk dpll4_m3x2_ck = {
 705         .name           = "dpll4_m3x2_ck",
 706         .parent         = &dpll4_m3_ck,
 707         .init           = &omap2_init_clksel_parent,
 708         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 709         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 710         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 711         .recalc         = &omap3_clkoutx2_recalc,
 712 };
 713
 714 static const struct clksel virt_omap_54m_fck_clksel[] = {
 715         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 716         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 717         { .parent = NULL }
 718 };
 719
 720 static struct clk virt_omap_54m_fck = {
 721         .name           = "virt_omap_54m_fck",
 722         .parent         = &dpll4_m3x2_ck,
 723         .init           = &omap2_init_clksel_parent,
 724         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 725         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 726         .clksel         = virt_omap_54m_fck_clksel,
 727         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 728                                 PARENT_CONTROLS_CLOCK,
 729         .recalc         = &omap2_clksel_recalc,
 730 };
 731
 732 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 733         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 734         { .div = 0 }
 735 };
 736
 737 static const struct clksel_rate omap_54m_alt_rates[] = {
 738         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 739         { .div = 0 }
 740 };
 741
 742 static const struct clksel omap_54m_clksel[] = {
 743         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 744         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 745         { .parent = NULL }
 746 };
 747
 748 static struct clk omap_54m_fck = {
 749         .name           = "omap_54m_fck",
 750         .init           = &omap2_init_clksel_parent,
 751         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 752         .clksel_mask    = OMAP3430_SOURCE_54M,
 753         .clksel         = omap_54m_clksel,
 754         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 755                                 PARENT_CONTROLS_CLOCK,
 756         .recalc         = &omap2_clksel_recalc,
 757 };
 758
 759 static const struct clksel_rate omap_48m_96md2_rates[] = {
 760         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 761         { .div = 0 }
 762 };
 763
 764 static const struct clksel_rate omap_48m_alt_rates[] = {
 765         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 766         { .div = 0 }
 767 };
 768
 769 static const struct clksel omap_48m_clksel[] = {
 770         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 771         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 772         { .parent = NULL }
 773 };
 774
 775 static struct clk omap_48m_fck = {
 776         .name           = "omap_48m_fck",
 777         .init           = &omap2_init_clksel_parent,
 778         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 779         .clksel_mask    = OMAP3430_SOURCE_48M,
 780         .clksel         = omap_48m_clksel,
 781         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 782                                 PARENT_CONTROLS_CLOCK,
 783         .recalc         = &omap2_clksel_recalc,
 784 };
 785
 786 static struct clk omap_12m_fck = {
 787         .name           = "omap_12m_fck",
 788         .parent         = &omap_48m_fck,
 789         .fixed_div      = 4,
 790         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 791                                 PARENT_CONTROLS_CLOCK,
 792         .recalc         = &omap2_fixed_divisor_recalc,
 793 };
 794
 795 /* This virstual clock is the source for dpll4_m4x2_ck */
 796 static struct clk dpll4_m4_ck = {
 797         .name           = "dpll4_m4_ck",
 798         .parent         = &dpll4_ck,
 799         .init           = &omap2_init_clksel_parent,
 800         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 801         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 802         .clksel         = div16_dpll4_clksel,
 803         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 804                                 PARENT_CONTROLS_CLOCK,
 805         .recalc         = &omap2_clksel_recalc,
 806 };
 807
 808 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 809 static struct clk dpll4_m4x2_ck = {
 810         .name           = "dpll4_m4x2_ck",
 811         .parent         = &dpll4_m4_ck,
 812         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 813         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 814         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 815         .recalc         = &omap3_clkoutx2_recalc,
 816 };
 817
 818 /* This virtual clock is the source for dpll4_m5x2_ck */
 819 static struct clk dpll4_m5_ck = {
 820         .name           = "dpll4_m5_ck",
 821         .parent         = &dpll4_ck,
 822         .init           = &omap2_init_clksel_parent,
 823         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 824         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 825         .clksel         = div16_dpll4_clksel,
 826         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 827                                 PARENT_CONTROLS_CLOCK,
 828         .recalc         = &omap2_clksel_recalc,
 829 };
 830
 831 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 832 static struct clk dpll4_m5x2_ck = {
 833         .name           = "dpll4_m5x2_ck",
 834         .parent         = &dpll4_m5_ck,
 835         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 836         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 837         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 838         .recalc         = &omap3_clkoutx2_recalc,
 839 };
 840
 841 /* This virtual clock is the source for dpll4_m6x2_ck */
 842 static struct clk dpll4_m6_ck = {
 843         .name           = "dpll4_m6_ck",
 844         .parent         = &dpll4_ck,
 845         .init           = &omap2_init_clksel_parent,
 846         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 847         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 848         .clksel         = div16_dpll4_clksel,
 849         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 850                                 PARENT_CONTROLS_CLOCK,
 851         .recalc         = &omap2_clksel_recalc,
 852 };
 853
 854 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 855 static struct clk dpll4_m6x2_ck = {
 856         .name           = "dpll4_m6x2_ck",
 857         .parent         = &dpll4_m6_ck,
 858         .init           = &omap2_init_clksel_parent,
 859         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 860         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 861         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 862         .recalc         = &omap3_clkoutx2_recalc,
 863 };
 864
 865 static struct clk emu_per_alwon_ck = {
 866         .name           = "emu_per_alwon_ck",
 867         .parent         = &dpll4_m6x2_ck,
 868         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 869                                 PARENT_CONTROLS_CLOCK,
 870         .recalc         = &followparent_recalc,
 871 };
 872
 873 /* DPLL5 */
 874 /* Supplies 120MHz clock, USIM source clock */
 875 /* Type: DPLL */
 876 /* 3430ES2 only */
 877 static struct dpll_data dpll5_dd = {
 878         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 879         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 880         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 881         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 882         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 883         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 884         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 885         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 886         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 887         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 888         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 889         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 890         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 891         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 892         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 893         .max_divider    = OMAP3_MAX_DPLL_DIV,
 894         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 895 };
 896
 897 static struct clk dpll5_ck = {
 898         .name           = "dpll5_ck",
 899         .parent         = &sys_ck,
 900         .dpll_data      = &dpll5_dd,
 901         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 902         .enable         = &omap3_noncore_dpll_enable,
 903         .disable        = &omap3_noncore_dpll_disable,
 904         .round_rate     = &omap2_dpll_round_rate,
 905         .set_rate       = &omap3_noncore_dpll_set_rate,
 906         .recalc         = &omap3_dpll_recalc,
 907 };
 908
 909 static const struct clksel div16_dpll5_clksel[] = {
 910         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 911         { .parent = NULL }
 912 };
 913
 914 static struct clk dpll5_m2_ck = {
 915         .name           = "dpll5_m2_ck",
 916         .parent         = &dpll5_ck,
 917         .init           = &omap2_init_clksel_parent,
 918         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 919         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 920         .clksel         = div16_dpll5_clksel,
 921         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 922                                 PARENT_CONTROLS_CLOCK,
 923         .recalc         = &omap2_clksel_recalc,
 924 };
 925
 926 static const struct clksel omap_120m_fck_clksel[] = {
 927         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 928         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 929         { .parent = NULL }
 930 };
 931
 932 static struct clk omap_120m_fck = {
 933         .name           = "omap_120m_fck",
 934         .parent         = &dpll5_m2_ck,
 935         .init           = &omap2_init_clksel_parent,
 936         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 937         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 938         .clksel         = omap_120m_fck_clksel,
 939         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 940                                 PARENT_CONTROLS_CLOCK,
 941         .recalc         = &omap2_clksel_recalc,
 942 };
 943
 944 /* CM EXTERNAL CLOCK OUTPUTS */
 945
 946 static const struct clksel_rate clkout2_src_core_rates[] = {
 947         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 948         { .div = 0 }
 949 };
 950
 951 static const struct clksel_rate clkout2_src_sys_rates[] = {
 952         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 953         { .div = 0 }
 954 };
 955
 956 static const struct clksel_rate clkout2_src_96m_rates[] = {
 957         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 958         { .div = 0 }
 959 };
 960
 961 static const struct clksel_rate clkout2_src_54m_rates[] = {
 962         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 963         { .div = 0 }
 964 };
 965
 966 static const struct clksel clkout2_src_clksel[] = {
 967         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 968         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 969         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 970         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 971         { .parent = NULL }
 972 };
 973
 974 static struct clk clkout2_src_ck = {
 975         .name           = "clkout2_src_ck",
 976         .init           = &omap2_init_clksel_parent,
 977         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
 978         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 979         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
 980         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 981         .clksel         = clkout2_src_clksel,
 982         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 983         .clkdm_name     = "core_clkdm",
 984         .recalc         = &omap2_clksel_recalc,
 985 };
 986
 987 static const struct clksel_rate sys_clkout2_rates[] = {
 988         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 989         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 990         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 991         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 992         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 993         { .div = 0 },
 994 };
 995
 996 static const struct clksel sys_clkout2_clksel[] = {
 997         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 998         { .parent = NULL },
 999 };
1000
1001 static struct clk sys_clkout2 = {
1002         .name           = "sys_clkout2",
1003         .init           = &omap2_init_clksel_parent,
1004         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1005         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1006         .clksel         = sys_clkout2_clksel,
1007         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1008         .recalc         = &omap2_clksel_recalc,
1009 };
1010
1011 /* CM OUTPUT CLOCKS */
1012
1013 static struct clk corex2_fck = {
1014         .name           = "corex2_fck",
1015         .parent         = &dpll3_m2x2_ck,
1016         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1017                                 PARENT_CONTROLS_CLOCK,
1018         .recalc         = &followparent_recalc,
1019 };
1020
1021 /* DPLL power domain clock controls */
1022
1023 static const struct clksel div2_core_clksel[] = {
1024         { .parent = &core_ck, .rates = div2_rates },
1025         { .parent = NULL }
1026 };
1027
1028 /*
1029  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1030  * may be inconsistent here?
1031  */
1032 static struct clk dpll1_fck = {
1033         .name           = "dpll1_fck",
1034         .parent         = &core_ck,
1035         .init           = &omap2_init_clksel_parent,
1036         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1037         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1038         .clksel         = div2_core_clksel,
1039         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1040                                 PARENT_CONTROLS_CLOCK,
1041         .recalc         = &omap2_clksel_recalc,
1042 };
1043
1044 /*
1045  * MPU clksel:
1046  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1047  * derives from the high-frequency bypass clock originating from DPLL3,
1048  * called 'dpll1_fck'
1049  */
1050 static const struct clksel mpu_clksel[] = {
1051         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1052         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1053         { .parent = NULL }
1054 };
1055
1056 static struct clk mpu_ck = {
1057         .name           = "mpu_ck",
1058         .parent         = &dpll1_x2m2_ck,
1059         .init           = &omap2_init_clksel_parent,
1060         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1061         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1062         .clksel         = mpu_clksel,
1063         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1064                                 PARENT_CONTROLS_CLOCK,
1065         .clkdm_name     = "mpu_clkdm",
1066         .recalc         = &omap2_clksel_recalc,
1067 };
1068
1069 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1070 static const struct clksel_rate arm_fck_rates[] = {
1071         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1072         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1073         { .div = 0 },
1074 };
1075
1076 static const struct clksel arm_fck_clksel[] = {
1077         { .parent = &mpu_ck, .rates = arm_fck_rates },
1078         { .parent = NULL }
1079 };
1080
1081 static struct clk arm_fck = {
1082         .name           = "arm_fck",
1083         .parent         = &mpu_ck,
1084         .init           = &omap2_init_clksel_parent,
1085         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1086         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1087         .clksel         = arm_fck_clksel,
1088         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1089                                 PARENT_CONTROLS_CLOCK,
1090         .recalc         = &omap2_clksel_recalc,
1091 };
1092
1093 /* XXX What about neon_clkdm ? */
1094
1095 /*
1096  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1097  * although it is referenced - so this is a guess
1098  */
1099 static struct clk emu_mpu_alwon_ck = {
1100         .name           = "emu_mpu_alwon_ck",
1101         .parent         = &mpu_ck,
1102         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1103                                 PARENT_CONTROLS_CLOCK,
1104         .recalc         = &followparent_recalc,
1105 };
1106
1107 static struct clk dpll2_fck = {
1108         .name           = "dpll2_fck",
1109         .parent         = &core_ck,
1110         .init           = &omap2_init_clksel_parent,
1111         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1112         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1113         .clksel         = div2_core_clksel,
1114         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1115                                 PARENT_CONTROLS_CLOCK,
1116         .recalc         = &omap2_clksel_recalc,
1117 };
1118
1119 /*
1120  * IVA2 clksel:
1121  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1122  * derives from the high-frequency bypass clock originating from DPLL3,
1123  * called 'dpll2_fck'
1124  */
1125
1126 static const struct clksel iva2_clksel[] = {
1127         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1128         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1129         { .parent = NULL }
1130 };
1131
1132 static struct clk iva2_ck = {
1133         .name           = "iva2_ck",
1134         .parent         = &dpll2_m2_ck,
1135         .init           = &omap2_init_clksel_parent,
1136         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1137         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1138         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1139                                           OMAP3430_CM_IDLEST_PLL),
1140         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1141         .clksel         = iva2_clksel,
1142         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1143         .clkdm_name     = "iva2_clkdm",
1144         .recalc         = &omap2_clksel_recalc,
1145 };
1146
1147 /* Common interface clocks */
1148
1149 static struct clk l3_ick = {
1150         .name           = "l3_ick",
1151         .parent         = &core_ck,
1152         .init           = &omap2_init_clksel_parent,
1153         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1154         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1155         .clksel         = div2_core_clksel,
1156         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1157                                 PARENT_CONTROLS_CLOCK,
1158         .clkdm_name     = "core_l3_clkdm",
1159         .recalc         = &omap2_clksel_recalc,
1160 };
1161
1162 static const struct clksel div2_l3_clksel[] = {
1163         { .parent = &l3_ick, .rates = div2_rates },
1164         { .parent = NULL }
1165 };
1166
1167 static struct clk l4_ick = {
1168         .name           = "l4_ick",
1169         .parent         = &l3_ick,
1170         .init           = &omap2_init_clksel_parent,
1171         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1172         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1173         .clksel         = div2_l3_clksel,
1174         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1175                                 PARENT_CONTROLS_CLOCK,
1176         .clkdm_name     = "core_l4_clkdm",
1177         .recalc         = &omap2_clksel_recalc,
1178
1179 };
1180
1181 static const struct clksel div2_l4_clksel[] = {
1182         { .parent = &l4_ick, .rates = div2_rates },
1183         { .parent = NULL }
1184 };
1185
1186 static struct clk rm_ick = {
1187         .name           = "rm_ick",
1188         .parent         = &l4_ick,
1189         .init           = &omap2_init_clksel_parent,
1190         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1191         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1192         .clksel         = div2_l4_clksel,
1193         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1194         .recalc         = &omap2_clksel_recalc,
1195 };
1196
1197 /* GFX power domain */
1198
1199 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1200
1201 static const struct clksel gfx_l3_clksel[] = {
1202         { .parent = &l3_ick, .rates = gfx_l3_rates },
1203         { .parent = NULL }
1204 };
1205
1206 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1207 static struct clk gfx_l3_ck = {
1208         .name           = "gfx_l3_ck",
1209         .parent         = &l3_ick,
1210         .init           = &omap2_init_clksel_parent,
1211         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1212         .enable_bit     = OMAP_EN_GFX_SHIFT,
1213         .flags          = CLOCK_IN_OMAP3430ES1,
1214         .recalc         = &followparent_recalc,
1215 };
1216
1217 static struct clk gfx_l3_fck = {
1218         .name           = "gfx_l3_fck",
1219         .parent         = &gfx_l3_ck,
1220         .init           = &omap2_init_clksel_parent,
1221         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1222         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1223         .clksel         = gfx_l3_clksel,
1224         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1225                                 PARENT_CONTROLS_CLOCK,
1226         .clkdm_name     = "gfx_3430es1_clkdm",
1227         .recalc         = &omap2_clksel_recalc,
1228 };
1229
1230 static struct clk gfx_l3_ick = {
1231         .name           = "gfx_l3_ick",
1232         .parent         = &gfx_l3_ck,
1233         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1234         .clkdm_name     = "gfx_3430es1_clkdm",
1235         .recalc         = &followparent_recalc,
1236 };
1237
1238 static struct clk gfx_cg1_ck = {
1239         .name           = "gfx_cg1_ck",
1240         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1241         .init           = &omap2_init_clk_clkdm,
1242         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1243         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1244         .flags          = CLOCK_IN_OMAP3430ES1,
1245         .clkdm_name     = "gfx_3430es1_clkdm",
1246         .recalc         = &followparent_recalc,
1247 };
1248
1249 static struct clk gfx_cg2_ck = {
1250         .name           = "gfx_cg2_ck",
1251         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1252         .init           = &omap2_init_clk_clkdm,
1253         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1254         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1255         .flags          = CLOCK_IN_OMAP3430ES1,
1256         .clkdm_name     = "gfx_3430es1_clkdm",
1257         .recalc         = &followparent_recalc,
1258 };
1259
1260 /* SGX power domain - 3430ES2 only */
1261
1262 static const struct clksel_rate sgx_core_rates[] = {
1263         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1264         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1265         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1266         { .div = 0 },
1267 };
1268
1269 static const struct clksel_rate sgx_96m_rates[] = {
1270         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1271         { .div = 0 },
1272 };
1273
1274 static const struct clksel sgx_clksel[] = {
1275         { .parent = &core_ck,    .rates = sgx_core_rates },
1276         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1277         { .parent = NULL },
1278 };
1279
1280 static struct clk sgx_fck = {
1281         .name           = "sgx_fck",
1282         .init           = &omap2_init_clksel_parent,
1283         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1284         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1285         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1286         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1287         .clksel         = sgx_clksel,
1288         .flags          = CLOCK_IN_OMAP3430ES2,
1289         .clkdm_name     = "sgx_clkdm",
1290         .recalc         = &omap2_clksel_recalc,
1291 };
1292
1293 static struct clk sgx_ick = {
1294         .name           = "sgx_ick",
1295         .parent         = &l3_ick,
1296         .init           = &omap2_init_clk_clkdm,
1297         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1298         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1299         .flags          = CLOCK_IN_OMAP3430ES2,
1300         .clkdm_name     = "sgx_clkdm",
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 /* CORE power domain */
1305
1306 static struct clk d2d_26m_fck = {
1307         .name           = "d2d_26m_fck",
1308         .parent         = &sys_ck,
1309         .init           = &omap2_init_clk_clkdm,
1310         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1311         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1312         .flags          = CLOCK_IN_OMAP3430ES1,
1313         .clkdm_name     = "d2d_clkdm",
1314         .recalc         = &followparent_recalc,
1315 };
1316
1317 static const struct clksel omap343x_gpt_clksel[] = {
1318         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1319         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1320         { .parent = NULL}
1321 };
1322
1323 static struct clk gpt10_fck = {
1324         .name           = "gpt10_fck",
1325         .parent         = &sys_ck,
1326         .init           = &omap2_init_clksel_parent,
1327         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1328         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1329         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1330         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1331         .clksel         = omap343x_gpt_clksel,
1332         .flags          = CLOCK_IN_OMAP343X,
1333         .clkdm_name     = "core_l4_clkdm",
1334         .recalc         = &omap2_clksel_recalc,
1335 };
1336
1337 static struct clk gpt11_fck = {
1338         .name           = "gpt11_fck",
1339         .parent         = &sys_ck,
1340         .init           = &omap2_init_clksel_parent,
1341         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1342         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1343         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1344         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1345         .clksel         = omap343x_gpt_clksel,
1346         .flags          = CLOCK_IN_OMAP343X,
1347         .clkdm_name     = "core_l4_clkdm",
1348         .recalc         = &omap2_clksel_recalc,
1349 };
1350
1351 static struct clk cpefuse_fck = {
1352         .name           = "cpefuse_fck",
1353         .parent         = &sys_ck,
1354         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1355         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1356         .flags          = CLOCK_IN_OMAP3430ES2,
1357         .recalc         = &followparent_recalc,
1358 };
1359
1360 static struct clk ts_fck = {
1361         .name           = "ts_fck",
1362         .parent         = &omap_32k_fck,
1363         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1364         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1365         .flags          = CLOCK_IN_OMAP3430ES2,
1366         .recalc         = &followparent_recalc,
1367 };
1368
1369 static struct clk usbtll_fck = {
1370         .name           = "usbtll_fck",
1371         .parent         = &omap_120m_fck,
1372         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1373         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1374         .flags          = CLOCK_IN_OMAP3430ES2,
1375         .recalc         = &followparent_recalc,
1376 };
1377
1378 /* CORE 96M FCLK-derived clocks */
1379
1380 static struct clk core_96m_fck = {
1381         .name           = "core_96m_fck",
1382         .parent         = &omap_96m_fck,
1383         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1384                                 PARENT_CONTROLS_CLOCK,
1385         .clkdm_name     = "core_l4_clkdm",
1386         .recalc         = &followparent_recalc,
1387 };
1388
1389 static struct clk mmchs3_fck = {
1390         .name           = "mmchs_fck",
1391         .id             = 3,
1392         .parent         = &core_96m_fck,
1393         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1394         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1395         .flags          = CLOCK_IN_OMAP3430ES2,
1396         .clkdm_name     = "core_l4_clkdm",
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 static struct clk mmchs2_fck = {
1401         .name           = "mmchs_fck",
1402         .id             = 2,
1403         .parent         = &core_96m_fck,
1404         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1405         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1406         .flags          = CLOCK_IN_OMAP343X,
1407         .clkdm_name     = "core_l4_clkdm",
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk mspro_fck = {
1412         .name           = "mspro_fck",
1413         .parent         = &core_96m_fck,
1414         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1415         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1416         .flags          = CLOCK_IN_OMAP343X,
1417         .clkdm_name     = "core_l4_clkdm",
1418         .recalc         = &followparent_recalc,
1419 };
1420
1421 static struct clk mmchs1_fck = {
1422         .name           = "mmchs_fck",
1423         .id             = 1,
1424         .parent         = &core_96m_fck,
1425         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1426         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1427         .flags          = CLOCK_IN_OMAP343X,
1428         .clkdm_name     = "core_l4_clkdm",
1429         .recalc         = &followparent_recalc,
1430 };
1431
1432 static struct clk i2c3_fck = {
1433         .name           = "i2c_fck",
1434         .id             = 3,
1435         .parent         = &core_96m_fck,
1436         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1438         .flags          = CLOCK_IN_OMAP343X,
1439         .clkdm_name     = "core_l4_clkdm",
1440         .recalc         = &followparent_recalc,
1441 };
1442
1443 static struct clk i2c2_fck = {
1444         .name           = "i2c_fck",
1445         .id             = 2,
1446         .parent         = &core_96m_fck,
1447         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1449         .flags          = CLOCK_IN_OMAP343X,
1450         .clkdm_name     = "core_l4_clkdm",
1451         .recalc         = &followparent_recalc,
1452 };
1453
1454 static struct clk i2c1_fck = {
1455         .name           = "i2c_fck",
1456         .id             = 1,
1457         .parent         = &core_96m_fck,
1458         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1459         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1460         .flags          = CLOCK_IN_OMAP343X,
1461         .clkdm_name     = "core_l4_clkdm",
1462         .recalc         = &followparent_recalc,
1463 };
1464
1465 /*
1466  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1467  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1468  */
1469 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1470         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1471         { .div = 0 }
1472 };
1473
1474 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1475         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1476         { .div = 0 }
1477 };
1478
1479 static const struct clksel mcbsp_15_clksel[] = {
1480         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1481         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1482         { .parent = NULL }
1483 };
1484
1485 static struct clk mcbsp5_fck = {
1486         .name           = "mcbsp_fck",
1487         .id             = 5,
1488         .init           = &omap2_init_clksel_parent,
1489         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1490         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1491         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1492         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1493         .clksel         = mcbsp_15_clksel,
1494         .flags          = CLOCK_IN_OMAP343X,
1495         .clkdm_name     = "core_l4_clkdm",
1496         .recalc         = &omap2_clksel_recalc,
1497 };
1498
1499 static struct clk mcbsp1_fck = {
1500         .name           = "mcbsp_fck",
1501         .id             = 1,
1502         .init           = &omap2_init_clksel_parent,
1503         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1505         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1506         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1507         .clksel         = mcbsp_15_clksel,
1508         .flags          = CLOCK_IN_OMAP343X,
1509         .clkdm_name     = "core_l4_clkdm",
1510         .recalc         = &omap2_clksel_recalc,
1511 };
1512
1513 /* CORE_48M_FCK-derived clocks */
1514
1515 static struct clk core_48m_fck = {
1516         .name           = "core_48m_fck",
1517         .parent         = &omap_48m_fck,
1518         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1519                                 PARENT_CONTROLS_CLOCK,
1520         .clkdm_name     = "core_l4_clkdm",
1521         .recalc         = &followparent_recalc,
1522 };
1523
1524 static struct clk mcspi4_fck = {
1525         .name           = "mcspi_fck",
1526         .id             = 4,
1527         .parent         = &core_48m_fck,
1528         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1529         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1530         .flags          = CLOCK_IN_OMAP343X,
1531         .recalc         = &followparent_recalc,
1532 };
1533
1534 static struct clk mcspi3_fck = {
1535         .name           = "mcspi_fck",
1536         .id             = 3,
1537         .parent         = &core_48m_fck,
1538         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1539         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1540         .flags          = CLOCK_IN_OMAP343X,
1541         .recalc         = &followparent_recalc,
1542 };
1543
1544 static struct clk mcspi2_fck = {
1545         .name           = "mcspi_fck",
1546         .id             = 2,
1547         .parent         = &core_48m_fck,
1548         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1549         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1550         .flags          = CLOCK_IN_OMAP343X,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk mcspi1_fck = {
1555         .name           = "mcspi_fck",
1556         .id             = 1,
1557         .parent         = &core_48m_fck,
1558         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1560         .flags          = CLOCK_IN_OMAP343X,
1561         .recalc         = &followparent_recalc,
1562 };
1563
1564 static struct clk uart2_fck = {
1565         .name           = "uart2_fck",
1566         .parent         = &core_48m_fck,
1567         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1568         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1569         .flags          = CLOCK_IN_OMAP343X,
1570         .recalc         = &followparent_recalc,
1571 };
1572
1573 static struct clk uart1_fck = {
1574         .name           = "uart1_fck",
1575         .parent         = &core_48m_fck,
1576         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1578         .flags          = CLOCK_IN_OMAP343X,
1579         .recalc         = &followparent_recalc,
1580 };
1581
1582 static struct clk fshostusb_fck = {
1583         .name           = "fshostusb_fck",
1584         .parent         = &core_48m_fck,
1585         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1587         .flags          = CLOCK_IN_OMAP3430ES1,
1588         .recalc         = &followparent_recalc,
1589 };
1590
1591 /* CORE_12M_FCK based clocks */
1592
1593 static struct clk core_12m_fck = {
1594         .name           = "core_12m_fck",
1595         .parent         = &omap_12m_fck,
1596         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1597                                 PARENT_CONTROLS_CLOCK,
1598         .clkdm_name     = "core_l4_clkdm",
1599         .recalc         = &followparent_recalc,
1600 };
1601
1602 static struct clk hdq_fck = {
1603         .name           = "hdq_fck",
1604         .parent         = &core_12m_fck,
1605         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1606         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1607         .flags          = CLOCK_IN_OMAP343X,
1608         .recalc         = &followparent_recalc,
1609 };
1610
1611 /* DPLL3-derived clock */
1612
1613 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1614         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1615         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1616         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1617         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1618         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1619         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1620         { .div = 0 }
1621 };
1622
1623 static const struct clksel ssi_ssr_clksel[] = {
1624         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1625         { .parent = NULL }
1626 };
1627
1628 static struct clk ssi_ssr_fck = {
1629         .name           = "ssi_ssr_fck",
1630         .init           = &omap2_init_clksel_parent,
1631         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1632         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1633         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1634         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1635         .clksel         = ssi_ssr_clksel,
1636         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1637         .clkdm_name     = "core_l4_clkdm",
1638         .recalc         = &omap2_clksel_recalc,
1639 };
1640
1641 static struct clk ssi_sst_fck = {
1642         .name           = "ssi_sst_fck",
1643         .parent         = &ssi_ssr_fck,
1644         .fixed_div      = 2,
1645         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1646         .recalc         = &omap2_fixed_divisor_recalc,
1647 };
1648
1649
1650
1651 /* CORE_L3_ICK based clocks */
1652
1653 /*
1654  * XXX must add clk_enable/clk_disable for these if standard code won't
1655  * handle it
1656  */
1657 static struct clk core_l3_ick = {
1658         .name           = "core_l3_ick",
1659         .parent         = &l3_ick,
1660         .init           = &omap2_init_clk_clkdm,
1661         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1662                                 PARENT_CONTROLS_CLOCK,
1663         .clkdm_name     = "core_l3_clkdm",
1664         .recalc         = &followparent_recalc,
1665 };
1666
1667 static struct clk hsotgusb_ick = {
1668         .name           = "hsotgusb_ick",
1669         .parent         = &core_l3_ick,
1670         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1671         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1672         .flags          = CLOCK_IN_OMAP343X,
1673         .clkdm_name     = "core_l3_clkdm",
1674         .recalc         = &followparent_recalc,
1675 };
1676
1677 static struct clk sdrc_ick = {
1678         .name           = "sdrc_ick",
1679         .parent         = &core_l3_ick,
1680         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1681         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1682         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1683         .clkdm_name     = "core_l3_clkdm",
1684         .recalc         = &followparent_recalc,
1685 };
1686
1687 static struct clk gpmc_fck = {
1688         .name           = "gpmc_fck",
1689         .parent         = &core_l3_ick,
1690         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1691                                 ENABLE_ON_INIT,
1692         .clkdm_name     = "core_l3_clkdm",
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 /* SECURITY_L3_ICK based clocks */
1697
1698 static struct clk security_l3_ick = {
1699         .name           = "security_l3_ick",
1700         .parent         = &l3_ick,
1701         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1702                                 PARENT_CONTROLS_CLOCK,
1703         .recalc         = &followparent_recalc,
1704 };
1705
1706 static struct clk pka_ick = {
1707         .name           = "pka_ick",
1708         .parent         = &security_l3_ick,
1709         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1710         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1711         .flags          = CLOCK_IN_OMAP343X,
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 /* CORE_L4_ICK based clocks */
1716
1717 static struct clk core_l4_ick = {
1718         .name           = "core_l4_ick",
1719         .parent         = &l4_ick,
1720         .init           = &omap2_init_clk_clkdm,
1721         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1722                                 PARENT_CONTROLS_CLOCK,
1723         .clkdm_name     = "core_l4_clkdm",
1724         .recalc         = &followparent_recalc,
1725 };
1726
1727 static struct clk usbtll_ick = {
1728         .name           = "usbtll_ick",
1729         .parent         = &core_l4_ick,
1730         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1731         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1732         .flags          = CLOCK_IN_OMAP3430ES2,
1733         .clkdm_name     = "core_l4_clkdm",
1734         .recalc         = &followparent_recalc,
1735 };
1736
1737 static struct clk mmchs3_ick = {
1738         .name           = "mmchs_ick",
1739         .id             = 3,
1740         .parent         = &core_l4_ick,
1741         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1743         .flags          = CLOCK_IN_OMAP3430ES2,
1744         .clkdm_name     = "core_l4_clkdm",
1745         .recalc         = &followparent_recalc,
1746 };
1747
1748 /* Intersystem Communication Registers - chassis mode only */
1749 static struct clk icr_ick = {
1750         .name           = "icr_ick",
1751         .parent         = &core_l4_ick,
1752         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1753         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1754         .flags          = CLOCK_IN_OMAP343X,
1755         .clkdm_name     = "core_l4_clkdm",
1756         .recalc         = &followparent_recalc,
1757 };
1758
1759 static struct clk aes2_ick = {
1760         .name           = "aes2_ick",
1761         .parent         = &core_l4_ick,
1762         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1763         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1764         .flags          = CLOCK_IN_OMAP343X,
1765         .clkdm_name     = "core_l4_clkdm",
1766         .recalc         = &followparent_recalc,
1767 };
1768
1769 static struct clk sha12_ick = {
1770         .name           = "sha12_ick",
1771         .parent         = &core_l4_ick,
1772         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1773         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1774         .flags          = CLOCK_IN_OMAP343X,
1775         .clkdm_name     = "core_l4_clkdm",
1776         .recalc         = &followparent_recalc,
1777 };
1778
1779 static struct clk des2_ick = {
1780         .name           = "des2_ick",
1781         .parent         = &core_l4_ick,
1782         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1783         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1784         .flags          = CLOCK_IN_OMAP343X,
1785         .clkdm_name     = "core_l4_clkdm",
1786         .recalc         = &followparent_recalc,
1787 };
1788
1789 static struct clk mmchs2_ick = {
1790         .name           = "mmchs_ick",
1791         .id             = 2,
1792         .parent         = &core_l4_ick,
1793         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1794         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1795         .flags          = CLOCK_IN_OMAP343X,
1796         .clkdm_name     = "core_l4_clkdm",
1797         .recalc         = &followparent_recalc,
1798 };
1799
1800 static struct clk mmchs1_ick = {
1801         .name           = "mmchs_ick",
1802         .id             = 1,
1803         .parent         = &core_l4_ick,
1804         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1805         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1806         .flags          = CLOCK_IN_OMAP343X,
1807         .clkdm_name     = "core_l4_clkdm",
1808         .recalc         = &followparent_recalc,
1809 };
1810
1811 static struct clk mspro_ick = {
1812         .name           = "mspro_ick",
1813         .parent         = &core_l4_ick,
1814         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1816         .flags          = CLOCK_IN_OMAP343X,
1817         .clkdm_name     = "core_l4_clkdm",
1818         .recalc         = &followparent_recalc,
1819 };
1820
1821 static struct clk hdq_ick = {
1822         .name           = "hdq_ick",
1823         .parent         = &core_l4_ick,
1824         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1825         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1826         .flags          = CLOCK_IN_OMAP343X,
1827         .clkdm_name     = "core_l4_clkdm",
1828         .recalc         = &followparent_recalc,
1829 };
1830
1831 static struct clk mcspi4_ick = {
1832         .name           = "mcspi_ick",
1833         .id             = 4,
1834         .parent         = &core_l4_ick,
1835         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1836         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1837         .flags          = CLOCK_IN_OMAP343X,
1838         .clkdm_name     = "core_l4_clkdm",
1839         .recalc         = &followparent_recalc,
1840 };
1841
1842 static struct clk mcspi3_ick = {
1843         .name           = "mcspi_ick",
1844         .id             = 3,
1845         .parent         = &core_l4_ick,
1846         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1848         .flags          = CLOCK_IN_OMAP343X,
1849         .clkdm_name     = "core_l4_clkdm",
1850         .recalc         = &followparent_recalc,
1851 };
1852
1853 static struct clk mcspi2_ick = {
1854         .name           = "mcspi_ick",
1855         .id             = 2,
1856         .parent         = &core_l4_ick,
1857         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1858         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1859         .flags          = CLOCK_IN_OMAP343X,
1860         .clkdm_name     = "core_l4_clkdm",
1861         .recalc         = &followparent_recalc,
1862 };
1863
1864 static struct clk mcspi1_ick = {
1865         .name           = "mcspi_ick",
1866         .id             = 1,
1867         .parent         = &core_l4_ick,
1868         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1869         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1870         .flags          = CLOCK_IN_OMAP343X,
1871         .clkdm_name     = "core_l4_clkdm",
1872         .recalc         = &followparent_recalc,
1873 };
1874
1875 static struct clk i2c3_ick = {
1876         .name           = "i2c_ick",
1877         .id             = 3,
1878         .parent         = &core_l4_ick,
1879         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1880         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1881         .flags          = CLOCK_IN_OMAP343X,
1882         .clkdm_name     = "core_l4_clkdm",
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk i2c2_ick = {
1887         .name           = "i2c_ick",
1888         .id             = 2,
1889         .parent         = &core_l4_ick,
1890         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1891         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1892         .flags          = CLOCK_IN_OMAP343X,
1893         .clkdm_name     = "core_l4_clkdm",
1894         .recalc         = &followparent_recalc,
1895 };
1896
1897 static struct clk i2c1_ick = {
1898         .name           = "i2c_ick",
1899         .id             = 1,
1900         .parent         = &core_l4_ick,
1901         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1903         .flags          = CLOCK_IN_OMAP343X,
1904         .clkdm_name     = "core_l4_clkdm",
1905         .recalc         = &followparent_recalc,
1906 };
1907
1908 static struct clk uart2_ick = {
1909         .name           = "uart2_ick",
1910         .parent         = &core_l4_ick,
1911         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1913         .flags          = CLOCK_IN_OMAP343X,
1914         .clkdm_name     = "core_l4_clkdm",
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk uart1_ick = {
1919         .name           = "uart1_ick",
1920         .parent         = &core_l4_ick,
1921         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1923         .flags          = CLOCK_IN_OMAP343X,
1924         .clkdm_name     = "core_l4_clkdm",
1925         .recalc         = &followparent_recalc,
1926 };
1927
1928 static struct clk gpt11_ick = {
1929         .name           = "gpt11_ick",
1930         .parent         = &core_l4_ick,
1931         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1932         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1933         .flags          = CLOCK_IN_OMAP343X,
1934         .clkdm_name     = "core_l4_clkdm",
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk gpt10_ick = {
1939         .name           = "gpt10_ick",
1940         .parent         = &core_l4_ick,
1941         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1942         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1943         .flags          = CLOCK_IN_OMAP343X,
1944         .clkdm_name     = "core_l4_clkdm",
1945         .recalc         = &followparent_recalc,
1946 };
1947
1948 static struct clk mcbsp5_ick = {
1949         .name           = "mcbsp_ick",
1950         .id             = 5,
1951         .parent         = &core_l4_ick,
1952         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1953         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1954         .flags          = CLOCK_IN_OMAP343X,
1955         .clkdm_name     = "core_l4_clkdm",
1956         .recalc         = &followparent_recalc,
1957 };
1958
1959 static struct clk mcbsp1_ick = {
1960         .name           = "mcbsp_ick",
1961         .id             = 1,
1962         .parent         = &core_l4_ick,
1963         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1964         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1965         .flags          = CLOCK_IN_OMAP343X,
1966         .clkdm_name     = "core_l4_clkdm",
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk fac_ick = {
1971         .name           = "fac_ick",
1972         .parent         = &core_l4_ick,
1973         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1974         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1975         .flags          = CLOCK_IN_OMAP3430ES1,
1976         .clkdm_name     = "core_l4_clkdm",
1977         .recalc         = &followparent_recalc,
1978 };
1979
1980 static struct clk mailboxes_ick = {
1981         .name           = "mailboxes_ick",
1982         .parent         = &core_l4_ick,
1983         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1984         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1985         .flags          = CLOCK_IN_OMAP343X,
1986         .clkdm_name     = "core_l4_clkdm",
1987         .recalc         = &followparent_recalc,
1988 };
1989
1990 static struct clk omapctrl_ick = {
1991         .name           = "omapctrl_ick",
1992         .parent         = &core_l4_ick,
1993         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1994         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1995         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1996         .recalc         = &followparent_recalc,
1997 };
1998
1999 /* SSI_L4_ICK based clocks */
2000
2001 static struct clk ssi_l4_ick = {
2002         .name           = "ssi_l4_ick",
2003         .parent         = &l4_ick,
2004         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2005                                 PARENT_CONTROLS_CLOCK,
2006         .clkdm_name     = "core_l4_clkdm",
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 static struct clk ssi_ick = {
2011         .name           = "ssi_ick",
2012         .parent         = &ssi_l4_ick,
2013         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2014         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2015         .flags          = CLOCK_IN_OMAP343X,
2016         .clkdm_name     = "core_l4_clkdm",
2017         .recalc         = &followparent_recalc,
2018 };
2019
2020 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2021  * but l4_ick makes more sense to me */
2022
2023 static const struct clksel usb_l4_clksel[] = {
2024         { .parent = &l4_ick, .rates = div2_rates },
2025         { .parent = NULL },
2026 };
2027
2028 static struct clk usb_l4_ick = {
2029         .name           = "usb_l4_ick",
2030         .parent         = &l4_ick,
2031         .init           = &omap2_init_clksel_parent,
2032         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2033         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2034         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2035         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2036         .clksel         = usb_l4_clksel,
2037         .flags          = CLOCK_IN_OMAP3430ES1,
2038         .recalc         = &omap2_clksel_recalc,
2039 };
2040
2041 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2042
2043 /* SECURITY_L4_ICK2 based clocks */
2044
2045 static struct clk security_l4_ick2 = {
2046         .name           = "security_l4_ick2",
2047         .parent         = &l4_ick,
2048         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2049                                 PARENT_CONTROLS_CLOCK,
2050         .recalc         = &followparent_recalc,
2051 };
2052
2053 static struct clk aes1_ick = {
2054         .name           = "aes1_ick",
2055         .parent         = &security_l4_ick2,
2056         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2057         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2058         .flags          = CLOCK_IN_OMAP343X,
2059         .recalc         = &followparent_recalc,
2060 };
2061
2062 static struct clk rng_ick = {
2063         .name           = "rng_ick",
2064         .parent         = &security_l4_ick2,
2065         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2066         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2067         .flags          = CLOCK_IN_OMAP343X,
2068         .recalc         = &followparent_recalc,
2069 };
2070
2071 static struct clk sha11_ick = {
2072         .name           = "sha11_ick",
2073         .parent         = &security_l4_ick2,
2074         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2075         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2076         .flags          = CLOCK_IN_OMAP343X,
2077         .recalc         = &followparent_recalc,
2078 };
2079
2080 static struct clk des1_ick = {
2081         .name           = "des1_ick",
2082         .parent         = &security_l4_ick2,
2083         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2084         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2085         .flags          = CLOCK_IN_OMAP343X,
2086         .recalc         = &followparent_recalc,
2087 };
2088
2089 /* DSS */
2090 static const struct clksel dss1_alwon_fck_clksel[] = {
2091         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2092         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2093         { .parent = NULL }
2094 };
2095
2096 static struct clk dss1_alwon_fck = {
2097         .name           = "dss1_alwon_fck",
2098         .parent         = &dpll4_m4x2_ck,
2099         .init           = &omap2_init_clksel_parent,
2100         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2101         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2102         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2103         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2104         .clksel         = dss1_alwon_fck_clksel,
2105         .flags          = CLOCK_IN_OMAP343X,
2106         .clkdm_name     = "dss_clkdm",
2107         .recalc         = &omap2_clksel_recalc,
2108 };
2109
2110 static struct clk dss_tv_fck = {
2111         .name           = "dss_tv_fck",
2112         .parent         = &omap_54m_fck,
2113         .init           = &omap2_init_clk_clkdm,
2114         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2115         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2116         .flags          = CLOCK_IN_OMAP343X,
2117         .clkdm_name     = "dss_clkdm",
2118         .recalc         = &followparent_recalc,
2119 };
2120
2121 static struct clk dss_96m_fck = {
2122         .name           = "dss_96m_fck",
2123         .parent         = &omap_96m_fck,
2124         .init           = &omap2_init_clk_clkdm,
2125         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2126         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2127         .flags          = CLOCK_IN_OMAP343X,
2128         .clkdm_name     = "dss_clkdm",
2129         .recalc         = &followparent_recalc,
2130 };
2131
2132 static struct clk dss2_alwon_fck = {
2133         .name           = "dss2_alwon_fck",
2134         .parent         = &sys_ck,
2135         .init           = &omap2_init_clk_clkdm,
2136         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2137         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2138         .flags          = CLOCK_IN_OMAP343X,
2139         .clkdm_name     = "dss_clkdm",
2140         .recalc         = &followparent_recalc,
2141 };
2142
2143 static struct clk dss_ick = {
2144         /* Handles both L3 and L4 clocks */
2145         .name           = "dss_ick",
2146         .parent         = &l4_ick,
2147         .init           = &omap2_init_clk_clkdm,
2148         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2149         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2150         .flags          = CLOCK_IN_OMAP343X,
2151         .clkdm_name     = "dss_clkdm",
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 /* CAM */
2156
2157 static const struct clksel cam_mclk_clksel[] = {
2158         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2159         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2160         { .parent = NULL }
2161 };
2162
2163 static struct clk cam_mclk = {
2164         .name           = "cam_mclk",
2165         .parent         = &dpll4_m5x2_ck,
2166         .init           = &omap2_init_clksel_parent,
2167         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2168         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2169         .clksel         = cam_mclk_clksel,
2170         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2171         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2172         .flags          = CLOCK_IN_OMAP343X,
2173         .clkdm_name     = "cam_clkdm",
2174         .recalc         = &omap2_clksel_recalc,
2175 };
2176
2177 static struct clk cam_ick = {
2178         /* Handles both L3 and L4 clocks */
2179         .name           = "cam_ick",
2180         .parent         = &l4_ick,
2181         .init           = &omap2_init_clk_clkdm,
2182         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2183         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2184         .flags          = CLOCK_IN_OMAP343X,
2185         .clkdm_name     = "cam_clkdm",
2186         .recalc         = &followparent_recalc,
2187 };
2188
2189 /* USBHOST - 3430ES2 only */
2190
2191 static struct clk usbhost_120m_fck = {
2192         .name           = "usbhost_120m_fck",
2193         .parent         = &omap_120m_fck,
2194         .init           = &omap2_init_clk_clkdm,
2195         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2196         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2197         .flags          = CLOCK_IN_OMAP3430ES2,
2198         .clkdm_name     = "usbhost_clkdm",
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk usbhost_48m_fck = {
2203         .name           = "usbhost_48m_fck",
2204         .parent         = &omap_48m_fck,
2205         .init           = &omap2_init_clk_clkdm,
2206         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2207         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2208         .flags          = CLOCK_IN_OMAP3430ES2,
2209         .clkdm_name     = "usbhost_clkdm",
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 static struct clk usbhost_ick = {
2214         /* Handles both L3 and L4 clocks */
2215         .name           = "usbhost_ick",
2216         .parent         = &l4_ick,
2217         .init           = &omap2_init_clk_clkdm,
2218         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2219         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2220         .flags          = CLOCK_IN_OMAP3430ES2,
2221         .clkdm_name     = "usbhost_clkdm",
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk usbhost_sar_fck = {
2226         .name           = "usbhost_sar_fck",
2227         .parent         = &osc_sys_ck,
2228         .init           = &omap2_init_clk_clkdm,
2229         .enable_reg     = OMAP34XX_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2230         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2231         .flags          = CLOCK_IN_OMAP3430ES2,
2232         .clkdm_name     = "usbhost_clkdm",
2233         .recalc         = &followparent_recalc,
2234 };
2235
2236 /* WKUP */
2237
2238 static const struct clksel_rate usim_96m_rates[] = {
2239         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2240         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2241         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2242         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2243         { .div = 0 },
2244 };
2245
2246 static const struct clksel_rate usim_120m_rates[] = {
2247         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2248         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2249         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2250         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2251         { .div = 0 },
2252 };
2253
2254 static const struct clksel usim_clksel[] = {
2255         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2256         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2257         { .parent = &sys_ck,            .rates = div2_rates },
2258         { .parent = NULL },
2259 };
2260
2261 /* 3430ES2 only */
2262 static struct clk usim_fck = {
2263         .name           = "usim_fck",
2264         .init           = &omap2_init_clksel_parent,
2265         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2266         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2267         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2268         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2269         .clksel         = usim_clksel,
2270         .flags          = CLOCK_IN_OMAP3430ES2,
2271         .recalc         = &omap2_clksel_recalc,
2272 };
2273
2274 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2275 static struct clk gpt1_fck = {
2276         .name           = "gpt1_fck",
2277         .init           = &omap2_init_clksel_parent,
2278         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2279         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2280         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2281         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2282         .clksel         = omap343x_gpt_clksel,
2283         .flags          = CLOCK_IN_OMAP343X,
2284         .clkdm_name     = "wkup_clkdm",
2285         .recalc         = &omap2_clksel_recalc,
2286 };
2287
2288 static struct clk wkup_32k_fck = {
2289         .name           = "wkup_32k_fck",
2290         .init           = &omap2_init_clk_clkdm,
2291         .parent         = &omap_32k_fck,
2292         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2293         .clkdm_name     = "wkup_clkdm",
2294         .recalc         = &followparent_recalc,
2295 };
2296
2297 static struct clk gpio1_fck = {
2298         .name           = "gpio1_fck",
2299         .parent         = &wkup_32k_fck,
2300         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2301         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2302         .flags          = CLOCK_IN_OMAP343X,
2303         .clkdm_name     = "wkup_clkdm",
2304         .recalc         = &followparent_recalc,
2305 };
2306
2307 static struct clk wdt2_fck = {
2308         .name           = "wdt2_fck",
2309         .parent         = &wkup_32k_fck,
2310         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2311         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2312         .flags          = CLOCK_IN_OMAP343X,
2313         .clkdm_name     = "wkup_clkdm",
2314         .recalc         = &followparent_recalc,
2315 };
2316
2317 static struct clk wkup_l4_ick = {
2318         .name           = "wkup_l4_ick",
2319         .parent         = &sys_ck,
2320         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2321         .clkdm_name     = "wkup_clkdm",
2322         .recalc         = &followparent_recalc,
2323 };
2324
2325 /* 3430ES2 only */
2326 /* Never specifically named in the TRM, so we have to infer a likely name */
2327 static struct clk usim_ick = {
2328         .name           = "usim_ick",
2329         .parent         = &wkup_l4_ick,
2330         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2331         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2332         .flags          = CLOCK_IN_OMAP3430ES2,
2333         .clkdm_name     = "wkup_clkdm",
2334         .recalc         = &followparent_recalc,
2335 };
2336
2337 static struct clk wdt2_ick = {
2338         .name           = "wdt2_ick",
2339         .parent         = &wkup_l4_ick,
2340         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2341         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2342         .flags          = CLOCK_IN_OMAP343X,
2343         .clkdm_name     = "wkup_clkdm",
2344         .recalc         = &followparent_recalc,
2345 };
2346
2347 static struct clk wdt1_ick = {
2348         .name           = "wdt1_ick",
2349         .parent         = &wkup_l4_ick,
2350         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2351         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2352         .flags          = CLOCK_IN_OMAP343X,
2353         .clkdm_name     = "wkup_clkdm",
2354         .recalc         = &followparent_recalc,
2355 };
2356
2357 static struct clk gpio1_ick = {
2358         .name           = "gpio1_ick",
2359         .parent         = &wkup_l4_ick,
2360         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2361         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2362         .flags          = CLOCK_IN_OMAP343X,
2363         .clkdm_name     = "wkup_clkdm",
2364         .recalc         = &followparent_recalc,
2365 };
2366
2367 static struct clk omap_32ksync_ick = {
2368         .name           = "omap_32ksync_ick",
2369         .parent         = &wkup_l4_ick,
2370         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2371         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2372         .flags          = CLOCK_IN_OMAP343X,
2373         .clkdm_name     = "wkup_clkdm",
2374         .recalc         = &followparent_recalc,
2375 };
2376
2377 /* XXX This clock no longer exists in 3430 TRM rev F */
2378 static struct clk gpt12_ick = {
2379         .name           = "gpt12_ick",
2380         .parent         = &wkup_l4_ick,
2381         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2382         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2383         .flags          = CLOCK_IN_OMAP343X,
2384         .clkdm_name     = "wkup_clkdm",
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk gpt1_ick = {
2389         .name           = "gpt1_ick",
2390         .parent         = &wkup_l4_ick,
2391         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2392         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2393         .flags          = CLOCK_IN_OMAP343X,
2394         .clkdm_name     = "wkup_clkdm",
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398
2399
2400 /* PER clock domain */
2401
2402 static struct clk per_96m_fck = {
2403         .name           = "per_96m_fck",
2404         .parent         = &omap_96m_alwon_fck,
2405         .init           = &omap2_init_clk_clkdm,
2406         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2407                                 PARENT_CONTROLS_CLOCK,
2408         .clkdm_name     = "per_clkdm",
2409         .recalc         = &followparent_recalc,
2410 };
2411
2412 static struct clk per_48m_fck = {
2413         .name           = "per_48m_fck",
2414         .parent         = &omap_48m_fck,
2415         .init           = &omap2_init_clk_clkdm,
2416         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2417                                 PARENT_CONTROLS_CLOCK,
2418         .clkdm_name     = "per_clkdm",
2419         .recalc         = &followparent_recalc,
2420 };
2421
2422 static struct clk uart3_fck = {
2423         .name           = "uart3_fck",
2424         .parent         = &per_48m_fck,
2425         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2426         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2427         .flags          = CLOCK_IN_OMAP343X,
2428         .clkdm_name     = "per_clkdm",
2429         .recalc         = &followparent_recalc,
2430 };
2431
2432 static struct clk gpt2_fck = {
2433         .name           = "gpt2_fck",
2434         .init           = &omap2_init_clksel_parent,
2435         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2436         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2437         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2438         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2439         .clksel         = omap343x_gpt_clksel,
2440         .flags          = CLOCK_IN_OMAP343X,
2441         .clkdm_name     = "per_clkdm",
2442         .recalc         = &omap2_clksel_recalc,
2443 };
2444
2445 static struct clk gpt3_fck = {
2446         .name           = "gpt3_fck",
2447         .init           = &omap2_init_clksel_parent,
2448         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2449         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2450         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2451         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2452         .clksel         = omap343x_gpt_clksel,
2453         .flags          = CLOCK_IN_OMAP343X,
2454         .clkdm_name     = "per_clkdm",
2455         .recalc         = &omap2_clksel_recalc,
2456 };
2457
2458 static struct clk gpt4_fck = {
2459         .name           = "gpt4_fck",
2460         .init           = &omap2_init_clksel_parent,
2461         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2462         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2463         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2464         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2465         .clksel         = omap343x_gpt_clksel,
2466         .flags          = CLOCK_IN_OMAP343X,
2467         .clkdm_name     = "per_clkdm",
2468         .recalc         = &omap2_clksel_recalc,
2469 };
2470
2471 static struct clk gpt5_fck = {
2472         .name           = "gpt5_fck",
2473         .init           = &omap2_init_clksel_parent,
2474         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2475         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2476         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2477         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2478         .clksel         = omap343x_gpt_clksel,
2479         .flags          = CLOCK_IN_OMAP343X,
2480         .clkdm_name     = "per_clkdm",
2481         .recalc         = &omap2_clksel_recalc,
2482 };
2483
2484 static struct clk gpt6_fck = {
2485         .name           = "gpt6_fck",
2486         .init           = &omap2_init_clksel_parent,
2487         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2488         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2489         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2490         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2491         .clksel         = omap343x_gpt_clksel,
2492         .flags          = CLOCK_IN_OMAP343X,
2493         .clkdm_name     = "per_clkdm",
2494         .recalc         = &omap2_clksel_recalc,
2495 };
2496
2497 static struct clk gpt7_fck = {
2498         .name           = "gpt7_fck",
2499         .init           = &omap2_init_clksel_parent,
2500         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2501         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2502         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2503         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2504         .clksel         = omap343x_gpt_clksel,
2505         .flags          = CLOCK_IN_OMAP343X,
2506         .clkdm_name     = "per_clkdm",
2507         .recalc         = &omap2_clksel_recalc,
2508 };
2509
2510 static struct clk gpt8_fck = {
2511         .name           = "gpt8_fck",
2512         .init           = &omap2_init_clksel_parent,
2513         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2514         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2515         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2516         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2517         .clksel         = omap343x_gpt_clksel,
2518         .flags          = CLOCK_IN_OMAP343X,
2519         .clkdm_name     = "per_clkdm",
2520         .recalc         = &omap2_clksel_recalc,
2521 };
2522
2523 static struct clk gpt9_fck = {
2524         .name           = "gpt9_fck",
2525         .init           = &omap2_init_clksel_parent,
2526         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2527         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2528         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2529         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2530         .clksel         = omap343x_gpt_clksel,
2531         .flags          = CLOCK_IN_OMAP343X,
2532         .clkdm_name     = "per_clkdm",
2533         .recalc         = &omap2_clksel_recalc,
2534 };
2535
2536 static struct clk per_32k_alwon_fck = {
2537         .name           = "per_32k_alwon_fck",
2538         .parent         = &omap_32k_fck,
2539         .clkdm_name     = "per_clkdm",
2540         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2541         .recalc         = &followparent_recalc,
2542 };
2543
2544 static struct clk gpio6_fck = {
2545         .name           = "gpio6_fck",
2546         .parent         = &per_32k_alwon_fck,
2547         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2548         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2549         .flags          = CLOCK_IN_OMAP343X,
2550         .clkdm_name     = "per_clkdm",
2551         .recalc         = &followparent_recalc,
2552 };
2553
2554 static struct clk gpio5_fck = {
2555         .name           = "gpio5_fck",
2556         .parent         = &per_32k_alwon_fck,
2557         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2558         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2559         .flags          = CLOCK_IN_OMAP343X,
2560         .clkdm_name     = "per_clkdm",
2561         .recalc         = &followparent_recalc,
2562 };
2563
2564 static struct clk gpio4_fck = {
2565         .name           = "gpio4_fck",
2566         .parent         = &per_32k_alwon_fck,
2567         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2568         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2569         .flags          = CLOCK_IN_OMAP343X,
2570         .clkdm_name     = "per_clkdm",
2571         .recalc         = &followparent_recalc,
2572 };
2573
2574 static struct clk gpio3_fck = {
2575         .name           = "gpio3_fck",
2576         .parent         = &per_32k_alwon_fck,
2577         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2578         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2579         .flags          = CLOCK_IN_OMAP343X,
2580         .clkdm_name     = "per_clkdm",
2581         .recalc         = &followparent_recalc,
2582 };
2583
2584 static struct clk gpio2_fck = {
2585         .name           = "gpio2_fck",
2586         .parent         = &per_32k_alwon_fck,
2587         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2588         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2589         .flags          = CLOCK_IN_OMAP343X,
2590         .clkdm_name     = "per_clkdm",
2591         .recalc         = &followparent_recalc,
2592 };
2593
2594 static struct clk wdt3_fck = {
2595         .name           = "wdt3_fck",
2596         .parent         = &per_32k_alwon_fck,
2597         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2598         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2599         .flags          = CLOCK_IN_OMAP343X,
2600         .clkdm_name     = "per_clkdm",
2601         .recalc         = &followparent_recalc,
2602 };
2603
2604 static struct clk per_l4_ick = {
2605         .name           = "per_l4_ick",
2606         .parent         = &l4_ick,
2607         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2608                                 PARENT_CONTROLS_CLOCK,
2609         .clkdm_name     = "per_clkdm",
2610         .recalc         = &followparent_recalc,
2611 };
2612
2613 static struct clk gpio6_ick = {
2614         .name           = "gpio6_ick",
2615         .parent         = &per_l4_ick,
2616         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2617         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2618         .flags          = CLOCK_IN_OMAP343X,
2619         .clkdm_name     = "per_clkdm",
2620         .recalc         = &followparent_recalc,
2621 };
2622
2623 static struct clk gpio5_ick = {
2624         .name           = "gpio5_ick",
2625         .parent         = &per_l4_ick,
2626         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2627         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2628         .flags          = CLOCK_IN_OMAP343X,
2629         .clkdm_name     = "per_clkdm",
2630         .recalc         = &followparent_recalc,
2631 };
2632
2633 static struct clk gpio4_ick = {
2634         .name           = "gpio4_ick",
2635         .parent         = &per_l4_ick,
2636         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2637         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2638         .flags          = CLOCK_IN_OMAP343X,
2639         .clkdm_name     = "per_clkdm",
2640         .recalc         = &followparent_recalc,
2641 };
2642
2643 static struct clk gpio3_ick = {
2644         .name           = "gpio3_ick",
2645         .parent         = &per_l4_ick,
2646         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2647         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2648         .flags          = CLOCK_IN_OMAP343X,
2649         .clkdm_name     = "per_clkdm",
2650         .recalc         = &followparent_recalc,
2651 };
2652
2653 static struct clk gpio2_ick = {
2654         .name           = "gpio2_ick",
2655         .parent         = &per_l4_ick,
2656         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2657         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2658         .flags          = CLOCK_IN_OMAP343X,
2659         .clkdm_name     = "per_clkdm",
2660         .recalc         = &followparent_recalc,
2661 };
2662
2663 static struct clk wdt3_ick = {
2664         .name           = "wdt3_ick",
2665         .parent         = &per_l4_ick,
2666         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2667         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2668         .flags          = CLOCK_IN_OMAP343X,
2669         .clkdm_name     = "per_clkdm",
2670         .recalc         = &followparent_recalc,
2671 };
2672
2673 static struct clk uart3_ick = {
2674         .name           = "uart3_ick",
2675         .parent         = &per_l4_ick,
2676         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2677         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2678         .flags          = CLOCK_IN_OMAP343X,
2679         .clkdm_name     = "per_clkdm",
2680         .recalc         = &followparent_recalc,
2681 };
2682
2683 static struct clk gpt9_ick = {
2684         .name           = "gpt9_ick",
2685         .parent         = &per_l4_ick,
2686         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2687         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2688         .flags          = CLOCK_IN_OMAP343X,
2689         .clkdm_name     = "per_clkdm",
2690         .recalc         = &followparent_recalc,
2691 };
2692
2693 static struct clk gpt8_ick = {
2694         .name           = "gpt8_ick",
2695         .parent         = &per_l4_ick,
2696         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2697         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2698         .flags          = CLOCK_IN_OMAP343X,
2699         .clkdm_name     = "per_clkdm",
2700         .recalc         = &followparent_recalc,
2701 };
2702
2703 static struct clk gpt7_ick = {
2704         .name           = "gpt7_ick",
2705         .parent         = &per_l4_ick,
2706         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2707         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2708         .flags          = CLOCK_IN_OMAP343X,
2709         .clkdm_name     = "per_clkdm",
2710         .recalc         = &followparent_recalc,
2711 };
2712
2713 static struct clk gpt6_ick = {
2714         .name           = "gpt6_ick",
2715         .parent         = &per_l4_ick,
2716         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2717         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2718         .flags          = CLOCK_IN_OMAP343X,
2719         .clkdm_name     = "per_clkdm",
2720         .recalc         = &followparent_recalc,
2721 };
2722
2723 static struct clk gpt5_ick = {
2724         .name           = "gpt5_ick",
2725         .parent         = &per_l4_ick,
2726         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2727         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2728         .flags          = CLOCK_IN_OMAP343X,
2729         .clkdm_name     = "per_clkdm",
2730         .recalc         = &followparent_recalc,
2731 };
2732
2733 static struct clk gpt4_ick = {
2734         .name           = "gpt4_ick",
2735         .parent         = &per_l4_ick,
2736         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2737         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2738         .flags          = CLOCK_IN_OMAP343X,
2739         .clkdm_name     = "per_clkdm",
2740         .recalc         = &followparent_recalc,
2741 };
2742
2743 static struct clk gpt3_ick = {
2744         .name           = "gpt3_ick",
2745         .parent         = &per_l4_ick,
2746         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2747         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2748         .flags          = CLOCK_IN_OMAP343X,
2749         .clkdm_name     = "per_clkdm",
2750         .recalc         = &followparent_recalc,
2751 };
2752
2753 static struct clk gpt2_ick = {
2754         .name           = "gpt2_ick",
2755         .parent         = &per_l4_ick,
2756         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2757         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2758         .flags          = CLOCK_IN_OMAP343X,
2759         .clkdm_name     = "per_clkdm",
2760         .recalc         = &followparent_recalc,
2761 };
2762
2763 static struct clk mcbsp2_ick = {
2764         .name           = "mcbsp_ick",
2765         .id             = 2,
2766         .parent         = &per_l4_ick,
2767         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2768         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2769         .flags          = CLOCK_IN_OMAP343X,
2770         .clkdm_name     = "per_clkdm",
2771         .recalc         = &followparent_recalc,
2772 };
2773
2774 static struct clk mcbsp3_ick = {
2775         .name           = "mcbsp_ick",
2776         .id             = 3,
2777         .parent         = &per_l4_ick,
2778         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2780         .flags          = CLOCK_IN_OMAP343X,
2781         .clkdm_name     = "per_clkdm",
2782         .recalc         = &followparent_recalc,
2783 };
2784
2785 static struct clk mcbsp4_ick = {
2786         .name           = "mcbsp_ick",
2787         .id             = 4,
2788         .parent         = &per_l4_ick,
2789         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2790         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2791         .flags          = CLOCK_IN_OMAP343X,
2792         .clkdm_name     = "per_clkdm",
2793         .recalc         = &followparent_recalc,
2794 };
2795
2796 static const struct clksel mcbsp_234_clksel[] = {
2797         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2798         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2799         { .parent = NULL }
2800 };
2801
2802 static struct clk mcbsp2_fck = {
2803         .name           = "mcbsp_fck",
2804         .id             = 2,
2805         .init           = &omap2_init_clksel_parent,
2806         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2807         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2808         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2809         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2810         .clksel         = mcbsp_234_clksel,
2811         .flags          = CLOCK_IN_OMAP343X,
2812         .clkdm_name     = "per_clkdm",
2813         .recalc         = &omap2_clksel_recalc,
2814 };
2815
2816 static struct clk mcbsp3_fck = {
2817         .name           = "mcbsp_fck",
2818         .id             = 3,
2819         .init           = &omap2_init_clksel_parent,
2820         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2821         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2822         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2823         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2824         .clksel         = mcbsp_234_clksel,
2825         .flags          = CLOCK_IN_OMAP343X,
2826         .clkdm_name     = "per_clkdm",
2827         .recalc         = &omap2_clksel_recalc,
2828 };
2829
2830 static struct clk mcbsp4_fck = {
2831         .name           = "mcbsp_fck",
2832         .id             = 4,
2833         .init           = &omap2_init_clksel_parent,
2834         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2835         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2836         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2837         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2838         .clksel         = mcbsp_234_clksel,
2839         .flags          = CLOCK_IN_OMAP343X,
2840         .clkdm_name     = "per_clkdm",
2841         .recalc         = &omap2_clksel_recalc,
2842 };
2843
2844 /* EMU clocks */
2845
2846 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2847
2848 static const struct clksel_rate emu_src_sys_rates[] = {
2849         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2850         { .div = 0 },
2851 };
2852
2853 static const struct clksel_rate emu_src_core_rates[] = {
2854         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2855         { .div = 0 },
2856 };
2857
2858 static const struct clksel_rate emu_src_per_rates[] = {
2859         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2860         { .div = 0 },
2861 };
2862
2863 static const struct clksel_rate emu_src_mpu_rates[] = {
2864         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2865         { .div = 0 },
2866 };
2867
2868 static const struct clksel emu_src_clksel[] = {
2869         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2870         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2871         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2872         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2873         { .parent = NULL },
2874 };
2875
2876 /*
2877  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2878  * to switch the source of some of the EMU clocks.
2879  * XXX Are there CLKEN bits for these EMU clks?
2880  */
2881 static struct clk emu_src_ck = {
2882         .name           = "emu_src_ck",
2883         .init           = &omap2_init_clksel_parent,
2884         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2885         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2886         .clksel         = emu_src_clksel,
2887         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2888         .clkdm_name     = "emu_clkdm",
2889         .recalc         = &omap2_clksel_recalc,
2890 };
2891
2892 static const struct clksel_rate pclk_emu_rates[] = {
2893         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2894         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2895         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2896         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2897         { .div = 0 },
2898 };
2899
2900 static const struct clksel pclk_emu_clksel[] = {
2901         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2902         { .parent = NULL },
2903 };
2904
2905 static struct clk pclk_fck = {
2906         .name           = "pclk_fck",
2907         .init           = &omap2_init_clksel_parent,
2908         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2909         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2910         .clksel         = pclk_emu_clksel,
2911         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2912         .clkdm_name     = "emu_clkdm",
2913         .recalc         = &omap2_clksel_recalc,
2914 };
2915
2916 static const struct clksel_rate pclkx2_emu_rates[] = {
2917         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2918         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2919         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2920         { .div = 0 },
2921 };
2922
2923 static const struct clksel pclkx2_emu_clksel[] = {
2924         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2925         { .parent = NULL },
2926 };
2927
2928 static struct clk pclkx2_fck = {
2929         .name           = "pclkx2_fck",
2930         .init           = &omap2_init_clksel_parent,
2931         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2932         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2933         .clksel         = pclkx2_emu_clksel,
2934         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2935         .clkdm_name     = "emu_clkdm",
2936         .recalc         = &omap2_clksel_recalc,
2937 };
2938
2939 static const struct clksel atclk_emu_clksel[] = {
2940         { .parent = &emu_src_ck, .rates = div2_rates },
2941         { .parent = NULL },
2942 };
2943
2944 static struct clk atclk_fck = {
2945         .name           = "atclk_fck",
2946         .init           = &omap2_init_clksel_parent,
2947         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2948         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2949         .clksel         = atclk_emu_clksel,
2950         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2951         .clkdm_name     = "emu_clkdm",
2952         .recalc         = &omap2_clksel_recalc,
2953 };
2954
2955 static struct clk traceclk_src_fck = {
2956         .name           = "traceclk_src_fck",
2957         .init           = &omap2_init_clksel_parent,
2958         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2959         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2960         .clksel         = emu_src_clksel,
2961         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2962         .clkdm_name     = "emu_clkdm",
2963         .recalc         = &omap2_clksel_recalc,
2964 };
2965
2966 static const struct clksel_rate traceclk_rates[] = {
2967         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2968         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2969         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2970         { .div = 0 },
2971 };
2972
2973 static const struct clksel traceclk_clksel[] = {
2974         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2975         { .parent = NULL },
2976 };
2977
2978 static struct clk traceclk_fck = {
2979         .name           = "traceclk_fck",
2980         .init           = &omap2_init_clksel_parent,
2981         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2982         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2983         .clksel         = traceclk_clksel,
2984         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2985         .clkdm_name     = "emu_clkdm",
2986         .recalc         = &omap2_clksel_recalc,
2987 };
2988
2989 /* SR clocks */
2990
2991 /* SmartReflex fclk (VDD1) */
2992 static struct clk sr1_fck = {
2993         .name           = "sr1_fck",
2994         .parent         = &sys_ck,
2995         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2996         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2997         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2998         .recalc         = &followparent_recalc,
2999 };
3000
3001 /* SmartReflex fclk (VDD2) */
3002 static struct clk sr2_fck = {
3003         .name           = "sr2_fck",
3004         .parent         = &sys_ck,
3005         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3006         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3007         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3008         .recalc         = &followparent_recalc,
3009 };
3010
3011 static struct clk sr_l4_ick = {
3012         .name           = "sr_l4_ick",
3013         .parent         = &l4_ick,
3014         .flags          = CLOCK_IN_OMAP343X,
3015         .clkdm_name     = "core_l4_clkdm",
3016         .recalc         = &followparent_recalc,
3017 };
3018
3019 /* SECURE_32K_FCK clocks */
3020
3021 /* XXX This clock no longer exists in 3430 TRM rev F */
3022 static struct clk gpt12_fck = {
3023         .name           = "gpt12_fck",
3024         .parent         = &secure_32k_fck,
3025         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3026         .recalc         = &followparent_recalc,
3027 };
3028
3029 static struct clk wdt1_fck = {
3030         .name           = "wdt1_fck",
3031         .parent         = &secure_32k_fck,
3032         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3033         .recalc         = &followparent_recalc,
3034 };
3035
3036 static struct clk *onchip_34xx_clks[] __initdata = {
3037         &omap_32k_fck,
3038         &virt_12m_ck,
3039         &virt_13m_ck,
3040         &virt_16_8m_ck,
3041         &virt_19_2m_ck,
3042         &virt_26m_ck,
3043         &virt_38_4m_ck,
3044         &osc_sys_ck,
3045         &sys_ck,
3046         &sys_altclk,
3047         &mcbsp_clks,
3048         &sys_clkout1,
3049         &dpll1_ck,
3050         &dpll1_x2_ck,
3051         &dpll1_x2m2_ck,
3052         &dpll2_ck,
3053         &dpll2_m2_ck,
3054         &dpll3_ck,
3055         &core_ck,
3056         &dpll3_x2_ck,
3057         &dpll3_m2_ck,
3058         &dpll3_m2x2_ck,
3059         &dpll3_m3_ck,
3060         &dpll3_m3x2_ck,
3061         &emu_core_alwon_ck,
3062         &dpll4_ck,
3063         &dpll4_x2_ck,
3064         &omap_96m_alwon_fck,
3065         &omap_96m_fck,
3066         &cm_96m_fck,
3067         &virt_omap_54m_fck,
3068         &omap_54m_fck,
3069         &omap_48m_fck,
3070         &omap_12m_fck,
3071         &dpll4_m2_ck,
3072         &dpll4_m2x2_ck,
3073         &dpll4_m3_ck,
3074         &dpll4_m3x2_ck,
3075         &dpll4_m4_ck,
3076         &dpll4_m4x2_ck,
3077         &dpll4_m5_ck,
3078         &dpll4_m5x2_ck,
3079         &dpll4_m6_ck,
3080         &dpll4_m6x2_ck,
3081         &emu_per_alwon_ck,
3082         &dpll5_ck,
3083         &dpll5_m2_ck,
3084         &omap_120m_fck,
3085         &clkout2_src_ck,
3086         &sys_clkout2,
3087         &corex2_fck,
3088         &dpll1_fck,
3089         &mpu_ck,
3090         &arm_fck,
3091         &emu_mpu_alwon_ck,
3092         &dpll2_fck,
3093         &iva2_ck,
3094         &l3_ick,
3095         &l4_ick,
3096         &rm_ick,
3097         &gfx_l3_ck,
3098         &gfx_l3_fck,
3099         &gfx_l3_ick,
3100         &gfx_cg1_ck,
3101         &gfx_cg2_ck,
3102         &sgx_fck,
3103         &sgx_ick,
3104         &d2d_26m_fck,
3105         &gpt10_fck,
3106         &gpt11_fck,
3107         &cpefuse_fck,
3108         &ts_fck,
3109         &usbtll_fck,
3110         &core_96m_fck,
3111         &mmchs3_fck,
3112         &mmchs2_fck,
3113         &mspro_fck,
3114         &mmchs1_fck,
3115         &i2c3_fck,
3116         &i2c2_fck,
3117         &i2c1_fck,
3118         &mcbsp5_fck,
3119         &mcbsp1_fck,
3120         &core_48m_fck,
3121         &mcspi4_fck,
3122         &mcspi3_fck,
3123         &mcspi2_fck,
3124         &mcspi1_fck,
3125         &uart2_fck,
3126         &uart1_fck,
3127         &fshostusb_fck,
3128         &core_12m_fck,
3129         &hdq_fck,
3130         &ssi_ssr_fck,
3131         &ssi_sst_fck,
3132         &core_l3_ick,
3133         &hsotgusb_ick,
3134         &sdrc_ick,
3135         &gpmc_fck,
3136         &security_l3_ick,
3137         &pka_ick,
3138         &core_l4_ick,
3139         &usbtll_ick,
3140         &mmchs3_ick,
3141         &icr_ick,
3142         &aes2_ick,
3143         &sha12_ick,
3144         &des2_ick,
3145         &mmchs2_ick,
3146         &mmchs1_ick,
3147         &mspro_ick,
3148         &hdq_ick,
3149         &mcspi4_ick,
3150         &mcspi3_ick,
3151         &mcspi2_ick,
3152         &mcspi1_ick,
3153         &i2c3_ick,
3154         &i2c2_ick,
3155         &i2c1_ick,
3156         &uart2_ick,
3157         &uart1_ick,
3158         &gpt11_ick,
3159         &gpt10_ick,
3160         &mcbsp5_ick,
3161         &mcbsp1_ick,
3162         &fac_ick,
3163         &mailboxes_ick,
3164         &omapctrl_ick,
3165         &ssi_l4_ick,
3166         &ssi_ick,
3167         &usb_l4_ick,
3168         &security_l4_ick2,
3169         &aes1_ick,
3170         &rng_ick,
3171         &sha11_ick,
3172         &des1_ick,
3173         &dss1_alwon_fck,
3174         &dss_tv_fck,
3175         &dss_96m_fck,
3176         &dss2_alwon_fck,
3177         &dss_ick,
3178         &cam_mclk,
3179         &cam_ick,
3180         &usbhost_120m_fck,
3181         &usbhost_48m_fck,
3182         &usbhost_ick,
3183         &usbhost_sar_fck,
3184         &usim_fck,
3185         &gpt1_fck,
3186         &wkup_32k_fck,
3187         &gpio1_fck,
3188         &wdt2_fck,
3189         &wkup_l4_ick,
3190         &usim_ick,
3191         &wdt2_ick,
3192         &wdt1_ick,
3193         &gpio1_ick,
3194         &omap_32ksync_ick,
3195         &gpt12_ick,
3196         &gpt1_ick,
3197         &per_96m_fck,
3198         &per_48m_fck,
3199         &uart3_fck,
3200         &gpt2_fck,
3201         &gpt3_fck,
3202         &gpt4_fck,
3203         &gpt5_fck,
3204         &gpt6_fck,
3205         &gpt7_fck,
3206         &gpt8_fck,
3207         &gpt9_fck,
3208         &per_32k_alwon_fck,
3209         &gpio6_fck,
3210         &gpio5_fck,
3211         &gpio4_fck,
3212         &gpio3_fck,
3213         &gpio2_fck,
3214         &wdt3_fck,
3215         &per_l4_ick,
3216         &gpio6_ick,
3217         &gpio5_ick,
3218         &gpio4_ick,
3219         &gpio3_ick,
3220         &gpio2_ick,
3221         &wdt3_ick,
3222         &uart3_ick,
3223         &gpt9_ick,
3224         &gpt8_ick,
3225         &gpt7_ick,
3226         &gpt6_ick,
3227         &gpt5_ick,
3228         &gpt4_ick,
3229         &gpt3_ick,
3230         &gpt2_ick,
3231         &mcbsp2_ick,
3232         &mcbsp3_ick,
3233         &mcbsp4_ick,
3234         &mcbsp2_fck,
3235         &mcbsp3_fck,
3236         &mcbsp4_fck,
3237         &emu_src_ck,
3238         &pclk_fck,
3239         &pclkx2_fck,
3240         &atclk_fck,
3241         &traceclk_src_fck,
3242         &traceclk_fck,
3243         &sr1_fck,
3244         &sr2_fck,
3245         &sr_l4_ick,
3246         &secure_32k_fck,
3247         &gpt12_fck,
3248         &wdt1_fck,
3249 };
3250
3251 #endif