arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <asm/arch/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  52 #define DPLL_LOW_POWER_STOP             0x1
  53 #define DPLL_LOW_POWER_BYPASS           0x5
  54 #define DPLL_LOCKED                     0x7
  55
  56 /* PRM CLOCKS */
  57
  58 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  59 static struct clk omap_32k_fck = {
  60         .name           = "omap_32k_fck",
  61         .rate           = 32768,
  62         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  63                                 ALWAYS_ENABLED,
  64         .recalc         = &propagate_rate,
  65 };
  66
  67 static struct clk secure_32k_fck = {
  68         .name           = "secure_32k_fck",
  69         .rate           = 32768,
  70         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  71                                 ALWAYS_ENABLED,
  72         .recalc         = &propagate_rate,
  73 };
  74
  75 /* Virtual source clocks for osc_sys_ck */
  76 static struct clk virt_12m_ck = {
  77         .name           = "virt_12m_ck",
  78         .rate           = 12000000,
  79         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  80                                 ALWAYS_ENABLED,
  81         .recalc         = &propagate_rate,
  82 };
  83
  84 static struct clk virt_13m_ck = {
  85         .name           = "virt_13m_ck",
  86         .rate           = 13000000,
  87         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  88                                 ALWAYS_ENABLED,
  89         .recalc         = &propagate_rate,
  90 };
  91
  92 static struct clk virt_16_8m_ck = {
  93         .name           = "virt_16_8m_ck",
  94         .rate           = 16800000,
  95         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  96                                 ALWAYS_ENABLED,
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_19_2m_ck = {
 101         .name           = "virt_19_2m_ck",
 102         .rate           = 19200000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .recalc         = &propagate_rate,
 106 };
 107
 108 static struct clk virt_26m_ck = {
 109         .name           = "virt_26m_ck",
 110         .rate           = 26000000,
 111         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 112                                 ALWAYS_ENABLED,
 113         .recalc         = &propagate_rate,
 114 };
 115
 116 static struct clk virt_38_4m_ck = {
 117         .name           = "virt_38_4m_ck",
 118         .rate           = 38400000,
 119         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 120                                 ALWAYS_ENABLED,
 121         .recalc         = &propagate_rate,
 122 };
 123
 124 static const struct clksel_rate osc_sys_12m_rates[] = {
 125         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 126         { .div = 0 }
 127 };
 128
 129 static const struct clksel_rate osc_sys_13m_rates[] = {
 130         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 131         { .div = 0 }
 132 };
 133
 134 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 135         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 136         { .div = 0 }
 137 };
 138
 139 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 141         { .div = 0 }
 142 };
 143
 144 static const struct clksel_rate osc_sys_26m_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 146         { .div = 0 }
 147 };
 148
 149 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 151         { .div = 0 }
 152 };
 153
 154 static const struct clksel osc_sys_clksel[] = {
 155         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 156         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 157         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 158         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 159         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 160         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 161         { .parent = NULL },
 162 };
 163
 164 /* Oscillator clock */
 165 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 166 static struct clk osc_sys_ck = {
 167         .name           = "osc_sys_ck",
 168         .init           = &omap2_init_clksel_parent,
 169         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 170         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 171         .clksel         = osc_sys_clksel,
 172         /* REVISIT: deal with autoextclkmode? */
 173         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 174                                 ALWAYS_ENABLED,
 175         .recalc         = &omap2_clksel_recalc,
 176 };
 177
 178 static const struct clksel_rate div2_rates[] = {
 179         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 180         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 181         { .div = 0 }
 182 };
 183
 184 static const struct clksel sys_clksel[] = {
 185         { .parent = &osc_sys_ck, .rates = div2_rates },
 186         { .parent = NULL }
 187 };
 188
 189 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 190 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 191 static struct clk sys_ck = {
 192         .name           = "sys_ck",
 193         .parent         = &osc_sys_ck,
 194         .init           = &omap2_init_clksel_parent,
 195         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 196         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 197         .clksel         = sys_clksel,
 198         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 199         .recalc         = &omap2_clksel_recalc,
 200 };
 201
 202 static struct clk sys_altclk = {
 203         .name           = "sys_altclk",
 204         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 205         .recalc         = &propagate_rate,
 206 };
 207
 208 /* Optional external clock input for some McBSPs */
 209 static struct clk mcbsp_clks = {
 210         .name           = "mcbsp_clks",
 211         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 212         .recalc         = &propagate_rate,
 213 };
 214
 215 /* PRM EXTERNAL CLOCK OUTPUT */
 216
 217 static struct clk sys_clkout1 = {
 218         .name           = "sys_clkout1",
 219         .parent         = &osc_sys_ck,
 220         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 221         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 222         .flags          = CLOCK_IN_OMAP343X,
 223         .recalc         = &followparent_recalc,
 224 };
 225
 226 /* DPLLS */
 227
 228 /* CM CLOCKS */
 229
 230 static const struct clksel_rate dpll_bypass_rates[] = {
 231         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 232         { .div = 0 }
 233 };
 234
 235 static const struct clksel_rate dpll_locked_rates[] = {
 236         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 237         { .div = 0 }
 238 };
 239
 240 static const struct clksel_rate div16_dpll_rates[] = {
 241         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 242         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 243         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 244         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 245         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 246         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 247         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 248         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 249         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 250         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 251         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 252         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 253         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 254         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 255         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 256         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 257         { .div = 0 }
 258 };
 259
 260 /* DPLL1 */
 261 /* MPU clock source */
 262 /* Type: DPLL */
 263 static struct dpll_data dpll1_dd = {
 264         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 265         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 266         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 267         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 268         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 269         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 270         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 271         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 272         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 273         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 274         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 275         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 276         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 277         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 278         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 279         .max_divider    = OMAP3_MAX_DPLL_DIV,
 280         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 281 };
 282
 283 static struct clk dpll1_ck = {
 284         .name           = "dpll1_ck",
 285         .parent         = &sys_ck,
 286         .dpll_data      = &dpll1_dd,
 287         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 288         .round_rate     = &omap2_dpll_round_rate,
 289         .set_rate       = &omap3_noncore_dpll_set_rate,
 290         .recalc         = &omap3_dpll_recalc,
 291 };
 292
 293 /*
 294  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 295  * DPLL isn't bypassed.
 296  */
 297 static struct clk dpll1_x2_ck = {
 298         .name           = "dpll1_x2_ck",
 299         .parent         = &dpll1_ck,
 300         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 301                                 PARENT_CONTROLS_CLOCK,
 302         .recalc         = &omap3_clkoutx2_recalc,
 303 };
 304
 305 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 306 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 307         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 308         { .parent = NULL }
 309 };
 310
 311 /*
 312  * Does not exist in the TRM - needed to separate the M2 divider from
 313  * bypass selection in mpu_ck
 314  */
 315 static struct clk dpll1_x2m2_ck = {
 316         .name           = "dpll1_x2m2_ck",
 317         .parent         = &dpll1_x2_ck,
 318         .init           = &omap2_init_clksel_parent,
 319         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 320         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 321         .clksel         = div16_dpll1_x2m2_clksel,
 322         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 323                                 PARENT_CONTROLS_CLOCK,
 324         .recalc         = &omap2_clksel_recalc,
 325 };
 326
 327 /* DPLL2 */
 328 /* IVA2 clock source */
 329 /* Type: DPLL */
 330
 331 static struct dpll_data dpll2_dd = {
 332         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 333         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 334         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 335         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 336         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 337         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 338         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 339                                 (1 << DPLL_LOW_POWER_BYPASS),
 340         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 341         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 342         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 343         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 344         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 345         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 346         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 347         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 348         .max_divider    = OMAP3_MAX_DPLL_DIV,
 349         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 350 };
 351
 352 static struct clk dpll2_ck = {
 353         .name           = "dpll2_ck",
 354         .parent         = &sys_ck,
 355         .dpll_data      = &dpll2_dd,
 356         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 357         .enable         = &omap3_noncore_dpll_enable,
 358         .disable        = &omap3_noncore_dpll_disable,
 359         .round_rate     = &omap2_dpll_round_rate,
 360         .set_rate       = &omap3_noncore_dpll_set_rate,
 361         .recalc         = &omap3_dpll_recalc,
 362 };
 363
 364 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 365         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 366         { .parent = NULL }
 367 };
 368
 369 /*
 370  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 371  * or CLKOUTX2. CLKOUT seems most plausible.
 372  */
 373 static struct clk dpll2_m2_ck = {
 374         .name           = "dpll2_m2_ck",
 375         .parent         = &dpll2_ck,
 376         .init           = &omap2_init_clksel_parent,
 377         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 378                                           OMAP3430_CM_CLKSEL2_PLL),
 379         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 380         .clksel         = div16_dpll2_m2x2_clksel,
 381         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 382                                 PARENT_CONTROLS_CLOCK,
 383         .recalc         = &omap2_clksel_recalc,
 384 };
 385
 386 /*
 387  * DPLL3
 388  * Source clock for all interfaces and for some device fclks
 389  * REVISIT: Also supports fast relock bypass - not included below
 390  */
 391 static struct dpll_data dpll3_dd = {
 392         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 393         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 394         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 395         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 396         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 397         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 398         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 399         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 400         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 401         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 402         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 403         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 404         .max_divider    = OMAP3_MAX_DPLL_DIV,
 405         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 406 };
 407
 408 static struct clk dpll3_ck = {
 409         .name           = "dpll3_ck",
 410         .parent         = &sys_ck,
 411         .dpll_data      = &dpll3_dd,
 412         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 413         .round_rate     = &omap2_dpll_round_rate,
 414         .recalc         = &omap3_dpll_recalc,
 415 };
 416
 417 /*
 418  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 419  * DPLL isn't bypassed
 420  */
 421 static struct clk dpll3_x2_ck = {
 422         .name           = "dpll3_x2_ck",
 423         .parent         = &dpll3_ck,
 424         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 425                                 PARENT_CONTROLS_CLOCK,
 426         .recalc         = &omap3_clkoutx2_recalc,
 427 };
 428
 429 static const struct clksel_rate div31_dpll3_rates[] = {
 430         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 431         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 432         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 433         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 434         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 435         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 436         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 437         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 438         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 439         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 440         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 441         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 442         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 443         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 444         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 445         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 446         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 447         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 448         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 449         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 450         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 451         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 452         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 453         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 454         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 455         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 456         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 457         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 458         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 459         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 460         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 461         { .div = 0 },
 462 };
 463
 464 static const struct clksel div31_dpll3m2_clksel[] = {
 465         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 466         { .parent = NULL }
 467 };
 468
 469 /*
 470  * DPLL3 output M2
 471  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 472  * that code is ready, this should remain a 'read-only' clksel clock.
 473  */
 474 static struct clk dpll3_m2_ck = {
 475         .name           = "dpll3_m2_ck",
 476         .parent         = &dpll3_ck,
 477         .init           = &omap2_init_clksel_parent,
 478         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 479         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 480         .clksel         = div31_dpll3m2_clksel,
 481         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 482                                 PARENT_CONTROLS_CLOCK,
 483         .recalc         = &omap2_clksel_recalc,
 484 };
 485
 486 static const struct clksel core_ck_clksel[] = {
 487         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 488         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 489         { .parent = NULL }
 490 };
 491
 492 static struct clk core_ck = {
 493         .name           = "core_ck",
 494         .init           = &omap2_init_clksel_parent,
 495         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 496         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 497         .clksel         = core_ck_clksel,
 498         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 499                                 PARENT_CONTROLS_CLOCK,
 500         .recalc         = &omap2_clksel_recalc,
 501 };
 502
 503 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 504         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 505         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 506         { .parent = NULL }
 507 };
 508
 509 static struct clk dpll3_m2x2_ck = {
 510         .name           = "dpll3_m2x2_ck",
 511         .init           = &omap2_init_clksel_parent,
 512         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 513         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 514         .clksel         = dpll3_m2x2_ck_clksel,
 515         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 516                                 PARENT_CONTROLS_CLOCK,
 517         .recalc         = &omap2_clksel_recalc,
 518 };
 519
 520 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 521 static const struct clksel div16_dpll3_clksel[] = {
 522         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 523         { .parent = NULL }
 524 };
 525
 526 /* This virtual clock is the source for dpll3_m3x2_ck */
 527 static struct clk dpll3_m3_ck = {
 528         .name           = "dpll3_m3_ck",
 529         .parent         = &dpll3_ck,
 530         .init           = &omap2_init_clksel_parent,
 531         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 532         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 533         .clksel         = div16_dpll3_clksel,
 534         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 535                                 PARENT_CONTROLS_CLOCK,
 536         .recalc         = &omap2_clksel_recalc,
 537 };
 538
 539 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 540 static struct clk dpll3_m3x2_ck = {
 541         .name           = "dpll3_m3x2_ck",
 542         .parent         = &dpll3_m3_ck,
 543         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 544         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 545         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 546         .recalc         = &omap3_clkoutx2_recalc,
 547 };
 548
 549 static const struct clksel emu_core_alwon_ck_clksel[] = {
 550         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 551         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 552         { .parent = NULL }
 553 };
 554
 555 static struct clk emu_core_alwon_ck = {
 556         .name           = "emu_core_alwon_ck",
 557         .parent         = &dpll3_m3x2_ck,
 558         .init           = &omap2_init_clksel_parent,
 559         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 560         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 561         .clksel         = emu_core_alwon_ck_clksel,
 562         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 563                                 PARENT_CONTROLS_CLOCK,
 564         .recalc         = &omap2_clksel_recalc,
 565 };
 566
 567 /* DPLL4 */
 568 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 569 /* Type: DPLL */
 570 static struct dpll_data dpll4_dd = {
 571         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 572         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 573         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 574         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 575         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 576         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 577         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 578         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 579         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 580         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 581         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 582         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 583         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 584         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 585         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 586         .max_divider    = OMAP3_MAX_DPLL_DIV,
 587         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 588 };
 589
 590 static struct clk dpll4_ck = {
 591         .name           = "dpll4_ck",
 592         .parent         = &sys_ck,
 593         .dpll_data      = &dpll4_dd,
 594         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 595         .enable         = &omap3_noncore_dpll_enable,
 596         .disable        = &omap3_noncore_dpll_disable,
 597         .round_rate     = &omap2_dpll_round_rate,
 598         .set_rate       = &omap3_noncore_dpll_set_rate,
 599         .recalc         = &omap3_dpll_recalc,
 600 };
 601
 602 /*
 603  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 604  * DPLL isn't bypassed --
 605  * XXX does this serve any downstream clocks?
 606  */
 607 static struct clk dpll4_x2_ck = {
 608         .name           = "dpll4_x2_ck",
 609         .parent         = &dpll4_ck,
 610         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 611                                 PARENT_CONTROLS_CLOCK,
 612         .recalc         = &omap3_clkoutx2_recalc,
 613 };
 614
 615 static const struct clksel div16_dpll4_clksel[] = {
 616         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 617         { .parent = NULL }
 618 };
 619
 620 /* This virtual clock is the source for dpll4_m2x2_ck */
 621 static struct clk dpll4_m2_ck = {
 622         .name           = "dpll4_m2_ck",
 623         .parent         = &dpll4_ck,
 624         .init           = &omap2_init_clksel_parent,
 625         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 626         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 627         .clksel         = div16_dpll4_clksel,
 628         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 629                                 PARENT_CONTROLS_CLOCK,
 630         .recalc         = &omap2_clksel_recalc,
 631 };
 632
 633 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 634 static struct clk dpll4_m2x2_ck = {
 635         .name           = "dpll4_m2x2_ck",
 636         .parent         = &dpll4_m2_ck,
 637         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 638         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 639         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 640         .recalc         = &omap3_clkoutx2_recalc,
 641 };
 642
 643 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 644         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 645         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 646         { .parent = NULL }
 647 };
 648
 649 static struct clk omap_96m_alwon_fck = {
 650         .name           = "omap_96m_alwon_fck",
 651         .parent         = &dpll4_m2x2_ck,
 652         .init           = &omap2_init_clksel_parent,
 653         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 654         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 655         .clksel         = omap_96m_alwon_fck_clksel,
 656         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 657                                  PARENT_CONTROLS_CLOCK,
 658         .recalc         = &omap2_clksel_recalc,
 659 };
 660
 661 static struct clk omap_96m_fck = {
 662         .name           = "omap_96m_fck",
 663         .parent         = &omap_96m_alwon_fck,
 664         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 665                                 PARENT_CONTROLS_CLOCK,
 666         .recalc         = &followparent_recalc,
 667 };
 668
 669 static const struct clksel cm_96m_fck_clksel[] = {
 670         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 671         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 672         { .parent = NULL }
 673 };
 674
 675 static struct clk cm_96m_fck = {
 676         .name           = "cm_96m_fck",
 677         .parent         = &dpll4_m2x2_ck,
 678         .init           = &omap2_init_clksel_parent,
 679         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 680         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 681         .clksel         = cm_96m_fck_clksel,
 682         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 683                                 PARENT_CONTROLS_CLOCK,
 684         .recalc         = &omap2_clksel_recalc,
 685 };
 686
 687 /* This virtual clock is the source for dpll4_m3x2_ck */
 688 static struct clk dpll4_m3_ck = {
 689         .name           = "dpll4_m3_ck",
 690         .parent         = &dpll4_ck,
 691         .init           = &omap2_init_clksel_parent,
 692         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 693         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 694         .clksel         = div16_dpll4_clksel,
 695         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 696                                 PARENT_CONTROLS_CLOCK,
 697         .recalc         = &omap2_clksel_recalc,
 698 };
 699
 700 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 701 static struct clk dpll4_m3x2_ck = {
 702         .name           = "dpll4_m3x2_ck",
 703         .parent         = &dpll4_m3_ck,
 704         .init           = &omap2_init_clksel_parent,
 705         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 706         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 707         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 708         .recalc         = &omap3_clkoutx2_recalc,
 709 };
 710
 711 static const struct clksel virt_omap_54m_fck_clksel[] = {
 712         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 713         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 714         { .parent = NULL }
 715 };
 716
 717 static struct clk virt_omap_54m_fck = {
 718         .name           = "virt_omap_54m_fck",
 719         .parent         = &dpll4_m3x2_ck,
 720         .init           = &omap2_init_clksel_parent,
 721         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 722         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 723         .clksel         = virt_omap_54m_fck_clksel,
 724         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 725                                 PARENT_CONTROLS_CLOCK,
 726         .recalc         = &omap2_clksel_recalc,
 727 };
 728
 729 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 730         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 731         { .div = 0 }
 732 };
 733
 734 static const struct clksel_rate omap_54m_alt_rates[] = {
 735         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 736         { .div = 0 }
 737 };
 738
 739 static const struct clksel omap_54m_clksel[] = {
 740         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 741         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 742         { .parent = NULL }
 743 };
 744
 745 static struct clk omap_54m_fck = {
 746         .name           = "omap_54m_fck",
 747         .init           = &omap2_init_clksel_parent,
 748         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 749         .clksel_mask    = OMAP3430_SOURCE_54M,
 750         .clksel         = omap_54m_clksel,
 751         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 752                                 PARENT_CONTROLS_CLOCK,
 753         .recalc         = &omap2_clksel_recalc,
 754 };
 755
 756 static const struct clksel_rate omap_48m_96md2_rates[] = {
 757         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 758         { .div = 0 }
 759 };
 760
 761 static const struct clksel_rate omap_48m_alt_rates[] = {
 762         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 763         { .div = 0 }
 764 };
 765
 766 static const struct clksel omap_48m_clksel[] = {
 767         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 768         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 769         { .parent = NULL }
 770 };
 771
 772 static struct clk omap_48m_fck = {
 773         .name           = "omap_48m_fck",
 774         .init           = &omap2_init_clksel_parent,
 775         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 776         .clksel_mask    = OMAP3430_SOURCE_48M,
 777         .clksel         = omap_48m_clksel,
 778         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 779                                 PARENT_CONTROLS_CLOCK,
 780         .recalc         = &omap2_clksel_recalc,
 781 };
 782
 783 static struct clk omap_12m_fck = {
 784         .name           = "omap_12m_fck",
 785         .parent         = &omap_48m_fck,
 786         .fixed_div      = 4,
 787         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 788                                 PARENT_CONTROLS_CLOCK,
 789         .recalc         = &omap2_fixed_divisor_recalc,
 790 };
 791
 792 /* This virstual clock is the source for dpll4_m4x2_ck */
 793 static struct clk dpll4_m4_ck = {
 794         .name           = "dpll4_m4_ck",
 795         .parent         = &dpll4_ck,
 796         .init           = &omap2_init_clksel_parent,
 797         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 798         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 799         .clksel         = div16_dpll4_clksel,
 800         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 801                                 PARENT_CONTROLS_CLOCK,
 802         .recalc         = &omap2_clksel_recalc,
 803 };
 804
 805 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 806 static struct clk dpll4_m4x2_ck = {
 807         .name           = "dpll4_m4x2_ck",
 808         .parent         = &dpll4_m4_ck,
 809         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 810         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 811         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 812         .recalc         = &omap3_clkoutx2_recalc,
 813 };
 814
 815 /* This virtual clock is the source for dpll4_m5x2_ck */
 816 static struct clk dpll4_m5_ck = {
 817         .name           = "dpll4_m5_ck",
 818         .parent         = &dpll4_ck,
 819         .init           = &omap2_init_clksel_parent,
 820         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 821         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 822         .clksel         = div16_dpll4_clksel,
 823         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 824                                 PARENT_CONTROLS_CLOCK,
 825         .recalc         = &omap2_clksel_recalc,
 826 };
 827
 828 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 829 static struct clk dpll4_m5x2_ck = {
 830         .name           = "dpll4_m5x2_ck",
 831         .parent         = &dpll4_m5_ck,
 832         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 833         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 834         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 835         .recalc         = &omap3_clkoutx2_recalc,
 836 };
 837
 838 /* This virtual clock is the source for dpll4_m6x2_ck */
 839 static struct clk dpll4_m6_ck = {
 840         .name           = "dpll4_m6_ck",
 841         .parent         = &dpll4_ck,
 842         .init           = &omap2_init_clksel_parent,
 843         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 844         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 845         .clksel         = div16_dpll4_clksel,
 846         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 847                                 PARENT_CONTROLS_CLOCK,
 848         .recalc         = &omap2_clksel_recalc,
 849 };
 850
 851 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 852 static struct clk dpll4_m6x2_ck = {
 853         .name           = "dpll4_m6x2_ck",
 854         .parent         = &dpll4_m6_ck,
 855         .init           = &omap2_init_clksel_parent,
 856         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 857         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 858         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 859         .recalc         = &omap3_clkoutx2_recalc,
 860 };
 861
 862 static struct clk emu_per_alwon_ck = {
 863         .name           = "emu_per_alwon_ck",
 864         .parent         = &dpll4_m6x2_ck,
 865         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 866                                 PARENT_CONTROLS_CLOCK,
 867         .recalc         = &followparent_recalc,
 868 };
 869
 870 /* DPLL5 */
 871 /* Supplies 120MHz clock, USIM source clock */
 872 /* Type: DPLL */
 873 /* 3430ES2 only */
 874 static struct dpll_data dpll5_dd = {
 875         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 876         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 877         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 878         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 879         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 880         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 881         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 882         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 883         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 884         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 885         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 886         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 887         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 888         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 889         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 890         .max_divider    = OMAP3_MAX_DPLL_DIV,
 891         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 892 };
 893
 894 static struct clk dpll5_ck = {
 895         .name           = "dpll5_ck",
 896         .parent         = &sys_ck,
 897         .dpll_data      = &dpll5_dd,
 898         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 899         .enable         = &omap3_noncore_dpll_enable,
 900         .disable        = &omap3_noncore_dpll_disable,
 901         .round_rate     = &omap2_dpll_round_rate,
 902         .set_rate       = &omap3_noncore_dpll_set_rate,
 903         .recalc         = &omap3_dpll_recalc,
 904 };
 905
 906 static const struct clksel div16_dpll5_clksel[] = {
 907         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 908         { .parent = NULL }
 909 };
 910
 911 static struct clk dpll5_m2_ck = {
 912         .name           = "dpll5_m2_ck",
 913         .parent         = &dpll5_ck,
 914         .init           = &omap2_init_clksel_parent,
 915         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 916         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 917         .clksel         = div16_dpll5_clksel,
 918         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 919                                 PARENT_CONTROLS_CLOCK,
 920         .recalc         = &omap2_clksel_recalc,
 921 };
 922
 923 static const struct clksel omap_120m_fck_clksel[] = {
 924         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 925         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 926         { .parent = NULL }
 927 };
 928
 929 static struct clk omap_120m_fck = {
 930         .name           = "omap_120m_fck",
 931         .parent         = &dpll5_m2_ck,
 932         .init           = &omap2_init_clksel_parent,
 933         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 934         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 935         .clksel         = omap_120m_fck_clksel,
 936         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 937                                 PARENT_CONTROLS_CLOCK,
 938         .recalc         = &omap2_clksel_recalc,
 939 };
 940
 941 /* CM EXTERNAL CLOCK OUTPUTS */
 942
 943 static const struct clksel_rate clkout2_src_core_rates[] = {
 944         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 945         { .div = 0 }
 946 };
 947
 948 static const struct clksel_rate clkout2_src_sys_rates[] = {
 949         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 950         { .div = 0 }
 951 };
 952
 953 static const struct clksel_rate clkout2_src_96m_rates[] = {
 954         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 955         { .div = 0 }
 956 };
 957
 958 static const struct clksel_rate clkout2_src_54m_rates[] = {
 959         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 960         { .div = 0 }
 961 };
 962
 963 static const struct clksel clkout2_src_clksel[] = {
 964         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 965         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 966         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 967         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 968         { .parent = NULL }
 969 };
 970
 971 static struct clk clkout2_src_ck = {
 972         .name           = "clkout2_src_ck",
 973         .init           = &omap2_init_clksel_parent,
 974         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 975         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 976         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 977         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 978         .clksel         = clkout2_src_clksel,
 979         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 980         .clkdm_name     = "core_clkdm",
 981         .recalc         = &omap2_clksel_recalc,
 982 };
 983
 984 static const struct clksel_rate sys_clkout2_rates[] = {
 985         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 986         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 987         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 988         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 989         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 990         { .div = 0 },
 991 };
 992
 993 static const struct clksel sys_clkout2_clksel[] = {
 994         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 995         { .parent = NULL },
 996 };
 997
 998 static struct clk sys_clkout2 = {
 999         .name           = "sys_clkout2",
1000         .init           = &omap2_init_clksel_parent,
1001         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1002         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1003         .clksel         = sys_clkout2_clksel,
1004         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1005         .recalc         = &omap2_clksel_recalc,
1006 };
1007
1008 /* CM OUTPUT CLOCKS */
1009
1010 static struct clk corex2_fck = {
1011         .name           = "corex2_fck",
1012         .parent         = &dpll3_m2x2_ck,
1013         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1014                                 PARENT_CONTROLS_CLOCK,
1015         .recalc         = &followparent_recalc,
1016 };
1017
1018 /* DPLL power domain clock controls */
1019
1020 static const struct clksel div2_core_clksel[] = {
1021         { .parent = &core_ck, .rates = div2_rates },
1022         { .parent = NULL }
1023 };
1024
1025 /*
1026  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1027  * may be inconsistent here?
1028  */
1029 static struct clk dpll1_fck = {
1030         .name           = "dpll1_fck",
1031         .parent         = &core_ck,
1032         .init           = &omap2_init_clksel_parent,
1033         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1034         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1035         .clksel         = div2_core_clksel,
1036         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1037                                 PARENT_CONTROLS_CLOCK,
1038         .recalc         = &omap2_clksel_recalc,
1039 };
1040
1041 /*
1042  * MPU clksel:
1043  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1044  * derives from the high-frequency bypass clock originating from DPLL3,
1045  * called 'dpll1_fck'
1046  */
1047 static const struct clksel mpu_clksel[] = {
1048         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1049         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1050         { .parent = NULL }
1051 };
1052
1053 static struct clk mpu_ck = {
1054         .name           = "mpu_ck",
1055         .parent         = &dpll1_x2m2_ck,
1056         .init           = &omap2_init_clksel_parent,
1057         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1058         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1059         .clksel         = mpu_clksel,
1060         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1061                                 PARENT_CONTROLS_CLOCK,
1062         .clkdm_name     = "mpu_clkdm",
1063         .recalc         = &omap2_clksel_recalc,
1064 };
1065
1066 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1067 static const struct clksel_rate arm_fck_rates[] = {
1068         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1069         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1070         { .div = 0 },
1071 };
1072
1073 static const struct clksel arm_fck_clksel[] = {
1074         { .parent = &mpu_ck, .rates = arm_fck_rates },
1075         { .parent = NULL }
1076 };
1077
1078 static struct clk arm_fck = {
1079         .name           = "arm_fck",
1080         .parent         = &mpu_ck,
1081         .init           = &omap2_init_clksel_parent,
1082         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1083         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1084         .clksel         = arm_fck_clksel,
1085         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1086                                 PARENT_CONTROLS_CLOCK,
1087         .recalc         = &omap2_clksel_recalc,
1088 };
1089
1090 /* XXX What about neon_clkdm ? */
1091
1092 /*
1093  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1094  * although it is referenced - so this is a guess
1095  */
1096 static struct clk emu_mpu_alwon_ck = {
1097         .name           = "emu_mpu_alwon_ck",
1098         .parent         = &mpu_ck,
1099         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1100                                 PARENT_CONTROLS_CLOCK,
1101         .recalc         = &followparent_recalc,
1102 };
1103
1104 static struct clk dpll2_fck = {
1105         .name           = "dpll2_fck",
1106         .parent         = &core_ck,
1107         .init           = &omap2_init_clksel_parent,
1108         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1109         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1110         .clksel         = div2_core_clksel,
1111         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1112                                 PARENT_CONTROLS_CLOCK,
1113         .recalc         = &omap2_clksel_recalc,
1114 };
1115
1116 /*
1117  * IVA2 clksel:
1118  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1119  * derives from the high-frequency bypass clock originating from DPLL3,
1120  * called 'dpll2_fck'
1121  */
1122
1123 static const struct clksel iva2_clksel[] = {
1124         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1125         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1126         { .parent = NULL }
1127 };
1128
1129 static struct clk iva2_ck = {
1130         .name           = "iva2_ck",
1131         .parent         = &dpll2_m2_ck,
1132         .init           = &omap2_init_clksel_parent,
1133         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1134         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1135         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1136                                           OMAP3430_CM_IDLEST_PLL),
1137         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1138         .clksel         = iva2_clksel,
1139         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1140         .clkdm_name     = "iva2_clkdm",
1141         .recalc         = &omap2_clksel_recalc,
1142 };
1143
1144 /* Common interface clocks */
1145
1146 static struct clk l3_ick = {
1147         .name           = "l3_ick",
1148         .parent         = &core_ck,
1149         .init           = &omap2_init_clksel_parent,
1150         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1151         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1152         .clksel         = div2_core_clksel,
1153         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1154                                 PARENT_CONTROLS_CLOCK,
1155         .clkdm_name     = "core_l3_clkdm",
1156         .recalc         = &omap2_clksel_recalc,
1157 };
1158
1159 static const struct clksel div2_l3_clksel[] = {
1160         { .parent = &l3_ick, .rates = div2_rates },
1161         { .parent = NULL }
1162 };
1163
1164 static struct clk l4_ick = {
1165         .name           = "l4_ick",
1166         .parent         = &l3_ick,
1167         .init           = &omap2_init_clksel_parent,
1168         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1169         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1170         .clksel         = div2_l3_clksel,
1171         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1172                                 PARENT_CONTROLS_CLOCK,
1173         .clkdm_name     = "core_l4_clkdm",
1174         .recalc         = &omap2_clksel_recalc,
1175
1176 };
1177
1178 static const struct clksel div2_l4_clksel[] = {
1179         { .parent = &l4_ick, .rates = div2_rates },
1180         { .parent = NULL }
1181 };
1182
1183 static struct clk rm_ick = {
1184         .name           = "rm_ick",
1185         .parent         = &l4_ick,
1186         .init           = &omap2_init_clksel_parent,
1187         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1188         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1189         .clksel         = div2_l4_clksel,
1190         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1191         .recalc         = &omap2_clksel_recalc,
1192 };
1193
1194 /* GFX power domain */
1195
1196 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1197
1198 static const struct clksel gfx_l3_clksel[] = {
1199         { .parent = &l3_ick, .rates = gfx_l3_rates },
1200         { .parent = NULL }
1201 };
1202
1203 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1204 static struct clk gfx_l3_ck = {
1205         .name           = "gfx_l3_ck",
1206         .parent         = &l3_ick,
1207         .init           = &omap2_init_clksel_parent,
1208         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1209         .enable_bit     = OMAP_EN_GFX_SHIFT,
1210         .flags          = CLOCK_IN_OMAP3430ES1,
1211         .recalc         = &followparent_recalc,
1212 };
1213
1214 static struct clk gfx_l3_fck = {
1215         .name           = "gfx_l3_fck",
1216         .parent         = &gfx_l3_ck,
1217         .init           = &omap2_init_clksel_parent,
1218         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1219         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1220         .clksel         = gfx_l3_clksel,
1221         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1222                                 PARENT_CONTROLS_CLOCK,
1223         .clkdm_name     = "gfx_3430es1_clkdm",
1224         .recalc         = &omap2_clksel_recalc,
1225 };
1226
1227 static struct clk gfx_l3_ick = {
1228         .name           = "gfx_l3_ick",
1229         .parent         = &gfx_l3_ck,
1230         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1231         .clkdm_name     = "gfx_3430es1_clkdm",
1232         .recalc         = &followparent_recalc,
1233 };
1234
1235 static struct clk gfx_cg1_ck = {
1236         .name           = "gfx_cg1_ck",
1237         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1238         .init           = &omap2_init_clk_clkdm,
1239         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1241         .flags          = CLOCK_IN_OMAP3430ES1,
1242         .clkdm_name     = "gfx_3430es1_clkdm",
1243         .recalc         = &followparent_recalc,
1244 };
1245
1246 static struct clk gfx_cg2_ck = {
1247         .name           = "gfx_cg2_ck",
1248         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1249         .init           = &omap2_init_clk_clkdm,
1250         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1251         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1252         .flags          = CLOCK_IN_OMAP3430ES1,
1253         .clkdm_name     = "gfx_3430es1_clkdm",
1254         .recalc         = &followparent_recalc,
1255 };
1256
1257 /* SGX power domain - 3430ES2 only */
1258
1259 static const struct clksel_rate sgx_core_rates[] = {
1260         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1261         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1262         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1263         { .div = 0 },
1264 };
1265
1266 static const struct clksel_rate sgx_96m_rates[] = {
1267         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1268         { .div = 0 },
1269 };
1270
1271 static const struct clksel sgx_clksel[] = {
1272         { .parent = &core_ck,    .rates = sgx_core_rates },
1273         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1274         { .parent = NULL },
1275 };
1276
1277 static struct clk sgx_fck = {
1278         .name           = "sgx_fck",
1279         .init           = &omap2_init_clksel_parent,
1280         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1281         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1282         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1283         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1284         .clksel         = sgx_clksel,
1285         .flags          = CLOCK_IN_OMAP3430ES2,
1286         .clkdm_name     = "sgx_clkdm",
1287         .recalc         = &omap2_clksel_recalc,
1288 };
1289
1290 static struct clk sgx_ick = {
1291         .name           = "sgx_ick",
1292         .parent         = &l3_ick,
1293         .init           = &omap2_init_clk_clkdm,
1294         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1295         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1296         .flags          = CLOCK_IN_OMAP3430ES2,
1297         .clkdm_name     = "sgx_clkdm",
1298         .recalc         = &followparent_recalc,
1299 };
1300
1301 /* CORE power domain */
1302
1303 static struct clk d2d_26m_fck = {
1304         .name           = "d2d_26m_fck",
1305         .parent         = &sys_ck,
1306         .init           = &omap2_init_clk_clkdm,
1307         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1308         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1309         .flags          = CLOCK_IN_OMAP3430ES1,
1310         .clkdm_name     = "d2d_clkdm",
1311         .recalc         = &followparent_recalc,
1312 };
1313
1314 static const struct clksel omap343x_gpt_clksel[] = {
1315         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1316         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1317         { .parent = NULL}
1318 };
1319
1320 static struct clk gpt10_fck = {
1321         .name           = "gpt10_fck",
1322         .parent         = &sys_ck,
1323         .init           = &omap2_init_clksel_parent,
1324         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1325         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1326         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1327         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1328         .clksel         = omap343x_gpt_clksel,
1329         .flags          = CLOCK_IN_OMAP343X,
1330         .clkdm_name     = "core_l4_clkdm",
1331         .recalc         = &omap2_clksel_recalc,
1332 };
1333
1334 static struct clk gpt11_fck = {
1335         .name           = "gpt11_fck",
1336         .parent         = &sys_ck,
1337         .init           = &omap2_init_clksel_parent,
1338         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1339         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1340         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1341         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1342         .clksel         = omap343x_gpt_clksel,
1343         .flags          = CLOCK_IN_OMAP343X,
1344         .clkdm_name     = "core_l4_clkdm",
1345         .recalc         = &omap2_clksel_recalc,
1346 };
1347
1348 static struct clk cpefuse_fck = {
1349         .name           = "cpefuse_fck",
1350         .parent         = &sys_ck,
1351         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1352         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1353         .flags          = CLOCK_IN_OMAP3430ES2,
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static struct clk ts_fck = {
1358         .name           = "ts_fck",
1359         .parent         = &omap_32k_fck,
1360         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1361         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1362         .flags          = CLOCK_IN_OMAP3430ES2,
1363         .recalc         = &followparent_recalc,
1364 };
1365
1366 static struct clk usbtll_fck = {
1367         .name           = "usbtll_fck",
1368         .parent         = &omap_120m_fck,
1369         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1370         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1371         .flags          = CLOCK_IN_OMAP3430ES2,
1372         .recalc         = &followparent_recalc,
1373 };
1374
1375 /* CORE 96M FCLK-derived clocks */
1376
1377 static struct clk core_96m_fck = {
1378         .name           = "core_96m_fck",
1379         .parent         = &omap_96m_fck,
1380         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1381                                 PARENT_CONTROLS_CLOCK,
1382         .clkdm_name     = "core_l4_clkdm",
1383         .recalc         = &followparent_recalc,
1384 };
1385
1386 static struct clk mmchs3_fck = {
1387         .name           = "mmchs_fck",
1388         .id             = 3,
1389         .parent         = &core_96m_fck,
1390         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1392         .flags          = CLOCK_IN_OMAP3430ES2,
1393         .clkdm_name     = "core_l4_clkdm",
1394         .recalc         = &followparent_recalc,
1395 };
1396
1397 static struct clk mmchs2_fck = {
1398         .name           = "mmchs_fck",
1399         .id             = 2,
1400         .parent         = &core_96m_fck,
1401         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1402         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1403         .flags          = CLOCK_IN_OMAP343X,
1404         .clkdm_name     = "core_l4_clkdm",
1405         .recalc         = &followparent_recalc,
1406 };
1407
1408 static struct clk mspro_fck = {
1409         .name           = "mspro_fck",
1410         .parent         = &core_96m_fck,
1411         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1412         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1413         .flags          = CLOCK_IN_OMAP343X,
1414         .clkdm_name     = "core_l4_clkdm",
1415         .recalc         = &followparent_recalc,
1416 };
1417
1418 static struct clk mmchs1_fck = {
1419         .name           = "mmchs_fck",
1420         .id             = 1,
1421         .parent         = &core_96m_fck,
1422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1423         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1424         .flags          = CLOCK_IN_OMAP343X,
1425         .clkdm_name     = "core_l4_clkdm",
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk i2c3_fck = {
1430         .name           = "i2c_fck",
1431         .id             = 3,
1432         .parent         = &core_96m_fck,
1433         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1435         .flags          = CLOCK_IN_OMAP343X,
1436         .clkdm_name     = "core_l4_clkdm",
1437         .recalc         = &followparent_recalc,
1438 };
1439
1440 static struct clk i2c2_fck = {
1441         .name           = "i2c_fck",
1442         .id             = 2,
1443         .parent         = &core_96m_fck,
1444         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1445         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1446         .flags          = CLOCK_IN_OMAP343X,
1447         .clkdm_name     = "core_l4_clkdm",
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 static struct clk i2c1_fck = {
1452         .name           = "i2c_fck",
1453         .id             = 1,
1454         .parent         = &core_96m_fck,
1455         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1456         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1457         .flags          = CLOCK_IN_OMAP343X,
1458         .clkdm_name     = "core_l4_clkdm",
1459         .recalc         = &followparent_recalc,
1460 };
1461
1462 /*
1463  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1464  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1465  */
1466 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1467         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1468         { .div = 0 }
1469 };
1470
1471 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1472         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1473         { .div = 0 }
1474 };
1475
1476 static const struct clksel mcbsp_15_clksel[] = {
1477         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1478         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1479         { .parent = NULL }
1480 };
1481
1482 static struct clk mcbsp5_fck = {
1483         .name           = "mcbsp5_fck",
1484         .init           = &omap2_init_clksel_parent,
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1487         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1488         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1489         .clksel         = mcbsp_15_clksel,
1490         .flags          = CLOCK_IN_OMAP343X,
1491         .clkdm_name     = "core_l4_clkdm",
1492         .recalc         = &omap2_clksel_recalc,
1493 };
1494
1495 static struct clk mcbsp1_fck = {
1496         .name           = "mcbsp1_fck",
1497         .init           = &omap2_init_clksel_parent,
1498         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1499         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1500         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1501         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1502         .clksel         = mcbsp_15_clksel,
1503         .flags          = CLOCK_IN_OMAP343X,
1504         .clkdm_name     = "core_l4_clkdm",
1505         .recalc         = &omap2_clksel_recalc,
1506 };
1507
1508 /* CORE_48M_FCK-derived clocks */
1509
1510 static struct clk core_48m_fck = {
1511         .name           = "core_48m_fck",
1512         .parent         = &omap_48m_fck,
1513         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1514                                 PARENT_CONTROLS_CLOCK,
1515         .clkdm_name     = "core_l4_clkdm",
1516         .recalc         = &followparent_recalc,
1517 };
1518
1519 static struct clk mcspi4_fck = {
1520         .name           = "mcspi_fck",
1521         .id             = 4,
1522         .parent         = &core_48m_fck,
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1525         .flags          = CLOCK_IN_OMAP343X,
1526         .recalc         = &followparent_recalc,
1527 };
1528
1529 static struct clk mcspi3_fck = {
1530         .name           = "mcspi_fck",
1531         .id             = 3,
1532         .parent         = &core_48m_fck,
1533         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1535         .flags          = CLOCK_IN_OMAP343X,
1536         .recalc         = &followparent_recalc,
1537 };
1538
1539 static struct clk mcspi2_fck = {
1540         .name           = "mcspi_fck",
1541         .id             = 2,
1542         .parent         = &core_48m_fck,
1543         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1545         .flags          = CLOCK_IN_OMAP343X,
1546         .recalc         = &followparent_recalc,
1547 };
1548
1549 static struct clk mcspi1_fck = {
1550         .name           = "mcspi_fck",
1551         .id             = 1,
1552         .parent         = &core_48m_fck,
1553         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1554         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1555         .flags          = CLOCK_IN_OMAP343X,
1556         .recalc         = &followparent_recalc,
1557 };
1558
1559 static struct clk uart2_fck = {
1560         .name           = "uart2_fck",
1561         .parent         = &core_48m_fck,
1562         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1563         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1564         .flags          = CLOCK_IN_OMAP343X,
1565         .recalc         = &followparent_recalc,
1566 };
1567
1568 static struct clk uart1_fck = {
1569         .name           = "uart1_fck",
1570         .parent         = &core_48m_fck,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1573         .flags          = CLOCK_IN_OMAP343X,
1574         .recalc         = &followparent_recalc,
1575 };
1576
1577 static struct clk fshostusb_fck = {
1578         .name           = "fshostusb_fck",
1579         .parent         = &core_48m_fck,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1582         .flags          = CLOCK_IN_OMAP3430ES1,
1583         .recalc         = &followparent_recalc,
1584 };
1585
1586 /* CORE_12M_FCK based clocks */
1587
1588 static struct clk core_12m_fck = {
1589         .name           = "core_12m_fck",
1590         .parent         = &omap_12m_fck,
1591         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1592                                 PARENT_CONTROLS_CLOCK,
1593         .clkdm_name     = "core_l4_clkdm",
1594         .recalc         = &followparent_recalc,
1595 };
1596
1597 static struct clk hdq_fck = {
1598         .name           = "hdq_fck",
1599         .parent         = &core_12m_fck,
1600         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1601         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1602         .flags          = CLOCK_IN_OMAP343X,
1603         .recalc         = &followparent_recalc,
1604 };
1605
1606 /* DPLL3-derived clock */
1607
1608 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1609         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1610         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1611         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1612         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1613         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1614         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1615         { .div = 0 }
1616 };
1617
1618 static const struct clksel ssi_ssr_clksel[] = {
1619         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1620         { .parent = NULL }
1621 };
1622
1623 static struct clk ssi_ssr_fck = {
1624         .name           = "ssi_ssr_fck",
1625         .init           = &omap2_init_clksel_parent,
1626         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1627         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1628         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1629         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1630         .clksel         = ssi_ssr_clksel,
1631         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1632         .clkdm_name     = "core_l4_clkdm",
1633         .recalc         = &omap2_clksel_recalc,
1634 };
1635
1636 static struct clk ssi_sst_fck = {
1637         .name           = "ssi_sst_fck",
1638         .parent         = &ssi_ssr_fck,
1639         .fixed_div      = 2,
1640         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1641         .recalc         = &omap2_fixed_divisor_recalc,
1642 };
1643
1644
1645
1646 /* CORE_L3_ICK based clocks */
1647
1648 /*
1649  * XXX must add clk_enable/clk_disable for these if standard code won't
1650  * handle it
1651  */
1652 static struct clk core_l3_ick = {
1653         .name           = "core_l3_ick",
1654         .parent         = &l3_ick,
1655         .init           = &omap2_init_clk_clkdm,
1656         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1657                                 PARENT_CONTROLS_CLOCK,
1658         .clkdm_name     = "core_l3_clkdm",
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 static struct clk hsotgusb_ick = {
1663         .name           = "hsotgusb_ick",
1664         .parent         = &core_l3_ick,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1667         .flags          = CLOCK_IN_OMAP343X,
1668         .clkdm_name     = "core_l3_clkdm",
1669         .recalc         = &followparent_recalc,
1670 };
1671
1672 static struct clk sdrc_ick = {
1673         .name           = "sdrc_ick",
1674         .parent         = &core_l3_ick,
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1676         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1677         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1678         .clkdm_name     = "core_l3_clkdm",
1679         .recalc         = &followparent_recalc,
1680 };
1681
1682 static struct clk gpmc_fck = {
1683         .name           = "gpmc_fck",
1684         .parent         = &core_l3_ick,
1685         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1686                                 ENABLE_ON_INIT,
1687         .clkdm_name     = "core_l3_clkdm",
1688         .recalc         = &followparent_recalc,
1689 };
1690
1691 /* SECURITY_L3_ICK based clocks */
1692
1693 static struct clk security_l3_ick = {
1694         .name           = "security_l3_ick",
1695         .parent         = &l3_ick,
1696         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1697                                 PARENT_CONTROLS_CLOCK,
1698         .recalc         = &followparent_recalc,
1699 };
1700
1701 static struct clk pka_ick = {
1702         .name           = "pka_ick",
1703         .parent         = &security_l3_ick,
1704         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1705         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1706         .flags          = CLOCK_IN_OMAP343X,
1707         .recalc         = &followparent_recalc,
1708 };
1709
1710 /* CORE_L4_ICK based clocks */
1711
1712 static struct clk core_l4_ick = {
1713         .name           = "core_l4_ick",
1714         .parent         = &l4_ick,
1715         .init           = &omap2_init_clk_clkdm,
1716         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1717                                 PARENT_CONTROLS_CLOCK,
1718         .clkdm_name     = "core_l4_clkdm",
1719         .recalc         = &followparent_recalc,
1720 };
1721
1722 static struct clk usbtll_ick = {
1723         .name           = "usbtll_ick",
1724         .parent         = &core_l4_ick,
1725         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1726         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1727         .flags          = CLOCK_IN_OMAP3430ES2,
1728         .clkdm_name     = "core_l4_clkdm",
1729         .recalc         = &followparent_recalc,
1730 };
1731
1732 static struct clk mmchs3_ick = {
1733         .name           = "mmchs_ick",
1734         .id             = 3,
1735         .parent         = &core_l4_ick,
1736         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1737         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1738         .flags          = CLOCK_IN_OMAP3430ES2,
1739         .clkdm_name     = "core_l4_clkdm",
1740         .recalc         = &followparent_recalc,
1741 };
1742
1743 /* Intersystem Communication Registers - chassis mode only */
1744 static struct clk icr_ick = {
1745         .name           = "icr_ick",
1746         .parent         = &core_l4_ick,
1747         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1749         .flags          = CLOCK_IN_OMAP343X,
1750         .clkdm_name     = "core_l4_clkdm",
1751         .recalc         = &followparent_recalc,
1752 };
1753
1754 static struct clk aes2_ick = {
1755         .name           = "aes2_ick",
1756         .parent         = &core_l4_ick,
1757         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1759         .flags          = CLOCK_IN_OMAP343X,
1760         .clkdm_name     = "core_l4_clkdm",
1761         .recalc         = &followparent_recalc,
1762 };
1763
1764 static struct clk sha12_ick = {
1765         .name           = "sha12_ick",
1766         .parent         = &core_l4_ick,
1767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1769         .flags          = CLOCK_IN_OMAP343X,
1770         .clkdm_name     = "core_l4_clkdm",
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk des2_ick = {
1775         .name           = "des2_ick",
1776         .parent         = &core_l4_ick,
1777         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1778         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1779         .flags          = CLOCK_IN_OMAP343X,
1780         .clkdm_name     = "core_l4_clkdm",
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 static struct clk mmchs2_ick = {
1785         .name           = "mmchs_ick",
1786         .id             = 2,
1787         .parent         = &core_l4_ick,
1788         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1790         .flags          = CLOCK_IN_OMAP343X,
1791         .clkdm_name     = "core_l4_clkdm",
1792         .recalc         = &followparent_recalc,
1793 };
1794
1795 static struct clk mmchs1_ick = {
1796         .name           = "mmchs_ick",
1797         .id             = 1,
1798         .parent         = &core_l4_ick,
1799         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1800         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1801         .flags          = CLOCK_IN_OMAP343X,
1802         .clkdm_name     = "core_l4_clkdm",
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mspro_ick = {
1807         .name           = "mspro_ick",
1808         .parent         = &core_l4_ick,
1809         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1811         .flags          = CLOCK_IN_OMAP343X,
1812         .clkdm_name     = "core_l4_clkdm",
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk hdq_ick = {
1817         .name           = "hdq_ick",
1818         .parent         = &core_l4_ick,
1819         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1821         .flags          = CLOCK_IN_OMAP343X,
1822         .clkdm_name     = "core_l4_clkdm",
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcspi4_ick = {
1827         .name           = "mcspi_ick",
1828         .id             = 4,
1829         .parent         = &core_l4_ick,
1830         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1832         .flags          = CLOCK_IN_OMAP343X,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk mcspi3_ick = {
1838         .name           = "mcspi_ick",
1839         .id             = 3,
1840         .parent         = &core_l4_ick,
1841         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1843         .flags          = CLOCK_IN_OMAP343X,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcspi2_ick = {
1849         .name           = "mcspi_ick",
1850         .id             = 2,
1851         .parent         = &core_l4_ick,
1852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1854         .flags          = CLOCK_IN_OMAP343X,
1855         .clkdm_name     = "core_l4_clkdm",
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk mcspi1_ick = {
1860         .name           = "mcspi_ick",
1861         .id             = 1,
1862         .parent         = &core_l4_ick,
1863         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1864         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1865         .flags          = CLOCK_IN_OMAP343X,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk i2c3_ick = {
1871         .name           = "i2c_ick",
1872         .id             = 3,
1873         .parent         = &core_l4_ick,
1874         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1876         .flags          = CLOCK_IN_OMAP343X,
1877         .clkdm_name     = "core_l4_clkdm",
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk i2c2_ick = {
1882         .name           = "i2c_ick",
1883         .id             = 2,
1884         .parent         = &core_l4_ick,
1885         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1887         .flags          = CLOCK_IN_OMAP343X,
1888         .clkdm_name     = "core_l4_clkdm",
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk i2c1_ick = {
1893         .name           = "i2c_ick",
1894         .id             = 1,
1895         .parent         = &core_l4_ick,
1896         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1897         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1898         .flags          = CLOCK_IN_OMAP343X,
1899         .clkdm_name     = "core_l4_clkdm",
1900         .recalc         = &followparent_recalc,
1901 };
1902
1903 static struct clk uart2_ick = {
1904         .name           = "uart2_ick",
1905         .parent         = &core_l4_ick,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1908         .flags          = CLOCK_IN_OMAP343X,
1909         .clkdm_name     = "core_l4_clkdm",
1910         .recalc         = &followparent_recalc,
1911 };
1912
1913 static struct clk uart1_ick = {
1914         .name           = "uart1_ick",
1915         .parent         = &core_l4_ick,
1916         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1917         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1918         .flags          = CLOCK_IN_OMAP343X,
1919         .clkdm_name     = "core_l4_clkdm",
1920         .recalc         = &followparent_recalc,
1921 };
1922
1923 static struct clk gpt11_ick = {
1924         .name           = "gpt11_ick",
1925         .parent         = &core_l4_ick,
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1928         .flags          = CLOCK_IN_OMAP343X,
1929         .clkdm_name     = "core_l4_clkdm",
1930         .recalc         = &followparent_recalc,
1931 };
1932
1933 static struct clk gpt10_ick = {
1934         .name           = "gpt10_ick",
1935         .parent         = &core_l4_ick,
1936         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1938         .flags          = CLOCK_IN_OMAP343X,
1939         .clkdm_name     = "core_l4_clkdm",
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk mcbsp5_ick = {
1944         .name           = "mcbsp5_ick",
1945         .parent         = &core_l4_ick,
1946         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1948         .flags          = CLOCK_IN_OMAP343X,
1949         .clkdm_name     = "core_l4_clkdm",
1950         .recalc         = &followparent_recalc,
1951 };
1952
1953 static struct clk mcbsp1_ick = {
1954         .name           = "mcbsp1_ick",
1955         .parent         = &core_l4_ick,
1956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1957         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1958         .flags          = CLOCK_IN_OMAP343X,
1959         .clkdm_name     = "core_l4_clkdm",
1960         .recalc         = &followparent_recalc,
1961 };
1962
1963 static struct clk fac_ick = {
1964         .name           = "fac_ick",
1965         .parent         = &core_l4_ick,
1966         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1967         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1968         .flags          = CLOCK_IN_OMAP3430ES1,
1969         .clkdm_name     = "core_l4_clkdm",
1970         .recalc         = &followparent_recalc,
1971 };
1972
1973 static struct clk mailboxes_ick = {
1974         .name           = "mailboxes_ick",
1975         .parent         = &core_l4_ick,
1976         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1978         .flags          = CLOCK_IN_OMAP343X,
1979         .clkdm_name     = "core_l4_clkdm",
1980         .recalc         = &followparent_recalc,
1981 };
1982
1983 static struct clk omapctrl_ick = {
1984         .name           = "omapctrl_ick",
1985         .parent         = &core_l4_ick,
1986         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1988         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1989         .recalc         = &followparent_recalc,
1990 };
1991
1992 /* SSI_L4_ICK based clocks */
1993
1994 static struct clk ssi_l4_ick = {
1995         .name           = "ssi_l4_ick",
1996         .parent         = &l4_ick,
1997         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1998                                 PARENT_CONTROLS_CLOCK,
1999         .clkdm_name     = "core_l4_clkdm",
2000         .recalc         = &followparent_recalc,
2001 };
2002
2003 static struct clk ssi_ick = {
2004         .name           = "ssi_ick",
2005         .parent         = &ssi_l4_ick,
2006         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2008         .flags          = CLOCK_IN_OMAP343X,
2009         .clkdm_name     = "core_l4_clkdm",
2010         .recalc         = &followparent_recalc,
2011 };
2012
2013 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2014  * but l4_ick makes more sense to me */
2015
2016 static const struct clksel usb_l4_clksel[] = {
2017         { .parent = &l4_ick, .rates = div2_rates },
2018         { .parent = NULL },
2019 };
2020
2021 static struct clk usb_l4_ick = {
2022         .name           = "usb_l4_ick",
2023         .parent         = &l4_ick,
2024         .init           = &omap2_init_clksel_parent,
2025         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2026         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2027         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2028         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2029         .clksel         = usb_l4_clksel,
2030         .flags          = CLOCK_IN_OMAP3430ES1,
2031         .recalc         = &omap2_clksel_recalc,
2032 };
2033
2034 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2035
2036 /* SECURITY_L4_ICK2 based clocks */
2037
2038 static struct clk security_l4_ick2 = {
2039         .name           = "security_l4_ick2",
2040         .parent         = &l4_ick,
2041         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2042                                 PARENT_CONTROLS_CLOCK,
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static struct clk aes1_ick = {
2047         .name           = "aes1_ick",
2048         .parent         = &security_l4_ick2,
2049         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2050         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2051         .flags          = CLOCK_IN_OMAP343X,
2052         .recalc         = &followparent_recalc,
2053 };
2054
2055 static struct clk rng_ick = {
2056         .name           = "rng_ick",
2057         .parent         = &security_l4_ick2,
2058         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2059         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2060         .flags          = CLOCK_IN_OMAP343X,
2061         .recalc         = &followparent_recalc,
2062 };
2063
2064 static struct clk sha11_ick = {
2065         .name           = "sha11_ick",
2066         .parent         = &security_l4_ick2,
2067         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2068         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2069         .flags          = CLOCK_IN_OMAP343X,
2070         .recalc         = &followparent_recalc,
2071 };
2072
2073 static struct clk des1_ick = {
2074         .name           = "des1_ick",
2075         .parent         = &security_l4_ick2,
2076         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2077         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2078         .flags          = CLOCK_IN_OMAP343X,
2079         .recalc         = &followparent_recalc,
2080 };
2081
2082 /* DSS */
2083 static const struct clksel dss1_alwon_fck_clksel[] = {
2084         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2085         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2086         { .parent = NULL }
2087 };
2088
2089 static struct clk dss1_alwon_fck = {
2090         .name           = "dss1_alwon_fck",
2091         .parent         = &dpll4_m4x2_ck,
2092         .init           = &omap2_init_clksel_parent,
2093         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2094         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2095         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2096         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2097         .clksel         = dss1_alwon_fck_clksel,
2098         .flags          = CLOCK_IN_OMAP343X,
2099         .clkdm_name     = "dss_clkdm",
2100         .recalc         = &omap2_clksel_recalc,
2101 };
2102
2103 static struct clk dss_tv_fck = {
2104         .name           = "dss_tv_fck",
2105         .parent         = &omap_54m_fck,
2106         .init           = &omap2_init_clk_clkdm,
2107         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2108         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2109         .flags          = CLOCK_IN_OMAP343X,
2110         .clkdm_name     = "dss_clkdm",
2111         .recalc         = &followparent_recalc,
2112 };
2113
2114 static struct clk dss_96m_fck = {
2115         .name           = "dss_96m_fck",
2116         .parent         = &omap_96m_fck,
2117         .init           = &omap2_init_clk_clkdm,
2118         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2119         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2120         .flags          = CLOCK_IN_OMAP343X,
2121         .clkdm_name     = "dss_clkdm",
2122         .recalc         = &followparent_recalc,
2123 };
2124
2125 static struct clk dss2_alwon_fck = {
2126         .name           = "dss2_alwon_fck",
2127         .parent         = &sys_ck,
2128         .init           = &omap2_init_clk_clkdm,
2129         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2130         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2131         .flags          = CLOCK_IN_OMAP343X,
2132         .clkdm_name     = "dss_clkdm",
2133         .recalc         = &followparent_recalc,
2134 };
2135
2136 static struct clk dss_ick = {
2137         /* Handles both L3 and L4 clocks */
2138         .name           = "dss_ick",
2139         .parent         = &l4_ick,
2140         .init           = &omap2_init_clk_clkdm,
2141         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2142         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2143         .flags          = CLOCK_IN_OMAP343X,
2144         .clkdm_name     = "dss_clkdm",
2145         .recalc         = &followparent_recalc,
2146 };
2147
2148 /* CAM */
2149
2150 static const struct clksel cam_mclk_clksel[] = {
2151         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2152         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2153         { .parent = NULL }
2154 };
2155
2156 static struct clk cam_mclk = {
2157         .name           = "cam_mclk",
2158         .parent         = &dpll4_m5x2_ck,
2159         .init           = &omap2_init_clksel_parent,
2160         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2161         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2162         .clksel         = cam_mclk_clksel,
2163         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2164         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2165         .flags          = CLOCK_IN_OMAP343X,
2166         .clkdm_name     = "cam_clkdm",
2167         .recalc         = &omap2_clksel_recalc,
2168 };
2169
2170 static struct clk cam_ick = {
2171         /* Handles both L3 and L4 clocks */
2172         .name           = "cam_ick",
2173         .parent         = &l4_ick,
2174         .init           = &omap2_init_clk_clkdm,
2175         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2176         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2177         .flags          = CLOCK_IN_OMAP343X,
2178         .clkdm_name     = "cam_clkdm",
2179         .recalc         = &followparent_recalc,
2180 };
2181
2182 /* USBHOST - 3430ES2 only */
2183
2184 static struct clk usbhost_120m_fck = {
2185         .name           = "usbhost_120m_fck",
2186         .parent         = &omap_120m_fck,
2187         .init           = &omap2_init_clk_clkdm,
2188         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2189         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2190         .flags          = CLOCK_IN_OMAP3430ES2,
2191         .clkdm_name     = "usbhost_clkdm",
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk usbhost_48m_fck = {
2196         .name           = "usbhost_48m_fck",
2197         .parent         = &omap_48m_fck,
2198         .init           = &omap2_init_clk_clkdm,
2199         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2200         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2201         .flags          = CLOCK_IN_OMAP3430ES2,
2202         .clkdm_name     = "usbhost_clkdm",
2203         .recalc         = &followparent_recalc,
2204 };
2205
2206 static struct clk usbhost_ick = {
2207         /* Handles both L3 and L4 clocks */
2208         .name           = "usbhost_ick",
2209         .parent         = &l4_ick,
2210         .init           = &omap2_init_clk_clkdm,
2211         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2212         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2213         .flags          = CLOCK_IN_OMAP3430ES2,
2214         .clkdm_name     = "usbhost_clkdm",
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 static struct clk usbhost_sar_fck = {
2219         .name           = "usbhost_sar_fck",
2220         .parent         = &osc_sys_ck,
2221         .init           = &omap2_init_clk_clkdm,
2222         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2223         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2224         .flags          = CLOCK_IN_OMAP3430ES2,
2225         .clkdm_name     = "usbhost_clkdm",
2226         .recalc         = &followparent_recalc,
2227 };
2228
2229 /* WKUP */
2230
2231 static const struct clksel_rate usim_96m_rates[] = {
2232         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2233         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2234         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2235         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2236         { .div = 0 },
2237 };
2238
2239 static const struct clksel_rate usim_120m_rates[] = {
2240         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2241         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2242         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2243         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2244         { .div = 0 },
2245 };
2246
2247 static const struct clksel usim_clksel[] = {
2248         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2249         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2250         { .parent = &sys_ck,            .rates = div2_rates },
2251         { .parent = NULL },
2252 };
2253
2254 /* 3430ES2 only */
2255 static struct clk usim_fck = {
2256         .name           = "usim_fck",
2257         .init           = &omap2_init_clksel_parent,
2258         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2259         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2260         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2261         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2262         .clksel         = usim_clksel,
2263         .flags          = CLOCK_IN_OMAP3430ES2,
2264         .recalc         = &omap2_clksel_recalc,
2265 };
2266
2267 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2268 static struct clk gpt1_fck = {
2269         .name           = "gpt1_fck",
2270         .init           = &omap2_init_clksel_parent,
2271         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2272         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2273         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2274         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2275         .clksel         = omap343x_gpt_clksel,
2276         .flags          = CLOCK_IN_OMAP343X,
2277         .clkdm_name     = "wkup_clkdm",
2278         .recalc         = &omap2_clksel_recalc,
2279 };
2280
2281 static struct clk wkup_32k_fck = {
2282         .name           = "wkup_32k_fck",
2283         .init           = &omap2_init_clk_clkdm,
2284         .parent         = &omap_32k_fck,
2285         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2286         .clkdm_name     = "wkup_clkdm",
2287         .recalc         = &followparent_recalc,
2288 };
2289
2290 static struct clk gpio1_fck = {
2291         .name           = "gpio1_fck",
2292         .parent         = &wkup_32k_fck,
2293         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2294         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2295         .flags          = CLOCK_IN_OMAP343X,
2296         .clkdm_name     = "wkup_clkdm",
2297         .recalc         = &followparent_recalc,
2298 };
2299
2300 static struct clk wdt2_fck = {
2301         .name           = "wdt2_fck",
2302         .parent         = &wkup_32k_fck,
2303         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2304         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2305         .flags          = CLOCK_IN_OMAP343X,
2306         .clkdm_name     = "wkup_clkdm",
2307         .recalc         = &followparent_recalc,
2308 };
2309
2310 static struct clk wkup_l4_ick = {
2311         .name           = "wkup_l4_ick",
2312         .parent         = &sys_ck,
2313         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2314         .clkdm_name     = "wkup_clkdm",
2315         .recalc         = &followparent_recalc,
2316 };
2317
2318 /* 3430ES2 only */
2319 /* Never specifically named in the TRM, so we have to infer a likely name */
2320 static struct clk usim_ick = {
2321         .name           = "usim_ick",
2322         .parent         = &wkup_l4_ick,
2323         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2324         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2325         .flags          = CLOCK_IN_OMAP3430ES2,
2326         .clkdm_name     = "wkup_clkdm",
2327         .recalc         = &followparent_recalc,
2328 };
2329
2330 static struct clk wdt2_ick = {
2331         .name           = "wdt2_ick",
2332         .parent         = &wkup_l4_ick,
2333         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2334         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2335         .flags          = CLOCK_IN_OMAP343X,
2336         .clkdm_name     = "wkup_clkdm",
2337         .recalc         = &followparent_recalc,
2338 };
2339
2340 static struct clk wdt1_ick = {
2341         .name           = "wdt1_ick",
2342         .parent         = &wkup_l4_ick,
2343         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2344         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2345         .flags          = CLOCK_IN_OMAP343X,
2346         .clkdm_name     = "wkup_clkdm",
2347         .recalc         = &followparent_recalc,
2348 };
2349
2350 static struct clk gpio1_ick = {
2351         .name           = "gpio1_ick",
2352         .parent         = &wkup_l4_ick,
2353         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2354         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2355         .flags          = CLOCK_IN_OMAP343X,
2356         .clkdm_name     = "wkup_clkdm",
2357         .recalc         = &followparent_recalc,
2358 };
2359
2360 static struct clk omap_32ksync_ick = {
2361         .name           = "omap_32ksync_ick",
2362         .parent         = &wkup_l4_ick,
2363         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2364         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2365         .flags          = CLOCK_IN_OMAP343X,
2366         .clkdm_name     = "wkup_clkdm",
2367         .recalc         = &followparent_recalc,
2368 };
2369
2370 /* XXX This clock no longer exists in 3430 TRM rev F */
2371 static struct clk gpt12_ick = {
2372         .name           = "gpt12_ick",
2373         .parent         = &wkup_l4_ick,
2374         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2375         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2376         .flags          = CLOCK_IN_OMAP343X,
2377         .clkdm_name     = "wkup_clkdm",
2378         .recalc         = &followparent_recalc,
2379 };
2380
2381 static struct clk gpt1_ick = {
2382         .name           = "gpt1_ick",
2383         .parent         = &wkup_l4_ick,
2384         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2385         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2386         .flags          = CLOCK_IN_OMAP343X,
2387         .clkdm_name     = "wkup_clkdm",
2388         .recalc         = &followparent_recalc,
2389 };
2390
2391
2392
2393 /* PER clock domain */
2394
2395 static struct clk per_96m_fck = {
2396         .name           = "per_96m_fck",
2397         .parent         = &omap_96m_alwon_fck,
2398         .init           = &omap2_init_clk_clkdm,
2399         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2400                                 PARENT_CONTROLS_CLOCK,
2401         .clkdm_name     = "per_clkdm",
2402         .recalc         = &followparent_recalc,
2403 };
2404
2405 static struct clk per_48m_fck = {
2406         .name           = "per_48m_fck",
2407         .parent         = &omap_48m_fck,
2408         .init           = &omap2_init_clk_clkdm,
2409         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2410                                 PARENT_CONTROLS_CLOCK,
2411         .clkdm_name     = "per_clkdm",
2412         .recalc         = &followparent_recalc,
2413 };
2414
2415 static struct clk uart3_fck = {
2416         .name           = "uart3_fck",
2417         .parent         = &per_48m_fck,
2418         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2419         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2420         .flags          = CLOCK_IN_OMAP343X,
2421         .clkdm_name     = "per_clkdm",
2422         .recalc         = &followparent_recalc,
2423 };
2424
2425 static struct clk gpt2_fck = {
2426         .name           = "gpt2_fck",
2427         .init           = &omap2_init_clksel_parent,
2428         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2429         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2430         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2431         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2432         .clksel         = omap343x_gpt_clksel,
2433         .flags          = CLOCK_IN_OMAP343X,
2434         .clkdm_name     = "per_clkdm",
2435         .recalc         = &omap2_clksel_recalc,
2436 };
2437
2438 static struct clk gpt3_fck = {
2439         .name           = "gpt3_fck",
2440         .init           = &omap2_init_clksel_parent,
2441         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2442         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2443         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2444         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2445         .clksel         = omap343x_gpt_clksel,
2446         .flags          = CLOCK_IN_OMAP343X,
2447         .clkdm_name     = "per_clkdm",
2448         .recalc         = &omap2_clksel_recalc,
2449 };
2450
2451 static struct clk gpt4_fck = {
2452         .name           = "gpt4_fck",
2453         .init           = &omap2_init_clksel_parent,
2454         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2455         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2456         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2457         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2458         .clksel         = omap343x_gpt_clksel,
2459         .flags          = CLOCK_IN_OMAP343X,
2460         .clkdm_name     = "per_clkdm",
2461         .recalc         = &omap2_clksel_recalc,
2462 };
2463
2464 static struct clk gpt5_fck = {
2465         .name           = "gpt5_fck",
2466         .init           = &omap2_init_clksel_parent,
2467         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2469         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2470         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2471         .clksel         = omap343x_gpt_clksel,
2472         .flags          = CLOCK_IN_OMAP343X,
2473         .clkdm_name     = "per_clkdm",
2474         .recalc         = &omap2_clksel_recalc,
2475 };
2476
2477 static struct clk gpt6_fck = {
2478         .name           = "gpt6_fck",
2479         .init           = &omap2_init_clksel_parent,
2480         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2481         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2482         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2483         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2484         .clksel         = omap343x_gpt_clksel,
2485         .flags          = CLOCK_IN_OMAP343X,
2486         .clkdm_name     = "per_clkdm",
2487         .recalc         = &omap2_clksel_recalc,
2488 };
2489
2490 static struct clk gpt7_fck = {
2491         .name           = "gpt7_fck",
2492         .init           = &omap2_init_clksel_parent,
2493         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2494         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2495         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2496         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2497         .clksel         = omap343x_gpt_clksel,
2498         .flags          = CLOCK_IN_OMAP343X,
2499         .clkdm_name     = "per_clkdm",
2500         .recalc         = &omap2_clksel_recalc,
2501 };
2502
2503 static struct clk gpt8_fck = {
2504         .name           = "gpt8_fck",
2505         .init           = &omap2_init_clksel_parent,
2506         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2507         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2508         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2509         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2510         .clksel         = omap343x_gpt_clksel,
2511         .flags          = CLOCK_IN_OMAP343X,
2512         .clkdm_name     = "per_clkdm",
2513         .recalc         = &omap2_clksel_recalc,
2514 };
2515
2516 static struct clk gpt9_fck = {
2517         .name           = "gpt9_fck",
2518         .init           = &omap2_init_clksel_parent,
2519         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2520         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2521         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2522         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2523         .clksel         = omap343x_gpt_clksel,
2524         .flags          = CLOCK_IN_OMAP343X,
2525         .clkdm_name     = "per_clkdm",
2526         .recalc         = &omap2_clksel_recalc,
2527 };
2528
2529 static struct clk per_32k_alwon_fck = {
2530         .name           = "per_32k_alwon_fck",
2531         .parent         = &omap_32k_fck,
2532         .clkdm_name     = "per_clkdm",
2533         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2534         .recalc         = &followparent_recalc,
2535 };
2536
2537 static struct clk gpio6_fck = {
2538         .name           = "gpio6_fck",
2539         .parent         = &per_32k_alwon_fck,
2540         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2541         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2542         .flags          = CLOCK_IN_OMAP343X,
2543         .clkdm_name     = "per_clkdm",
2544         .recalc         = &followparent_recalc,
2545 };
2546
2547 static struct clk gpio5_fck = {
2548         .name           = "gpio5_fck",
2549         .parent         = &per_32k_alwon_fck,
2550         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2551         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2552         .flags          = CLOCK_IN_OMAP343X,
2553         .clkdm_name     = "per_clkdm",
2554         .recalc         = &followparent_recalc,
2555 };
2556
2557 static struct clk gpio4_fck = {
2558         .name           = "gpio4_fck",
2559         .parent         = &per_32k_alwon_fck,
2560         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2561         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2562         .flags          = CLOCK_IN_OMAP343X,
2563         .clkdm_name     = "per_clkdm",
2564         .recalc         = &followparent_recalc,
2565 };
2566
2567 static struct clk gpio3_fck = {
2568         .name           = "gpio3_fck",
2569         .parent         = &per_32k_alwon_fck,
2570         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2571         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2572         .flags          = CLOCK_IN_OMAP343X,
2573         .clkdm_name     = "per_clkdm",
2574         .recalc         = &followparent_recalc,
2575 };
2576
2577 static struct clk gpio2_fck = {
2578         .name           = "gpio2_fck",
2579         .parent         = &per_32k_alwon_fck,
2580         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2581         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2582         .flags          = CLOCK_IN_OMAP343X,
2583         .clkdm_name     = "per_clkdm",
2584         .recalc         = &followparent_recalc,
2585 };
2586
2587 static struct clk wdt3_fck = {
2588         .name           = "wdt3_fck",
2589         .parent         = &per_32k_alwon_fck,
2590         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2591         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2592         .flags          = CLOCK_IN_OMAP343X,
2593         .clkdm_name     = "per_clkdm",
2594         .recalc         = &followparent_recalc,
2595 };
2596
2597 static struct clk per_l4_ick = {
2598         .name           = "per_l4_ick",
2599         .parent         = &l4_ick,
2600         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2601                                 PARENT_CONTROLS_CLOCK,
2602         .clkdm_name     = "per_clkdm",
2603         .recalc         = &followparent_recalc,
2604 };
2605
2606 static struct clk gpio6_ick = {
2607         .name           = "gpio6_ick",
2608         .parent         = &per_l4_ick,
2609         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2610         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2611         .flags          = CLOCK_IN_OMAP343X,
2612         .clkdm_name     = "per_clkdm",
2613         .recalc         = &followparent_recalc,
2614 };
2615
2616 static struct clk gpio5_ick = {
2617         .name           = "gpio5_ick",
2618         .parent         = &per_l4_ick,
2619         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2620         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2621         .flags          = CLOCK_IN_OMAP343X,
2622         .clkdm_name     = "per_clkdm",
2623         .recalc         = &followparent_recalc,
2624 };
2625
2626 static struct clk gpio4_ick = {
2627         .name           = "gpio4_ick",
2628         .parent         = &per_l4_ick,
2629         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2630         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2631         .flags          = CLOCK_IN_OMAP343X,
2632         .clkdm_name     = "per_clkdm",
2633         .recalc         = &followparent_recalc,
2634 };
2635
2636 static struct clk gpio3_ick = {
2637         .name           = "gpio3_ick",
2638         .parent         = &per_l4_ick,
2639         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2640         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2641         .flags          = CLOCK_IN_OMAP343X,
2642         .clkdm_name     = "per_clkdm",
2643         .recalc         = &followparent_recalc,
2644 };
2645
2646 static struct clk gpio2_ick = {
2647         .name           = "gpio2_ick",
2648         .parent         = &per_l4_ick,
2649         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2650         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2651         .flags          = CLOCK_IN_OMAP343X,
2652         .clkdm_name     = "per_clkdm",
2653         .recalc         = &followparent_recalc,
2654 };
2655
2656 static struct clk wdt3_ick = {
2657         .name           = "wdt3_ick",
2658         .parent         = &per_l4_ick,
2659         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2660         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2661         .flags          = CLOCK_IN_OMAP343X,
2662         .clkdm_name     = "per_clkdm",
2663         .recalc         = &followparent_recalc,
2664 };
2665
2666 static struct clk uart3_ick = {
2667         .name           = "uart3_ick",
2668         .parent         = &per_l4_ick,
2669         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2670         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2671         .flags          = CLOCK_IN_OMAP343X,
2672         .clkdm_name     = "per_clkdm",
2673         .recalc         = &followparent_recalc,
2674 };
2675
2676 static struct clk gpt9_ick = {
2677         .name           = "gpt9_ick",
2678         .parent         = &per_l4_ick,
2679         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2680         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2681         .flags          = CLOCK_IN_OMAP343X,
2682         .clkdm_name     = "per_clkdm",
2683         .recalc         = &followparent_recalc,
2684 };
2685
2686 static struct clk gpt8_ick = {
2687         .name           = "gpt8_ick",
2688         .parent         = &per_l4_ick,
2689         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2690         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2691         .flags          = CLOCK_IN_OMAP343X,
2692         .clkdm_name     = "per_clkdm",
2693         .recalc         = &followparent_recalc,
2694 };
2695
2696 static struct clk gpt7_ick = {
2697         .name           = "gpt7_ick",
2698         .parent         = &per_l4_ick,
2699         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2700         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2701         .flags          = CLOCK_IN_OMAP343X,
2702         .clkdm_name     = "per_clkdm",
2703         .recalc         = &followparent_recalc,
2704 };
2705
2706 static struct clk gpt6_ick = {
2707         .name           = "gpt6_ick",
2708         .parent         = &per_l4_ick,
2709         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2710         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2711         .flags          = CLOCK_IN_OMAP343X,
2712         .clkdm_name     = "per_clkdm",
2713         .recalc         = &followparent_recalc,
2714 };
2715
2716 static struct clk gpt5_ick = {
2717         .name           = "gpt5_ick",
2718         .parent         = &per_l4_ick,
2719         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2720         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2721         .flags          = CLOCK_IN_OMAP343X,
2722         .clkdm_name     = "per_clkdm",
2723         .recalc         = &followparent_recalc,
2724 };
2725
2726 static struct clk gpt4_ick = {
2727         .name           = "gpt4_ick",
2728         .parent         = &per_l4_ick,
2729         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2730         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2731         .flags          = CLOCK_IN_OMAP343X,
2732         .clkdm_name     = "per_clkdm",
2733         .recalc         = &followparent_recalc,
2734 };
2735
2736 static struct clk gpt3_ick = {
2737         .name           = "gpt3_ick",
2738         .parent         = &per_l4_ick,
2739         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2740         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2741         .flags          = CLOCK_IN_OMAP343X,
2742         .clkdm_name     = "per_clkdm",
2743         .recalc         = &followparent_recalc,
2744 };
2745
2746 static struct clk gpt2_ick = {
2747         .name           = "gpt2_ick",
2748         .parent         = &per_l4_ick,
2749         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2750         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2751         .flags          = CLOCK_IN_OMAP343X,
2752         .clkdm_name     = "per_clkdm",
2753         .recalc         = &followparent_recalc,
2754 };
2755
2756 static struct clk mcbsp2_ick = {
2757         .name           = "mcbsp2_ick",
2758         .parent         = &per_l4_ick,
2759         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2760         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2761         .flags          = CLOCK_IN_OMAP343X,
2762         .clkdm_name     = "per_clkdm",
2763         .recalc         = &followparent_recalc,
2764 };
2765
2766 static struct clk mcbsp3_ick = {
2767         .name           = "mcbsp3_ick",
2768         .parent         = &per_l4_ick,
2769         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2770         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2771         .flags          = CLOCK_IN_OMAP343X,
2772         .clkdm_name     = "per_clkdm",
2773         .recalc         = &followparent_recalc,
2774 };
2775
2776 static struct clk mcbsp4_ick = {
2777         .name           = "mcbsp4_ick",
2778         .parent         = &per_l4_ick,
2779         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2780         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2781         .flags          = CLOCK_IN_OMAP343X,
2782         .clkdm_name     = "per_clkdm",
2783         .recalc         = &followparent_recalc,
2784 };
2785
2786 static const struct clksel mcbsp_234_clksel[] = {
2787         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2788         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2789         { .parent = NULL }
2790 };
2791
2792 static struct clk mcbsp2_fck = {
2793         .name           = "mcbsp2_fck",
2794         .init           = &omap2_init_clksel_parent,
2795         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2796         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2797         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2798         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2799         .clksel         = mcbsp_234_clksel,
2800         .flags          = CLOCK_IN_OMAP343X,
2801         .clkdm_name     = "per_clkdm",
2802         .recalc         = &omap2_clksel_recalc,
2803 };
2804
2805 static struct clk mcbsp3_fck = {
2806         .name           = "mcbsp3_fck",
2807         .init           = &omap2_init_clksel_parent,
2808         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2809         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2810         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2811         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2812         .clksel         = mcbsp_234_clksel,
2813         .flags          = CLOCK_IN_OMAP343X,
2814         .clkdm_name     = "per_clkdm",
2815         .recalc         = &omap2_clksel_recalc,
2816 };
2817
2818 static struct clk mcbsp4_fck = {
2819         .name           = "mcbsp4_fck",
2820         .init           = &omap2_init_clksel_parent,
2821         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2822         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2823         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2824         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2825         .clksel         = mcbsp_234_clksel,
2826         .flags          = CLOCK_IN_OMAP343X,
2827         .clkdm_name     = "per_clkdm",
2828         .recalc         = &omap2_clksel_recalc,
2829 };
2830
2831 /* EMU clocks */
2832
2833 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2834
2835 static const struct clksel_rate emu_src_sys_rates[] = {
2836         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2837         { .div = 0 },
2838 };
2839
2840 static const struct clksel_rate emu_src_core_rates[] = {
2841         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2842         { .div = 0 },
2843 };
2844
2845 static const struct clksel_rate emu_src_per_rates[] = {
2846         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2847         { .div = 0 },
2848 };
2849
2850 static const struct clksel_rate emu_src_mpu_rates[] = {
2851         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2852         { .div = 0 },
2853 };
2854
2855 static const struct clksel emu_src_clksel[] = {
2856         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2857         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2858         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2859         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2860         { .parent = NULL },
2861 };
2862
2863 /*
2864  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2865  * to switch the source of some of the EMU clocks.
2866  * XXX Are there CLKEN bits for these EMU clks?
2867  */
2868 static struct clk emu_src_ck = {
2869         .name           = "emu_src_ck",
2870         .init           = &omap2_init_clksel_parent,
2871         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2872         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2873         .clksel         = emu_src_clksel,
2874         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2875         .clkdm_name     = "emu_clkdm",
2876         .recalc         = &omap2_clksel_recalc,
2877 };
2878
2879 static const struct clksel_rate pclk_emu_rates[] = {
2880         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2881         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2882         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2883         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2884         { .div = 0 },
2885 };
2886
2887 static const struct clksel pclk_emu_clksel[] = {
2888         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2889         { .parent = NULL },
2890 };
2891
2892 static struct clk pclk_fck = {
2893         .name           = "pclk_fck",
2894         .init           = &omap2_init_clksel_parent,
2895         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2896         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2897         .clksel         = pclk_emu_clksel,
2898         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2899         .clkdm_name     = "emu_clkdm",
2900         .recalc         = &omap2_clksel_recalc,
2901 };
2902
2903 static const struct clksel_rate pclkx2_emu_rates[] = {
2904         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2905         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2906         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2907         { .div = 0 },
2908 };
2909
2910 static const struct clksel pclkx2_emu_clksel[] = {
2911         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2912         { .parent = NULL },
2913 };
2914
2915 static struct clk pclkx2_fck = {
2916         .name           = "pclkx2_fck",
2917         .init           = &omap2_init_clksel_parent,
2918         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2919         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2920         .clksel         = pclkx2_emu_clksel,
2921         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2922         .clkdm_name     = "emu_clkdm",
2923         .recalc         = &omap2_clksel_recalc,
2924 };
2925
2926 static const struct clksel atclk_emu_clksel[] = {
2927         { .parent = &emu_src_ck, .rates = div2_rates },
2928         { .parent = NULL },
2929 };
2930
2931 static struct clk atclk_fck = {
2932         .name           = "atclk_fck",
2933         .init           = &omap2_init_clksel_parent,
2934         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2935         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2936         .clksel         = atclk_emu_clksel,
2937         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2938         .clkdm_name     = "emu_clkdm",
2939         .recalc         = &omap2_clksel_recalc,
2940 };
2941
2942 static struct clk traceclk_src_fck = {
2943         .name           = "traceclk_src_fck",
2944         .init           = &omap2_init_clksel_parent,
2945         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2946         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2947         .clksel         = emu_src_clksel,
2948         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2949         .clkdm_name     = "emu_clkdm",
2950         .recalc         = &omap2_clksel_recalc,
2951 };
2952
2953 static const struct clksel_rate traceclk_rates[] = {
2954         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2955         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2956         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2957         { .div = 0 },
2958 };
2959
2960 static const struct clksel traceclk_clksel[] = {
2961         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2962         { .parent = NULL },
2963 };
2964
2965 static struct clk traceclk_fck = {
2966         .name           = "traceclk_fck",
2967         .init           = &omap2_init_clksel_parent,
2968         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2969         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2970         .clksel         = traceclk_clksel,
2971         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2972         .clkdm_name     = "emu_clkdm",
2973         .recalc         = &omap2_clksel_recalc,
2974 };
2975
2976 /* SR clocks */
2977
2978 /* SmartReflex fclk (VDD1) */
2979 static struct clk sr1_fck = {
2980         .name           = "sr1_fck",
2981         .parent         = &sys_ck,
2982         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2983         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2984         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2985         .recalc         = &followparent_recalc,
2986 };
2987
2988 /* SmartReflex fclk (VDD2) */
2989 static struct clk sr2_fck = {
2990         .name           = "sr2_fck",
2991         .parent         = &sys_ck,
2992         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2993         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2994         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2995         .recalc         = &followparent_recalc,
2996 };
2997
2998 static struct clk sr_l4_ick = {
2999         .name           = "sr_l4_ick",
3000         .parent         = &l4_ick,
3001         .flags          = CLOCK_IN_OMAP343X,
3002         .clkdm_name     = "core_l4_clkdm",
3003         .recalc         = &followparent_recalc,
3004 };
3005
3006 /* SECURE_32K_FCK clocks */
3007
3008 /* XXX This clock no longer exists in 3430 TRM rev F */
3009 static struct clk gpt12_fck = {
3010         .name           = "gpt12_fck",
3011         .parent         = &secure_32k_fck,
3012         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3013         .recalc         = &followparent_recalc,
3014 };
3015
3016 static struct clk wdt1_fck = {
3017         .name           = "wdt1_fck",
3018         .parent         = &secure_32k_fck,
3019         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3020         .recalc         = &followparent_recalc,
3021 };
3022
3023 static struct clk *onchip_34xx_clks[] __initdata = {
3024         &omap_32k_fck,
3025         &virt_12m_ck,
3026         &virt_13m_ck,
3027         &virt_16_8m_ck,
3028         &virt_19_2m_ck,
3029         &virt_26m_ck,
3030         &virt_38_4m_ck,
3031         &osc_sys_ck,
3032         &sys_ck,
3033         &sys_altclk,
3034         &mcbsp_clks,
3035         &sys_clkout1,
3036         &dpll1_ck,
3037         &dpll1_x2_ck,
3038         &dpll1_x2m2_ck,
3039         &dpll2_ck,
3040         &dpll2_m2_ck,
3041         &dpll3_ck,
3042         &core_ck,
3043         &dpll3_x2_ck,
3044         &dpll3_m2_ck,
3045         &dpll3_m2x2_ck,
3046         &dpll3_m3_ck,
3047         &dpll3_m3x2_ck,
3048         &emu_core_alwon_ck,
3049         &dpll4_ck,
3050         &dpll4_x2_ck,
3051         &omap_96m_alwon_fck,
3052         &omap_96m_fck,
3053         &cm_96m_fck,
3054         &virt_omap_54m_fck,
3055         &omap_54m_fck,
3056         &omap_48m_fck,
3057         &omap_12m_fck,
3058         &dpll4_m2_ck,
3059         &dpll4_m2x2_ck,
3060         &dpll4_m3_ck,
3061         &dpll4_m3x2_ck,
3062         &dpll4_m4_ck,
3063         &dpll4_m4x2_ck,
3064         &dpll4_m5_ck,
3065         &dpll4_m5x2_ck,
3066         &dpll4_m6_ck,
3067         &dpll4_m6x2_ck,
3068         &emu_per_alwon_ck,
3069         &dpll5_ck,
3070         &dpll5_m2_ck,
3071         &omap_120m_fck,
3072         &clkout2_src_ck,
3073         &sys_clkout2,
3074         &corex2_fck,
3075         &dpll1_fck,
3076         &mpu_ck,
3077         &arm_fck,
3078         &emu_mpu_alwon_ck,
3079         &dpll2_fck,
3080         &iva2_ck,
3081         &l3_ick,
3082         &l4_ick,
3083         &rm_ick,
3084         &gfx_l3_ck,
3085         &gfx_l3_fck,
3086         &gfx_l3_ick,
3087         &gfx_cg1_ck,
3088         &gfx_cg2_ck,
3089         &sgx_fck,
3090         &sgx_ick,
3091         &d2d_26m_fck,
3092         &gpt10_fck,
3093         &gpt11_fck,
3094         &cpefuse_fck,
3095         &ts_fck,
3096         &usbtll_fck,
3097         &core_96m_fck,
3098         &mmchs3_fck,
3099         &mmchs2_fck,
3100         &mspro_fck,
3101         &mmchs1_fck,
3102         &i2c3_fck,
3103         &i2c2_fck,
3104         &i2c1_fck,
3105         &mcbsp5_fck,
3106         &mcbsp1_fck,
3107         &core_48m_fck,
3108         &mcspi4_fck,
3109         &mcspi3_fck,
3110         &mcspi2_fck,
3111         &mcspi1_fck,
3112         &uart2_fck,
3113         &uart1_fck,
3114         &fshostusb_fck,
3115         &core_12m_fck,
3116         &hdq_fck,
3117         &ssi_ssr_fck,
3118         &ssi_sst_fck,
3119         &core_l3_ick,
3120         &hsotgusb_ick,
3121         &sdrc_ick,
3122         &gpmc_fck,
3123         &security_l3_ick,
3124         &pka_ick,
3125         &core_l4_ick,
3126         &usbtll_ick,
3127         &mmchs3_ick,
3128         &icr_ick,
3129         &aes2_ick,
3130         &sha12_ick,
3131         &des2_ick,
3132         &mmchs2_ick,
3133         &mmchs1_ick,
3134         &mspro_ick,
3135         &hdq_ick,
3136         &mcspi4_ick,
3137         &mcspi3_ick,
3138         &mcspi2_ick,
3139         &mcspi1_ick,
3140         &i2c3_ick,
3141         &i2c2_ick,
3142         &i2c1_ick,
3143         &uart2_ick,
3144         &uart1_ick,
3145         &gpt11_ick,
3146         &gpt10_ick,
3147         &mcbsp5_ick,
3148         &mcbsp1_ick,
3149         &fac_ick,
3150         &mailboxes_ick,
3151         &omapctrl_ick,
3152         &ssi_l4_ick,
3153         &ssi_ick,
3154         &usb_l4_ick,
3155         &security_l4_ick2,
3156         &aes1_ick,
3157         &rng_ick,
3158         &sha11_ick,
3159         &des1_ick,
3160         &dss1_alwon_fck,
3161         &dss_tv_fck,
3162         &dss_96m_fck,
3163         &dss2_alwon_fck,
3164         &dss_ick,
3165         &cam_mclk,
3166         &cam_ick,
3167         &usbhost_120m_fck,
3168         &usbhost_48m_fck,
3169         &usbhost_ick,
3170         &usbhost_sar_fck,
3171         &usim_fck,
3172         &gpt1_fck,
3173         &wkup_32k_fck,
3174         &gpio1_fck,
3175         &wdt2_fck,
3176         &wkup_l4_ick,
3177         &usim_ick,
3178         &wdt2_ick,
3179         &wdt1_ick,
3180         &gpio1_ick,
3181         &omap_32ksync_ick,
3182         &gpt12_ick,
3183         &gpt1_ick,
3184         &per_96m_fck,
3185         &per_48m_fck,
3186         &uart3_fck,
3187         &gpt2_fck,
3188         &gpt3_fck,
3189         &gpt4_fck,
3190         &gpt5_fck,
3191         &gpt6_fck,
3192         &gpt7_fck,
3193         &gpt8_fck,
3194         &gpt9_fck,
3195         &per_32k_alwon_fck,
3196         &gpio6_fck,
3197         &gpio5_fck,
3198         &gpio4_fck,
3199         &gpio3_fck,
3200         &gpio2_fck,
3201         &wdt3_fck,
3202         &per_l4_ick,
3203         &gpio6_ick,
3204         &gpio5_ick,
3205         &gpio4_ick,
3206         &gpio3_ick,
3207         &gpio2_ick,
3208         &wdt3_ick,
3209         &uart3_ick,
3210         &gpt9_ick,
3211         &gpt8_ick,
3212         &gpt7_ick,
3213         &gpt6_ick,
3214         &gpt5_ick,
3215         &gpt4_ick,
3216         &gpt3_ick,
3217         &gpt2_ick,
3218         &mcbsp2_ick,
3219         &mcbsp3_ick,
3220         &mcbsp4_ick,
3221         &mcbsp2_fck,
3222         &mcbsp3_fck,
3223         &mcbsp4_fck,
3224         &emu_src_ck,
3225         &pclk_fck,
3226         &pclkx2_fck,
3227         &atclk_fck,
3228         &traceclk_src_fck,
3229         &traceclk_fck,
3230         &sr1_fck,
3231         &sr2_fck,
3232         &sr_l4_ick,
3233         &secure_32k_fck,
3234         &gpt12_fck,
3235         &wdt1_fck,
3236 };
3237
3238 #endif