arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  53 #define DPLL_LOW_POWER_STOP             0x1
  54 #define DPLL_LOW_POWER_BYPASS           0x5
  55 #define DPLL_LOCKED                     0x7
  56
  57 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  58         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  59
  60 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  61         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  62
  63 #define OMAP3430_PRM_CLKSEL                                             \
  64         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  65
  66 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  67         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  68
  69 /* PRM CLOCKS */
  70
  71 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  72 static struct clk omap_32k_fck = {
  73         .name           = "omap_32k_fck",
  74         .rate           = 32768,
  75         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .clkdm          = { .name = "prm_clkdm" },
  78         .recalc         = &propagate_rate,
  79 };
  80
  81 static struct clk secure_32k_fck = {
  82         .name           = "secure_32k_fck",
  83         .rate           = 32768,
  84         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  85                                 ALWAYS_ENABLED,
  86         .clkdm          = { .name = "prm_clkdm" },
  87         .recalc         = &propagate_rate,
  88 };
  89
  90 /* Virtual source clocks for osc_sys_ck */
  91 static struct clk virt_12m_ck = {
  92         .name           = "virt_12m_ck",
  93         .rate           = 12000000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .clkdm          = { .name = "prm_clkdm" },
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_13m_ck = {
 101         .name           = "virt_13m_ck",
 102         .rate           = 13000000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .clkdm          = { .name = "prm_clkdm" },
 106         .recalc         = &propagate_rate,
 107 };
 108
 109 static struct clk virt_16_8m_ck = {
 110         .name           = "virt_16_8m_ck",
 111         .rate           = 16800000,
 112         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 113                                 ALWAYS_ENABLED,
 114         .clkdm          = { .name = "prm_clkdm" },
 115         .recalc         = &propagate_rate,
 116 };
 117
 118 static struct clk virt_19_2m_ck = {
 119         .name           = "virt_19_2m_ck",
 120         .rate           = 19200000,
 121         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 122                                 ALWAYS_ENABLED,
 123         .clkdm          = { .name = "prm_clkdm" },
 124         .recalc         = &propagate_rate,
 125 };
 126
 127 static struct clk virt_26m_ck = {
 128         .name           = "virt_26m_ck",
 129         .rate           = 26000000,
 130         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 131                                 ALWAYS_ENABLED,
 132         .clkdm          = { .name = "prm_clkdm" },
 133         .recalc         = &propagate_rate,
 134 };
 135
 136 static struct clk virt_38_4m_ck = {
 137         .name           = "virt_38_4m_ck",
 138         .rate           = 38400000,
 139         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 140                                 ALWAYS_ENABLED,
 141         .clkdm          = { .name = "prm_clkdm" },
 142         .recalc         = &propagate_rate,
 143 };
 144
 145 static const struct clksel_rate osc_sys_12m_rates[] = {
 146         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 147         { .div = 0 }
 148 };
 149
 150 static const struct clksel_rate osc_sys_13m_rates[] = {
 151         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 152         { .div = 0 }
 153 };
 154
 155 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 156         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 161         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 162         { .div = 0 }
 163 };
 164
 165 static const struct clksel_rate osc_sys_26m_rates[] = {
 166         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 167         { .div = 0 }
 168 };
 169
 170 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 171         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel osc_sys_clksel[] = {
 176         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 177         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 178         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 179         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 180         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 181         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 182         { .parent = NULL },
 183 };
 184
 185 /* Oscillator clock */
 186 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 187 static struct clk osc_sys_ck = {
 188         .name           = "osc_sys_ck",
 189         .init           = &omap2_init_clksel_parent,
 190         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 191         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 192         .clksel         = osc_sys_clksel,
 193         /* REVISIT: deal with autoextclkmode? */
 194         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 195                                 ALWAYS_ENABLED,
 196         .clkdm          = { .name = "prm_clkdm" },
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static const struct clksel_rate div2_rates[] = {
 201         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 202         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 203         { .div = 0 }
 204 };
 205
 206 static const struct clksel sys_clksel[] = {
 207         { .parent = &osc_sys_ck, .rates = div2_rates },
 208         { .parent = NULL }
 209 };
 210
 211 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 212 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 213 static struct clk sys_ck = {
 214         .name           = "sys_ck",
 215         .parent         = &osc_sys_ck,
 216         .init           = &omap2_init_clksel_parent,
 217         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 218         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 219         .clksel         = sys_clksel,
 220         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 221         .clkdm          = { .name = "prm_clkdm" },
 222         .recalc         = &omap2_clksel_recalc,
 223 };
 224
 225 static struct clk sys_altclk = {
 226         .name           = "sys_altclk",
 227         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 228         .recalc         = &propagate_rate,
 229 };
 230
 231 /* Optional external clock input for some McBSPs */
 232 static struct clk mcbsp_clks = {
 233         .name           = "mcbsp_clks",
 234         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 235         .clkdm          = { .name = "prm_clkdm" },
 236         .recalc         = &propagate_rate,
 237 };
 238
 239 /* PRM EXTERNAL CLOCK OUTPUT */
 240
 241 static struct clk sys_clkout1 = {
 242         .name           = "sys_clkout1",
 243         .parent         = &osc_sys_ck,
 244         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 245         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 246         .flags          = CLOCK_IN_OMAP343X,
 247         .clkdm          = { .name = "prm_clkdm" },
 248         .recalc         = &followparent_recalc,
 249 };
 250
 251 /* DPLLS */
 252
 253 /* CM CLOCKS */
 254
 255 static const struct clksel_rate dpll_bypass_rates[] = {
 256         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 257         { .div = 0 }
 258 };
 259
 260 static const struct clksel_rate dpll_locked_rates[] = {
 261         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 262         { .div = 0 }
 263 };
 264
 265 static const struct clksel_rate div16_dpll_rates[] = {
 266         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 267         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 268         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 269         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 270         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 271         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 272         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 273         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 274         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 275         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 276         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 277         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 278         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 279         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 280         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 281         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 282         { .div = 0 }
 283 };
 284
 285 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 286         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 287
 288 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 289         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 290
 291 /* DPLL1 */
 292 /* MPU clock source */
 293 /* Type: DPLL */
 294 static struct dpll_data dpll1_dd = {
 295         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 296         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 297         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 298         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 299         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 300         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 301         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 302         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 303         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 304         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 305         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 306         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 307         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 308         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 309         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 310         .max_divider    = OMAP3_MAX_DPLL_DIV,
 311         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 312 };
 313
 314 static struct clk dpll1_ck = {
 315         .name           = "dpll1_ck",
 316         .parent         = &sys_ck,
 317         .dpll_data      = &dpll1_dd,
 318         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 319         .round_rate     = &omap2_dpll_round_rate,
 320         .set_rate       = &omap3_noncore_dpll_set_rate,
 321         .recalc         = &omap3_dpll_recalc,
 322 };
 323
 324 /*
 325  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 326  * DPLL isn't bypassed.
 327  */
 328 static struct clk dpll1_x2_ck = {
 329         .name           = "dpll1_x2_ck",
 330         .parent         = &dpll1_ck,
 331         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 332                                 PARENT_CONTROLS_CLOCK,
 333         .recalc         = &omap3_clkoutx2_recalc,
 334 };
 335
 336 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 337 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 338         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 339         { .parent = NULL }
 340 };
 341
 342 /*
 343  * Does not exist in the TRM - needed to separate the M2 divider from
 344  * bypass selection in mpu_ck
 345  */
 346 static struct clk dpll1_x2m2_ck = {
 347         .name           = "dpll1_x2m2_ck",
 348         .parent         = &dpll1_x2_ck,
 349         .init           = &omap2_init_clksel_parent,
 350         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 351         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 352         .clksel         = div16_dpll1_x2m2_clksel,
 353         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 354                                 PARENT_CONTROLS_CLOCK,
 355         .recalc         = &omap2_clksel_recalc,
 356 };
 357
 358 /* DPLL2 */
 359 /* IVA2 clock source */
 360 /* Type: DPLL */
 361
 362 static struct dpll_data dpll2_dd = {
 363         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 364         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 365         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 366         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 367         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 368         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 369         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 370                                 (1 << DPLL_LOW_POWER_BYPASS),
 371         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 372         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 373         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 374         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 375         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 376         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 377         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 378         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 379         .max_divider    = OMAP3_MAX_DPLL_DIV,
 380         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 381 };
 382
 383 static struct clk dpll2_ck = {
 384         .name           = "dpll2_ck",
 385         .parent         = &sys_ck,
 386         .dpll_data      = &dpll2_dd,
 387         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 388         .enable         = &omap3_noncore_dpll_enable,
 389         .disable        = &omap3_noncore_dpll_disable,
 390         .round_rate     = &omap2_dpll_round_rate,
 391         .set_rate       = &omap3_noncore_dpll_set_rate,
 392         .recalc         = &omap3_dpll_recalc,
 393 };
 394
 395 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 396         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 397         { .parent = NULL }
 398 };
 399
 400 /*
 401  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 402  * or CLKOUTX2. CLKOUT seems most plausible.
 403  */
 404 static struct clk dpll2_m2_ck = {
 405         .name           = "dpll2_m2_ck",
 406         .parent         = &dpll2_ck,
 407         .init           = &omap2_init_clksel_parent,
 408         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 409                                           OMAP3430_CM_CLKSEL2_PLL),
 410         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 411         .clksel         = div16_dpll2_m2x2_clksel,
 412         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 413                                 PARENT_CONTROLS_CLOCK,
 414         .recalc         = &omap2_clksel_recalc,
 415 };
 416
 417 /*
 418  * DPLL3
 419  * Source clock for all interfaces and for some device fclks
 420  * REVISIT: Also supports fast relock bypass - not included below
 421  */
 422 static struct dpll_data dpll3_dd = {
 423         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 424         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 425         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 426         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 427         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 428         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 429         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 430         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 431         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 432         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 433         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 434         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 435         .max_divider    = OMAP3_MAX_DPLL_DIV,
 436         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 437 };
 438
 439 static struct clk dpll3_ck = {
 440         .name           = "dpll3_ck",
 441         .parent         = &sys_ck,
 442         .dpll_data      = &dpll3_dd,
 443         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 444         .round_rate     = &omap2_dpll_round_rate,
 445         .recalc         = &omap3_dpll_recalc,
 446 };
 447
 448 /*
 449  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 450  * DPLL isn't bypassed
 451  */
 452 static struct clk dpll3_x2_ck = {
 453         .name           = "dpll3_x2_ck",
 454         .parent         = &dpll3_ck,
 455         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 456                                 PARENT_CONTROLS_CLOCK,
 457         .recalc         = &omap3_clkoutx2_recalc,
 458 };
 459
 460 static const struct clksel_rate div31_dpll3_rates[] = {
 461         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 462         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 463         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 464         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 465         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 466         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 467         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 468         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 469         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 470         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 471         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 472         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 473         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 474         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 475         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 476         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 477         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 478         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 479         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 480         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 481         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 482         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 483         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 484         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 485         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 486         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 487         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 488         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 489         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 490         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 491         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 492         { .div = 0 },
 493 };
 494
 495 static const struct clksel div31_dpll3m2_clksel[] = {
 496         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 497         { .parent = NULL }
 498 };
 499
 500 /* DPLL3 output M2 - primary control point for CORE speed */
 501 static struct clk dpll3_m2_ck = {
 502         .name           = "dpll3_m2_ck",
 503         .parent         = &dpll3_ck,
 504         .init           = &omap2_init_clksel_parent,
 505         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 506         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 507         .clksel         = div31_dpll3m2_clksel,
 508         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 509                                 PARENT_CONTROLS_CLOCK,
 510         .round_rate     = &omap2_clksel_round_rate,
 511         .set_rate       = &omap3_core_dpll_m2_set_rate,
 512         .recalc         = &omap2_clksel_recalc,
 513 };
 514
 515 static const struct clksel core_ck_clksel[] = {
 516         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 517         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 518         { .parent = NULL }
 519 };
 520
 521 static struct clk core_ck = {
 522         .name           = "core_ck",
 523         .init           = &omap2_init_clksel_parent,
 524         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 525         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 526         .clksel         = core_ck_clksel,
 527         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 528                                 PARENT_CONTROLS_CLOCK,
 529         .recalc         = &omap2_clksel_recalc,
 530 };
 531
 532 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 533         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 534         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 535         { .parent = NULL }
 536 };
 537
 538 static struct clk dpll3_m2x2_ck = {
 539         .name           = "dpll3_m2x2_ck",
 540         .init           = &omap2_init_clksel_parent,
 541         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 542         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 543         .clksel         = dpll3_m2x2_ck_clksel,
 544         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 545                                 PARENT_CONTROLS_CLOCK,
 546         .recalc         = &omap2_clksel_recalc,
 547 };
 548
 549 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 550 static const struct clksel div16_dpll3_clksel[] = {
 551         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 552         { .parent = NULL }
 553 };
 554
 555 /* This virtual clock is the source for dpll3_m3x2_ck */
 556 static struct clk dpll3_m3_ck = {
 557         .name           = "dpll3_m3_ck",
 558         .parent         = &dpll3_ck,
 559         .init           = &omap2_init_clksel_parent,
 560         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 561         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 562         .clksel         = div16_dpll3_clksel,
 563         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 564                                 PARENT_CONTROLS_CLOCK,
 565         .recalc         = &omap2_clksel_recalc,
 566 };
 567
 568 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 569 static struct clk dpll3_m3x2_ck = {
 570         .name           = "dpll3_m3x2_ck",
 571         .parent         = &dpll3_m3_ck,
 572         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 573         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 574         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 575         .recalc         = &omap3_clkoutx2_recalc,
 576 };
 577
 578 static const struct clksel emu_core_alwon_ck_clksel[] = {
 579         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 580         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 581         { .parent = NULL }
 582 };
 583
 584 static struct clk emu_core_alwon_ck = {
 585         .name           = "emu_core_alwon_ck",
 586         .parent         = &dpll3_m3x2_ck,
 587         .init           = &omap2_init_clksel_parent,
 588         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 589         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 590         .clksel         = emu_core_alwon_ck_clksel,
 591         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 592                                 PARENT_CONTROLS_CLOCK,
 593         .recalc         = &omap2_clksel_recalc,
 594 };
 595
 596 /* DPLL4 */
 597 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 598 /* Type: DPLL */
 599 static struct dpll_data dpll4_dd = {
 600         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 601         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 602         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 603         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 604         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 605         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 606         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 607         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 608         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 609         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 610         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 611         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 612         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 613         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 614         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 615         .max_divider    = OMAP3_MAX_DPLL_DIV,
 616         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 617 };
 618
 619 static struct clk dpll4_ck = {
 620         .name           = "dpll4_ck",
 621         .parent         = &sys_ck,
 622         .dpll_data      = &dpll4_dd,
 623         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 624         .enable         = &omap3_noncore_dpll_enable,
 625         .disable        = &omap3_noncore_dpll_disable,
 626         .round_rate     = &omap2_dpll_round_rate,
 627         .set_rate       = &omap3_noncore_dpll_set_rate,
 628         .recalc         = &omap3_dpll_recalc,
 629 };
 630
 631 /*
 632  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 633  * DPLL isn't bypassed --
 634  * XXX does this serve any downstream clocks?
 635  */
 636 static struct clk dpll4_x2_ck = {
 637         .name           = "dpll4_x2_ck",
 638         .parent         = &dpll4_ck,
 639         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 640                                 PARENT_CONTROLS_CLOCK,
 641         .recalc         = &omap3_clkoutx2_recalc,
 642 };
 643
 644 static const struct clksel div16_dpll4_clksel[] = {
 645         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 646         { .parent = NULL }
 647 };
 648
 649 /* This virtual clock is the source for dpll4_m2x2_ck */
 650 static struct clk dpll4_m2_ck = {
 651         .name           = "dpll4_m2_ck",
 652         .parent         = &dpll4_ck,
 653         .init           = &omap2_init_clksel_parent,
 654         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 655         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 656         .clksel         = div16_dpll4_clksel,
 657         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 658                                 PARENT_CONTROLS_CLOCK,
 659         .recalc         = &omap2_clksel_recalc,
 660 };
 661
 662 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 663 static struct clk dpll4_m2x2_ck = {
 664         .name           = "dpll4_m2x2_ck",
 665         .parent         = &dpll4_m2_ck,
 666         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 667         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 668         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 669         .recalc         = &omap3_clkoutx2_recalc,
 670 };
 671
 672 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 673         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 674         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 675         { .parent = NULL }
 676 };
 677
 678 /*
 679  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 680  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 681  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 682  * CM_96K_(F)CLK.
 683  */
 684 static struct clk omap_96m_alwon_fck = {
 685         .name           = "omap_96m_alwon_fck",
 686         .parent         = &dpll4_m2x2_ck,
 687         .init           = &omap2_init_clksel_parent,
 688         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 689         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 690         .clksel         = omap_96m_alwon_fck_clksel,
 691         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 692                                 PARENT_CONTROLS_CLOCK,
 693         .clkdm          = { .name = "prm_clkdm" },
 694         .recalc         = &omap2_clksel_recalc,
 695 };
 696
 697 static struct clk cm_96m_fck = {
 698         .name           = "cm_96m_fck",
 699         .parent         = &omap_96m_alwon_fck,
 700         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 701                                 PARENT_CONTROLS_CLOCK,
 702         .recalc         = &followparent_recalc,
 703 };
 704
 705 static const struct clksel_rate omap_96m_dpll_rates[] = {
 706         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 707         { .div = 0 }
 708 };
 709
 710 static const struct clksel_rate omap_96m_sys_rates[] = {
 711         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 712         { .div = 0 }
 713 };
 714
 715 static const struct clksel omap_96m_fck_clksel[] = {
 716         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 717         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 718         { .parent = NULL }
 719 };
 720
 721 static struct clk omap_96m_fck = {
 722         .name           = "omap_96m_fck",
 723         .parent         = &sys_ck,
 724         .init           = &omap2_init_clksel_parent,
 725         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 726         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 727         .clksel         = omap_96m_fck_clksel,
 728         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 729                                 PARENT_CONTROLS_CLOCK,
 730         .recalc         = &omap2_clksel_recalc,
 731 };
 732
 733 /* This virtual clock is the source for dpll4_m3x2_ck */
 734 static struct clk dpll4_m3_ck = {
 735         .name           = "dpll4_m3_ck",
 736         .parent         = &dpll4_ck,
 737         .init           = &omap2_init_clksel_parent,
 738         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 739         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 740         .clksel         = div16_dpll4_clksel,
 741         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 742                                 PARENT_CONTROLS_CLOCK,
 743         .recalc         = &omap2_clksel_recalc,
 744 };
 745
 746 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 747 static struct clk dpll4_m3x2_ck = {
 748         .name           = "dpll4_m3x2_ck",
 749         .parent         = &dpll4_m3_ck,
 750         .init           = &omap2_init_clksel_parent,
 751         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 752         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 753         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 754         .recalc         = &omap3_clkoutx2_recalc,
 755 };
 756
 757 static const struct clksel virt_omap_54m_fck_clksel[] = {
 758         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 759         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 760         { .parent = NULL }
 761 };
 762
 763 static struct clk virt_omap_54m_fck = {
 764         .name           = "virt_omap_54m_fck",
 765         .parent         = &dpll4_m3x2_ck,
 766         .init           = &omap2_init_clksel_parent,
 767         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 768         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 769         .clksel         = virt_omap_54m_fck_clksel,
 770         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 771                                 PARENT_CONTROLS_CLOCK,
 772         .recalc         = &omap2_clksel_recalc,
 773 };
 774
 775 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 776         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 777         { .div = 0 }
 778 };
 779
 780 static const struct clksel_rate omap_54m_alt_rates[] = {
 781         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 782         { .div = 0 }
 783 };
 784
 785 static const struct clksel omap_54m_clksel[] = {
 786         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 787         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 788         { .parent = NULL }
 789 };
 790
 791 static struct clk omap_54m_fck = {
 792         .name           = "omap_54m_fck",
 793         .init           = &omap2_init_clksel_parent,
 794         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 795         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 796         .clksel         = omap_54m_clksel,
 797         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 798                                 PARENT_CONTROLS_CLOCK,
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 803         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 804         { .div = 0 }
 805 };
 806
 807 static const struct clksel_rate omap_48m_alt_rates[] = {
 808         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 809         { .div = 0 }
 810 };
 811
 812 static const struct clksel omap_48m_clksel[] = {
 813         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 814         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 815         { .parent = NULL }
 816 };
 817
 818 static struct clk omap_48m_fck = {
 819         .name           = "omap_48m_fck",
 820         .init           = &omap2_init_clksel_parent,
 821         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 822         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 823         .clksel         = omap_48m_clksel,
 824         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 825                                 PARENT_CONTROLS_CLOCK,
 826         .recalc         = &omap2_clksel_recalc,
 827 };
 828
 829 static struct clk omap_12m_fck = {
 830         .name           = "omap_12m_fck",
 831         .parent         = &omap_48m_fck,
 832         .fixed_div      = 4,
 833         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 834                                 PARENT_CONTROLS_CLOCK,
 835         .recalc         = &omap2_fixed_divisor_recalc,
 836 };
 837
 838 /* This virstual clock is the source for dpll4_m4x2_ck */
 839 static struct clk dpll4_m4_ck = {
 840         .name           = "dpll4_m4_ck",
 841         .parent         = &dpll4_ck,
 842         .init           = &omap2_init_clksel_parent,
 843         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 844         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 845         .clksel         = div16_dpll4_clksel,
 846         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 847                                 PARENT_CONTROLS_CLOCK,
 848         .recalc         = &omap2_clksel_recalc,
 849 };
 850
 851 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 852 static struct clk dpll4_m4x2_ck = {
 853         .name           = "dpll4_m4x2_ck",
 854         .parent         = &dpll4_m4_ck,
 855         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 856         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 857         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 858         .recalc         = &omap3_clkoutx2_recalc,
 859 };
 860
 861 /* This virtual clock is the source for dpll4_m5x2_ck */
 862 static struct clk dpll4_m5_ck = {
 863         .name           = "dpll4_m5_ck",
 864         .parent         = &dpll4_ck,
 865         .init           = &omap2_init_clksel_parent,
 866         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 867         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 868         .clksel         = div16_dpll4_clksel,
 869         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 870                                 PARENT_CONTROLS_CLOCK,
 871         .recalc         = &omap2_clksel_recalc,
 872 };
 873
 874 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 875 static struct clk dpll4_m5x2_ck = {
 876         .name           = "dpll4_m5x2_ck",
 877         .parent         = &dpll4_m5_ck,
 878         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 879         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 880         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 881         .recalc         = &omap3_clkoutx2_recalc,
 882 };
 883
 884 /* This virtual clock is the source for dpll4_m6x2_ck */
 885 static struct clk dpll4_m6_ck = {
 886         .name           = "dpll4_m6_ck",
 887         .parent         = &dpll4_ck,
 888         .init           = &omap2_init_clksel_parent,
 889         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 890         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 891         .clksel         = div16_dpll4_clksel,
 892         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 893                                 PARENT_CONTROLS_CLOCK,
 894         .recalc         = &omap2_clksel_recalc,
 895 };
 896
 897 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 898 static struct clk dpll4_m6x2_ck = {
 899         .name           = "dpll4_m6x2_ck",
 900         .parent         = &dpll4_m6_ck,
 901         .init           = &omap2_init_clksel_parent,
 902         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 903         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 904         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 905         .recalc         = &omap3_clkoutx2_recalc,
 906 };
 907
 908 static struct clk emu_per_alwon_ck = {
 909         .name           = "emu_per_alwon_ck",
 910         .parent         = &dpll4_m6x2_ck,
 911         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 912                                 PARENT_CONTROLS_CLOCK,
 913         .recalc         = &followparent_recalc,
 914 };
 915
 916 /* DPLL5 */
 917 /* Supplies 120MHz clock, USIM source clock */
 918 /* Type: DPLL */
 919 /* 3430ES2 only */
 920 static struct dpll_data dpll5_dd = {
 921         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 922         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 923         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 924         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 925         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 926         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 927         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 928         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 929         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 930         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 931         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 932         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 933         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 934         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 935         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 936         .max_divider    = OMAP3_MAX_DPLL_DIV,
 937         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 938 };
 939
 940 static struct clk dpll5_ck = {
 941         .name           = "dpll5_ck",
 942         .parent         = &sys_ck,
 943         .dpll_data      = &dpll5_dd,
 944         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 945         .enable         = &omap3_noncore_dpll_enable,
 946         .disable        = &omap3_noncore_dpll_disable,
 947         .round_rate     = &omap2_dpll_round_rate,
 948         .set_rate       = &omap3_noncore_dpll_set_rate,
 949         .recalc         = &omap3_dpll_recalc,
 950 };
 951
 952 static const struct clksel div16_dpll5_clksel[] = {
 953         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 954         { .parent = NULL }
 955 };
 956
 957 static struct clk dpll5_m2_ck = {
 958         .name           = "dpll5_m2_ck",
 959         .parent         = &dpll5_ck,
 960         .init           = &omap2_init_clksel_parent,
 961         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 962         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 963         .clksel         = div16_dpll5_clksel,
 964         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 965                                 PARENT_CONTROLS_CLOCK,
 966         .recalc         = &omap2_clksel_recalc,
 967 };
 968
 969 static const struct clksel omap_120m_fck_clksel[] = {
 970         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 971         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 972         { .parent = NULL }
 973 };
 974
 975 static struct clk omap_120m_fck = {
 976         .name           = "omap_120m_fck",
 977         .parent         = &dpll5_m2_ck,
 978         .init           = &omap2_init_clksel_parent,
 979         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 980         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 981         .clksel         = omap_120m_fck_clksel,
 982         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 983                                 PARENT_CONTROLS_CLOCK,
 984         .recalc         = &omap2_clksel_recalc,
 985 };
 986
 987 /* CM EXTERNAL CLOCK OUTPUTS */
 988
 989 static const struct clksel_rate clkout2_src_core_rates[] = {
 990         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 991         { .div = 0 }
 992 };
 993
 994 static const struct clksel_rate clkout2_src_sys_rates[] = {
 995         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 996         { .div = 0 }
 997 };
 998
 999 static const struct clksel_rate clkout2_src_96m_rates[] = {
1000         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1001         { .div = 0 }
1002 };
1003
1004 static const struct clksel_rate clkout2_src_54m_rates[] = {
1005         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1006         { .div = 0 }
1007 };
1008
1009 static const struct clksel clkout2_src_clksel[] = {
1010         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1011         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1012         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1013         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1014         { .parent = NULL }
1015 };
1016
1017 static struct clk clkout2_src_ck = {
1018         .name           = "clkout2_src_ck",
1019         .init           = &omap2_init_clksel_parent,
1020         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1021         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1022         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1023         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1024         .clksel         = clkout2_src_clksel,
1025         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1026         .clkdm          = { .name = "cm_clkdm" },
1027         .recalc         = &omap2_clksel_recalc,
1028 };
1029
1030 static const struct clksel_rate sys_clkout2_rates[] = {
1031         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1032         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1033         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1034         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1035         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1036         { .div = 0 },
1037 };
1038
1039 static const struct clksel sys_clkout2_clksel[] = {
1040         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1041         { .parent = NULL },
1042 };
1043
1044 static struct clk sys_clkout2 = {
1045         .name           = "sys_clkout2",
1046         .init           = &omap2_init_clksel_parent,
1047         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1048         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1049         .clksel         = sys_clkout2_clksel,
1050         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1051         .recalc         = &omap2_clksel_recalc,
1052 };
1053
1054 /* CM OUTPUT CLOCKS */
1055
1056 static struct clk corex2_fck = {
1057         .name           = "corex2_fck",
1058         .parent         = &dpll3_m2x2_ck,
1059         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1060                                 PARENT_CONTROLS_CLOCK,
1061         .recalc         = &followparent_recalc,
1062 };
1063
1064 /* DPLL power domain clock controls */
1065
1066 static const struct clksel_rate div4_rates[] = {
1067         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1068         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1069         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1070         { .div = 0 }
1071 };
1072
1073 static const struct clksel div4_core_clksel[] = {
1074         { .parent = &core_ck, .rates = div4_rates },
1075         { .parent = NULL }
1076 };
1077
1078 /*
1079  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1080  * may be inconsistent here?
1081  */
1082 static struct clk dpll1_fck = {
1083         .name           = "dpll1_fck",
1084         .parent         = &core_ck,
1085         .init           = &omap2_init_clksel_parent,
1086         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1087         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1088         .clksel         = div4_core_clksel,
1089         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1090                                 PARENT_CONTROLS_CLOCK,
1091         .recalc         = &omap2_clksel_recalc,
1092 };
1093
1094 /*
1095  * MPU clksel:
1096  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1097  * derives from the high-frequency bypass clock originating from DPLL3,
1098  * called 'dpll1_fck'
1099  */
1100 static const struct clksel mpu_clksel[] = {
1101         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1102         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1103         { .parent = NULL }
1104 };
1105
1106 static struct clk mpu_ck = {
1107         .name           = "mpu_ck",
1108         .parent         = &dpll1_x2m2_ck,
1109         .init           = &omap2_init_clksel_parent,
1110         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1111         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1112         .clksel         = mpu_clksel,
1113         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1114                                 PARENT_CONTROLS_CLOCK,
1115         .clkdm          = { .name = "mpu_clkdm" },
1116         .recalc         = &omap2_clksel_recalc,
1117 };
1118
1119 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1120 static const struct clksel_rate arm_fck_rates[] = {
1121         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1122         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1123         { .div = 0 },
1124 };
1125
1126 static const struct clksel arm_fck_clksel[] = {
1127         { .parent = &mpu_ck, .rates = arm_fck_rates },
1128         { .parent = NULL }
1129 };
1130
1131 static struct clk arm_fck = {
1132         .name           = "arm_fck",
1133         .parent         = &mpu_ck,
1134         .init           = &omap2_init_clksel_parent,
1135         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1136         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1137         .clksel         = arm_fck_clksel,
1138         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1139                                 PARENT_CONTROLS_CLOCK,
1140         .recalc         = &omap2_clksel_recalc,
1141 };
1142
1143 /* XXX What about neon_clkdm ? */
1144
1145 /*
1146  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1147  * although it is referenced - so this is a guess
1148  */
1149 static struct clk emu_mpu_alwon_ck = {
1150         .name           = "emu_mpu_alwon_ck",
1151         .parent         = &mpu_ck,
1152         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1153                                 PARENT_CONTROLS_CLOCK,
1154         .recalc         = &followparent_recalc,
1155 };
1156
1157 static struct clk dpll2_fck = {
1158         .name           = "dpll2_fck",
1159         .parent         = &core_ck,
1160         .init           = &omap2_init_clksel_parent,
1161         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1162         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1163         .clksel         = div4_core_clksel,
1164         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1165                                 PARENT_CONTROLS_CLOCK,
1166         .recalc         = &omap2_clksel_recalc,
1167 };
1168
1169 /*
1170  * IVA2 clksel:
1171  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1172  * derives from the high-frequency bypass clock originating from DPLL3,
1173  * called 'dpll2_fck'
1174  */
1175
1176 static const struct clksel iva2_clksel[] = {
1177         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1178         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1179         { .parent = NULL }
1180 };
1181
1182 static struct clk iva2_ck = {
1183         .name           = "iva2_ck",
1184         .parent         = &dpll2_m2_ck,
1185         .init           = &omap2_init_clksel_parent,
1186         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1187         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1188         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1189                                           OMAP3430_CM_IDLEST_PLL),
1190         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1191         .clksel         = iva2_clksel,
1192         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1193         .clkdm          = { .name = "iva2_clkdm" },
1194         .recalc         = &omap2_clksel_recalc,
1195 };
1196
1197 /* Common interface clocks */
1198
1199 static const struct clksel div2_core_clksel[] = {
1200         { .parent = &core_ck, .rates = div2_rates },
1201         { .parent = NULL }
1202 };
1203
1204 static struct clk l3_ick = {
1205         .name           = "l3_ick",
1206         .parent         = &core_ck,
1207         .init           = &omap2_init_clksel_parent,
1208         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1209         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1210         .clksel         = div2_core_clksel,
1211         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1212                                 PARENT_CONTROLS_CLOCK,
1213         .clkdm          = { .name = "core_l3_clkdm" },
1214         .recalc         = &omap2_clksel_recalc,
1215 };
1216
1217 static const struct clksel div2_l3_clksel[] = {
1218         { .parent = &l3_ick, .rates = div2_rates },
1219         { .parent = NULL }
1220 };
1221
1222 static struct clk l4_ick = {
1223         .name           = "l4_ick",
1224         .parent         = &l3_ick,
1225         .init           = &omap2_init_clksel_parent,
1226         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1227         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1228         .clksel         = div2_l3_clksel,
1229         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1230                                 PARENT_CONTROLS_CLOCK,
1231         .clkdm          = { .name = "core_l4_clkdm" },
1232         .recalc         = &omap2_clksel_recalc,
1233
1234 };
1235
1236 static const struct clksel div2_l4_clksel[] = {
1237         { .parent = &l4_ick, .rates = div2_rates },
1238         { .parent = NULL }
1239 };
1240
1241 static struct clk rm_ick = {
1242         .name           = "rm_ick",
1243         .parent         = &l4_ick,
1244         .init           = &omap2_init_clksel_parent,
1245         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1246         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1247         .clksel         = div2_l4_clksel,
1248         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1249         .recalc         = &omap2_clksel_recalc,
1250 };
1251
1252 /* GFX power domain */
1253
1254 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1255
1256 static const struct clksel gfx_l3_clksel[] = {
1257         { .parent = &l3_ick, .rates = gfx_l3_rates },
1258         { .parent = NULL }
1259 };
1260
1261 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1262 static struct clk gfx_l3_ck = {
1263         .name           = "gfx_l3_ck",
1264         .parent         = &l3_ick,
1265         .init           = &omap2_init_clksel_parent,
1266         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1267         .enable_bit     = OMAP_EN_GFX_SHIFT,
1268         .flags          = CLOCK_IN_OMAP3430ES1,
1269         .recalc         = &followparent_recalc,
1270 };
1271
1272 static struct clk gfx_l3_fck = {
1273         .name           = "gfx_l3_fck",
1274         .parent         = &gfx_l3_ck,
1275         .init           = &omap2_init_clksel_parent,
1276         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1277         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1278         .clksel         = gfx_l3_clksel,
1279         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1280                                 PARENT_CONTROLS_CLOCK,
1281         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1282         .recalc         = &omap2_clksel_recalc,
1283 };
1284
1285 static struct clk gfx_l3_ick = {
1286         .name           = "gfx_l3_ick",
1287         .parent         = &gfx_l3_ck,
1288         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1289         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1290         .recalc         = &followparent_recalc,
1291 };
1292
1293 static struct clk gfx_cg1_ck = {
1294         .name           = "gfx_cg1_ck",
1295         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1296         .init           = &omap2_init_clk_clkdm,
1297         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1298         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1299         .flags          = CLOCK_IN_OMAP3430ES1,
1300         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 static struct clk gfx_cg2_ck = {
1305         .name           = "gfx_cg2_ck",
1306         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1307         .init           = &omap2_init_clk_clkdm,
1308         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1309         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1310         .flags          = CLOCK_IN_OMAP3430ES1,
1311         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315 /* SGX power domain - 3430ES2 only */
1316
1317 static const struct clksel_rate sgx_core_rates[] = {
1318         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1319         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1320         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1321         { .div = 0 },
1322 };
1323
1324 static const struct clksel_rate sgx_96m_rates[] = {
1325         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1326         { .div = 0 },
1327 };
1328
1329 static const struct clksel sgx_clksel[] = {
1330         { .parent = &core_ck,    .rates = sgx_core_rates },
1331         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1332         { .parent = NULL },
1333 };
1334
1335 static struct clk sgx_fck = {
1336         .name           = "sgx_fck",
1337         .init           = &omap2_init_clksel_parent,
1338         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1339         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1340         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1341         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1342         .clksel         = sgx_clksel,
1343         .flags          = CLOCK_IN_OMAP3430ES2,
1344         .clkdm          = { .name = "sgx_clkdm" },
1345         .recalc         = &omap2_clksel_recalc,
1346 };
1347
1348 static struct clk sgx_ick = {
1349         .name           = "sgx_ick",
1350         .parent         = &l3_ick,
1351         .init           = &omap2_init_clk_clkdm,
1352         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1353         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1354         .flags          = CLOCK_IN_OMAP3430ES2,
1355         .clkdm          = { .name = "sgx_clkdm" },
1356         .recalc         = &followparent_recalc,
1357 };
1358
1359 /* CORE power domain */
1360
1361 static struct clk d2d_26m_fck = {
1362         .name           = "d2d_26m_fck",
1363         .parent         = &sys_ck,
1364         .init           = &omap2_init_clk_clkdm,
1365         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1366         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1367         .flags          = CLOCK_IN_OMAP3430ES1,
1368         .clkdm          = { .name = "d2d_clkdm" },
1369         .recalc         = &followparent_recalc,
1370 };
1371
1372 static const struct clksel omap343x_gpt_clksel[] = {
1373         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1374         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1375         { .parent = NULL}
1376 };
1377
1378 static struct clk gpt10_fck = {
1379         .name           = "gpt10_fck",
1380         .parent         = &sys_ck,
1381         .init           = &omap2_init_clksel_parent,
1382         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1384         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1385         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1386         .clksel         = omap343x_gpt_clksel,
1387         .flags          = CLOCK_IN_OMAP343X,
1388         .clkdm          = { .name = "core_l4_clkdm" },
1389         .recalc         = &omap2_clksel_recalc,
1390 };
1391
1392 static struct clk gpt11_fck = {
1393         .name           = "gpt11_fck",
1394         .parent         = &sys_ck,
1395         .init           = &omap2_init_clksel_parent,
1396         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1397         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1398         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1399         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1400         .clksel         = omap343x_gpt_clksel,
1401         .flags          = CLOCK_IN_OMAP343X,
1402         .clkdm          = { .name = "core_l4_clkdm" },
1403         .recalc         = &omap2_clksel_recalc,
1404 };
1405
1406 static struct clk cpefuse_fck = {
1407         .name           = "cpefuse_fck",
1408         .parent         = &sys_ck,
1409         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1410         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1411         .flags          = CLOCK_IN_OMAP3430ES2,
1412         .recalc         = &followparent_recalc,
1413 };
1414
1415 static struct clk ts_fck = {
1416         .name           = "ts_fck",
1417         .parent         = &omap_32k_fck,
1418         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1419         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1420         .flags          = CLOCK_IN_OMAP3430ES2,
1421         .recalc         = &followparent_recalc,
1422 };
1423
1424 static struct clk usbtll_fck = {
1425         .name           = "usbtll_fck",
1426         .parent         = &omap_120m_fck,
1427         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1428         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1429         .flags          = CLOCK_IN_OMAP3430ES2,
1430         .recalc         = &followparent_recalc,
1431 };
1432
1433 /* CORE 96M FCLK-derived clocks */
1434
1435 static struct clk core_96m_fck = {
1436         .name           = "core_96m_fck",
1437         .parent         = &omap_96m_fck,
1438         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1439                                 PARENT_CONTROLS_CLOCK,
1440         .clkdm          = { .name = "core_l4_clkdm" },
1441         .recalc         = &followparent_recalc,
1442 };
1443
1444 static struct clk mmchs3_fck = {
1445         .name           = "mmchs_fck",
1446         .id             = 3,
1447         .parent         = &core_96m_fck,
1448         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1449         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1450         .flags          = CLOCK_IN_OMAP3430ES2,
1451         .clkdm          = { .name = "core_l4_clkdm" },
1452         .recalc         = &followparent_recalc,
1453 };
1454
1455 static struct clk mmchs2_fck = {
1456         .name           = "mmchs_fck",
1457         .id             = 2,
1458         .parent         = &core_96m_fck,
1459         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1460         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1461         .flags          = CLOCK_IN_OMAP343X,
1462         .clkdm          = { .name = "core_l4_clkdm" },
1463         .recalc         = &followparent_recalc,
1464 };
1465
1466 static struct clk mspro_fck = {
1467         .name           = "mspro_fck",
1468         .parent         = &core_96m_fck,
1469         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1470         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1471         .flags          = CLOCK_IN_OMAP343X,
1472         .clkdm          = { .name = "core_l4_clkdm" },
1473         .recalc         = &followparent_recalc,
1474 };
1475
1476 static struct clk mmchs1_fck = {
1477         .name           = "mmchs_fck",
1478         .id             = 1,
1479         .parent         = &core_96m_fck,
1480         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1481         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1482         .flags          = CLOCK_IN_OMAP343X,
1483         .clkdm          = { .name = "core_l4_clkdm" },
1484         .recalc         = &followparent_recalc,
1485 };
1486
1487 static struct clk i2c3_fck = {
1488         .name           = "i2c_fck",
1489         .id             = 3,
1490         .parent         = &core_96m_fck,
1491         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1492         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1493         .flags          = CLOCK_IN_OMAP343X,
1494         .clkdm          = { .name = "core_l4_clkdm" },
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk i2c2_fck = {
1499         .name           = "i2c_fck",
1500         .id             = 2,
1501         .parent         = &core_96m_fck,
1502         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1503         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1504         .flags          = CLOCK_IN_OMAP343X,
1505         .clkdm          = { .name = "core_l4_clkdm" },
1506         .recalc         = &followparent_recalc,
1507 };
1508
1509 static struct clk i2c1_fck = {
1510         .name           = "i2c_fck",
1511         .id             = 1,
1512         .parent         = &core_96m_fck,
1513         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1515         .flags          = CLOCK_IN_OMAP343X,
1516         .clkdm          = { .name = "core_l4_clkdm" },
1517         .recalc         = &followparent_recalc,
1518 };
1519
1520 /*
1521  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1522  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1523  */
1524 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1525         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1526         { .div = 0 }
1527 };
1528
1529 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1530         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1531         { .div = 0 }
1532 };
1533
1534 static const struct clksel mcbsp_15_clksel[] = {
1535         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1536         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1537         { .parent = NULL }
1538 };
1539
1540 static struct clk mcbsp5_fck = {
1541         .name           = "mcbsp_fck",
1542         .id             = 5,
1543         .init           = &omap2_init_clksel_parent,
1544         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1545         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1546         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1547         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1548         .clksel         = mcbsp_15_clksel,
1549         .flags          = CLOCK_IN_OMAP343X,
1550         .clkdm          = { .name = "core_l4_clkdm" },
1551         .recalc         = &omap2_clksel_recalc,
1552 };
1553
1554 static struct clk mcbsp1_fck = {
1555         .name           = "mcbsp_fck",
1556         .id             = 1,
1557         .init           = &omap2_init_clksel_parent,
1558         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1560         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1561         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1562         .clksel         = mcbsp_15_clksel,
1563         .flags          = CLOCK_IN_OMAP343X,
1564         .clkdm          = { .name = "core_l4_clkdm" },
1565         .recalc         = &omap2_clksel_recalc,
1566 };
1567
1568 /* CORE_48M_FCK-derived clocks */
1569
1570 static struct clk core_48m_fck = {
1571         .name           = "core_48m_fck",
1572         .parent         = &omap_48m_fck,
1573         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1574                                 PARENT_CONTROLS_CLOCK,
1575         .clkdm          = { .name = "core_l4_clkdm" },
1576         .recalc         = &followparent_recalc,
1577 };
1578
1579 static struct clk mcspi4_fck = {
1580         .name           = "mcspi_fck",
1581         .id             = 4,
1582         .parent         = &core_48m_fck,
1583         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1584         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1585         .flags          = CLOCK_IN_OMAP343X,
1586         .recalc         = &followparent_recalc,
1587 };
1588
1589 static struct clk mcspi3_fck = {
1590         .name           = "mcspi_fck",
1591         .id             = 3,
1592         .parent         = &core_48m_fck,
1593         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1595         .flags          = CLOCK_IN_OMAP343X,
1596         .recalc         = &followparent_recalc,
1597 };
1598
1599 static struct clk mcspi2_fck = {
1600         .name           = "mcspi_fck",
1601         .id             = 2,
1602         .parent         = &core_48m_fck,
1603         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1604         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1605         .flags          = CLOCK_IN_OMAP343X,
1606         .recalc         = &followparent_recalc,
1607 };
1608
1609 static struct clk mcspi1_fck = {
1610         .name           = "mcspi_fck",
1611         .id             = 1,
1612         .parent         = &core_48m_fck,
1613         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1614         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1615         .flags          = CLOCK_IN_OMAP343X,
1616         .recalc         = &followparent_recalc,
1617 };
1618
1619 static struct clk uart2_fck = {
1620         .name           = "uart2_fck",
1621         .parent         = &core_48m_fck,
1622         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1623         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1624         .flags          = CLOCK_IN_OMAP343X,
1625         .recalc         = &followparent_recalc,
1626 };
1627
1628 static struct clk uart1_fck = {
1629         .name           = "uart1_fck",
1630         .parent         = &core_48m_fck,
1631         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1632         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1633         .flags          = CLOCK_IN_OMAP343X,
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 static struct clk fshostusb_fck = {
1638         .name           = "fshostusb_fck",
1639         .parent         = &core_48m_fck,
1640         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1641         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1642         .flags          = CLOCK_IN_OMAP3430ES1,
1643         .recalc         = &followparent_recalc,
1644 };
1645
1646 /* CORE_12M_FCK based clocks */
1647
1648 static struct clk core_12m_fck = {
1649         .name           = "core_12m_fck",
1650         .parent         = &omap_12m_fck,
1651         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1652                                 PARENT_CONTROLS_CLOCK,
1653         .clkdm          = { .name = "core_l4_clkdm" },
1654         .recalc         = &followparent_recalc,
1655 };
1656
1657 static struct clk hdq_fck = {
1658         .name           = "hdq_fck",
1659         .parent         = &core_12m_fck,
1660         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1661         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1662         .flags          = CLOCK_IN_OMAP343X,
1663         .recalc         = &followparent_recalc,
1664 };
1665
1666 /* DPLL3-derived clock */
1667
1668 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1669         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1670         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1671         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1672         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1673         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1674         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1675         { .div = 0 }
1676 };
1677
1678 static const struct clksel ssi_ssr_clksel[] = {
1679         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1680         { .parent = NULL }
1681 };
1682
1683 static struct clk ssi_ssr_fck = {
1684         .name           = "ssi_ssr_fck",
1685         .init           = &omap2_init_clksel_parent,
1686         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1687         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1688         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1689         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1690         .clksel         = ssi_ssr_clksel,
1691         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1692         .clkdm          = { .name = "core_l4_clkdm" },
1693         .recalc         = &omap2_clksel_recalc,
1694 };
1695
1696 static struct clk ssi_sst_fck = {
1697         .name           = "ssi_sst_fck",
1698         .parent         = &ssi_ssr_fck,
1699         .fixed_div      = 2,
1700         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1701         .recalc         = &omap2_fixed_divisor_recalc,
1702 };
1703
1704
1705
1706 /* CORE_L3_ICK based clocks */
1707
1708 /*
1709  * XXX must add clk_enable/clk_disable for these if standard code won't
1710  * handle it
1711  */
1712 static struct clk core_l3_ick = {
1713         .name           = "core_l3_ick",
1714         .parent         = &l3_ick,
1715         .init           = &omap2_init_clk_clkdm,
1716         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1717                                 PARENT_CONTROLS_CLOCK,
1718         .clkdm          = { .name = "core_l3_clkdm" },
1719         .recalc         = &followparent_recalc,
1720 };
1721
1722 static struct clk hsotgusb_ick = {
1723         .name           = "hsotgusb_ick",
1724         .parent         = &core_l3_ick,
1725         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1726         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1727         .flags          = CLOCK_IN_OMAP343X,
1728         .clkdm          = { .name = "core_l3_clkdm" },
1729         .recalc         = &followparent_recalc,
1730 };
1731
1732 static struct clk sdrc_ick = {
1733         .name           = "sdrc_ick",
1734         .parent         = &core_l3_ick,
1735         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1736         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1737         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1738         .clkdm          = { .name = "core_l3_clkdm" },
1739         .recalc         = &followparent_recalc,
1740 };
1741
1742 static struct clk gpmc_fck = {
1743         .name           = "gpmc_fck",
1744         .parent         = &core_l3_ick,
1745         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1746                                 ENABLE_ON_INIT,
1747         .clkdm          = { .name = "core_l3_clkdm" },
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 /* SECURITY_L3_ICK based clocks */
1752
1753 static struct clk security_l3_ick = {
1754         .name           = "security_l3_ick",
1755         .parent         = &l3_ick,
1756         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1757                                 PARENT_CONTROLS_CLOCK,
1758         .recalc         = &followparent_recalc,
1759 };
1760
1761 static struct clk pka_ick = {
1762         .name           = "pka_ick",
1763         .parent         = &security_l3_ick,
1764         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1765         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1766         .flags          = CLOCK_IN_OMAP343X,
1767         .recalc         = &followparent_recalc,
1768 };
1769
1770 /* CORE_L4_ICK based clocks */
1771
1772 static struct clk core_l4_ick = {
1773         .name           = "core_l4_ick",
1774         .parent         = &l4_ick,
1775         .init           = &omap2_init_clk_clkdm,
1776         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1777                                 PARENT_CONTROLS_CLOCK,
1778         .clkdm          = { .name = "core_l4_clkdm" },
1779         .recalc         = &followparent_recalc,
1780 };
1781
1782 static struct clk usbtll_ick = {
1783         .name           = "usbtll_ick",
1784         .parent         = &core_l4_ick,
1785         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1786         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1787         .flags          = CLOCK_IN_OMAP3430ES2,
1788         .clkdm          = { .name = "core_l4_clkdm" },
1789         .recalc         = &followparent_recalc,
1790 };
1791
1792 static struct clk mmchs3_ick = {
1793         .name           = "mmchs_ick",
1794         .id             = 3,
1795         .parent         = &core_l4_ick,
1796         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1797         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1798         .flags          = CLOCK_IN_OMAP3430ES2,
1799         .clkdm          = { .name = "core_l4_clkdm" },
1800         .recalc         = &followparent_recalc,
1801 };
1802
1803 /* Intersystem Communication Registers - chassis mode only */
1804 static struct clk icr_ick = {
1805         .name           = "icr_ick",
1806         .parent         = &core_l4_ick,
1807         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1809         .flags          = CLOCK_IN_OMAP343X,
1810         .clkdm          = { .name = "core_l4_clkdm" },
1811         .recalc         = &followparent_recalc,
1812 };
1813
1814 static struct clk aes2_ick = {
1815         .name           = "aes2_ick",
1816         .parent         = &core_l4_ick,
1817         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1818         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1819         .flags          = CLOCK_IN_OMAP343X,
1820         .clkdm          = { .name = "core_l4_clkdm" },
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk sha12_ick = {
1825         .name           = "sha12_ick",
1826         .parent         = &core_l4_ick,
1827         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1828         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1829         .flags          = CLOCK_IN_OMAP343X,
1830         .clkdm          = { .name = "core_l4_clkdm" },
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 static struct clk des2_ick = {
1835         .name           = "des2_ick",
1836         .parent         = &core_l4_ick,
1837         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1838         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1839         .flags          = CLOCK_IN_OMAP343X,
1840         .clkdm          = { .name = "core_l4_clkdm" },
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 static struct clk mmchs2_ick = {
1845         .name           = "mmchs_ick",
1846         .id             = 2,
1847         .parent         = &core_l4_ick,
1848         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1849         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1850         .flags          = CLOCK_IN_OMAP343X,
1851         .clkdm          = { .name = "core_l4_clkdm" },
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk mmchs1_ick = {
1856         .name           = "mmchs_ick",
1857         .id             = 1,
1858         .parent         = &core_l4_ick,
1859         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1860         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1861         .flags          = CLOCK_IN_OMAP343X,
1862         .clkdm          = { .name = "core_l4_clkdm" },
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 static struct clk mspro_ick = {
1867         .name           = "mspro_ick",
1868         .parent         = &core_l4_ick,
1869         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1870         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1871         .flags          = CLOCK_IN_OMAP343X,
1872         .clkdm          = { .name = "core_l4_clkdm" },
1873         .recalc         = &followparent_recalc,
1874 };
1875
1876 static struct clk hdq_ick = {
1877         .name           = "hdq_ick",
1878         .parent         = &core_l4_ick,
1879         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1880         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1881         .flags          = CLOCK_IN_OMAP343X,
1882         .clkdm          = { .name = "core_l4_clkdm" },
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk mcspi4_ick = {
1887         .name           = "mcspi_ick",
1888         .id             = 4,
1889         .parent         = &core_l4_ick,
1890         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1891         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1892         .flags          = CLOCK_IN_OMAP343X,
1893         .clkdm          = { .name = "core_l4_clkdm" },
1894         .recalc         = &followparent_recalc,
1895 };
1896
1897 static struct clk mcspi3_ick = {
1898         .name           = "mcspi_ick",
1899         .id             = 3,
1900         .parent         = &core_l4_ick,
1901         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1903         .flags          = CLOCK_IN_OMAP343X,
1904         .clkdm          = { .name = "core_l4_clkdm" },
1905         .recalc         = &followparent_recalc,
1906 };
1907
1908 static struct clk mcspi2_ick = {
1909         .name           = "mcspi_ick",
1910         .id             = 2,
1911         .parent         = &core_l4_ick,
1912         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1914         .flags          = CLOCK_IN_OMAP343X,
1915         .clkdm          = { .name = "core_l4_clkdm" },
1916         .recalc         = &followparent_recalc,
1917 };
1918
1919 static struct clk mcspi1_ick = {
1920         .name           = "mcspi_ick",
1921         .id             = 1,
1922         .parent         = &core_l4_ick,
1923         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1924         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1925         .flags          = CLOCK_IN_OMAP343X,
1926         .clkdm          = { .name = "core_l4_clkdm" },
1927         .recalc         = &followparent_recalc,
1928 };
1929
1930 static struct clk i2c3_ick = {
1931         .name           = "i2c_ick",
1932         .id             = 3,
1933         .parent         = &core_l4_ick,
1934         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1935         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1936         .flags          = CLOCK_IN_OMAP343X,
1937         .clkdm          = { .name = "core_l4_clkdm" },
1938         .recalc         = &followparent_recalc,
1939 };
1940
1941 static struct clk i2c2_ick = {
1942         .name           = "i2c_ick",
1943         .id             = 2,
1944         .parent         = &core_l4_ick,
1945         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1946         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1947         .flags          = CLOCK_IN_OMAP343X,
1948         .clkdm          = { .name = "core_l4_clkdm" },
1949         .recalc         = &followparent_recalc,
1950 };
1951
1952 static struct clk i2c1_ick = {
1953         .name           = "i2c_ick",
1954         .id             = 1,
1955         .parent         = &core_l4_ick,
1956         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1957         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1958         .flags          = CLOCK_IN_OMAP343X,
1959         .clkdm          = { .name = "core_l4_clkdm" },
1960         .recalc         = &followparent_recalc,
1961 };
1962
1963 static struct clk uart2_ick = {
1964         .name           = "uart2_ick",
1965         .parent         = &core_l4_ick,
1966         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1967         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1968         .flags          = CLOCK_IN_OMAP343X,
1969         .clkdm          = { .name = "core_l4_clkdm" },
1970         .recalc         = &followparent_recalc,
1971 };
1972
1973 static struct clk uart1_ick = {
1974         .name           = "uart1_ick",
1975         .parent         = &core_l4_ick,
1976         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1978         .flags          = CLOCK_IN_OMAP343X,
1979         .clkdm          = { .name = "core_l4_clkdm" },
1980         .recalc         = &followparent_recalc,
1981 };
1982
1983 static struct clk gpt11_ick = {
1984         .name           = "gpt11_ick",
1985         .parent         = &core_l4_ick,
1986         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1988         .flags          = CLOCK_IN_OMAP343X,
1989         .clkdm          = { .name = "core_l4_clkdm" },
1990         .recalc         = &followparent_recalc,
1991 };
1992
1993 static struct clk gpt10_ick = {
1994         .name           = "gpt10_ick",
1995         .parent         = &core_l4_ick,
1996         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1997         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1998         .flags          = CLOCK_IN_OMAP343X,
1999         .clkdm          = { .name = "core_l4_clkdm" },
2000         .recalc         = &followparent_recalc,
2001 };
2002
2003 static struct clk mcbsp5_ick = {
2004         .name           = "mcbsp_ick",
2005         .id             = 5,
2006         .parent         = &core_l4_ick,
2007         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2008         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2009         .flags          = CLOCK_IN_OMAP343X,
2010         .clkdm          = { .name = "core_l4_clkdm" },
2011         .recalc         = &followparent_recalc,
2012 };
2013
2014 static struct clk mcbsp1_ick = {
2015         .name           = "mcbsp_ick",
2016         .id             = 1,
2017         .parent         = &core_l4_ick,
2018         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2020         .flags          = CLOCK_IN_OMAP343X,
2021         .clkdm          = { .name = "core_l4_clkdm" },
2022         .recalc         = &followparent_recalc,
2023 };
2024
2025 static struct clk fac_ick = {
2026         .name           = "fac_ick",
2027         .parent         = &core_l4_ick,
2028         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2029         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2030         .flags          = CLOCK_IN_OMAP3430ES1,
2031         .clkdm          = { .name = "core_l4_clkdm" },
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 static struct clk mailboxes_ick = {
2036         .name           = "mailboxes_ick",
2037         .parent         = &core_l4_ick,
2038         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2039         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2040         .flags          = CLOCK_IN_OMAP343X,
2041         .clkdm          = { .name = "core_l4_clkdm" },
2042         .recalc         = &followparent_recalc,
2043 };
2044
2045 static struct clk omapctrl_ick = {
2046         .name           = "omapctrl_ick",
2047         .parent         = &core_l4_ick,
2048         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2050         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2051         .recalc         = &followparent_recalc,
2052 };
2053
2054 /* SSI_L4_ICK based clocks */
2055
2056 static struct clk ssi_l4_ick = {
2057         .name           = "ssi_l4_ick",
2058         .parent         = &l4_ick,
2059         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2060                                 PARENT_CONTROLS_CLOCK,
2061         .clkdm          = { .name = "core_l4_clkdm" },
2062         .recalc         = &followparent_recalc,
2063 };
2064
2065 static struct clk ssi_ick = {
2066         .name           = "ssi_ick",
2067         .parent         = &ssi_l4_ick,
2068         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2069         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2070         .flags          = CLOCK_IN_OMAP343X,
2071         .clkdm          = { .name = "core_l4_clkdm" },
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2076  * but l4_ick makes more sense to me */
2077
2078 static const struct clksel usb_l4_clksel[] = {
2079         { .parent = &l4_ick, .rates = div2_rates },
2080         { .parent = NULL },
2081 };
2082
2083 static struct clk usb_l4_ick = {
2084         .name           = "usb_l4_ick",
2085         .parent         = &l4_ick,
2086         .init           = &omap2_init_clksel_parent,
2087         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2088         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2089         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2090         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2091         .clksel         = usb_l4_clksel,
2092         .flags          = CLOCK_IN_OMAP3430ES1,
2093         .recalc         = &omap2_clksel_recalc,
2094 };
2095
2096 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2097
2098 /* SECURITY_L4_ICK2 based clocks */
2099
2100 static struct clk security_l4_ick2 = {
2101         .name           = "security_l4_ick2",
2102         .parent         = &l4_ick,
2103         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2104                                 PARENT_CONTROLS_CLOCK,
2105         .recalc         = &followparent_recalc,
2106 };
2107
2108 static struct clk aes1_ick = {
2109         .name           = "aes1_ick",
2110         .parent         = &security_l4_ick2,
2111         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2112         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2113         .flags          = CLOCK_IN_OMAP343X,
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk rng_ick = {
2118         .name           = "rng_ick",
2119         .parent         = &security_l4_ick2,
2120         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2121         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2122         .flags          = CLOCK_IN_OMAP343X,
2123         .recalc         = &followparent_recalc,
2124 };
2125
2126 static struct clk sha11_ick = {
2127         .name           = "sha11_ick",
2128         .parent         = &security_l4_ick2,
2129         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2130         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2131         .flags          = CLOCK_IN_OMAP343X,
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk des1_ick = {
2136         .name           = "des1_ick",
2137         .parent         = &security_l4_ick2,
2138         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2139         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2140         .flags          = CLOCK_IN_OMAP343X,
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 /* DSS */
2145 static const struct clksel dss1_alwon_fck_clksel[] = {
2146         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2147         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2148         { .parent = NULL }
2149 };
2150
2151 static struct clk dss1_alwon_fck = {
2152         .name           = "dss1_alwon_fck",
2153         .parent         = &dpll4_m4x2_ck,
2154         .init           = &omap2_init_clksel_parent,
2155         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2156         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2157         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2158         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2159         .clksel         = dss1_alwon_fck_clksel,
2160         .flags          = CLOCK_IN_OMAP343X,
2161         .clkdm          = { .name = "dss_clkdm" },
2162         .recalc         = &omap2_clksel_recalc,
2163 };
2164
2165 static struct clk dss_tv_fck = {
2166         .name           = "dss_tv_fck",
2167         .parent         = &omap_54m_fck,
2168         .init           = &omap2_init_clk_clkdm,
2169         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2170         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2171         .flags          = CLOCK_IN_OMAP343X,
2172         .clkdm          = { .name = "dss_clkdm" },
2173         .recalc         = &followparent_recalc,
2174 };
2175
2176 static struct clk dss_96m_fck = {
2177         .name           = "dss_96m_fck",
2178         .parent         = &omap_96m_fck,
2179         .init           = &omap2_init_clk_clkdm,
2180         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2181         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2182         .flags          = CLOCK_IN_OMAP343X,
2183         .clkdm          = { .name = "dss_clkdm" },
2184         .recalc         = &followparent_recalc,
2185 };
2186
2187 static struct clk dss2_alwon_fck = {
2188         .name           = "dss2_alwon_fck",
2189         .parent         = &sys_ck,
2190         .init           = &omap2_init_clk_clkdm,
2191         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2192         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2193         .flags          = CLOCK_IN_OMAP343X,
2194         .clkdm          = { .name = "dss_clkdm" },
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk dss_ick = {
2199         /* Handles both L3 and L4 clocks */
2200         .name           = "dss_ick",
2201         .parent         = &l4_ick,
2202         .init           = &omap2_init_clk_clkdm,
2203         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2204         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2205         .flags          = CLOCK_IN_OMAP343X,
2206         .clkdm          = { .name = "dss_clkdm" },
2207         .recalc         = &followparent_recalc,
2208 };
2209
2210 /* CAM */
2211
2212 static const struct clksel cam_mclk_clksel[] = {
2213         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2214         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2215         { .parent = NULL }
2216 };
2217
2218 static struct clk cam_mclk = {
2219         .name           = "cam_mclk",
2220         .parent         = &dpll4_m5x2_ck,
2221         .init           = &omap2_init_clksel_parent,
2222         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2223         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2224         .clksel         = cam_mclk_clksel,
2225         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2226         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2227         .flags          = CLOCK_IN_OMAP343X,
2228         .clkdm          = { .name = "cam_clkdm" },
2229         .recalc         = &omap2_clksel_recalc,
2230 };
2231
2232 static struct clk cam_ick = {
2233         /* Handles both L3 and L4 clocks */
2234         .name           = "cam_ick",
2235         .parent         = &l4_ick,
2236         .init           = &omap2_init_clk_clkdm,
2237         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2238         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2239         .flags          = CLOCK_IN_OMAP343X,
2240         .clkdm          = { .name = "cam_clkdm" },
2241         .recalc         = &followparent_recalc,
2242 };
2243
2244 static struct clk csi2_96m_fck = {
2245         .name           = "csi2_96m_fck",
2246         .parent         = &core_96m_fck,
2247         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2248         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2249         .flags          = CLOCK_IN_OMAP343X,
2250         .clkdm          = { .name = "cam_clkdm" },
2251         .recalc         = &followparent_recalc,
2252 };
2253
2254 /* USBHOST - 3430ES2 only */
2255
2256 static struct clk usbhost_120m_fck = {
2257         .name           = "usbhost_120m_fck",
2258         .parent         = &omap_120m_fck,
2259         .init           = &omap2_init_clk_clkdm,
2260         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2261         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2262         .flags          = CLOCK_IN_OMAP3430ES2,
2263         .clkdm          = { .name = "usbhost_clkdm" },
2264         .recalc         = &followparent_recalc,
2265 };
2266
2267 static struct clk usbhost_48m_fck = {
2268         .name           = "usbhost_48m_fck",
2269         .parent         = &omap_48m_fck,
2270         .init           = &omap2_init_clk_clkdm,
2271         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2272         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2273         .flags          = CLOCK_IN_OMAP3430ES2,
2274         .clkdm          = { .name = "usbhost_clkdm" },
2275         .recalc         = &followparent_recalc,
2276 };
2277
2278 static struct clk usbhost_ick = {
2279         /* Handles both L3 and L4 clocks */
2280         .name           = "usbhost_ick",
2281         .parent         = &l4_ick,
2282         .init           = &omap2_init_clk_clkdm,
2283         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2284         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2285         .flags          = CLOCK_IN_OMAP3430ES2,
2286         .clkdm          = { .name = "usbhost_clkdm" },
2287         .recalc         = &followparent_recalc,
2288 };
2289
2290 /* WKUP */
2291
2292 static const struct clksel_rate usim_96m_rates[] = {
2293         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2294         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2295         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2296         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2297         { .div = 0 },
2298 };
2299
2300 static const struct clksel_rate usim_120m_rates[] = {
2301         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2302         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2303         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2304         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2305         { .div = 0 },
2306 };
2307
2308 static const struct clksel usim_clksel[] = {
2309         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2310         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2311         { .parent = &sys_ck,            .rates = div2_rates },
2312         { .parent = NULL },
2313 };
2314
2315 /* 3430ES2 only */
2316 static struct clk usim_fck = {
2317         .name           = "usim_fck",
2318         .init           = &omap2_init_clksel_parent,
2319         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2320         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2321         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2322         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2323         .clksel         = usim_clksel,
2324         .flags          = CLOCK_IN_OMAP3430ES2,
2325         .clkdm          = { .name = "prm_clkdm" },
2326         .recalc         = &omap2_clksel_recalc,
2327 };
2328
2329 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2330 static struct clk gpt1_fck = {
2331         .name           = "gpt1_fck",
2332         .init           = &omap2_init_clksel_parent,
2333         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2334         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2335         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2336         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2337         .clksel         = omap343x_gpt_clksel,
2338         .flags          = CLOCK_IN_OMAP343X,
2339         .clkdm          = { .name = "prm_clkdm" },
2340         .recalc         = &omap2_clksel_recalc,
2341 };
2342
2343 static struct clk wkup_32k_fck = {
2344         .name           = "wkup_32k_fck",
2345         .init           = &omap2_init_clk_clkdm,
2346         .parent         = &omap_32k_fck,
2347         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2348         .clkdm          = { .name = "prm_clkdm" },
2349         .recalc         = &followparent_recalc,
2350 };
2351
2352 static struct clk gpio1_fck = {
2353         .name           = "gpio1_fck",
2354         .parent         = &wkup_32k_fck,
2355         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2356         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2357         .flags          = CLOCK_IN_OMAP343X,
2358         .clkdm          = { .name = "prm_clkdm" },
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk wdt2_fck = {
2363         .name           = "wdt2_fck",
2364         .parent         = &wkup_32k_fck,
2365         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2366         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2367         .flags          = CLOCK_IN_OMAP343X,
2368         .clkdm          = { .name = "prm_clkdm" },
2369         .recalc         = &followparent_recalc,
2370 };
2371
2372 static struct clk wkup_l4_ick = {
2373         .name           = "wkup_l4_ick",
2374         .parent         = &sys_ck,
2375         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2376         .clkdm          = { .name = "prm_clkdm" },
2377         .recalc         = &followparent_recalc,
2378 };
2379
2380 /* 3430ES2 only */
2381 /* Never specifically named in the TRM, so we have to infer a likely name */
2382 static struct clk usim_ick = {
2383         .name           = "usim_ick",
2384         .parent         = &wkup_l4_ick,
2385         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2386         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2387         .flags          = CLOCK_IN_OMAP3430ES2,
2388         .clkdm          = { .name = "prm_clkdm" },
2389         .recalc         = &followparent_recalc,
2390 };
2391
2392 static struct clk wdt2_ick = {
2393         .name           = "wdt2_ick",
2394         .parent         = &wkup_l4_ick,
2395         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2396         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2397         .flags          = CLOCK_IN_OMAP343X,
2398         .clkdm          = { .name = "prm_clkdm" },
2399         .recalc         = &followparent_recalc,
2400 };
2401
2402 static struct clk wdt1_ick = {
2403         .name           = "wdt1_ick",
2404         .parent         = &wkup_l4_ick,
2405         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2406         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2407         .flags          = CLOCK_IN_OMAP343X,
2408         .clkdm          = { .name = "prm_clkdm" },
2409         .recalc         = &followparent_recalc,
2410 };
2411
2412 static struct clk gpio1_ick = {
2413         .name           = "gpio1_ick",
2414         .parent         = &wkup_l4_ick,
2415         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2416         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2417         .flags          = CLOCK_IN_OMAP343X,
2418         .clkdm          = { .name = "prm_clkdm" },
2419         .recalc         = &followparent_recalc,
2420 };
2421
2422 static struct clk omap_32ksync_ick = {
2423         .name           = "omap_32ksync_ick",
2424         .parent         = &wkup_l4_ick,
2425         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2426         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2427         .flags          = CLOCK_IN_OMAP343X,
2428         .clkdm          = { .name = "prm_clkdm" },
2429         .recalc         = &followparent_recalc,
2430 };
2431
2432 static struct clk gpt12_ick = {
2433         .name           = "gpt12_ick",
2434         .parent         = &wkup_l4_ick,
2435         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2436         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2437         .flags          = CLOCK_IN_OMAP343X,
2438         .clkdm          = { .name = "prm_clkdm" },
2439         .recalc         = &followparent_recalc,
2440 };
2441
2442 static struct clk gpt1_ick = {
2443         .name           = "gpt1_ick",
2444         .parent         = &wkup_l4_ick,
2445         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2446         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2447         .flags          = CLOCK_IN_OMAP343X,
2448         .clkdm          = { .name = "prm_clkdm" },
2449         .recalc         = &followparent_recalc,
2450 };
2451
2452
2453
2454 /* PER clock domain */
2455
2456 static struct clk per_96m_fck = {
2457         .name           = "per_96m_fck",
2458         .parent         = &omap_96m_alwon_fck,
2459         .init           = &omap2_init_clk_clkdm,
2460         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2461                                 PARENT_CONTROLS_CLOCK,
2462         .clkdm          = { .name = "per_clkdm" },
2463         .recalc         = &followparent_recalc,
2464 };
2465
2466 static struct clk per_48m_fck = {
2467         .name           = "per_48m_fck",
2468         .parent         = &omap_48m_fck,
2469         .init           = &omap2_init_clk_clkdm,
2470         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2471                                 PARENT_CONTROLS_CLOCK,
2472         .clkdm          = { .name = "per_clkdm" },
2473         .recalc         = &followparent_recalc,
2474 };
2475
2476 static struct clk uart3_fck = {
2477         .name           = "uart3_fck",
2478         .parent         = &per_48m_fck,
2479         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2480         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2481         .flags          = CLOCK_IN_OMAP343X,
2482         .clkdm          = { .name = "per_clkdm" },
2483         .recalc         = &followparent_recalc,
2484 };
2485
2486 static struct clk gpt2_fck = {
2487         .name           = "gpt2_fck",
2488         .init           = &omap2_init_clksel_parent,
2489         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2490         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2491         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2492         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2493         .clksel         = omap343x_gpt_clksel,
2494         .flags          = CLOCK_IN_OMAP343X,
2495         .clkdm          = { .name = "per_clkdm" },
2496         .recalc         = &omap2_clksel_recalc,
2497 };
2498
2499 static struct clk gpt3_fck = {
2500         .name           = "gpt3_fck",
2501         .init           = &omap2_init_clksel_parent,
2502         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2503         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2504         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2505         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2506         .clksel         = omap343x_gpt_clksel,
2507         .flags          = CLOCK_IN_OMAP343X,
2508         .clkdm          = { .name = "per_clkdm" },
2509         .recalc         = &omap2_clksel_recalc,
2510 };
2511
2512 static struct clk gpt4_fck = {
2513         .name           = "gpt4_fck",
2514         .init           = &omap2_init_clksel_parent,
2515         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2516         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2517         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2518         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2519         .clksel         = omap343x_gpt_clksel,
2520         .flags          = CLOCK_IN_OMAP343X,
2521         .clkdm          = { .name = "per_clkdm" },
2522         .recalc         = &omap2_clksel_recalc,
2523 };
2524
2525 static struct clk gpt5_fck = {
2526         .name           = "gpt5_fck",
2527         .init           = &omap2_init_clksel_parent,
2528         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2529         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2530         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2531         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2532         .clksel         = omap343x_gpt_clksel,
2533         .flags          = CLOCK_IN_OMAP343X,
2534         .clkdm          = { .name = "per_clkdm" },
2535         .recalc         = &omap2_clksel_recalc,
2536 };
2537
2538 static struct clk gpt6_fck = {
2539         .name           = "gpt6_fck",
2540         .init           = &omap2_init_clksel_parent,
2541         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2542         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2543         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2544         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2545         .clksel         = omap343x_gpt_clksel,
2546         .flags          = CLOCK_IN_OMAP343X,
2547         .clkdm          = { .name = "per_clkdm" },
2548         .recalc         = &omap2_clksel_recalc,
2549 };
2550
2551 static struct clk gpt7_fck = {
2552         .name           = "gpt7_fck",
2553         .init           = &omap2_init_clksel_parent,
2554         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2555         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2556         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2557         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2558         .clksel         = omap343x_gpt_clksel,
2559         .flags          = CLOCK_IN_OMAP343X,
2560         .clkdm          = { .name = "per_clkdm" },
2561         .recalc         = &omap2_clksel_recalc,
2562 };
2563
2564 static struct clk gpt8_fck = {
2565         .name           = "gpt8_fck",
2566         .init           = &omap2_init_clksel_parent,
2567         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2568         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2569         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2570         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2571         .clksel         = omap343x_gpt_clksel,
2572         .flags          = CLOCK_IN_OMAP343X,
2573         .clkdm          = { .name = "per_clkdm" },
2574         .recalc         = &omap2_clksel_recalc,
2575 };
2576
2577 static struct clk gpt9_fck = {
2578         .name           = "gpt9_fck",
2579         .init           = &omap2_init_clksel_parent,
2580         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2581         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2582         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2583         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2584         .clksel         = omap343x_gpt_clksel,
2585         .flags          = CLOCK_IN_OMAP343X,
2586         .clkdm          = { .name = "per_clkdm" },
2587         .recalc         = &omap2_clksel_recalc,
2588 };
2589
2590 static struct clk per_32k_alwon_fck = {
2591         .name           = "per_32k_alwon_fck",
2592         .parent         = &omap_32k_fck,
2593         .clkdm          = { .name = "per_clkdm" },
2594         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2595         .recalc         = &followparent_recalc,
2596 };
2597
2598 static struct clk gpio6_fck = {
2599         .name           = "gpio6_fck",
2600         .parent         = &per_32k_alwon_fck,
2601         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2602         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2603         .flags          = CLOCK_IN_OMAP343X,
2604         .clkdm          = { .name = "per_clkdm" },
2605         .recalc         = &followparent_recalc,
2606 };
2607
2608 static struct clk gpio5_fck = {
2609         .name           = "gpio5_fck",
2610         .parent         = &per_32k_alwon_fck,
2611         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2612         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2613         .flags          = CLOCK_IN_OMAP343X,
2614         .clkdm          = { .name = "per_clkdm" },
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk gpio4_fck = {
2619         .name           = "gpio4_fck",
2620         .parent         = &per_32k_alwon_fck,
2621         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2622         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2623         .flags          = CLOCK_IN_OMAP343X,
2624         .clkdm          = { .name = "per_clkdm" },
2625         .recalc         = &followparent_recalc,
2626 };
2627
2628 static struct clk gpio3_fck = {
2629         .name           = "gpio3_fck",
2630         .parent         = &per_32k_alwon_fck,
2631         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2632         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2633         .flags          = CLOCK_IN_OMAP343X,
2634         .clkdm          = { .name = "per_clkdm" },
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static struct clk gpio2_fck = {
2639         .name           = "gpio2_fck",
2640         .parent         = &per_32k_alwon_fck,
2641         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2642         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2643         .flags          = CLOCK_IN_OMAP343X,
2644         .clkdm          = { .name = "per_clkdm" },
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static struct clk wdt3_fck = {
2649         .name           = "wdt3_fck",
2650         .parent         = &per_32k_alwon_fck,
2651         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2652         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2653         .flags          = CLOCK_IN_OMAP343X,
2654         .clkdm          = { .name = "per_clkdm" },
2655         .recalc         = &followparent_recalc,
2656 };
2657
2658 static struct clk per_l4_ick = {
2659         .name           = "per_l4_ick",
2660         .parent         = &l4_ick,
2661         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2662                                 PARENT_CONTROLS_CLOCK,
2663         .clkdm          = { .name = "per_clkdm" },
2664         .recalc         = &followparent_recalc,
2665 };
2666
2667 static struct clk gpio6_ick = {
2668         .name           = "gpio6_ick",
2669         .parent         = &per_l4_ick,
2670         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2671         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2672         .flags          = CLOCK_IN_OMAP343X,
2673         .clkdm          = { .name = "per_clkdm" },
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static struct clk gpio5_ick = {
2678         .name           = "gpio5_ick",
2679         .parent         = &per_l4_ick,
2680         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2681         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2682         .flags          = CLOCK_IN_OMAP343X,
2683         .clkdm          = { .name = "per_clkdm" },
2684         .recalc         = &followparent_recalc,
2685 };
2686
2687 static struct clk gpio4_ick = {
2688         .name           = "gpio4_ick",
2689         .parent         = &per_l4_ick,
2690         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2691         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2692         .flags          = CLOCK_IN_OMAP343X,
2693         .clkdm          = { .name = "per_clkdm" },
2694         .recalc         = &followparent_recalc,
2695 };
2696
2697 static struct clk gpio3_ick = {
2698         .name           = "gpio3_ick",
2699         .parent         = &per_l4_ick,
2700         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2701         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2702         .flags          = CLOCK_IN_OMAP343X,
2703         .clkdm          = { .name = "per_clkdm" },
2704         .recalc         = &followparent_recalc,
2705 };
2706
2707 static struct clk gpio2_ick = {
2708         .name           = "gpio2_ick",
2709         .parent         = &per_l4_ick,
2710         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2711         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2712         .flags          = CLOCK_IN_OMAP343X,
2713         .clkdm          = { .name = "per_clkdm" },
2714         .recalc         = &followparent_recalc,
2715 };
2716
2717 static struct clk wdt3_ick = {
2718         .name           = "wdt3_ick",
2719         .parent         = &per_l4_ick,
2720         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2721         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2722         .flags          = CLOCK_IN_OMAP343X,
2723         .clkdm          = { .name = "per_clkdm" },
2724         .recalc         = &followparent_recalc,
2725 };
2726
2727 static struct clk uart3_ick = {
2728         .name           = "uart3_ick",
2729         .parent         = &per_l4_ick,
2730         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2731         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2732         .flags          = CLOCK_IN_OMAP343X,
2733         .clkdm          = { .name = "per_clkdm" },
2734         .recalc         = &followparent_recalc,
2735 };
2736
2737 static struct clk gpt9_ick = {
2738         .name           = "gpt9_ick",
2739         .parent         = &per_l4_ick,
2740         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2741         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2742         .flags          = CLOCK_IN_OMAP343X,
2743         .clkdm          = { .name = "per_clkdm" },
2744         .recalc         = &followparent_recalc,
2745 };
2746
2747 static struct clk gpt8_ick = {
2748         .name           = "gpt8_ick",
2749         .parent         = &per_l4_ick,
2750         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2751         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2752         .flags          = CLOCK_IN_OMAP343X,
2753         .clkdm          = { .name = "per_clkdm" },
2754         .recalc         = &followparent_recalc,
2755 };
2756
2757 static struct clk gpt7_ick = {
2758         .name           = "gpt7_ick",
2759         .parent         = &per_l4_ick,
2760         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2761         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2762         .flags          = CLOCK_IN_OMAP343X,
2763         .clkdm          = { .name = "per_clkdm" },
2764         .recalc         = &followparent_recalc,
2765 };
2766
2767 static struct clk gpt6_ick = {
2768         .name           = "gpt6_ick",
2769         .parent         = &per_l4_ick,
2770         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2771         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2772         .flags          = CLOCK_IN_OMAP343X,
2773         .clkdm          = { .name = "per_clkdm" },
2774         .recalc         = &followparent_recalc,
2775 };
2776
2777 static struct clk gpt5_ick = {
2778         .name           = "gpt5_ick",
2779         .parent         = &per_l4_ick,
2780         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2781         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2782         .flags          = CLOCK_IN_OMAP343X,
2783         .clkdm          = { .name = "per_clkdm" },
2784         .recalc         = &followparent_recalc,
2785 };
2786
2787 static struct clk gpt4_ick = {
2788         .name           = "gpt4_ick",
2789         .parent         = &per_l4_ick,
2790         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2791         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2792         .flags          = CLOCK_IN_OMAP343X,
2793         .clkdm          = { .name = "per_clkdm" },
2794         .recalc         = &followparent_recalc,
2795 };
2796
2797 static struct clk gpt3_ick = {
2798         .name           = "gpt3_ick",
2799         .parent         = &per_l4_ick,
2800         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2801         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2802         .flags          = CLOCK_IN_OMAP343X,
2803         .clkdm          = { .name = "per_clkdm" },
2804         .recalc         = &followparent_recalc,
2805 };
2806
2807 static struct clk gpt2_ick = {
2808         .name           = "gpt2_ick",
2809         .parent         = &per_l4_ick,
2810         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2811         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2812         .flags          = CLOCK_IN_OMAP343X,
2813         .clkdm          = { .name = "per_clkdm" },
2814         .recalc         = &followparent_recalc,
2815 };
2816
2817 static struct clk mcbsp2_ick = {
2818         .name           = "mcbsp_ick",
2819         .id             = 2,
2820         .parent         = &per_l4_ick,
2821         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2822         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2823         .flags          = CLOCK_IN_OMAP343X,
2824         .clkdm          = { .name = "per_clkdm" },
2825         .recalc         = &followparent_recalc,
2826 };
2827
2828 static struct clk mcbsp3_ick = {
2829         .name           = "mcbsp_ick",
2830         .id             = 3,
2831         .parent         = &per_l4_ick,
2832         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2833         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2834         .flags          = CLOCK_IN_OMAP343X,
2835         .clkdm          = { .name = "per_clkdm" },
2836         .recalc         = &followparent_recalc,
2837 };
2838
2839 static struct clk mcbsp4_ick = {
2840         .name           = "mcbsp_ick",
2841         .id             = 4,
2842         .parent         = &per_l4_ick,
2843         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2844         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2845         .flags          = CLOCK_IN_OMAP343X,
2846         .clkdm          = { .name = "per_clkdm" },
2847         .recalc         = &followparent_recalc,
2848 };
2849
2850 static const struct clksel mcbsp_234_clksel[] = {
2851         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2852         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2853         { .parent = NULL }
2854 };
2855
2856 static struct clk mcbsp2_fck = {
2857         .name           = "mcbsp_fck",
2858         .id             = 2,
2859         .init           = &omap2_init_clksel_parent,
2860         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2861         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2862         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2863         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2864         .clksel         = mcbsp_234_clksel,
2865         .flags          = CLOCK_IN_OMAP343X,
2866         .clkdm          = { .name = "per_clkdm" },
2867         .recalc         = &omap2_clksel_recalc,
2868 };
2869
2870 static struct clk mcbsp3_fck = {
2871         .name           = "mcbsp_fck",
2872         .id             = 3,
2873         .init           = &omap2_init_clksel_parent,
2874         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2875         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2876         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2877         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2878         .clksel         = mcbsp_234_clksel,
2879         .flags          = CLOCK_IN_OMAP343X,
2880         .clkdm          = { .name = "per_clkdm" },
2881         .recalc         = &omap2_clksel_recalc,
2882 };
2883
2884 static struct clk mcbsp4_fck = {
2885         .name           = "mcbsp_fck",
2886         .id             = 4,
2887         .init           = &omap2_init_clksel_parent,
2888         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2889         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2890         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2891         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2892         .clksel         = mcbsp_234_clksel,
2893         .flags          = CLOCK_IN_OMAP343X,
2894         .clkdm          = { .name = "per_clkdm" },
2895         .recalc         = &omap2_clksel_recalc,
2896 };
2897
2898 /* EMU clocks */
2899
2900 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2901
2902 static const struct clksel_rate emu_src_sys_rates[] = {
2903         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2904         { .div = 0 },
2905 };
2906
2907 static const struct clksel_rate emu_src_core_rates[] = {
2908         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2909         { .div = 0 },
2910 };
2911
2912 static const struct clksel_rate emu_src_per_rates[] = {
2913         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2914         { .div = 0 },
2915 };
2916
2917 static const struct clksel_rate emu_src_mpu_rates[] = {
2918         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2919         { .div = 0 },
2920 };
2921
2922 static const struct clksel emu_src_clksel[] = {
2923         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2924         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2925         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2926         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2927         { .parent = NULL },
2928 };
2929
2930 /*
2931  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2932  * to switch the source of some of the EMU clocks.
2933  * XXX Are there CLKEN bits for these EMU clks?
2934  */
2935 static struct clk emu_src_ck = {
2936         .name           = "emu_src_ck",
2937         .init           = &omap2_init_clksel_parent,
2938         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2939         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2940         .clksel         = emu_src_clksel,
2941         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2942         .clkdm          = { .name = "emu_clkdm" },
2943         .recalc         = &omap2_clksel_recalc,
2944 };
2945
2946 static const struct clksel_rate pclk_emu_rates[] = {
2947         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2948         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2949         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2950         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2951         { .div = 0 },
2952 };
2953
2954 static const struct clksel pclk_emu_clksel[] = {
2955         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2956         { .parent = NULL },
2957 };
2958
2959 static struct clk pclk_fck = {
2960         .name           = "pclk_fck",
2961         .init           = &omap2_init_clksel_parent,
2962         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2963         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2964         .clksel         = pclk_emu_clksel,
2965         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2966         .clkdm          = { .name = "emu_clkdm" },
2967         .recalc         = &omap2_clksel_recalc,
2968 };
2969
2970 static const struct clksel_rate pclkx2_emu_rates[] = {
2971         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2972         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2973         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2974         { .div = 0 },
2975 };
2976
2977 static const struct clksel pclkx2_emu_clksel[] = {
2978         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2979         { .parent = NULL },
2980 };
2981
2982 static struct clk pclkx2_fck = {
2983         .name           = "pclkx2_fck",
2984         .init           = &omap2_init_clksel_parent,
2985         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2986         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2987         .clksel         = pclkx2_emu_clksel,
2988         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2989         .clkdm          = { .name = "emu_clkdm" },
2990         .recalc         = &omap2_clksel_recalc,
2991 };
2992
2993 static const struct clksel atclk_emu_clksel[] = {
2994         { .parent = &emu_src_ck, .rates = div2_rates },
2995         { .parent = NULL },
2996 };
2997
2998 static struct clk atclk_fck = {
2999         .name           = "atclk_fck",
3000         .init           = &omap2_init_clksel_parent,
3001         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3002         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3003         .clksel         = atclk_emu_clksel,
3004         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3005         .clkdm          = { .name = "emu_clkdm" },
3006         .recalc         = &omap2_clksel_recalc,
3007 };
3008
3009 static struct clk traceclk_src_fck = {
3010         .name           = "traceclk_src_fck",
3011         .init           = &omap2_init_clksel_parent,
3012         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3013         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3014         .clksel         = emu_src_clksel,
3015         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3016         .clkdm          = { .name = "emu_clkdm" },
3017         .recalc         = &omap2_clksel_recalc,
3018 };
3019
3020 static const struct clksel_rate traceclk_rates[] = {
3021         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3022         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3023         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3024         { .div = 0 },
3025 };
3026
3027 static const struct clksel traceclk_clksel[] = {
3028         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3029         { .parent = NULL },
3030 };
3031
3032 static struct clk traceclk_fck = {
3033         .name           = "traceclk_fck",
3034         .init           = &omap2_init_clksel_parent,
3035         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3036         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3037         .clksel         = traceclk_clksel,
3038         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3039         .clkdm          = { .name = "emu_clkdm" },
3040         .recalc         = &omap2_clksel_recalc,
3041 };
3042
3043 /* SR clocks */
3044
3045 /* SmartReflex fclk (VDD1) */
3046 static struct clk sr1_fck = {
3047         .name           = "sr1_fck",
3048         .parent         = &sys_ck,
3049         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3050         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3051         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3052         .clkdm          = { .name = "prm_clkdm" },
3053         .recalc         = &followparent_recalc,
3054 };
3055
3056 /* SmartReflex fclk (VDD2) */
3057 static struct clk sr2_fck = {
3058         .name           = "sr2_fck",
3059         .parent         = &sys_ck,
3060         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3061         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3062         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3063         .clkdm          = { .name = "prm_clkdm" },
3064         .recalc         = &followparent_recalc,
3065 };
3066
3067 static struct clk sr_l4_ick = {
3068         .name           = "sr_l4_ick",
3069         .parent         = &l4_ick,
3070         .flags          = CLOCK_IN_OMAP343X,
3071         .clkdm          = { .name = "core_l4_clkdm" },
3072         .recalc         = &followparent_recalc,
3073 };
3074
3075 /* SECURE_32K_FCK clocks */
3076
3077 /* XXX This clock no longer exists in 3430 TRM rev F */
3078 static struct clk gpt12_fck = {
3079         .name           = "gpt12_fck",
3080         .parent         = &secure_32k_fck,
3081         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3082         .clkdm          = { .name = "prm_clkdm" },
3083         .recalc         = &followparent_recalc,
3084 };
3085
3086 static struct clk wdt1_fck = {
3087         .name           = "wdt1_fck",
3088         .parent         = &secure_32k_fck,
3089         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3090         .clkdm          = { .name = "prm_clkdm" },
3091         .recalc         = &followparent_recalc,
3092 };
3093
3094 static struct clk *onchip_34xx_clks[] __initdata = {
3095         &omap_32k_fck,
3096         &virt_12m_ck,
3097         &virt_13m_ck,
3098         &virt_16_8m_ck,
3099         &virt_19_2m_ck,
3100         &virt_26m_ck,
3101         &virt_38_4m_ck,
3102         &osc_sys_ck,
3103         &sys_ck,
3104         &sys_altclk,
3105         &mcbsp_clks,
3106         &sys_clkout1,
3107         &dpll1_ck,
3108         &dpll1_x2_ck,
3109         &dpll1_x2m2_ck,
3110         &dpll2_ck,
3111         &dpll2_m2_ck,
3112         &dpll3_ck,
3113         &core_ck,
3114         &dpll3_x2_ck,
3115         &dpll3_m2_ck,
3116         &dpll3_m2x2_ck,
3117         &dpll3_m3_ck,
3118         &dpll3_m3x2_ck,
3119         &emu_core_alwon_ck,
3120         &dpll4_ck,
3121         &dpll4_x2_ck,
3122         &omap_96m_alwon_fck,
3123         &omap_96m_fck,
3124         &cm_96m_fck,
3125         &virt_omap_54m_fck,
3126         &omap_54m_fck,
3127         &omap_48m_fck,
3128         &omap_12m_fck,
3129         &dpll4_m2_ck,
3130         &dpll4_m2x2_ck,
3131         &dpll4_m3_ck,
3132         &dpll4_m3x2_ck,
3133         &dpll4_m4_ck,
3134         &dpll4_m4x2_ck,
3135         &dpll4_m5_ck,
3136         &dpll4_m5x2_ck,
3137         &dpll4_m6_ck,
3138         &dpll4_m6x2_ck,
3139         &emu_per_alwon_ck,
3140         &dpll5_ck,
3141         &dpll5_m2_ck,
3142         &omap_120m_fck,
3143         &clkout2_src_ck,
3144         &sys_clkout2,
3145         &corex2_fck,
3146         &dpll1_fck,
3147         &mpu_ck,
3148         &arm_fck,
3149         &emu_mpu_alwon_ck,
3150         &dpll2_fck,
3151         &iva2_ck,
3152         &l3_ick,
3153         &l4_ick,
3154         &rm_ick,
3155         &gfx_l3_ck,
3156         &gfx_l3_fck,
3157         &gfx_l3_ick,
3158         &gfx_cg1_ck,
3159         &gfx_cg2_ck,
3160         &sgx_fck,
3161         &sgx_ick,
3162         &d2d_26m_fck,
3163         &gpt10_fck,
3164         &gpt11_fck,
3165         &cpefuse_fck,
3166         &ts_fck,
3167         &usbtll_fck,
3168         &core_96m_fck,
3169         &mmchs3_fck,
3170         &mmchs2_fck,
3171         &mspro_fck,
3172         &mmchs1_fck,
3173         &i2c3_fck,
3174         &i2c2_fck,
3175         &i2c1_fck,
3176         &mcbsp5_fck,
3177         &mcbsp1_fck,
3178         &core_48m_fck,
3179         &mcspi4_fck,
3180         &mcspi3_fck,
3181         &mcspi2_fck,
3182         &mcspi1_fck,
3183         &uart2_fck,
3184         &uart1_fck,
3185         &fshostusb_fck,
3186         &core_12m_fck,
3187         &hdq_fck,
3188         &ssi_ssr_fck,
3189         &ssi_sst_fck,
3190         &core_l3_ick,
3191         &hsotgusb_ick,
3192         &sdrc_ick,
3193         &gpmc_fck,
3194         &security_l3_ick,
3195         &pka_ick,
3196         &core_l4_ick,
3197         &usbtll_ick,
3198         &mmchs3_ick,
3199         &icr_ick,
3200         &aes2_ick,
3201         &sha12_ick,
3202         &des2_ick,
3203         &mmchs2_ick,
3204         &mmchs1_ick,
3205         &mspro_ick,
3206         &hdq_ick,
3207         &mcspi4_ick,
3208         &mcspi3_ick,
3209         &mcspi2_ick,
3210         &mcspi1_ick,
3211         &i2c3_ick,
3212         &i2c2_ick,
3213         &i2c1_ick,
3214         &uart2_ick,
3215         &uart1_ick,
3216         &gpt11_ick,
3217         &gpt10_ick,
3218         &mcbsp5_ick,
3219         &mcbsp1_ick,
3220         &fac_ick,
3221         &mailboxes_ick,
3222         &omapctrl_ick,
3223         &ssi_l4_ick,
3224         &ssi_ick,
3225         &usb_l4_ick,
3226         &security_l4_ick2,
3227         &aes1_ick,
3228         &rng_ick,
3229         &sha11_ick,
3230         &des1_ick,
3231         &dss1_alwon_fck,
3232         &dss_tv_fck,
3233         &dss_96m_fck,
3234         &dss2_alwon_fck,
3235         &dss_ick,
3236         &cam_mclk,
3237         &cam_ick,
3238         &csi2_96m_fck,
3239         &usbhost_120m_fck,
3240         &usbhost_48m_fck,
3241         &usbhost_ick,
3242         &usim_fck,
3243         &gpt1_fck,
3244         &wkup_32k_fck,
3245         &gpio1_fck,
3246         &wdt2_fck,
3247         &wkup_l4_ick,
3248         &usim_ick,
3249         &wdt2_ick,
3250         &wdt1_ick,
3251         &gpio1_ick,
3252         &omap_32ksync_ick,
3253         &gpt12_ick,
3254         &gpt1_ick,
3255         &per_96m_fck,
3256         &per_48m_fck,
3257         &uart3_fck,
3258         &gpt2_fck,
3259         &gpt3_fck,
3260         &gpt4_fck,
3261         &gpt5_fck,
3262         &gpt6_fck,
3263         &gpt7_fck,
3264         &gpt8_fck,
3265         &gpt9_fck,
3266         &per_32k_alwon_fck,
3267         &gpio6_fck,
3268         &gpio5_fck,
3269         &gpio4_fck,
3270         &gpio3_fck,
3271         &gpio2_fck,
3272         &wdt3_fck,
3273         &per_l4_ick,
3274         &gpio6_ick,
3275         &gpio5_ick,
3276         &gpio4_ick,
3277         &gpio3_ick,
3278         &gpio2_ick,
3279         &wdt3_ick,
3280         &uart3_ick,
3281         &gpt9_ick,
3282         &gpt8_ick,
3283         &gpt7_ick,
3284         &gpt6_ick,
3285         &gpt5_ick,
3286         &gpt4_ick,
3287         &gpt3_ick,
3288         &gpt2_ick,
3289         &mcbsp2_ick,
3290         &mcbsp3_ick,
3291         &mcbsp4_ick,
3292         &mcbsp2_fck,
3293         &mcbsp3_fck,
3294         &mcbsp4_fck,
3295         &emu_src_ck,
3296         &pclk_fck,
3297         &pclkx2_fck,
3298         &atclk_fck,
3299         &traceclk_src_fck,
3300         &traceclk_fck,
3301         &sr1_fck,
3302         &sr2_fck,
3303         &sr_l4_ick,
3304         &secure_32k_fck,
3305         &gpt12_fck,
3306         &wdt1_fck,
3307 };
3308
3309 #endif