2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
32 static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
34 static void omap3_dpll_allow_idle(struct clk *clk);
35 static void omap3_dpll_deny_idle(struct clk *clk);
36 static u32 omap3_dpll_autoidle_read(struct clk *clk);
37 static int omap3_noncore_dpll_enable(struct clk *clk);
38 static void omap3_noncore_dpll_disable(struct clk *clk);
39 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
40 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
42 /* Maximum DPLL multiplier, divider values for OMAP3 */
43 #define OMAP3_MAX_DPLL_MULT 2048
44 #define OMAP3_MAX_DPLL_DIV 128
47 * DPLL1 supplies clock to the MPU.
48 * DPLL2 supplies clock to the IVA2.
49 * DPLL3 supplies CORE domain clocks.
50 * DPLL4 supplies peripheral clocks.
51 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54 /* Forward declarations for DPLL bypass clocks */
55 static struct clk dpll1_fck;
56 static struct clk dpll2_fck;
58 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
59 #define DPLL_LOW_POWER_STOP 0x1
60 #define DPLL_LOW_POWER_BYPASS 0x5
61 #define DPLL_LOCKED 0x7
65 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
66 static struct clk omap_32k_fck = {
67 .name = "omap_32k_fck",
69 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
70 .clkdm = { .name = "prm_clkdm" },
73 static struct clk secure_32k_fck = {
74 .name = "secure_32k_fck",
76 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
77 .clkdm = { .name = "prm_clkdm" },
80 /* Virtual source clocks for osc_sys_ck */
81 static struct clk virt_12m_ck = {
82 .name = "virt_12m_ck",
84 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
85 .clkdm = { .name = "prm_clkdm" },
88 static struct clk virt_13m_ck = {
89 .name = "virt_13m_ck",
91 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
92 .clkdm = { .name = "prm_clkdm" },
95 static struct clk virt_16_8m_ck = {
96 .name = "virt_16_8m_ck",
98 .flags = CLOCK_IN_OMAP3430ES2 | ALWAYS_ENABLED,
99 .clkdm = { .name = "prm_clkdm" },
102 static struct clk virt_19_2m_ck = {
103 .name = "virt_19_2m_ck",
105 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
106 .clkdm = { .name = "prm_clkdm" },
109 static struct clk virt_26m_ck = {
110 .name = "virt_26m_ck",
112 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
113 .clkdm = { .name = "prm_clkdm" },
116 static struct clk virt_38_4m_ck = {
117 .name = "virt_38_4m_ck",
119 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
120 .clkdm = { .name = "prm_clkdm" },
123 static const struct clksel_rate osc_sys_12m_rates[] = {
124 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
128 static const struct clksel_rate osc_sys_13m_rates[] = {
129 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
133 static const struct clksel_rate osc_sys_16_8m_rates[] = {
134 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
138 static const struct clksel_rate osc_sys_19_2m_rates[] = {
139 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
143 static const struct clksel_rate osc_sys_26m_rates[] = {
144 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
148 static const struct clksel_rate osc_sys_38_4m_rates[] = {
149 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
153 static const struct clksel osc_sys_clksel[] = {
154 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
155 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
156 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
157 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
158 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
159 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
163 /* Oscillator clock */
164 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
165 static struct clk osc_sys_ck = {
166 .name = "osc_sys_ck",
167 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
168 .init = &omap2_init_clksel_parent,
169 .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET,
170 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
171 .clksel = osc_sys_clksel,
172 /* REVISIT: deal with autoextclkmode? */
173 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
174 .clkdm = { .name = "prm_clkdm" },
175 .recalc = &omap2_clksel_recalc,
178 static const struct clksel_rate div2_rates[] = {
179 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
180 { .div = 2, .val = 2, .flags = RATE_IN_343X },
184 static const struct clksel sys_clksel[] = {
185 { .parent = &osc_sys_ck, .rates = div2_rates },
189 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
190 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
191 static struct clk sys_ck = {
193 .parent = &osc_sys_ck,
194 .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
195 .init = &omap2_init_clksel_parent,
196 .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
197 .clksel_mask = OMAP_SYSCLKDIV_MASK,
198 .clksel = sys_clksel,
199 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
200 .clkdm = { .name = "prm_clkdm" },
201 .recalc = &omap2_clksel_recalc,
204 static struct clk sys_altclk = {
205 .name = "sys_altclk",
206 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
207 .clkdm = { .name = "cm_clkdm" },
211 * Optional external clock input for some McBSPs
212 * Apparently this is not really in prm_clkdm, but rather is fed into
213 * both CORE and PER separately.
215 static struct clk mcbsp_clks = {
216 .name = "mcbsp_clks",
217 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
218 .clkdm = { .name = "prm_clkdm" },
221 /* PRM EXTERNAL CLOCK OUTPUT */
223 static struct clk sys_clkout1 = {
224 .name = "sys_clkout1",
225 .parent = &osc_sys_ck,
226 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
227 .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
228 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
229 .flags = CLOCK_IN_OMAP343X,
230 .clkdm = { .name = "prm_clkdm" },
231 .recalc = &followparent_recalc,
238 static const struct clksel_rate div16_dpll_rates[] = {
239 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
240 { .div = 2, .val = 2, .flags = RATE_IN_343X },
241 { .div = 3, .val = 3, .flags = RATE_IN_343X },
242 { .div = 4, .val = 4, .flags = RATE_IN_343X },
243 { .div = 5, .val = 5, .flags = RATE_IN_343X },
244 { .div = 6, .val = 6, .flags = RATE_IN_343X },
245 { .div = 7, .val = 7, .flags = RATE_IN_343X },
246 { .div = 8, .val = 8, .flags = RATE_IN_343X },
247 { .div = 9, .val = 9, .flags = RATE_IN_343X },
248 { .div = 10, .val = 10, .flags = RATE_IN_343X },
249 { .div = 11, .val = 11, .flags = RATE_IN_343X },
250 { .div = 12, .val = 12, .flags = RATE_IN_343X },
251 { .div = 13, .val = 13, .flags = RATE_IN_343X },
252 { .div = 14, .val = 14, .flags = RATE_IN_343X },
253 { .div = 15, .val = 15, .flags = RATE_IN_343X },
254 { .div = 16, .val = 16, .flags = RATE_IN_343X },
259 /* MPU clock source */
261 static struct dpll_data dpll1_dd = {
262 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
263 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
264 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
265 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
266 .control_reg = OMAP3430_CM_CLKEN_PLL,
267 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
268 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
269 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
270 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
271 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
272 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
273 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
274 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
275 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
276 .bypass_clk = &dpll1_fck,
277 .max_multiplier = OMAP3_MAX_DPLL_MULT,
279 .max_divider = OMAP3_MAX_DPLL_DIV,
280 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
283 static struct clk dpll1_ck = {
287 .dpll_data = &dpll1_dd,
288 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
289 .round_rate = &omap2_dpll_round_rate,
290 .set_rate = &omap3_noncore_dpll_set_rate,
291 .clkdm = { .name = "dpll1_clkdm" },
292 .recalc = &omap3_dpll_recalc,
296 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
297 * DPLL isn't bypassed.
299 static struct clk dpll1_x2_ck = {
300 .name = "dpll1_x2_ck",
302 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
303 .clkdm = { .name = "dpll1_clkdm" },
304 .recalc = &omap3_clkoutx2_recalc,
307 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
308 static const struct clksel div16_dpll1_x2m2_clksel[] = {
309 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
314 * Does not exist in the TRM - needed to separate the M2 divider from
315 * bypass selection in mpu_ck
317 static struct clk dpll1_x2m2_ck = {
318 .name = "dpll1_x2m2_ck",
319 .parent = &dpll1_x2_ck,
321 .init = &omap2_init_clksel_parent,
322 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
323 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
324 .clksel = div16_dpll1_x2m2_clksel,
325 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
326 .clkdm = { .name = "dpll1_clkdm" },
327 .recalc = &omap2_clksel_recalc,
331 /* IVA2 clock source */
334 static struct dpll_data dpll2_dd = {
335 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
336 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
337 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
338 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
339 .control_reg = OMAP3430_CM_CLKEN_PLL,
340 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
341 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
342 (1 << DPLL_LOW_POWER_BYPASS),
343 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
344 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
345 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
346 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
347 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
348 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
349 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
350 .bypass_clk = &dpll2_fck,
351 .max_multiplier = OMAP3_MAX_DPLL_MULT,
353 .max_divider = OMAP3_MAX_DPLL_DIV,
354 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
357 static struct clk dpll2_ck = {
360 .prcm_mod = OMAP3430_IVA2_MOD,
361 .dpll_data = &dpll2_dd,
362 .flags = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
363 .enable = &omap3_noncore_dpll_enable,
364 .disable = &omap3_noncore_dpll_disable,
365 .round_rate = &omap2_dpll_round_rate,
366 .set_rate = &omap3_noncore_dpll_set_rate,
367 .clkdm = { .name = "dpll2_clkdm" },
368 .recalc = &omap3_dpll_recalc,
371 static const struct clksel div16_dpll2_m2x2_clksel[] = {
372 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
377 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
378 * or CLKOUTX2. CLKOUT seems most plausible.
380 static struct clk dpll2_m2_ck = {
381 .name = "dpll2_m2_ck",
383 .prcm_mod = OMAP3430_IVA2_MOD,
384 .init = &omap2_init_clksel_parent,
385 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
386 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
387 .clksel = div16_dpll2_m2x2_clksel,
388 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
389 .clkdm = { .name = "dpll2_clkdm" },
390 .recalc = &omap2_clksel_recalc,
395 * Source clock for all interfaces and for some device fclks
396 * REVISIT: Also supports fast relock bypass - not included below
398 static struct dpll_data dpll3_dd = {
399 .mult_div1_reg = CM_CLKSEL1,
400 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
401 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
402 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
403 .control_reg = CM_CLKEN,
404 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
405 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
406 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
407 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
408 .autoidle_reg = CM_AUTOIDLE,
409 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
410 .idlest_reg = CM_IDLEST,
411 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
412 .bypass_clk = &sys_ck,
413 .max_multiplier = OMAP3_MAX_DPLL_MULT,
415 .max_divider = OMAP3_MAX_DPLL_DIV,
416 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
419 static struct clk dpll3_ck = {
423 .dpll_data = &dpll3_dd,
424 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
425 .round_rate = &omap2_dpll_round_rate,
426 .clkdm = { .name = "dpll3_clkdm" },
427 .recalc = &omap3_dpll_recalc,
431 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
432 * DPLL isn't bypassed
434 static struct clk dpll3_x2_ck = {
435 .name = "dpll3_x2_ck",
437 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
438 .clkdm = { .name = "dpll3_clkdm" },
439 .recalc = &omap3_clkoutx2_recalc,
442 static const struct clksel_rate div31_dpll3_rates[] = {
443 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
444 { .div = 2, .val = 2, .flags = RATE_IN_343X },
445 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
446 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
447 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
448 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
449 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
450 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
451 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
452 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
453 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
454 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
455 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
456 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
457 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
458 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
459 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
460 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
461 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
462 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
463 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
464 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
465 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
466 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
467 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
468 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
469 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
470 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
471 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
472 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
473 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
477 static const struct clksel div31_dpll3m2_clksel[] = {
478 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
482 /* DPLL3 output M2 - primary control point for CORE speed */
483 static struct clk dpll3_m2_ck = {
484 .name = "dpll3_m2_ck",
487 .init = &omap2_init_clksel_parent,
488 .clksel_reg = CM_CLKSEL1,
489 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
490 .clksel = div31_dpll3m2_clksel,
491 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
492 .clkdm = { .name = "dpll3_clkdm" },
493 .round_rate = &omap2_clksel_round_rate,
494 .set_rate = &omap3_core_dpll_m2_set_rate,
495 .recalc = &omap2_clksel_recalc,
498 static struct clk core_ck = {
500 .parent = &dpll3_m2_ck,
501 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
502 .clkdm = { .name = "cm_clkdm" },
503 .recalc = &followparent_recalc,
506 static struct clk dpll3_m2x2_ck = {
507 .name = "dpll3_m2x2_ck",
508 .parent = &dpll3_x2_ck,
509 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
510 .clkdm = { .name = "dpll3_clkdm" },
511 .recalc = &followparent_recalc,
514 /* The PWRDN bit is apparently only available on 3430ES2 and above */
515 static const struct clksel div16_dpll3_clksel[] = {
516 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
520 /* This virtual clock is the source for dpll3_m3x2_ck */
521 static struct clk dpll3_m3_ck = {
522 .name = "dpll3_m3_ck",
524 .prcm_mod = OMAP3430_EMU_MOD,
525 .init = &omap2_init_clksel_parent,
526 .clksel_reg = CM_CLKSEL1,
527 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
528 .clksel = div16_dpll3_clksel,
529 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
530 .clkdm = { .name = "dpll3_clkdm" },
531 .recalc = &omap2_clksel_recalc,
534 /* The PWRDN bit is apparently only available on 3430ES2 and above */
535 static struct clk dpll3_m3x2_ck = {
536 .name = "dpll3_m3x2_ck",
537 .parent = &dpll3_m3_ck,
539 .enable_reg = CM_CLKEN,
540 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
541 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
542 .clkdm = { .name = "dpll3_clkdm" },
543 .recalc = &omap3_clkoutx2_recalc,
546 static struct clk emu_core_alwon_ck = {
547 .name = "emu_core_alwon_ck",
548 .parent = &dpll3_m3x2_ck,
549 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
550 .clkdm = { .name = "dpll3_clkdm" },
551 .recalc = &followparent_recalc,
555 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
557 static struct dpll_data dpll4_dd = {
558 .mult_div1_reg = CM_CLKSEL2,
559 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
560 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
561 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
562 .control_reg = CM_CLKEN,
563 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
564 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
565 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
566 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
567 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
568 .autoidle_reg = CM_AUTOIDLE,
569 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
570 .idlest_reg = CM_IDLEST,
571 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
572 .bypass_clk = &sys_ck,
573 .max_multiplier = OMAP3_MAX_DPLL_MULT,
575 .max_divider = OMAP3_MAX_DPLL_DIV,
576 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
579 static struct clk dpll4_ck = {
583 .dpll_data = &dpll4_dd,
584 .flags = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
585 .enable = &omap3_noncore_dpll_enable,
586 .disable = &omap3_noncore_dpll_disable,
587 .round_rate = &omap2_dpll_round_rate,
588 .set_rate = &omap3_noncore_dpll_set_rate,
589 .clkdm = { .name = "dpll4_clkdm" },
590 .recalc = &omap3_dpll_recalc,
594 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
595 * DPLL isn't bypassed --
596 * XXX does this serve any downstream clocks?
598 static struct clk dpll4_x2_ck = {
599 .name = "dpll4_x2_ck",
601 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
602 .clkdm = { .name = "dpll4_clkdm" },
603 .recalc = &omap3_clkoutx2_recalc,
606 static const struct clksel div16_dpll4_clksel[] = {
607 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
611 /* This virtual clock is the source for dpll4_m2x2_ck */
612 static struct clk dpll4_m2_ck = {
613 .name = "dpll4_m2_ck",
616 .init = &omap2_init_clksel_parent,
617 .clksel_reg = OMAP3430_CM_CLKSEL3,
618 .clksel_mask = OMAP3430_DIV_96M_MASK,
619 .clksel = div16_dpll4_clksel,
620 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
621 .clkdm = { .name = "dpll4_clkdm" },
622 .recalc = &omap2_clksel_recalc,
625 /* The PWRDN bit is apparently only available on 3430ES2 and above */
626 static struct clk dpll4_m2x2_ck = {
627 .name = "dpll4_m2x2_ck",
628 .parent = &dpll4_m2_ck,
630 .enable_reg = CM_CLKEN,
631 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
632 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
633 .clkdm = { .name = "dpll4_clkdm" },
634 .recalc = &omap3_clkoutx2_recalc,
638 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
639 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
640 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
643 static struct clk omap_96m_alwon_fck = {
644 .name = "omap_96m_alwon_fck",
645 .parent = &dpll4_m2x2_ck,
646 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
647 .clkdm = { .name = "prm_clkdm" },
648 .recalc = &followparent_recalc,
651 static struct clk cm_96m_fck = {
652 .name = "cm_96m_fck",
653 .parent = &omap_96m_alwon_fck,
654 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
655 .clkdm = { .name = "cm_clkdm" },
656 .recalc = &followparent_recalc,
659 static const struct clksel_rate omap_96m_dpll_rates[] = {
660 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
664 static const struct clksel_rate omap_96m_sys_rates[] = {
665 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
669 static const struct clksel omap_96m_fck_clksel[] = {
670 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
671 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
675 static struct clk omap_96m_fck = {
676 .name = "omap_96m_fck",
679 .init = &omap2_init_clksel_parent,
680 .clksel_reg = CM_CLKSEL1,
681 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
682 .clksel = omap_96m_fck_clksel,
683 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
684 .clkdm = { .name = "cm_clkdm" },
685 .recalc = &omap2_clksel_recalc,
688 /* This virtual clock is the source for dpll4_m3x2_ck */
689 static struct clk dpll4_m3_ck = {
690 .name = "dpll4_m3_ck",
692 .prcm_mod = OMAP3430_DSS_MOD,
693 .init = &omap2_init_clksel_parent,
694 .clksel_reg = CM_CLKSEL,
695 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
696 .clksel = div16_dpll4_clksel,
697 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
698 .clkdm = { .name = "dpll4_clkdm" },
699 .recalc = &omap2_clksel_recalc,
702 /* The PWRDN bit is apparently only available on 3430ES2 and above */
703 static struct clk dpll4_m3x2_ck = {
704 .name = "dpll4_m3x2_ck",
705 .parent = &dpll4_m3_ck,
707 .init = &omap2_init_clksel_parent,
708 .enable_reg = CM_CLKEN,
709 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
710 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
711 .clkdm = { .name = "dpll4_clkdm" },
712 .recalc = &omap3_clkoutx2_recalc,
715 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
716 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
720 static const struct clksel_rate omap_54m_alt_rates[] = {
721 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
725 static const struct clksel omap_54m_clksel[] = {
726 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
727 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
731 static struct clk omap_54m_fck = {
732 .name = "omap_54m_fck",
734 .init = &omap2_init_clksel_parent,
735 .clksel_reg = CM_CLKSEL1,
736 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
737 .clksel = omap_54m_clksel,
738 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
739 .clkdm = { .name = "cm_clkdm" },
740 .recalc = &omap2_clksel_recalc,
743 static const struct clksel_rate omap_48m_cm96m_rates[] = {
744 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
748 static const struct clksel_rate omap_48m_alt_rates[] = {
749 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
753 static const struct clksel omap_48m_clksel[] = {
754 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
755 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
759 static struct clk omap_48m_fck = {
760 .name = "omap_48m_fck",
762 .init = &omap2_init_clksel_parent,
763 .clksel_reg = CM_CLKSEL1,
764 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
765 .clksel = omap_48m_clksel,
766 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
767 .clkdm = { .name = "cm_clkdm" },
768 .recalc = &omap2_clksel_recalc,
771 static struct clk omap_12m_fck = {
772 .name = "omap_12m_fck",
773 .parent = &omap_48m_fck,
775 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
776 .clkdm = { .name = "cm_clkdm" },
777 .recalc = &omap2_fixed_divisor_recalc,
780 /* This virstual clock is the source for dpll4_m4x2_ck */
781 static struct clk dpll4_m4_ck = {
782 .name = "dpll4_m4_ck",
784 .prcm_mod = OMAP3430_DSS_MOD,
785 .init = &omap2_init_clksel_parent,
786 .clksel_reg = CM_CLKSEL,
787 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
788 .clksel = div16_dpll4_clksel,
789 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
790 .clkdm = { .name = "dpll4_clkdm" },
791 .recalc = &omap2_clksel_recalc,
792 .set_rate = &omap2_clksel_set_rate,
793 .round_rate = &omap2_clksel_round_rate,
796 /* The PWRDN bit is apparently only available on 3430ES2 and above */
797 static struct clk dpll4_m4x2_ck = {
798 .name = "dpll4_m4x2_ck",
799 .parent = &dpll4_m4_ck,
801 .enable_reg = CM_CLKEN,
802 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
803 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
804 .clkdm = { .name = "dpll4_clkdm" },
805 .recalc = &omap3_clkoutx2_recalc,
808 /* This virtual clock is the source for dpll4_m5x2_ck */
809 static struct clk dpll4_m5_ck = {
810 .name = "dpll4_m5_ck",
812 .prcm_mod = OMAP3430_CAM_MOD,
813 .init = &omap2_init_clksel_parent,
814 .clksel_reg = CM_CLKSEL,
815 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
816 .clksel = div16_dpll4_clksel,
817 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
818 .clkdm = { .name = "dpll4_clkdm" },
819 .recalc = &omap2_clksel_recalc,
822 /* The PWRDN bit is apparently only available on 3430ES2 and above */
823 static struct clk dpll4_m5x2_ck = {
824 .name = "dpll4_m5x2_ck",
825 .parent = &dpll4_m5_ck,
827 .enable_reg = CM_CLKEN,
828 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
829 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
830 .clkdm = { .name = "dpll4_clkdm" },
831 .recalc = &omap3_clkoutx2_recalc,
834 /* This virtual clock is the source for dpll4_m6x2_ck */
835 static struct clk dpll4_m6_ck = {
836 .name = "dpll4_m6_ck",
838 .prcm_mod = OMAP3430_EMU_MOD,
839 .init = &omap2_init_clksel_parent,
840 .clksel_reg = CM_CLKSEL1,
841 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
842 .clksel = div16_dpll4_clksel,
843 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
844 .clkdm = { .name = "dpll4_clkdm" },
845 .recalc = &omap2_clksel_recalc,
848 /* The PWRDN bit is apparently only available on 3430ES2 and above */
849 static struct clk dpll4_m6x2_ck = {
850 .name = "dpll4_m6x2_ck",
851 .parent = &dpll4_m6_ck,
853 .init = &omap2_init_clksel_parent,
854 .enable_reg = CM_CLKEN,
855 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
856 .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
857 .clkdm = { .name = "dpll4_clkdm" },
858 .recalc = &omap3_clkoutx2_recalc,
861 static struct clk emu_per_alwon_ck = {
862 .name = "emu_per_alwon_ck",
863 .parent = &dpll4_m6x2_ck,
864 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
865 .clkdm = { .name = "dpll4_clkdm" },
866 .recalc = &followparent_recalc,
870 /* Supplies 120MHz clock, USIM source clock */
873 static struct dpll_data dpll5_dd = {
874 .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4,
875 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
876 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
877 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
878 .control_reg = OMAP3430ES2_CM_CLKEN2,
879 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
880 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
881 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
882 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
883 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
884 .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL,
885 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
886 .idlest_reg = CM_IDLEST2,
887 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
888 .bypass_clk = &sys_ck,
889 .max_multiplier = OMAP3_MAX_DPLL_MULT,
891 .max_divider = OMAP3_MAX_DPLL_DIV,
892 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
895 static struct clk dpll5_ck = {
899 .dpll_data = &dpll5_dd,
900 .flags = CLOCK_IN_OMAP3430ES2 | RECALC_ON_ENABLE,
901 .enable = &omap3_noncore_dpll_enable,
902 .disable = &omap3_noncore_dpll_disable,
903 .round_rate = &omap2_dpll_round_rate,
904 .set_rate = &omap3_noncore_dpll_set_rate,
905 .clkdm = { .name = "dpll5_clkdm" },
906 .recalc = &omap3_dpll_recalc,
909 static const struct clksel div16_dpll5_clksel[] = {
910 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
914 static struct clk dpll5_m2_ck = {
915 .name = "dpll5_m2_ck",
918 .init = &omap2_init_clksel_parent,
919 .clksel_reg = OMAP3430ES2_CM_CLKSEL5,
920 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
921 .clksel = div16_dpll5_clksel,
922 .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
923 .clkdm = { .name = "dpll5_clkdm" },
924 .recalc = &omap2_clksel_recalc,
927 /* CM EXTERNAL CLOCK OUTPUTS */
929 static const struct clksel_rate clkout2_src_core_rates[] = {
930 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
934 static const struct clksel_rate clkout2_src_sys_rates[] = {
935 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
939 static const struct clksel_rate clkout2_src_96m_rates[] = {
940 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
944 static const struct clksel_rate clkout2_src_54m_rates[] = {
945 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
949 static const struct clksel clkout2_src_clksel[] = {
950 { .parent = &core_ck, .rates = clkout2_src_core_rates },
951 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
952 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
953 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
957 static struct clk clkout2_src_ck = {
958 .name = "clkout2_src_ck",
959 .prcm_mod = OMAP3430_CCR_MOD,
960 .init = &omap2_init_clksel_parent,
961 .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
962 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
963 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
964 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
965 .clksel = clkout2_src_clksel,
966 .flags = CLOCK_IN_OMAP343X,
967 .clkdm = { .name = "cm_clkdm" },
968 .recalc = &omap2_clksel_recalc,
971 static const struct clksel_rate sys_clkout2_rates[] = {
972 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
973 { .div = 2, .val = 1, .flags = RATE_IN_343X },
974 { .div = 4, .val = 2, .flags = RATE_IN_343X },
975 { .div = 8, .val = 3, .flags = RATE_IN_343X },
976 { .div = 16, .val = 4, .flags = RATE_IN_343X },
980 static const struct clksel sys_clkout2_clksel[] = {
981 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
985 static struct clk sys_clkout2 = {
986 .name = "sys_clkout2",
987 .prcm_mod = OMAP3430_CCR_MOD,
988 .init = &omap2_init_clksel_parent,
989 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
990 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
991 .clksel = sys_clkout2_clksel,
992 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
993 .clkdm = { .name = "cm_clkdm" },
994 .recalc = &omap2_clksel_recalc,
997 /* CM OUTPUT CLOCKS */
999 static struct clk corex2_fck = {
1000 .name = "corex2_fck",
1001 .parent = &dpll3_m2x2_ck,
1002 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1003 .clkdm = { .name = "cm_clkdm" },
1004 .recalc = &followparent_recalc,
1007 /* DPLL power domain clock controls */
1009 static const struct clksel_rate div4_rates[] = {
1010 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1011 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1012 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1016 static const struct clksel div4_core_clksel[] = {
1017 { .parent = &core_ck, .rates = div4_rates },
1021 static struct clk dpll1_fck = {
1022 .name = "dpll1_fck",
1024 .prcm_mod = MPU_MOD,
1025 .init = &omap2_init_clksel_parent,
1026 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1027 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1028 .clksel = div4_core_clksel,
1029 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1030 .clkdm = { .name = "cm_clkdm" },
1031 .recalc = &omap2_clksel_recalc,
1034 static struct clk mpu_ck = {
1036 .parent = &dpll1_x2m2_ck,
1037 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1038 .clkdm = { .name = "mpu_clkdm" },
1039 .recalc = &followparent_recalc,
1042 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1043 static const struct clksel_rate arm_fck_rates[] = {
1044 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1045 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1049 static const struct clksel arm_fck_clksel[] = {
1050 { .parent = &mpu_ck, .rates = arm_fck_rates },
1054 static struct clk arm_fck = {
1057 .prcm_mod = MPU_MOD,
1058 .init = &omap2_init_clksel_parent,
1059 .clksel_reg = OMAP3430_CM_IDLEST_PLL,
1060 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1061 .clksel = arm_fck_clksel,
1062 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1063 .clkdm = { .name = "mpu_clkdm" },
1064 .recalc = &omap2_clksel_recalc,
1067 /* XXX What about neon_clkdm ? */
1070 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1071 * although it is referenced - so this is a guess
1073 static struct clk emu_mpu_alwon_ck = {
1074 .name = "emu_mpu_alwon_ck",
1076 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1077 .clkdm = { .name = "mpu_clkdm" },
1078 .recalc = &followparent_recalc,
1081 static struct clk dpll2_fck = {
1082 .name = "dpll2_fck",
1084 .prcm_mod = OMAP3430_IVA2_MOD,
1085 .init = &omap2_init_clksel_parent,
1086 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1087 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1088 .clksel = div4_core_clksel,
1089 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1090 .clkdm = { .name = "cm_clkdm" },
1091 .recalc = &omap2_clksel_recalc,
1094 static struct clk iva2_ck = {
1096 .parent = &dpll2_m2_ck,
1097 .prcm_mod = OMAP3430_IVA2_MOD,
1098 .init = &omap2_init_clksel_parent,
1099 .enable_reg = CM_FCLKEN,
1100 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1101 .flags = CLOCK_IN_OMAP343X,
1102 .clkdm = { .name = "iva2_clkdm" },
1103 .recalc = &followparent_recalc,
1106 /* Common interface clocks */
1108 static const struct clksel div2_core_clksel[] = {
1109 { .parent = &core_ck, .rates = div2_rates },
1113 static struct clk l3_ick = {
1116 .prcm_mod = CORE_MOD,
1117 .init = &omap2_init_clksel_parent,
1118 .clksel_reg = CM_CLKSEL,
1119 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1120 .clksel = div2_core_clksel,
1121 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1122 .clkdm = { .name = "core_l3_clkdm" },
1123 .recalc = &omap2_clksel_recalc,
1126 static const struct clksel div2_l3_clksel[] = {
1127 { .parent = &l3_ick, .rates = div2_rates },
1131 static struct clk l4_ick = {
1134 .prcm_mod = CORE_MOD,
1135 .init = &omap2_init_clksel_parent,
1136 .clksel_reg = CM_CLKSEL,
1137 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1138 .clksel = div2_l3_clksel,
1139 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1140 .clkdm = { .name = "core_l4_clkdm" },
1141 .recalc = &omap2_clksel_recalc,
1145 static const struct clksel div2_l4_clksel[] = {
1146 { .parent = &l4_ick, .rates = div2_rates },
1150 static struct clk rm_ick = {
1153 .prcm_mod = WKUP_MOD,
1154 .init = &omap2_init_clksel_parent,
1155 .clksel_reg = CM_CLKSEL,
1156 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1157 .clksel = div2_l4_clksel,
1158 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1159 .clkdm = { .name = "cm_clkdm" },
1160 .recalc = &omap2_clksel_recalc,
1163 /* GFX power domain */
1165 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1167 static const struct clksel gfx_l3_clksel[] = {
1168 { .parent = &l3_ick, .rates = gfx_l3_rates },
1172 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1173 static struct clk gfx_l3_ck = {
1174 .name = "gfx_l3_ck",
1176 .prcm_mod = GFX_MOD,
1177 .init = &omap2_init_clksel_parent,
1178 .enable_reg = CM_ICLKEN,
1179 .enable_bit = OMAP_EN_GFX_SHIFT,
1180 .flags = CLOCK_IN_OMAP3430ES1,
1181 .clkdm = { .name = "gfx_3430es1_clkdm" },
1182 .recalc = &followparent_recalc,
1185 static struct clk gfx_l3_fck = {
1186 .name = "gfx_l3_fck",
1187 .parent = &gfx_l3_ck,
1188 .prcm_mod = GFX_MOD,
1189 .init = &omap2_init_clksel_parent,
1190 .clksel_reg = CM_CLKSEL,
1191 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1192 .clksel = gfx_l3_clksel,
1193 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1194 .clkdm = { .name = "gfx_3430es1_clkdm" },
1195 .recalc = &omap2_clksel_recalc,
1198 static struct clk gfx_l3_ick = {
1199 .name = "gfx_l3_ick",
1200 .parent = &gfx_l3_ck,
1201 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1202 .clkdm = { .name = "gfx_3430es1_clkdm" },
1203 .recalc = &followparent_recalc,
1206 static struct clk gfx_cg1_ck = {
1207 .name = "gfx_cg1_ck",
1208 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1209 .prcm_mod = GFX_MOD,
1210 .enable_reg = CM_FCLKEN,
1211 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1212 .flags = CLOCK_IN_OMAP3430ES1,
1213 .clkdm = { .name = "gfx_3430es1_clkdm" },
1214 .recalc = &followparent_recalc,
1217 static struct clk gfx_cg2_ck = {
1218 .name = "gfx_cg2_ck",
1219 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1220 .prcm_mod = GFX_MOD,
1221 .enable_reg = CM_FCLKEN,
1222 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1223 .flags = CLOCK_IN_OMAP3430ES1,
1224 .clkdm = { .name = "gfx_3430es1_clkdm" },
1225 .recalc = &followparent_recalc,
1228 /* SGX power domain - 3430ES2 only */
1230 static const struct clksel_rate sgx_core_rates[] = {
1231 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1232 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1233 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1237 static const struct clksel_rate sgx_96m_rates[] = {
1238 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1242 static const struct clksel sgx_clksel[] = {
1243 { .parent = &core_ck, .rates = sgx_core_rates },
1244 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1248 static struct clk sgx_fck = {
1250 .init = &omap2_init_clksel_parent,
1251 .prcm_mod = OMAP3430ES2_SGX_MOD,
1252 .enable_reg = CM_FCLKEN,
1253 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1254 .clksel_reg = CM_CLKSEL,
1255 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1256 .clksel = sgx_clksel,
1257 .flags = CLOCK_IN_OMAP3430ES2,
1258 .clkdm = { .name = "sgx_clkdm" },
1259 .recalc = &omap2_clksel_recalc,
1262 static struct clk sgx_ick = {
1265 .prcm_mod = OMAP3430ES2_SGX_MOD,
1266 .enable_reg = CM_ICLKEN,
1267 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1268 .flags = CLOCK_IN_OMAP3430ES2,
1269 .clkdm = { .name = "sgx_clkdm" },
1270 .recalc = &followparent_recalc,
1273 /* CORE power domain */
1275 static struct clk d2d_26m_fck = {
1276 .name = "d2d_26m_fck",
1278 .prcm_mod = CORE_MOD,
1279 .enable_reg = CM_FCLKEN1,
1280 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1281 .flags = CLOCK_IN_OMAP3430ES1,
1282 .clkdm = { .name = "d2d_clkdm" },
1283 .recalc = &followparent_recalc,
1286 static const struct clksel omap343x_gpt_clksel[] = {
1287 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1288 { .parent = &sys_ck, .rates = gpt_sys_rates },
1292 static struct clk gpt10_fck = {
1293 .name = "gpt10_fck",
1295 .prcm_mod = CORE_MOD,
1296 .init = &omap2_init_clksel_parent,
1297 .enable_reg = CM_FCLKEN1,
1298 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1299 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
1300 .clksel_reg = CM_CLKSEL,
1301 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1302 .clksel = omap343x_gpt_clksel,
1303 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1304 .clkdm = { .name = "core_l4_clkdm" },
1305 .recalc = &omap2_clksel_recalc,
1308 static struct clk gpt11_fck = {
1309 .name = "gpt11_fck",
1311 .prcm_mod = CORE_MOD,
1312 .init = &omap2_init_clksel_parent,
1313 .enable_reg = CM_FCLKEN1,
1314 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1315 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
1316 .clksel_reg = CM_CLKSEL,
1317 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1318 .clksel = omap343x_gpt_clksel,
1319 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1320 .clkdm = { .name = "core_l4_clkdm" },
1321 .recalc = &omap2_clksel_recalc,
1324 static struct clk cpefuse_fck = {
1325 .name = "cpefuse_fck",
1327 .prcm_mod = CORE_MOD,
1328 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1329 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1330 .idlest_bit = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1331 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1332 .clkdm = { .name = "cm_clkdm" },
1333 .recalc = &followparent_recalc,
1336 static struct clk ts_fck = {
1338 .parent = &omap_32k_fck,
1339 .prcm_mod = CORE_MOD,
1340 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1341 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1342 .flags = CLOCK_IN_OMAP3430ES2,
1343 .clkdm = { .name = "core_l4_clkdm" },
1344 .recalc = &followparent_recalc,
1347 static struct clk usbtll_fck = {
1348 .name = "usbtll_fck",
1349 .parent = &dpll5_m2_ck,
1350 .prcm_mod = CORE_MOD,
1351 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1352 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1353 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1354 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1355 .clkdm = { .name = "core_l4_clkdm" },
1356 .recalc = &followparent_recalc,
1359 /* CORE 96M FCLK-derived clocks */
1361 static struct clk core_96m_fck = {
1362 .name = "core_96m_fck",
1363 .parent = &omap_96m_fck,
1364 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1365 .clkdm = { .name = "core_l4_clkdm" },
1366 .recalc = &followparent_recalc,
1369 static struct clk mmchs3_fck = {
1370 .name = "mmchs_fck",
1372 .parent = &core_96m_fck,
1373 .prcm_mod = CORE_MOD,
1374 .enable_reg = CM_FCLKEN1,
1375 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1376 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1377 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1378 .clkdm = { .name = "core_l4_clkdm" },
1379 .recalc = &followparent_recalc,
1382 static struct clk mmchs2_fck = {
1383 .name = "mmchs_fck",
1385 .parent = &core_96m_fck,
1386 .prcm_mod = CORE_MOD,
1387 .enable_reg = CM_FCLKEN1,
1388 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1389 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1390 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1391 .clkdm = { .name = "core_l4_clkdm" },
1392 .recalc = &followparent_recalc,
1395 static struct clk mspro_fck = {
1396 .name = "mspro_fck",
1397 .parent = &core_96m_fck,
1398 .prcm_mod = CORE_MOD,
1399 .enable_reg = CM_FCLKEN1,
1400 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1401 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1402 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1403 .clkdm = { .name = "core_l4_clkdm" },
1404 .recalc = &followparent_recalc,
1407 static struct clk mmchs1_fck = {
1408 .name = "mmchs_fck",
1409 .parent = &core_96m_fck,
1410 .prcm_mod = CORE_MOD,
1411 .enable_reg = CM_FCLKEN1,
1412 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1413 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1414 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1415 .clkdm = { .name = "core_l4_clkdm" },
1416 .recalc = &followparent_recalc,
1419 static struct clk i2c3_fck = {
1422 .parent = &core_96m_fck,
1423 .prcm_mod = CORE_MOD,
1424 .enable_reg = CM_FCLKEN1,
1425 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1426 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
1427 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1428 .clkdm = { .name = "core_l4_clkdm" },
1429 .recalc = &followparent_recalc,
1432 static struct clk i2c2_fck = {
1435 .parent = &core_96m_fck,
1436 .prcm_mod = CORE_MOD,
1437 .enable_reg = CM_FCLKEN1,
1438 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1439 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
1440 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1441 .clkdm = { .name = "core_l4_clkdm" },
1442 .recalc = &followparent_recalc,
1445 static struct clk i2c1_fck = {
1448 .parent = &core_96m_fck,
1449 .prcm_mod = CORE_MOD,
1450 .enable_reg = CM_FCLKEN1,
1451 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1452 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
1453 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1454 .clkdm = { .name = "core_l4_clkdm" },
1455 .recalc = &followparent_recalc,
1459 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1460 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1462 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1463 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1467 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1468 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1472 static const struct clksel mcbsp_15_clksel[] = {
1473 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1474 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1478 static struct clk mcbsp5_src_fck = {
1479 .name = "mcbsp_src_fck",
1481 .prcm_mod = CLK_REG_IN_SCM,
1482 .init = &omap2_init_clksel_parent,
1483 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
1484 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1485 .clksel = mcbsp_15_clksel,
1486 .flags = CLOCK_IN_OMAP343X,
1487 .clkdm = { .name = "core_l4_clkdm" },
1488 .recalc = &omap2_clksel_recalc,
1491 static struct clk mcbsp5_fck = {
1492 .name = "mcbsp_fck",
1494 .parent = &mcbsp5_src_fck,
1495 .prcm_mod = CORE_MOD,
1496 .enable_reg = CM_FCLKEN1,
1497 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1498 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
1499 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1500 .clkdm = { .name = "core_l4_clkdm" },
1501 .recalc = &followparent_recalc,
1504 static struct clk mcbsp1_src_fck = {
1505 .name = "mcbsp_src_fck",
1507 .prcm_mod = CLK_REG_IN_SCM,
1508 .init = &omap2_init_clksel_parent,
1509 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
1510 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1511 .clksel = mcbsp_15_clksel,
1512 .flags = CLOCK_IN_OMAP343X,
1513 .clkdm = { .name = "core_l4_clkdm" },
1514 .recalc = &omap2_clksel_recalc,
1517 static struct clk mcbsp1_fck = {
1518 .name = "mcbsp_fck",
1520 .parent = &mcbsp1_src_fck,
1521 .prcm_mod = CORE_MOD,
1522 .enable_reg = CM_FCLKEN1,
1523 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1524 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
1525 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1526 .clkdm = { .name = "core_l4_clkdm" },
1527 .recalc = &followparent_recalc,
1530 /* CORE_48M_FCK-derived clocks */
1532 static struct clk core_48m_fck = {
1533 .name = "core_48m_fck",
1534 .parent = &omap_48m_fck,
1535 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1536 .clkdm = { .name = "core_l4_clkdm" },
1537 .recalc = &followparent_recalc,
1540 static struct clk mcspi4_fck = {
1541 .name = "mcspi_fck",
1543 .parent = &core_48m_fck,
1544 .prcm_mod = CORE_MOD,
1545 .enable_reg = CM_FCLKEN1,
1546 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1547 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1548 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1549 .clkdm = { .name = "core_l4_clkdm" },
1550 .recalc = &followparent_recalc,
1553 static struct clk mcspi3_fck = {
1554 .name = "mcspi_fck",
1556 .parent = &core_48m_fck,
1557 .prcm_mod = CORE_MOD,
1558 .enable_reg = CM_FCLKEN1,
1559 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1560 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
1561 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1562 .clkdm = { .name = "core_l4_clkdm" },
1563 .recalc = &followparent_recalc,
1566 static struct clk mcspi2_fck = {
1567 .name = "mcspi_fck",
1569 .parent = &core_48m_fck,
1570 .prcm_mod = CORE_MOD,
1571 .enable_reg = CM_FCLKEN1,
1572 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1573 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
1574 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1575 .clkdm = { .name = "core_l4_clkdm" },
1576 .recalc = &followparent_recalc,
1579 static struct clk mcspi1_fck = {
1580 .name = "mcspi_fck",
1582 .parent = &core_48m_fck,
1583 .prcm_mod = CORE_MOD,
1584 .enable_reg = CM_FCLKEN1,
1585 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1586 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
1587 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1588 .clkdm = { .name = "core_l4_clkdm" },
1589 .recalc = &followparent_recalc,
1592 static struct clk uart2_fck = {
1593 .name = "uart2_fck",
1594 .parent = &core_48m_fck,
1595 .prcm_mod = CORE_MOD,
1596 .enable_reg = CM_FCLKEN1,
1597 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1598 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
1599 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1600 .clkdm = { .name = "core_l4_clkdm" },
1601 .recalc = &followparent_recalc,
1604 static struct clk uart1_fck = {
1605 .name = "uart1_fck",
1606 .parent = &core_48m_fck,
1607 .prcm_mod = CORE_MOD,
1608 .enable_reg = CM_FCLKEN1,
1609 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1610 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
1611 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1612 .clkdm = { .name = "core_l4_clkdm" },
1613 .recalc = &followparent_recalc,
1616 /* XXX doublecheck: is this idle or standby? */
1617 static struct clk fshostusb_fck = {
1618 .name = "fshostusb_fck",
1619 .parent = &core_48m_fck,
1620 .prcm_mod = CORE_MOD,
1621 .enable_reg = CM_FCLKEN1,
1622 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1623 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1624 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1625 .clkdm = { .name = "core_l4_clkdm" },
1626 .recalc = &followparent_recalc,
1629 /* CORE_12M_FCK based clocks */
1631 static struct clk core_12m_fck = {
1632 .name = "core_12m_fck",
1633 .parent = &omap_12m_fck,
1634 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1635 .clkdm = { .name = "core_l4_clkdm" },
1636 .recalc = &followparent_recalc,
1639 static struct clk hdq_fck = {
1641 .parent = &core_12m_fck,
1642 .prcm_mod = CORE_MOD,
1643 .enable_reg = CM_FCLKEN1,
1644 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1645 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1646 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1647 .clkdm = { .name = "core_l4_clkdm" },
1648 .recalc = &followparent_recalc,
1651 /* DPLL3-derived clock */
1653 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1654 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1655 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1656 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1657 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1658 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1659 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1663 static const struct clksel ssi_ssr_clksel[] = {
1664 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1668 static struct clk ssi_ssr_fck_3430es1 = {
1669 .name = "ssi_ssr_fck",
1670 .init = &omap2_init_clksel_parent,
1671 .prcm_mod = CORE_MOD,
1672 .enable_reg = CM_FCLKEN1,
1673 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1674 .clksel_reg = CM_CLKSEL,
1675 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1676 .clksel = ssi_ssr_clksel,
1677 .flags = CLOCK_IN_OMAP3430ES1,
1678 .clkdm = { .name = "core_l4_clkdm" },
1679 .recalc = &omap2_clksel_recalc,
1682 static struct clk ssi_ssr_fck_3430es2 = {
1683 .name = "ssi_ssr_fck",
1684 .init = &omap2_init_clksel_parent,
1685 .prcm_mod = CORE_MOD,
1686 .enable_reg = CM_FCLKEN1,
1687 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1688 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1689 .clksel_reg = CM_CLKSEL,
1690 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1691 .clksel = ssi_ssr_clksel,
1692 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1693 .clkdm = { .name = "core_l4_clkdm" },
1694 .recalc = &omap2_clksel_recalc,
1697 /* It's unfortunate that we need to duplicate this clock. */
1698 static struct clk ssi_sst_fck_3430es1 = {
1699 .name = "ssi_sst_fck",
1700 .parent = &ssi_ssr_fck_3430es1,
1702 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1703 .clkdm = { .name = "core_l4_clkdm" },
1704 .recalc = &omap2_fixed_divisor_recalc,
1707 static struct clk ssi_sst_fck_3430es2 = {
1708 .name = "ssi_sst_fck",
1709 .parent = &ssi_ssr_fck_3430es2,
1711 .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1712 .clkdm = { .name = "core_l4_clkdm" },
1713 .recalc = &omap2_fixed_divisor_recalc,
1718 /* CORE_L3_ICK based clocks */
1721 * XXX must add clk_enable/clk_disable for these if standard code won't
1724 static struct clk core_l3_ick = {
1725 .name = "core_l3_ick",
1727 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1728 .clkdm = { .name = "core_l3_clkdm" },
1729 .recalc = &followparent_recalc,
1732 static struct clk hsotgusb_ick_3430es1 = {
1733 .name = "hsotgusb_ick",
1734 .parent = &core_l3_ick,
1735 .prcm_mod = CORE_MOD,
1736 .enable_reg = CM_ICLKEN1,
1737 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1738 .flags = CLOCK_IN_OMAP3430ES1,
1739 .clkdm = { .name = "core_l3_clkdm" },
1740 .recalc = &followparent_recalc,
1743 static struct clk hsotgusb_ick_3430es2 = {
1744 .name = "hsotgusb_ick",
1745 .parent = &core_l3_ick,
1746 .prcm_mod = CORE_MOD,
1747 .enable_reg = CM_ICLKEN1,
1748 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1749 .idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1750 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1751 .clkdm = { .name = "core_l3_clkdm" },
1752 .recalc = &followparent_recalc,
1755 static struct clk sdrc_ick = {
1757 .parent = &core_l3_ick,
1758 .prcm_mod = CORE_MOD,
1759 .enable_reg = CM_ICLKEN1,
1760 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1761 .idlest_bit = OMAP3430_ST_SDRC_SHIFT,
1762 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1763 .clkdm = { .name = "core_l3_clkdm" },
1764 .recalc = &followparent_recalc,
1767 static struct clk gpmc_fck = {
1769 .parent = &core_l3_ick,
1770 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1772 .clkdm = { .name = "core_l3_clkdm" },
1773 .recalc = &followparent_recalc,
1776 /* SECURITY_L3_ICK based clocks */
1778 static struct clk security_l3_ick = {
1779 .name = "security_l3_ick",
1781 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1782 .clkdm = { .name = "core_l3_clkdm" },
1783 .recalc = &followparent_recalc,
1786 static struct clk pka_ick = {
1788 .parent = &security_l3_ick,
1789 .prcm_mod = CORE_MOD,
1790 .enable_reg = CM_ICLKEN2,
1791 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1792 .idlest_bit = OMAP3430_ST_PKA_SHIFT,
1793 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1794 .clkdm = { .name = "core_l3_clkdm" },
1795 .recalc = &followparent_recalc,
1798 /* CORE_L4_ICK based clocks */
1800 static struct clk core_l4_ick = {
1801 .name = "core_l4_ick",
1803 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1804 .clkdm = { .name = "core_l4_clkdm" },
1805 .recalc = &followparent_recalc,
1808 static struct clk usbtll_ick = {
1809 .name = "usbtll_ick",
1810 .parent = &core_l4_ick,
1811 .prcm_mod = CORE_MOD,
1812 .enable_reg = CM_ICLKEN3,
1813 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1814 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1815 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1816 .clkdm = { .name = "core_l4_clkdm" },
1817 .recalc = &followparent_recalc,
1820 static struct clk mmchs3_ick = {
1821 .name = "mmchs_ick",
1823 .parent = &core_l4_ick,
1824 .prcm_mod = CORE_MOD,
1825 .enable_reg = CM_ICLKEN1,
1826 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1827 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1828 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1829 .clkdm = { .name = "core_l4_clkdm" },
1830 .recalc = &followparent_recalc,
1833 /* Intersystem Communication Registers - chassis mode only */
1834 static struct clk icr_ick = {
1836 .parent = &core_l4_ick,
1837 .prcm_mod = CORE_MOD,
1838 .enable_reg = CM_ICLKEN1,
1839 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1840 .idlest_bit = OMAP3430_ST_ICR_SHIFT,
1841 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1842 .clkdm = { .name = "core_l4_clkdm" },
1843 .recalc = &followparent_recalc,
1846 static struct clk aes2_ick = {
1848 .parent = &core_l4_ick,
1849 .prcm_mod = CORE_MOD,
1850 .enable_reg = CM_ICLKEN1,
1851 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1852 .idlest_bit = OMAP3430_ST_AES2_SHIFT,
1853 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1854 .clkdm = { .name = "core_l4_clkdm" },
1855 .recalc = &followparent_recalc,
1858 static struct clk sha12_ick = {
1859 .name = "sha12_ick",
1860 .parent = &core_l4_ick,
1861 .prcm_mod = CORE_MOD,
1862 .enable_reg = CM_ICLKEN1,
1863 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1864 .idlest_bit = OMAP3430_ST_SHA12_SHIFT,
1865 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1866 .clkdm = { .name = "core_l4_clkdm" },
1867 .recalc = &followparent_recalc,
1870 static struct clk des2_ick = {
1872 .parent = &core_l4_ick,
1873 .prcm_mod = CORE_MOD,
1874 .enable_reg = CM_ICLKEN1,
1875 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1876 .idlest_bit = OMAP3430_ST_DES2_SHIFT,
1877 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1878 .clkdm = { .name = "core_l4_clkdm" },
1879 .recalc = &followparent_recalc,
1882 static struct clk mmchs2_ick = {
1883 .name = "mmchs_ick",
1885 .parent = &core_l4_ick,
1886 .prcm_mod = CORE_MOD,
1887 .enable_reg = CM_ICLKEN1,
1888 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1889 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1890 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1891 .clkdm = { .name = "core_l4_clkdm" },
1892 .recalc = &followparent_recalc,
1895 static struct clk mmchs1_ick = {
1896 .name = "mmchs_ick",
1897 .parent = &core_l4_ick,
1898 .prcm_mod = CORE_MOD,
1899 .enable_reg = CM_ICLKEN1,
1900 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1901 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1902 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1903 .clkdm = { .name = "core_l4_clkdm" },
1904 .recalc = &followparent_recalc,
1907 static struct clk mspro_ick = {
1908 .name = "mspro_ick",
1909 .parent = &core_l4_ick,
1910 .prcm_mod = CORE_MOD,
1911 .enable_reg = CM_ICLKEN1,
1912 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1913 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1914 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1915 .clkdm = { .name = "core_l4_clkdm" },
1916 .recalc = &followparent_recalc,
1919 static struct clk hdq_ick = {
1921 .parent = &core_l4_ick,
1922 .prcm_mod = CORE_MOD,
1923 .enable_reg = CM_ICLKEN1,
1924 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1925 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1926 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1927 .clkdm = { .name = "core_l4_clkdm" },
1928 .recalc = &followparent_recalc,
1931 static struct clk mcspi4_ick = {
1932 .name = "mcspi_ick",
1934 .parent = &core_l4_ick,
1935 .prcm_mod = CORE_MOD,
1936 .enable_reg = CM_ICLKEN1,
1937 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1938 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1939 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1940 .clkdm = { .name = "core_l4_clkdm" },
1941 .recalc = &followparent_recalc,
1944 static struct clk mcspi3_ick = {
1945 .name = "mcspi_ick",
1947 .parent = &core_l4_ick,
1948 .prcm_mod = CORE_MOD,
1949 .enable_reg = CM_ICLKEN1,
1950 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1951 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
1952 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1953 .clkdm = { .name = "core_l4_clkdm" },
1954 .recalc = &followparent_recalc,
1957 static struct clk mcspi2_ick = {
1958 .name = "mcspi_ick",
1960 .parent = &core_l4_ick,
1961 .prcm_mod = CORE_MOD,
1962 .enable_reg = CM_ICLKEN1,
1963 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1964 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
1965 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1966 .clkdm = { .name = "core_l4_clkdm" },
1967 .recalc = &followparent_recalc,
1970 static struct clk mcspi1_ick = {
1971 .name = "mcspi_ick",
1973 .parent = &core_l4_ick,
1974 .prcm_mod = CORE_MOD,
1975 .enable_reg = CM_ICLKEN1,
1976 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1977 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
1978 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1979 .clkdm = { .name = "core_l4_clkdm" },
1980 .recalc = &followparent_recalc,
1983 static struct clk i2c3_ick = {
1986 .parent = &core_l4_ick,
1987 .prcm_mod = CORE_MOD,
1988 .enable_reg = CM_ICLKEN1,
1989 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1990 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
1991 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1992 .clkdm = { .name = "core_l4_clkdm" },
1993 .recalc = &followparent_recalc,
1996 static struct clk i2c2_ick = {
1999 .parent = &core_l4_ick,
2000 .prcm_mod = CORE_MOD,
2001 .enable_reg = CM_ICLKEN1,
2002 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2003 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
2004 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2005 .clkdm = { .name = "core_l4_clkdm" },
2006 .recalc = &followparent_recalc,
2009 static struct clk i2c1_ick = {
2012 .parent = &core_l4_ick,
2013 .prcm_mod = CORE_MOD,
2014 .enable_reg = CM_ICLKEN1,
2015 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
2016 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
2017 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2018 .clkdm = { .name = "core_l4_clkdm" },
2019 .recalc = &followparent_recalc,
2022 static struct clk uart2_ick = {
2023 .name = "uart2_ick",
2024 .parent = &core_l4_ick,
2025 .prcm_mod = CORE_MOD,
2026 .enable_reg = CM_ICLKEN1,
2027 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2028 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
2029 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2030 .clkdm = { .name = "core_l4_clkdm" },
2031 .recalc = &followparent_recalc,
2034 static struct clk uart1_ick = {
2035 .name = "uart1_ick",
2036 .parent = &core_l4_ick,
2037 .prcm_mod = CORE_MOD,
2038 .enable_reg = CM_ICLKEN1,
2039 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2040 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
2041 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2042 .clkdm = { .name = "core_l4_clkdm" },
2043 .recalc = &followparent_recalc,
2046 static struct clk gpt11_ick = {
2047 .name = "gpt11_ick",
2048 .parent = &core_l4_ick,
2049 .prcm_mod = CORE_MOD,
2050 .enable_reg = CM_ICLKEN1,
2051 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2052 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
2053 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2054 .clkdm = { .name = "core_l4_clkdm" },
2055 .recalc = &followparent_recalc,
2058 static struct clk gpt10_ick = {
2059 .name = "gpt10_ick",
2060 .parent = &core_l4_ick,
2061 .prcm_mod = CORE_MOD,
2062 .enable_reg = CM_ICLKEN1,
2063 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2064 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
2065 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2066 .clkdm = { .name = "core_l4_clkdm" },
2067 .recalc = &followparent_recalc,
2070 static struct clk mcbsp5_ick = {
2071 .name = "mcbsp_ick",
2073 .parent = &core_l4_ick,
2074 .prcm_mod = CORE_MOD,
2075 .enable_reg = CM_ICLKEN1,
2076 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2077 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
2078 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2079 .clkdm = { .name = "core_l4_clkdm" },
2080 .recalc = &followparent_recalc,
2083 static struct clk mcbsp1_ick = {
2084 .name = "mcbsp_ick",
2086 .parent = &core_l4_ick,
2087 .prcm_mod = CORE_MOD,
2088 .enable_reg = CM_ICLKEN1,
2089 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2090 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
2091 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2092 .clkdm = { .name = "core_l4_clkdm" },
2093 .recalc = &followparent_recalc,
2096 static struct clk fac_ick = {
2098 .parent = &core_l4_ick,
2099 .prcm_mod = CORE_MOD,
2100 .enable_reg = CM_ICLKEN1,
2101 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2102 .idlest_bit = OMAP3430ES1_ST_FAC_SHIFT,
2103 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2104 .clkdm = { .name = "core_l4_clkdm" },
2105 .recalc = &followparent_recalc,
2108 static struct clk mailboxes_ick = {
2109 .name = "mailboxes_ick",
2110 .parent = &core_l4_ick,
2111 .prcm_mod = CORE_MOD,
2112 .enable_reg = CM_ICLKEN1,
2113 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2114 .idlest_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2115 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2116 .clkdm = { .name = "core_l4_clkdm" },
2117 .recalc = &followparent_recalc,
2120 static struct clk omapctrl_ick = {
2121 .name = "omapctrl_ick",
2122 .parent = &core_l4_ick,
2123 .prcm_mod = CORE_MOD,
2124 .enable_reg = CM_ICLKEN1,
2125 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2126 .idlest_bit = OMAP3430_ST_OMAPCTRL_SHIFT,
2127 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2128 .clkdm = { .name = "core_l4_clkdm" },
2129 .recalc = &followparent_recalc,
2132 /* SSI_L4_ICK based clocks */
2134 static struct clk ssi_l4_ick = {
2135 .name = "ssi_l4_ick",
2137 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2138 .clkdm = { .name = "core_l4_clkdm" },
2139 .recalc = &followparent_recalc,
2142 static struct clk ssi_ick_3430es1 = {
2144 .parent = &ssi_l4_ick,
2145 .prcm_mod = CORE_MOD,
2146 .enable_reg = CM_ICLKEN1,
2147 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2148 .flags = CLOCK_IN_OMAP3430ES1,
2149 .clkdm = { .name = "core_l4_clkdm" },
2150 .recalc = &followparent_recalc,
2153 static struct clk ssi_ick_3430es2 = {
2155 .parent = &ssi_l4_ick,
2156 .prcm_mod = CORE_MOD,
2157 .enable_reg = CM_ICLKEN1,
2158 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2159 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2160 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2161 .clkdm = { .name = "core_l4_clkdm" },
2162 .recalc = &followparent_recalc,
2166 * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2167 * but l4_ick makes more sense to me
2169 static const struct clksel usb_l4_clksel[] = {
2170 { .parent = &l4_ick, .rates = div2_rates },
2174 static struct clk usb_l4_ick = {
2175 .name = "usb_l4_ick",
2177 .prcm_mod = CORE_MOD,
2178 .init = &omap2_init_clksel_parent,
2179 .enable_reg = CM_ICLKEN1,
2180 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2181 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2182 .clksel_reg = CM_CLKSEL,
2183 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2184 .clksel = usb_l4_clksel,
2185 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2186 .clkdm = { .name = "core_l4_clkdm" },
2187 .recalc = &omap2_clksel_recalc,
2190 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2192 /* SECURITY_L4_ICK2 based clocks */
2194 static struct clk security_l4_ick2 = {
2195 .name = "security_l4_ick2",
2197 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2198 .clkdm = { .name = "core_l4_clkdm" },
2199 .recalc = &followparent_recalc,
2202 static struct clk aes1_ick = {
2204 .parent = &security_l4_ick2,
2205 .prcm_mod = CORE_MOD,
2206 .enable_reg = CM_ICLKEN2,
2207 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2208 .idlest_bit = OMAP3430_ST_AES1_SHIFT,
2209 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2210 .clkdm = { .name = "core_l4_clkdm" },
2211 .recalc = &followparent_recalc,
2214 static struct clk rng_ick = {
2216 .parent = &security_l4_ick2,
2217 .prcm_mod = CORE_MOD,
2218 .enable_reg = CM_ICLKEN2,
2219 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2220 .idlest_bit = OMAP3430_ST_RNG_SHIFT,
2221 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2222 .clkdm = { .name = "core_l4_clkdm" },
2223 .recalc = &followparent_recalc,
2226 static struct clk sha11_ick = {
2227 .name = "sha11_ick",
2228 .parent = &security_l4_ick2,
2229 .prcm_mod = CORE_MOD,
2230 .enable_reg = CM_ICLKEN2,
2231 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2232 .idlest_bit = OMAP3430_ST_SHA11_SHIFT,
2233 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2234 .clkdm = { .name = "core_l4_clkdm" },
2235 .recalc = &followparent_recalc,
2238 static struct clk des1_ick = {
2240 .parent = &security_l4_ick2,
2241 .prcm_mod = CORE_MOD,
2242 .enable_reg = CM_ICLKEN2,
2243 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2244 .idlest_bit = OMAP3430_ST_DES1_SHIFT,
2245 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2246 .clkdm = { .name = "core_l4_clkdm" },
2247 .recalc = &followparent_recalc,
2251 static struct clk dss1_alwon_fck_3430es1 = {
2252 .name = "dss1_alwon_fck",
2253 .parent = &dpll4_m4x2_ck,
2254 .prcm_mod = OMAP3430_DSS_MOD,
2255 .enable_reg = CM_FCLKEN,
2256 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2257 .flags = CLOCK_IN_OMAP3430ES1,
2258 .clkdm = { .name = "dss_clkdm" },
2259 .recalc = &followparent_recalc,
2262 static struct clk dss1_alwon_fck_3430es2 = {
2263 .name = "dss1_alwon_fck",
2264 .parent = &dpll4_m4x2_ck,
2265 .init = &omap2_init_clksel_parent,
2266 .prcm_mod = OMAP3430_DSS_MOD,
2267 .enable_reg = CM_FCLKEN,
2268 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2269 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2270 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2271 .clkdm = { .name = "dss_clkdm" },
2272 .recalc = &followparent_recalc,
2275 static struct clk dss_tv_fck = {
2276 .name = "dss_tv_fck",
2277 .parent = &omap_54m_fck,
2278 .prcm_mod = OMAP3430_DSS_MOD,
2279 .enable_reg = CM_FCLKEN,
2280 .enable_bit = OMAP3430_EN_TV_SHIFT,
2281 .flags = CLOCK_IN_OMAP343X,
2282 .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2283 .recalc = &followparent_recalc,
2286 static struct clk dss_96m_fck = {
2287 .name = "dss_96m_fck",
2288 .parent = &omap_96m_fck,
2289 .prcm_mod = OMAP3430_DSS_MOD,
2290 .enable_reg = CM_FCLKEN,
2291 .enable_bit = OMAP3430_EN_TV_SHIFT,
2292 .flags = CLOCK_IN_OMAP343X,
2293 .clkdm = { .name = "dss_clkdm" },
2294 .recalc = &followparent_recalc,
2297 static struct clk dss2_alwon_fck = {
2298 .name = "dss2_alwon_fck",
2300 .prcm_mod = OMAP3430_DSS_MOD,
2301 .enable_reg = CM_FCLKEN,
2302 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2303 .flags = CLOCK_IN_OMAP343X,
2304 .clkdm = { .name = "dss_clkdm" },
2305 .recalc = &followparent_recalc,
2308 static struct clk dss_ick_3430es1 = {
2309 /* Handles both L3 and L4 clocks */
2312 .prcm_mod = OMAP3430_DSS_MOD,
2313 .enable_reg = CM_ICLKEN,
2314 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2315 .flags = CLOCK_IN_OMAP3430ES1,
2316 .clkdm = { .name = "dss_clkdm" },
2317 .recalc = &followparent_recalc,
2320 static struct clk dss_ick_3430es2 = {
2321 /* Handles both L3 and L4 clocks */
2324 .prcm_mod = OMAP3430_DSS_MOD,
2325 .enable_reg = CM_ICLKEN,
2326 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2327 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2328 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2329 .clkdm = { .name = "dss_clkdm" },
2330 .recalc = &followparent_recalc,
2335 static struct clk cam_mclk = {
2337 .parent = &dpll4_m5x2_ck,
2338 .prcm_mod = OMAP3430_CAM_MOD,
2339 .enable_reg = CM_FCLKEN,
2340 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2341 .flags = CLOCK_IN_OMAP343X,
2342 .clkdm = { .name = "cam_clkdm" },
2343 .recalc = &followparent_recalc,
2346 static struct clk cam_ick = {
2347 /* Handles both L3 and L4 clocks */
2350 .prcm_mod = OMAP3430_CAM_MOD,
2351 .enable_reg = CM_ICLKEN,
2352 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2353 .flags = CLOCK_IN_OMAP343X,
2354 .clkdm = { .name = "cam_clkdm" },
2355 .recalc = &followparent_recalc,
2358 static struct clk csi2_96m_fck = {
2359 .name = "csi2_96m_fck",
2360 .parent = &core_96m_fck,
2361 .prcm_mod = OMAP3430_CAM_MOD,
2362 .enable_reg = CM_FCLKEN,
2363 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2364 .flags = CLOCK_IN_OMAP343X,
2365 .clkdm = { .name = "cam_clkdm" },
2366 .recalc = &followparent_recalc,
2369 /* USBHOST - 3430ES2 only */
2371 static struct clk usbhost_120m_fck = {
2372 .name = "usbhost_120m_fck",
2373 .parent = &dpll5_m2_ck,
2374 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2375 .enable_reg = CM_FCLKEN,
2376 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2377 .flags = CLOCK_IN_OMAP3430ES2,
2378 .clkdm = { .name = "usbhost_clkdm" },
2379 .recalc = &followparent_recalc,
2382 static struct clk usbhost_48m_fck = {
2383 .name = "usbhost_48m_fck",
2384 .parent = &omap_48m_fck,
2385 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2386 .enable_reg = CM_FCLKEN,
2387 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2388 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2389 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2390 .clkdm = { .name = "usbhost_clkdm" },
2391 .recalc = &followparent_recalc,
2394 static struct clk usbhost_ick = {
2395 /* Handles both L3 and L4 clocks */
2396 .name = "usbhost_ick",
2398 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2399 .enable_reg = CM_ICLKEN,
2400 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2401 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2402 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2403 .clkdm = { .name = "usbhost_clkdm" },
2404 .recalc = &followparent_recalc,
2409 static const struct clksel_rate usim_96m_rates[] = {
2410 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2411 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2412 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2413 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2417 static const struct clksel_rate usim_120m_rates[] = {
2418 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2419 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2420 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2421 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2425 static const struct clksel usim_clksel[] = {
2426 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2427 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2428 { .parent = &sys_ck, .rates = div2_rates },
2433 static struct clk usim_fck = {
2435 .prcm_mod = WKUP_MOD,
2436 .init = &omap2_init_clksel_parent,
2437 .enable_reg = CM_FCLKEN,
2438 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2439 .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
2440 .clksel_reg = CM_CLKSEL,
2441 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2442 .clksel = usim_clksel,
2443 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2444 .clkdm = { .name = "prm_clkdm" },
2445 .recalc = &omap2_clksel_recalc,
2448 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2449 static struct clk gpt1_fck = {
2451 .prcm_mod = WKUP_MOD,
2452 .init = &omap2_init_clksel_parent,
2453 .enable_reg = CM_FCLKEN,
2454 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2455 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2456 .clksel_reg = CM_CLKSEL,
2457 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2458 .clksel = omap343x_gpt_clksel,
2459 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2460 .clkdm = { .name = "prm_clkdm" },
2461 .recalc = &omap2_clksel_recalc,
2464 static struct clk wkup_32k_fck = {
2465 .name = "wkup_32k_fck",
2466 .parent = &omap_32k_fck,
2467 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2468 .clkdm = { .name = "prm_clkdm" },
2469 .recalc = &followparent_recalc,
2472 static struct clk gpio1_dbck = {
2473 .name = "gpio1_dbck",
2474 .parent = &wkup_32k_fck,
2475 .prcm_mod = WKUP_MOD,
2476 .enable_reg = CM_FCLKEN,
2477 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2478 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2479 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2480 .clkdm = { .name = "prm_clkdm" },
2481 .recalc = &followparent_recalc,
2484 static struct clk wdt2_fck = {
2486 .parent = &wkup_32k_fck,
2487 .prcm_mod = WKUP_MOD,
2488 .enable_reg = CM_FCLKEN,
2489 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2490 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2491 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2492 .clkdm = { .name = "prm_clkdm" },
2493 .recalc = &followparent_recalc,
2496 static struct clk wkup_l4_ick = {
2497 .name = "wkup_l4_ick",
2499 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2500 .clkdm = { .name = "prm_clkdm" },
2501 .recalc = &followparent_recalc,
2504 static struct clk usim_ick = {
2506 .parent = &wkup_l4_ick,
2507 .prcm_mod = WKUP_MOD,
2508 .enable_reg = CM_ICLKEN,
2509 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2510 .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
2511 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2512 .clkdm = { .name = "prm_clkdm" },
2513 .recalc = &followparent_recalc,
2516 static struct clk wdt2_ick = {
2518 .parent = &wkup_l4_ick,
2519 .prcm_mod = WKUP_MOD,
2520 .enable_reg = CM_ICLKEN,
2521 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2522 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2523 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2524 .clkdm = { .name = "prm_clkdm" },
2525 .recalc = &followparent_recalc,
2528 static struct clk wdt1_ick = {
2530 .parent = &wkup_l4_ick,
2531 .prcm_mod = WKUP_MOD,
2532 .enable_reg = CM_ICLKEN,
2533 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2534 .idlest_bit = OMAP3430_ST_WDT1_SHIFT,
2535 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2536 .clkdm = { .name = "prm_clkdm" },
2537 .recalc = &followparent_recalc,
2540 static struct clk gpio1_ick = {
2541 .name = "gpio1_ick",
2542 .parent = &wkup_l4_ick,
2543 .prcm_mod = WKUP_MOD,
2544 .enable_reg = CM_ICLKEN,
2545 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2546 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2547 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2548 .clkdm = { .name = "prm_clkdm" },
2549 .recalc = &followparent_recalc,
2552 static struct clk omap_32ksync_ick = {
2553 .name = "omap_32ksync_ick",
2554 .parent = &wkup_l4_ick,
2555 .prcm_mod = WKUP_MOD,
2556 .enable_reg = CM_ICLKEN,
2557 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2558 .idlest_bit = OMAP3430_ST_32KSYNC_SHIFT,
2559 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2560 .clkdm = { .name = "prm_clkdm" },
2561 .recalc = &followparent_recalc,
2564 static struct clk gpt12_ick = {
2565 .name = "gpt12_ick",
2566 .parent = &wkup_l4_ick,
2567 .prcm_mod = WKUP_MOD,
2568 .enable_reg = CM_ICLKEN,
2569 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2570 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
2571 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2572 .clkdm = { .name = "prm_clkdm" },
2573 .recalc = &followparent_recalc,
2576 static struct clk gpt1_ick = {
2578 .parent = &wkup_l4_ick,
2579 .prcm_mod = WKUP_MOD,
2580 .enable_reg = CM_ICLKEN,
2581 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2582 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2583 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2584 .clkdm = { .name = "prm_clkdm" },
2585 .recalc = &followparent_recalc,
2590 /* PER clock domain */
2592 static struct clk per_96m_fck = {
2593 .name = "per_96m_fck",
2594 .parent = &omap_96m_alwon_fck,
2595 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2596 .clkdm = { .name = "per_clkdm" },
2597 .recalc = &followparent_recalc,
2600 static struct clk per_48m_fck = {
2601 .name = "per_48m_fck",
2602 .parent = &omap_48m_fck,
2603 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2604 .clkdm = { .name = "per_clkdm" },
2605 .recalc = &followparent_recalc,
2608 static struct clk uart3_fck = {
2609 .name = "uart3_fck",
2610 .parent = &per_48m_fck,
2611 .prcm_mod = OMAP3430_PER_MOD,
2612 .enable_reg = CM_FCLKEN,
2613 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2614 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2615 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2616 .clkdm = { .name = "per_clkdm" },
2617 .recalc = &followparent_recalc,
2620 static struct clk gpt2_fck = {
2622 .prcm_mod = OMAP3430_PER_MOD,
2623 .init = &omap2_init_clksel_parent,
2624 .enable_reg = CM_FCLKEN,
2625 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2626 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
2627 .clksel_reg = CM_CLKSEL,
2628 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2629 .clksel = omap343x_gpt_clksel,
2630 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2631 .clkdm = { .name = "per_clkdm" },
2632 .recalc = &omap2_clksel_recalc,
2635 static struct clk gpt3_fck = {
2637 .prcm_mod = OMAP3430_PER_MOD,
2638 .init = &omap2_init_clksel_parent,
2639 .enable_reg = CM_FCLKEN,
2640 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2641 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
2642 .clksel_reg = CM_CLKSEL,
2643 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2644 .clksel = omap343x_gpt_clksel,
2645 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2646 .clkdm = { .name = "per_clkdm" },
2647 .recalc = &omap2_clksel_recalc,
2650 static struct clk gpt4_fck = {
2652 .prcm_mod = OMAP3430_PER_MOD,
2653 .init = &omap2_init_clksel_parent,
2654 .enable_reg = CM_FCLKEN,
2655 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2656 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
2657 .clksel_reg = CM_CLKSEL,
2658 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2659 .clksel = omap343x_gpt_clksel,
2660 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2661 .clkdm = { .name = "per_clkdm" },
2662 .recalc = &omap2_clksel_recalc,
2665 static struct clk gpt5_fck = {
2667 .prcm_mod = OMAP3430_PER_MOD,
2668 .init = &omap2_init_clksel_parent,
2669 .enable_reg = CM_FCLKEN,
2670 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2671 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
2672 .clksel_reg = CM_CLKSEL,
2673 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2674 .clksel = omap343x_gpt_clksel,
2675 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2676 .clkdm = { .name = "per_clkdm" },
2677 .recalc = &omap2_clksel_recalc,
2680 static struct clk gpt6_fck = {
2682 .prcm_mod = OMAP3430_PER_MOD,
2683 .init = &omap2_init_clksel_parent,
2684 .enable_reg = CM_FCLKEN,
2685 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2686 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
2687 .clksel_reg = CM_CLKSEL,
2688 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2689 .clksel = omap343x_gpt_clksel,
2690 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2691 .clkdm = { .name = "per_clkdm" },
2692 .recalc = &omap2_clksel_recalc,
2695 static struct clk gpt7_fck = {
2697 .prcm_mod = OMAP3430_PER_MOD,
2698 .init = &omap2_init_clksel_parent,
2699 .enable_reg = CM_FCLKEN,
2700 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2701 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2702 .clksel_reg = CM_CLKSEL,
2703 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2704 .clksel = omap343x_gpt_clksel,
2705 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2706 .clkdm = { .name = "per_clkdm" },
2707 .recalc = &omap2_clksel_recalc,
2710 static struct clk gpt8_fck = {
2712 .prcm_mod = OMAP3430_PER_MOD,
2713 .init = &omap2_init_clksel_parent,
2714 .enable_reg = CM_FCLKEN,
2715 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2716 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2717 .clksel_reg = CM_CLKSEL,
2718 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2719 .clksel = omap343x_gpt_clksel,
2720 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2721 .clkdm = { .name = "per_clkdm" },
2722 .recalc = &omap2_clksel_recalc,
2725 static struct clk gpt9_fck = {
2727 .prcm_mod = OMAP3430_PER_MOD,
2728 .init = &omap2_init_clksel_parent,
2729 .enable_reg = CM_FCLKEN,
2730 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2731 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2732 .clksel_reg = CM_CLKSEL,
2733 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2734 .clksel = omap343x_gpt_clksel,
2735 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2736 .clkdm = { .name = "per_clkdm" },
2737 .recalc = &omap2_clksel_recalc,
2740 static struct clk per_32k_alwon_fck = {
2741 .name = "per_32k_alwon_fck",
2742 .parent = &omap_32k_fck,
2743 .clkdm = { .name = "per_clkdm" },
2744 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2745 .recalc = &followparent_recalc,
2748 static struct clk gpio6_dbck = {
2749 .name = "gpio6_dbck",
2750 .parent = &per_32k_alwon_fck,
2751 .prcm_mod = OMAP3430_PER_MOD,
2752 .enable_reg = CM_FCLKEN,
2753 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2754 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2755 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2756 .clkdm = { .name = "per_clkdm" },
2757 .recalc = &followparent_recalc,
2760 static struct clk gpio5_dbck = {
2761 .name = "gpio5_dbck",
2762 .parent = &per_32k_alwon_fck,
2763 .prcm_mod = OMAP3430_PER_MOD,
2764 .enable_reg = CM_FCLKEN,
2765 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2766 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2767 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2768 .clkdm = { .name = "per_clkdm" },
2769 .recalc = &followparent_recalc,
2772 static struct clk gpio4_dbck = {
2773 .name = "gpio4_dbck",
2774 .parent = &per_32k_alwon_fck,
2775 .prcm_mod = OMAP3430_PER_MOD,
2776 .enable_reg = CM_FCLKEN,
2777 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2778 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2779 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2780 .clkdm = { .name = "per_clkdm" },
2781 .recalc = &followparent_recalc,
2784 static struct clk gpio3_dbck = {
2785 .name = "gpio3_dbck",
2786 .parent = &per_32k_alwon_fck,
2787 .prcm_mod = OMAP3430_PER_MOD,
2788 .enable_reg = CM_FCLKEN,
2789 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2790 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2791 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2792 .clkdm = { .name = "per_clkdm" },
2793 .recalc = &followparent_recalc,
2796 static struct clk gpio2_dbck = {
2797 .name = "gpio2_dbck",
2798 .parent = &per_32k_alwon_fck,
2799 .prcm_mod = OMAP3430_PER_MOD,
2800 .enable_reg = CM_FCLKEN,
2801 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2802 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2803 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2804 .clkdm = { .name = "per_clkdm" },
2805 .recalc = &followparent_recalc,
2808 static struct clk wdt3_fck = {
2810 .parent = &per_32k_alwon_fck,
2811 .prcm_mod = OMAP3430_PER_MOD,
2812 .enable_reg = CM_FCLKEN,
2813 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2814 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2815 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2816 .clkdm = { .name = "per_clkdm" },
2817 .recalc = &followparent_recalc,
2820 static struct clk per_l4_ick = {
2821 .name = "per_l4_ick",
2823 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2824 .clkdm = { .name = "per_clkdm" },
2825 .recalc = &followparent_recalc,
2828 static struct clk gpio6_ick = {
2829 .name = "gpio6_ick",
2830 .parent = &per_l4_ick,
2831 .prcm_mod = OMAP3430_PER_MOD,
2832 .enable_reg = CM_ICLKEN,
2833 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2834 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2835 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2836 .clkdm = { .name = "per_clkdm" },
2837 .recalc = &followparent_recalc,
2840 static struct clk gpio5_ick = {
2841 .name = "gpio5_ick",
2842 .parent = &per_l4_ick,
2843 .prcm_mod = OMAP3430_PER_MOD,
2844 .enable_reg = CM_ICLKEN,
2845 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2846 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2847 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2848 .clkdm = { .name = "per_clkdm" },
2849 .recalc = &followparent_recalc,
2852 static struct clk gpio4_ick = {
2853 .name = "gpio4_ick",
2854 .parent = &per_l4_ick,
2855 .prcm_mod = OMAP3430_PER_MOD,
2856 .enable_reg = CM_ICLKEN,
2857 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2858 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2859 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2860 .clkdm = { .name = "per_clkdm" },
2861 .recalc = &followparent_recalc,
2864 static struct clk gpio3_ick = {
2865 .name = "gpio3_ick",
2866 .parent = &per_l4_ick,
2867 .prcm_mod = OMAP3430_PER_MOD,
2868 .enable_reg = CM_ICLKEN,
2869 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2870 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2871 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2872 .clkdm = { .name = "per_clkdm" },
2873 .recalc = &followparent_recalc,
2876 static struct clk gpio2_ick = {
2877 .name = "gpio2_ick",
2878 .parent = &per_l4_ick,
2879 .prcm_mod = OMAP3430_PER_MOD,
2880 .enable_reg = CM_ICLKEN,
2881 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2882 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2883 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2884 .clkdm = { .name = "per_clkdm" },
2885 .recalc = &followparent_recalc,
2888 static struct clk wdt3_ick = {
2890 .parent = &per_l4_ick,
2891 .prcm_mod = OMAP3430_PER_MOD,
2892 .enable_reg = CM_ICLKEN,
2893 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2894 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2895 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2896 .clkdm = { .name = "per_clkdm" },
2897 .recalc = &followparent_recalc,
2900 static struct clk uart3_ick = {
2901 .name = "uart3_ick",
2902 .parent = &per_l4_ick,
2903 .prcm_mod = OMAP3430_PER_MOD,
2904 .enable_reg = CM_ICLKEN,
2905 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2906 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2907 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2908 .clkdm = { .name = "per_clkdm" },
2909 .recalc = &followparent_recalc,
2912 static struct clk gpt9_ick = {
2914 .parent = &per_l4_ick,
2915 .prcm_mod = OMAP3430_PER_MOD,
2916 .enable_reg = CM_ICLKEN,
2917 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2918 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2919 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2920 .clkdm = { .name = "per_clkdm" },
2921 .recalc = &followparent_recalc,
2924 static struct clk gpt8_ick = {
2926 .parent = &per_l4_ick,
2927 .prcm_mod = OMAP3430_PER_MOD,
2928 .enable_reg = CM_ICLKEN,
2929 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2930 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2931 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2932 .clkdm = { .name = "per_clkdm" },
2933 .recalc = &followparent_recalc,
2936 static struct clk gpt7_ick = {
2938 .parent = &per_l4_ick,
2939 .prcm_mod = OMAP3430_PER_MOD,
2940 .enable_reg = CM_ICLKEN,
2941 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2942 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2943 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2944 .clkdm = { .name = "per_clkdm" },
2945 .recalc = &followparent_recalc,
2948 static struct clk gpt6_ick = {
2950 .parent = &per_l4_ick,
2951 .prcm_mod = OMAP3430_PER_MOD,
2952 .enable_reg = CM_ICLKEN,
2953 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2954 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
2955 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2956 .clkdm = { .name = "per_clkdm" },
2957 .recalc = &followparent_recalc,
2960 static struct clk gpt5_ick = {
2962 .parent = &per_l4_ick,
2963 .prcm_mod = OMAP3430_PER_MOD,
2964 .enable_reg = CM_ICLKEN,
2965 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2966 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
2967 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2968 .clkdm = { .name = "per_clkdm" },
2969 .recalc = &followparent_recalc,
2972 static struct clk gpt4_ick = {
2974 .parent = &per_l4_ick,
2975 .prcm_mod = OMAP3430_PER_MOD,
2976 .enable_reg = CM_ICLKEN,
2977 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2978 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
2979 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2980 .clkdm = { .name = "per_clkdm" },
2981 .recalc = &followparent_recalc,
2984 static struct clk gpt3_ick = {
2986 .parent = &per_l4_ick,
2987 .prcm_mod = OMAP3430_PER_MOD,
2988 .enable_reg = CM_ICLKEN,
2989 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2990 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
2991 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2992 .clkdm = { .name = "per_clkdm" },
2993 .recalc = &followparent_recalc,
2996 static struct clk gpt2_ick = {
2998 .parent = &per_l4_ick,
2999 .prcm_mod = OMAP3430_PER_MOD,
3000 .enable_reg = CM_ICLKEN,
3001 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
3002 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
3003 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3004 .clkdm = { .name = "per_clkdm" },
3005 .recalc = &followparent_recalc,
3008 static struct clk mcbsp2_ick = {
3009 .name = "mcbsp_ick",
3011 .parent = &per_l4_ick,
3012 .prcm_mod = OMAP3430_PER_MOD,
3013 .enable_reg = CM_ICLKEN,
3014 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3015 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3016 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3017 .clkdm = { .name = "per_clkdm" },
3018 .recalc = &followparent_recalc,
3021 static struct clk mcbsp3_ick = {
3022 .name = "mcbsp_ick",
3024 .parent = &per_l4_ick,
3025 .prcm_mod = OMAP3430_PER_MOD,
3026 .enable_reg = CM_ICLKEN,
3027 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3028 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3029 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3030 .clkdm = { .name = "per_clkdm" },
3031 .recalc = &followparent_recalc,
3034 static struct clk mcbsp4_ick = {
3035 .name = "mcbsp_ick",
3037 .parent = &per_l4_ick,
3038 .prcm_mod = OMAP3430_PER_MOD,
3039 .enable_reg = CM_ICLKEN,
3040 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3041 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3042 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3043 .clkdm = { .name = "per_clkdm" },
3044 .recalc = &followparent_recalc,
3047 static const struct clksel mcbsp_234_clksel[] = {
3048 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3049 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
3053 static struct clk mcbsp2_src_fck = {
3054 .name = "mcbsp_src_fck",
3056 .prcm_mod = CLK_REG_IN_SCM,
3057 .init = &omap2_init_clksel_parent,
3058 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
3059 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
3060 .clksel = mcbsp_234_clksel,
3061 .flags = CLOCK_IN_OMAP343X,
3062 .clkdm = { .name = "per_clkdm" },
3063 .recalc = &omap2_clksel_recalc,
3066 static struct clk mcbsp2_fck = {
3067 .name = "mcbsp_fck",
3069 .parent = &mcbsp2_src_fck,
3070 .prcm_mod = OMAP3430_PER_MOD,
3071 .enable_reg = CM_FCLKEN,
3072 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3073 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3074 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3075 .clkdm = { .name = "per_clkdm" },
3076 .recalc = &omap2_clksel_recalc,
3079 static struct clk mcbsp3_src_fck = {
3080 .name = "mcbsp_src_fck",
3082 .prcm_mod = CLK_REG_IN_SCM,
3083 .init = &omap2_init_clksel_parent,
3084 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3085 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
3086 .clksel = mcbsp_234_clksel,
3087 .flags = CLOCK_IN_OMAP343X,
3088 .clkdm = { .name = "per_clkdm" },
3089 .recalc = &omap2_clksel_recalc,
3092 static struct clk mcbsp3_fck = {
3093 .name = "mcbsp_fck",
3095 .parent = &mcbsp3_src_fck,
3096 .prcm_mod = OMAP3430_PER_MOD,
3097 .enable_reg = CM_FCLKEN,
3098 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3099 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3100 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3101 .clkdm = { .name = "per_clkdm" },
3102 .recalc = &omap2_clksel_recalc,
3105 static struct clk mcbsp4_src_fck = {
3106 .name = "mcbsp_src_fck",
3108 .prcm_mod = CLK_REG_IN_SCM,
3109 .init = &omap2_init_clksel_parent,
3110 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3111 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
3112 .clksel = mcbsp_234_clksel,
3113 .flags = CLOCK_IN_OMAP343X,
3114 .clkdm = { .name = "per_clkdm" },
3115 .recalc = &omap2_clksel_recalc,
3118 static struct clk mcbsp4_fck = {
3119 .name = "mcbsp_fck",
3121 .parent = &mcbsp4_src_fck,
3122 .prcm_mod = OMAP3430_PER_MOD,
3123 .enable_reg = CM_FCLKEN,
3124 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3125 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3126 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3127 .clkdm = { .name = "per_clkdm" },
3128 .recalc = &omap2_clksel_recalc,
3133 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3135 static const struct clksel_rate emu_src_sys_rates[] = {
3136 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3140 static const struct clksel_rate emu_src_core_rates[] = {
3141 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3145 static const struct clksel_rate emu_src_per_rates[] = {
3146 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3150 static const struct clksel_rate emu_src_mpu_rates[] = {
3151 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3155 static const struct clksel emu_src_clksel[] = {
3156 { .parent = &sys_ck, .rates = emu_src_sys_rates },
3157 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3158 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
3159 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
3164 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3165 * to switch the source of some of the EMU clocks.
3166 * XXX Are there CLKEN bits for these EMU clks?
3168 static struct clk emu_src_ck = {
3169 .name = "emu_src_ck",
3170 .prcm_mod = OMAP3430_EMU_MOD,
3171 .init = &omap2_init_clksel_parent,
3172 .clksel_reg = CM_CLKSEL1,
3173 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
3174 .clksel = emu_src_clksel,
3175 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3176 .clkdm = { .name = "emu_clkdm" },
3177 .recalc = &omap2_clksel_recalc,
3180 static const struct clksel_rate pclk_emu_rates[] = {
3181 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3182 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3183 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3184 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3188 static const struct clksel pclk_emu_clksel[] = {
3189 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3193 static struct clk pclk_fck = {
3195 .prcm_mod = OMAP3430_EMU_MOD,
3196 .init = &omap2_init_clksel_parent,
3197 .clksel_reg = CM_CLKSEL1,
3198 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3199 .clksel = pclk_emu_clksel,
3200 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3201 .clkdm = { .name = "emu_clkdm" },
3202 .recalc = &omap2_clksel_recalc,
3205 static const struct clksel_rate pclkx2_emu_rates[] = {
3206 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3207 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3208 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3212 static const struct clksel pclkx2_emu_clksel[] = {
3213 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3217 static struct clk pclkx2_fck = {
3218 .name = "pclkx2_fck",
3219 .prcm_mod = OMAP3430_EMU_MOD,
3220 .init = &omap2_init_clksel_parent,
3221 .clksel_reg = CM_CLKSEL1,
3222 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3223 .clksel = pclkx2_emu_clksel,
3224 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3225 .clkdm = { .name = "emu_clkdm" },
3226 .recalc = &omap2_clksel_recalc,
3229 static const struct clksel atclk_emu_clksel[] = {
3230 { .parent = &emu_src_ck, .rates = div2_rates },
3234 static struct clk atclk_fck = {
3235 .name = "atclk_fck",
3236 .prcm_mod = OMAP3430_EMU_MOD,
3237 .init = &omap2_init_clksel_parent,
3238 .clksel_reg = CM_CLKSEL1,
3239 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3240 .clksel = atclk_emu_clksel,
3241 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3242 .clkdm = { .name = "emu_clkdm" },
3243 .recalc = &omap2_clksel_recalc,
3246 static struct clk traceclk_src_fck = {
3247 .name = "traceclk_src_fck",
3248 .prcm_mod = OMAP3430_EMU_MOD,
3249 .init = &omap2_init_clksel_parent,
3250 .clksel_reg = CM_CLKSEL1,
3251 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3252 .clksel = emu_src_clksel,
3253 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3254 .clkdm = { .name = "emu_clkdm" },
3255 .recalc = &omap2_clksel_recalc,
3258 static const struct clksel_rate traceclk_rates[] = {
3259 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3260 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3261 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3265 static const struct clksel traceclk_clksel[] = {
3266 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3270 static struct clk traceclk_fck = {
3271 .name = "traceclk_fck",
3272 .prcm_mod = OMAP3430_EMU_MOD,
3273 .init = &omap2_init_clksel_parent,
3274 .clksel_reg = CM_CLKSEL1,
3275 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3276 .clksel = traceclk_clksel,
3277 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3278 .clkdm = { .name = "emu_clkdm" },
3279 .recalc = &omap2_clksel_recalc,
3284 /* SmartReflex fclk (VDD1) */
3285 static struct clk sr1_fck = {
3288 .prcm_mod = WKUP_MOD,
3289 .enable_reg = CM_FCLKEN,
3290 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3291 .idlest_bit = OMAP3430_ST_SR1_SHIFT,
3292 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3293 .clkdm = { .name = "prm_clkdm" },
3294 .recalc = &followparent_recalc,
3297 /* SmartReflex fclk (VDD2) */
3298 static struct clk sr2_fck = {
3301 .prcm_mod = WKUP_MOD,
3302 .enable_reg = CM_FCLKEN,
3303 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3304 .idlest_bit = OMAP3430_ST_SR2_SHIFT,
3305 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3306 .clkdm = { .name = "prm_clkdm" },
3307 .recalc = &followparent_recalc,
3310 static struct clk sr_l4_ick = {
3311 .name = "sr_l4_ick",
3313 .flags = CLOCK_IN_OMAP343X,
3314 .clkdm = { .name = "core_l4_clkdm" },
3315 .recalc = &followparent_recalc,
3318 /* SECURE_32K_FCK clocks */
3320 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3321 static struct clk gpt12_fck = {
3322 .name = "gpt12_fck",
3323 .parent = &secure_32k_fck,
3324 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
3325 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3326 .clkdm = { .name = "prm_clkdm" },
3327 .recalc = &followparent_recalc,
3330 static struct clk wdt1_fck = {
3332 .parent = &secure_32k_fck,
3333 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3334 .clkdm = { .name = "prm_clkdm" },
3335 .recalc = &followparent_recalc,
3338 static struct clk *onchip_34xx_clks[] __initdata = {
3366 &omap_96m_alwon_fck,
3432 &ssi_ssr_fck_3430es1,
3433 &ssi_ssr_fck_3430es2,
3434 &ssi_sst_fck_3430es1,
3435 &ssi_sst_fck_3430es2,
3437 &hsotgusb_ick_3430es1,
3438 &hsotgusb_ick_3430es2,
3479 &dss1_alwon_fck_3430es1,
3480 &dss1_alwon_fck_3430es2,