arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  53 #define DPLL_LOW_POWER_STOP             0x1
  54 #define DPLL_LOW_POWER_BYPASS           0x5
  55 #define DPLL_LOCKED                     0x7
  56
  57 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  58         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  59
  60 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  61         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  62
  63 #define OMAP3430_PRM_CLKSEL                                             \
  64         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  65
  66 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  67         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  68
  69 /* PRM CLOCKS */
  70
  71 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  72 static struct clk omap_32k_fck = {
  73         .name           = "omap_32k_fck",
  74         .rate           = 32768,
  75         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .clkdm          = { .name = "prm_clkdm" },
  78         .recalc         = &propagate_rate,
  79 };
  80
  81 static struct clk secure_32k_fck = {
  82         .name           = "secure_32k_fck",
  83         .rate           = 32768,
  84         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  85                                 ALWAYS_ENABLED,
  86         .clkdm          = { .name = "prm_clkdm" },
  87         .recalc         = &propagate_rate,
  88 };
  89
  90 /* Virtual source clocks for osc_sys_ck */
  91 static struct clk virt_12m_ck = {
  92         .name           = "virt_12m_ck",
  93         .rate           = 12000000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .clkdm          = { .name = "prm_clkdm" },
  97         .recalc         = &propagate_rate,
  98 };
  99
 100 static struct clk virt_13m_ck = {
 101         .name           = "virt_13m_ck",
 102         .rate           = 13000000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 104                                 ALWAYS_ENABLED,
 105         .clkdm          = { .name = "prm_clkdm" },
 106         .recalc         = &propagate_rate,
 107 };
 108
 109 static struct clk virt_16_8m_ck = {
 110         .name           = "virt_16_8m_ck",
 111         .rate           = 16800000,
 112         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 113                                 ALWAYS_ENABLED,
 114         .clkdm          = { .name = "prm_clkdm" },
 115         .recalc         = &propagate_rate,
 116 };
 117
 118 static struct clk virt_19_2m_ck = {
 119         .name           = "virt_19_2m_ck",
 120         .rate           = 19200000,
 121         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 122                                 ALWAYS_ENABLED,
 123         .clkdm          = { .name = "prm_clkdm" },
 124         .recalc         = &propagate_rate,
 125 };
 126
 127 static struct clk virt_26m_ck = {
 128         .name           = "virt_26m_ck",
 129         .rate           = 26000000,
 130         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 131                                 ALWAYS_ENABLED,
 132         .clkdm          = { .name = "prm_clkdm" },
 133         .recalc         = &propagate_rate,
 134 };
 135
 136 static struct clk virt_38_4m_ck = {
 137         .name           = "virt_38_4m_ck",
 138         .rate           = 38400000,
 139         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 140                                 ALWAYS_ENABLED,
 141         .clkdm          = { .name = "prm_clkdm" },
 142         .recalc         = &propagate_rate,
 143 };
 144
 145 static const struct clksel_rate osc_sys_12m_rates[] = {
 146         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 147         { .div = 0 }
 148 };
 149
 150 static const struct clksel_rate osc_sys_13m_rates[] = {
 151         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 152         { .div = 0 }
 153 };
 154
 155 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 156         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 161         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 162         { .div = 0 }
 163 };
 164
 165 static const struct clksel_rate osc_sys_26m_rates[] = {
 166         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 167         { .div = 0 }
 168 };
 169
 170 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 171         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel osc_sys_clksel[] = {
 176         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 177         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 178         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 179         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 180         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 181         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 182         { .parent = NULL },
 183 };
 184
 185 /* Oscillator clock */
 186 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 187 static struct clk osc_sys_ck = {
 188         .name           = "osc_sys_ck",
 189         .init           = &omap2_init_clksel_parent,
 190         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 191         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 192         .clksel         = osc_sys_clksel,
 193         /* REVISIT: deal with autoextclkmode? */
 194         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 195                                 ALWAYS_ENABLED,
 196         .clkdm          = { .name = "prm_clkdm" },
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static const struct clksel_rate div2_rates[] = {
 201         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 202         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 203         { .div = 0 }
 204 };
 205
 206 static const struct clksel sys_clksel[] = {
 207         { .parent = &osc_sys_ck, .rates = div2_rates },
 208         { .parent = NULL }
 209 };
 210
 211 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 212 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 213 static struct clk sys_ck = {
 214         .name           = "sys_ck",
 215         .parent         = &osc_sys_ck,
 216         .init           = &omap2_init_clksel_parent,
 217         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 218         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 219         .clksel         = sys_clksel,
 220         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 221         .clkdm          = { .name = "prm_clkdm" },
 222         .recalc         = &omap2_clksel_recalc,
 223 };
 224
 225 static struct clk sys_altclk = {
 226         .name           = "sys_altclk",
 227         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 228         .clkdm          = { .name = "cm_clkdm" },
 229         .recalc         = &propagate_rate,
 230 };
 231
 232 /*
 233  * Optional external clock input for some McBSPs
 234  * Apparently this is not really in prm_clkdm, but rather is fed into
 235  * both CORE and PER separately.
 236  */
 237 static struct clk mcbsp_clks = {
 238         .name           = "mcbsp_clks",
 239         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 240         .clkdm          = { .name = "prm_clkdm" },
 241         .recalc         = &propagate_rate,
 242 };
 243
 244 /* PRM EXTERNAL CLOCK OUTPUT */
 245
 246 static struct clk sys_clkout1 = {
 247         .name           = "sys_clkout1",
 248         .parent         = &osc_sys_ck,
 249         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 250         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 251         .flags          = CLOCK_IN_OMAP343X,
 252         .clkdm          = { .name = "prm_clkdm" },
 253         .recalc         = &followparent_recalc,
 254 };
 255
 256 /* DPLLS */
 257
 258 /* CM CLOCKS */
 259
 260 static const struct clksel_rate dpll_bypass_rates[] = {
 261         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 262         { .div = 0 }
 263 };
 264
 265 static const struct clksel_rate dpll_locked_rates[] = {
 266         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 267         { .div = 0 }
 268 };
 269
 270 static const struct clksel_rate div16_dpll_rates[] = {
 271         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 272         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 273         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 274         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 275         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 276         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 277         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 278         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 279         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 280         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 281         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 282         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 283         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 284         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 285         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 286         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 287         { .div = 0 }
 288 };
 289
 290 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 291         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 292
 293 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 294         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 295
 296 /* DPLL1 */
 297 /* MPU clock source */
 298 /* Type: DPLL */
 299 static struct dpll_data dpll1_dd = {
 300         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 301         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 302         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 303         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 304         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 305         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 306         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 307         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 308         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 309         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 310         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 311         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 312         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 313         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 314         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 315         .max_divider    = OMAP3_MAX_DPLL_DIV,
 316         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 317 };
 318
 319 static struct clk dpll1_ck = {
 320         .name           = "dpll1_ck",
 321         .parent         = &sys_ck,
 322         .dpll_data      = &dpll1_dd,
 323         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 324         .round_rate     = &omap2_dpll_round_rate,
 325         .set_rate       = &omap3_noncore_dpll_set_rate,
 326         .recalc         = &omap3_dpll_recalc,
 327 };
 328
 329 /*
 330  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 331  * DPLL isn't bypassed.
 332  */
 333 static struct clk dpll1_x2_ck = {
 334         .name           = "dpll1_x2_ck",
 335         .parent         = &dpll1_ck,
 336         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 337                                 PARENT_CONTROLS_CLOCK,
 338         .recalc         = &omap3_clkoutx2_recalc,
 339 };
 340
 341 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 342 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 343         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 344         { .parent = NULL }
 345 };
 346
 347 /*
 348  * Does not exist in the TRM - needed to separate the M2 divider from
 349  * bypass selection in mpu_ck
 350  */
 351 static struct clk dpll1_x2m2_ck = {
 352         .name           = "dpll1_x2m2_ck",
 353         .parent         = &dpll1_x2_ck,
 354         .init           = &omap2_init_clksel_parent,
 355         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 356         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 357         .clksel         = div16_dpll1_x2m2_clksel,
 358         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 359                                 PARENT_CONTROLS_CLOCK,
 360         .recalc         = &omap2_clksel_recalc,
 361 };
 362
 363 /* DPLL2 */
 364 /* IVA2 clock source */
 365 /* Type: DPLL */
 366
 367 static struct dpll_data dpll2_dd = {
 368         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 369         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 370         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 371         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 372         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 373         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 374         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 375                                 (1 << DPLL_LOW_POWER_BYPASS),
 376         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 377         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 378         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 379         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 380         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 381         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 382         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 383         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 384         .max_divider    = OMAP3_MAX_DPLL_DIV,
 385         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 386 };
 387
 388 static struct clk dpll2_ck = {
 389         .name           = "dpll2_ck",
 390         .parent         = &sys_ck,
 391         .dpll_data      = &dpll2_dd,
 392         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 393         .enable         = &omap3_noncore_dpll_enable,
 394         .disable        = &omap3_noncore_dpll_disable,
 395         .round_rate     = &omap2_dpll_round_rate,
 396         .set_rate       = &omap3_noncore_dpll_set_rate,
 397         .recalc         = &omap3_dpll_recalc,
 398 };
 399
 400 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 401         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 402         { .parent = NULL }
 403 };
 404
 405 /*
 406  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 407  * or CLKOUTX2. CLKOUT seems most plausible.
 408  */
 409 static struct clk dpll2_m2_ck = {
 410         .name           = "dpll2_m2_ck",
 411         .parent         = &dpll2_ck,
 412         .init           = &omap2_init_clksel_parent,
 413         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 414                                           OMAP3430_CM_CLKSEL2_PLL),
 415         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 416         .clksel         = div16_dpll2_m2x2_clksel,
 417         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 418                                 PARENT_CONTROLS_CLOCK,
 419         .recalc         = &omap2_clksel_recalc,
 420 };
 421
 422 /*
 423  * DPLL3
 424  * Source clock for all interfaces and for some device fclks
 425  * REVISIT: Also supports fast relock bypass - not included below
 426  */
 427 static struct dpll_data dpll3_dd = {
 428         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 429         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 430         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 431         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 432         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 433         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 434         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 435         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 436         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 437         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 438         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 439         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 440         .max_divider    = OMAP3_MAX_DPLL_DIV,
 441         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 442 };
 443
 444 static struct clk dpll3_ck = {
 445         .name           = "dpll3_ck",
 446         .parent         = &sys_ck,
 447         .dpll_data      = &dpll3_dd,
 448         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 449         .round_rate     = &omap2_dpll_round_rate,
 450         .recalc         = &omap3_dpll_recalc,
 451 };
 452
 453 /*
 454  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 455  * DPLL isn't bypassed
 456  */
 457 static struct clk dpll3_x2_ck = {
 458         .name           = "dpll3_x2_ck",
 459         .parent         = &dpll3_ck,
 460         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 461                                 PARENT_CONTROLS_CLOCK,
 462         .recalc         = &omap3_clkoutx2_recalc,
 463 };
 464
 465 static const struct clksel_rate div31_dpll3_rates[] = {
 466         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 467         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 468         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 469         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 470         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 471         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 472         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 473         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 474         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 475         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 476         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 477         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 478         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 479         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 480         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 481         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 482         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 483         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 484         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 485         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 486         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 487         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 488         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 489         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 490         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 491         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 492         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 493         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 494         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 495         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 496         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 497         { .div = 0 },
 498 };
 499
 500 static const struct clksel div31_dpll3m2_clksel[] = {
 501         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 502         { .parent = NULL }
 503 };
 504
 505 /* DPLL3 output M2 - primary control point for CORE speed */
 506 static struct clk dpll3_m2_ck = {
 507         .name           = "dpll3_m2_ck",
 508         .parent         = &dpll3_ck,
 509         .init           = &omap2_init_clksel_parent,
 510         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 511         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 512         .clksel         = div31_dpll3m2_clksel,
 513         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 514                                 PARENT_CONTROLS_CLOCK,
 515         .round_rate     = &omap2_clksel_round_rate,
 516         .set_rate       = &omap3_core_dpll_m2_set_rate,
 517         .recalc         = &omap2_clksel_recalc,
 518 };
 519
 520 static const struct clksel core_ck_clksel[] = {
 521         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 522         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 523         { .parent = NULL }
 524 };
 525
 526 static struct clk core_ck = {
 527         .name           = "core_ck",
 528         .init           = &omap2_init_clksel_parent,
 529         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 530         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 531         .clksel         = core_ck_clksel,
 532         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 533                                 PARENT_CONTROLS_CLOCK,
 534         .clkdm          = { .name = "cm_clkdm" },
 535         .recalc         = &omap2_clksel_recalc,
 536 };
 537
 538 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 539         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 540         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 541         { .parent = NULL }
 542 };
 543
 544 static struct clk dpll3_m2x2_ck = {
 545         .name           = "dpll3_m2x2_ck",
 546         .init           = &omap2_init_clksel_parent,
 547         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 548         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 549         .clksel         = dpll3_m2x2_ck_clksel,
 550         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 551                                 PARENT_CONTROLS_CLOCK,
 552         .recalc         = &omap2_clksel_recalc,
 553 };
 554
 555 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 556 static const struct clksel div16_dpll3_clksel[] = {
 557         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 558         { .parent = NULL }
 559 };
 560
 561 /* This virtual clock is the source for dpll3_m3x2_ck */
 562 static struct clk dpll3_m3_ck = {
 563         .name           = "dpll3_m3_ck",
 564         .parent         = &dpll3_ck,
 565         .init           = &omap2_init_clksel_parent,
 566         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 567         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 568         .clksel         = div16_dpll3_clksel,
 569         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 570                                 PARENT_CONTROLS_CLOCK,
 571         .recalc         = &omap2_clksel_recalc,
 572 };
 573
 574 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 575 static struct clk dpll3_m3x2_ck = {
 576         .name           = "dpll3_m3x2_ck",
 577         .parent         = &dpll3_m3_ck,
 578         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 579         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 580         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 581         .recalc         = &omap3_clkoutx2_recalc,
 582 };
 583
 584 static const struct clksel emu_core_alwon_ck_clksel[] = {
 585         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 586         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 587         { .parent = NULL }
 588 };
 589
 590 static struct clk emu_core_alwon_ck = {
 591         .name           = "emu_core_alwon_ck",
 592         .parent         = &dpll3_m3x2_ck,
 593         .init           = &omap2_init_clksel_parent,
 594         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 595         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 596         .clksel         = emu_core_alwon_ck_clksel,
 597         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 598                                 PARENT_CONTROLS_CLOCK,
 599         .recalc         = &omap2_clksel_recalc,
 600 };
 601
 602 /* DPLL4 */
 603 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 604 /* Type: DPLL */
 605 static struct dpll_data dpll4_dd = {
 606         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 607         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 608         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 609         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 610         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 611         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 612         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 613         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 614         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 615         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 616         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 617         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 618         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 619         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 620         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 621         .max_divider    = OMAP3_MAX_DPLL_DIV,
 622         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 623 };
 624
 625 static struct clk dpll4_ck = {
 626         .name           = "dpll4_ck",
 627         .parent         = &sys_ck,
 628         .dpll_data      = &dpll4_dd,
 629         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 630         .enable         = &omap3_noncore_dpll_enable,
 631         .disable        = &omap3_noncore_dpll_disable,
 632         .round_rate     = &omap2_dpll_round_rate,
 633         .set_rate       = &omap3_noncore_dpll_set_rate,
 634         .recalc         = &omap3_dpll_recalc,
 635 };
 636
 637 /*
 638  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 639  * DPLL isn't bypassed --
 640  * XXX does this serve any downstream clocks?
 641  */
 642 static struct clk dpll4_x2_ck = {
 643         .name           = "dpll4_x2_ck",
 644         .parent         = &dpll4_ck,
 645         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 646                                 PARENT_CONTROLS_CLOCK,
 647         .recalc         = &omap3_clkoutx2_recalc,
 648 };
 649
 650 static const struct clksel div16_dpll4_clksel[] = {
 651         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 652         { .parent = NULL }
 653 };
 654
 655 /* This virtual clock is the source for dpll4_m2x2_ck */
 656 static struct clk dpll4_m2_ck = {
 657         .name           = "dpll4_m2_ck",
 658         .parent         = &dpll4_ck,
 659         .init           = &omap2_init_clksel_parent,
 660         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 661         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 662         .clksel         = div16_dpll4_clksel,
 663         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 664                                 PARENT_CONTROLS_CLOCK,
 665         .recalc         = &omap2_clksel_recalc,
 666 };
 667
 668 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 669 static struct clk dpll4_m2x2_ck = {
 670         .name           = "dpll4_m2x2_ck",
 671         .parent         = &dpll4_m2_ck,
 672         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 673         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 674         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 675         .recalc         = &omap3_clkoutx2_recalc,
 676 };
 677
 678 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 679         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 680         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 681         { .parent = NULL }
 682 };
 683
 684 /*
 685  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 686  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 687  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 688  * CM_96K_(F)CLK.
 689  */
 690 static struct clk omap_96m_alwon_fck = {
 691         .name           = "omap_96m_alwon_fck",
 692         .parent         = &dpll4_m2x2_ck,
 693         .init           = &omap2_init_clksel_parent,
 694         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 695         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 696         .clksel         = omap_96m_alwon_fck_clksel,
 697         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 698                                 PARENT_CONTROLS_CLOCK,
 699         .clkdm          = { .name = "prm_clkdm" },
 700         .recalc         = &omap2_clksel_recalc,
 701 };
 702
 703 static struct clk cm_96m_fck = {
 704         .name           = "cm_96m_fck",
 705         .parent         = &omap_96m_alwon_fck,
 706         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 707                                 PARENT_CONTROLS_CLOCK,
 708         .clkdm          = { .name = "cm_clkdm" },
 709         .recalc         = &followparent_recalc,
 710 };
 711
 712 static const struct clksel_rate omap_96m_dpll_rates[] = {
 713         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 714         { .div = 0 }
 715 };
 716
 717 static const struct clksel_rate omap_96m_sys_rates[] = {
 718         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 719         { .div = 0 }
 720 };
 721
 722 static const struct clksel omap_96m_fck_clksel[] = {
 723         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 724         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 725         { .parent = NULL }
 726 };
 727
 728 static struct clk omap_96m_fck = {
 729         .name           = "omap_96m_fck",
 730         .parent         = &sys_ck,
 731         .init           = &omap2_init_clksel_parent,
 732         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 733         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 734         .clksel         = omap_96m_fck_clksel,
 735         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 736                                 PARENT_CONTROLS_CLOCK,
 737         .clkdm          = { .name = "cm_clkdm" },
 738         .recalc         = &omap2_clksel_recalc,
 739 };
 740
 741 /* This virtual clock is the source for dpll4_m3x2_ck */
 742 static struct clk dpll4_m3_ck = {
 743         .name           = "dpll4_m3_ck",
 744         .parent         = &dpll4_ck,
 745         .init           = &omap2_init_clksel_parent,
 746         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 747         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 748         .clksel         = div16_dpll4_clksel,
 749         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 750                                 PARENT_CONTROLS_CLOCK,
 751         .recalc         = &omap2_clksel_recalc,
 752 };
 753
 754 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 755 static struct clk dpll4_m3x2_ck = {
 756         .name           = "dpll4_m3x2_ck",
 757         .parent         = &dpll4_m3_ck,
 758         .init           = &omap2_init_clksel_parent,
 759         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 760         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 761         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 762         .recalc         = &omap3_clkoutx2_recalc,
 763 };
 764
 765 static const struct clksel virt_omap_54m_fck_clksel[] = {
 766         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 767         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 768         { .parent = NULL }
 769 };
 770
 771 static struct clk virt_omap_54m_fck = {
 772         .name           = "virt_omap_54m_fck",
 773         .parent         = &dpll4_m3x2_ck,
 774         .init           = &omap2_init_clksel_parent,
 775         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 776         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 777         .clksel         = virt_omap_54m_fck_clksel,
 778         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 779                                 PARENT_CONTROLS_CLOCK,
 780         .clkdm          = { .name = "cm_clkdm" },
 781         .recalc         = &omap2_clksel_recalc,
 782 };
 783
 784 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 785         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 786         { .div = 0 }
 787 };
 788
 789 static const struct clksel_rate omap_54m_alt_rates[] = {
 790         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 791         { .div = 0 }
 792 };
 793
 794 static const struct clksel omap_54m_clksel[] = {
 795         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 796         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 797         { .parent = NULL }
 798 };
 799
 800 static struct clk omap_54m_fck = {
 801         .name           = "omap_54m_fck",
 802         .init           = &omap2_init_clksel_parent,
 803         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 804         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 805         .clksel         = omap_54m_clksel,
 806         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 807                                 PARENT_CONTROLS_CLOCK,
 808         .clkdm          = { .name = "cm_clkdm" },
 809         .recalc         = &omap2_clksel_recalc,
 810 };
 811
 812 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 813         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 814         { .div = 0 }
 815 };
 816
 817 static const struct clksel_rate omap_48m_alt_rates[] = {
 818         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 819         { .div = 0 }
 820 };
 821
 822 static const struct clksel omap_48m_clksel[] = {
 823         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 824         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 825         { .parent = NULL }
 826 };
 827
 828 static struct clk omap_48m_fck = {
 829         .name           = "omap_48m_fck",
 830         .init           = &omap2_init_clksel_parent,
 831         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 832         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 833         .clksel         = omap_48m_clksel,
 834         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 835                                 PARENT_CONTROLS_CLOCK,
 836         .clkdm          = { .name = "cm_clkdm" },
 837         .recalc         = &omap2_clksel_recalc,
 838 };
 839
 840 static struct clk omap_12m_fck = {
 841         .name           = "omap_12m_fck",
 842         .parent         = &omap_48m_fck,
 843         .fixed_div      = 4,
 844         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 845                                 PARENT_CONTROLS_CLOCK,
 846         .clkdm          = { .name = "cm_clkdm" },
 847         .recalc         = &omap2_fixed_divisor_recalc,
 848 };
 849
 850 /* This virstual clock is the source for dpll4_m4x2_ck */
 851 static struct clk dpll4_m4_ck = {
 852         .name           = "dpll4_m4_ck",
 853         .parent         = &dpll4_ck,
 854         .init           = &omap2_init_clksel_parent,
 855         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 856         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 857         .clksel         = div16_dpll4_clksel,
 858         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 859                                 PARENT_CONTROLS_CLOCK,
 860         .recalc         = &omap2_clksel_recalc,
 861 };
 862
 863 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 864 static struct clk dpll4_m4x2_ck = {
 865         .name           = "dpll4_m4x2_ck",
 866         .parent         = &dpll4_m4_ck,
 867         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 868         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 869         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 870         .recalc         = &omap3_clkoutx2_recalc,
 871 };
 872
 873 /* This virtual clock is the source for dpll4_m5x2_ck */
 874 static struct clk dpll4_m5_ck = {
 875         .name           = "dpll4_m5_ck",
 876         .parent         = &dpll4_ck,
 877         .init           = &omap2_init_clksel_parent,
 878         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 879         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 880         .clksel         = div16_dpll4_clksel,
 881         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 882                                 PARENT_CONTROLS_CLOCK,
 883         .recalc         = &omap2_clksel_recalc,
 884 };
 885
 886 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 887 static struct clk dpll4_m5x2_ck = {
 888         .name           = "dpll4_m5x2_ck",
 889         .parent         = &dpll4_m5_ck,
 890         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 891         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 892         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 893         .recalc         = &omap3_clkoutx2_recalc,
 894 };
 895
 896 /* This virtual clock is the source for dpll4_m6x2_ck */
 897 static struct clk dpll4_m6_ck = {
 898         .name           = "dpll4_m6_ck",
 899         .parent         = &dpll4_ck,
 900         .init           = &omap2_init_clksel_parent,
 901         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 902         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 903         .clksel         = div16_dpll4_clksel,
 904         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 905                                 PARENT_CONTROLS_CLOCK,
 906         .recalc         = &omap2_clksel_recalc,
 907 };
 908
 909 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 910 static struct clk dpll4_m6x2_ck = {
 911         .name           = "dpll4_m6x2_ck",
 912         .parent         = &dpll4_m6_ck,
 913         .init           = &omap2_init_clksel_parent,
 914         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 915         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 916         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 917         .recalc         = &omap3_clkoutx2_recalc,
 918 };
 919
 920 static struct clk emu_per_alwon_ck = {
 921         .name           = "emu_per_alwon_ck",
 922         .parent         = &dpll4_m6x2_ck,
 923         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 924                                 PARENT_CONTROLS_CLOCK,
 925         .recalc         = &followparent_recalc,
 926 };
 927
 928 /* DPLL5 */
 929 /* Supplies 120MHz clock, USIM source clock */
 930 /* Type: DPLL */
 931 /* 3430ES2 only */
 932 static struct dpll_data dpll5_dd = {
 933         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 934         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 935         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 936         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 937         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 938         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 939         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 940         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 941         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 942         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 943         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 944         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 945         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 946         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 947         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 948         .max_divider    = OMAP3_MAX_DPLL_DIV,
 949         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 950 };
 951
 952 static struct clk dpll5_ck = {
 953         .name           = "dpll5_ck",
 954         .parent         = &sys_ck,
 955         .dpll_data      = &dpll5_dd,
 956         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 957         .enable         = &omap3_noncore_dpll_enable,
 958         .disable        = &omap3_noncore_dpll_disable,
 959         .round_rate     = &omap2_dpll_round_rate,
 960         .set_rate       = &omap3_noncore_dpll_set_rate,
 961         .recalc         = &omap3_dpll_recalc,
 962 };
 963
 964 static const struct clksel div16_dpll5_clksel[] = {
 965         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 966         { .parent = NULL }
 967 };
 968
 969 static struct clk dpll5_m2_ck = {
 970         .name           = "dpll5_m2_ck",
 971         .parent         = &dpll5_ck,
 972         .init           = &omap2_init_clksel_parent,
 973         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 974         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 975         .clksel         = div16_dpll5_clksel,
 976         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 977                                 PARENT_CONTROLS_CLOCK,
 978         .recalc         = &omap2_clksel_recalc,
 979 };
 980
 981 static const struct clksel omap_120m_fck_clksel[] = {
 982         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 983         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 984         { .parent = NULL }
 985 };
 986
 987 static struct clk omap_120m_fck = {
 988         .name           = "omap_120m_fck",
 989         .parent         = &dpll5_m2_ck,
 990         .init           = &omap2_init_clksel_parent,
 991         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 992         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 993         .clksel         = omap_120m_fck_clksel,
 994         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 995                                 PARENT_CONTROLS_CLOCK,
 996         .recalc         = &omap2_clksel_recalc,
 997 };
 998
 999 /* CM EXTERNAL CLOCK OUTPUTS */
1000
1001 static const struct clksel_rate clkout2_src_core_rates[] = {
1002         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1003         { .div = 0 }
1004 };
1005
1006 static const struct clksel_rate clkout2_src_sys_rates[] = {
1007         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1008         { .div = 0 }
1009 };
1010
1011 static const struct clksel_rate clkout2_src_96m_rates[] = {
1012         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1013         { .div = 0 }
1014 };
1015
1016 static const struct clksel_rate clkout2_src_54m_rates[] = {
1017         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1018         { .div = 0 }
1019 };
1020
1021 static const struct clksel clkout2_src_clksel[] = {
1022         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1023         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1024         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1025         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1026         { .parent = NULL }
1027 };
1028
1029 static struct clk clkout2_src_ck = {
1030         .name           = "clkout2_src_ck",
1031         .init           = &omap2_init_clksel_parent,
1032         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1033         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1034         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1035         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1036         .clksel         = clkout2_src_clksel,
1037         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1038         .clkdm          = { .name = "cm_clkdm" },
1039         .recalc         = &omap2_clksel_recalc,
1040 };
1041
1042 static const struct clksel_rate sys_clkout2_rates[] = {
1043         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1044         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1045         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1046         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1047         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1048         { .div = 0 },
1049 };
1050
1051 static const struct clksel sys_clkout2_clksel[] = {
1052         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1053         { .parent = NULL },
1054 };
1055
1056 static struct clk sys_clkout2 = {
1057         .name           = "sys_clkout2",
1058         .init           = &omap2_init_clksel_parent,
1059         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1060         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1061         .clksel         = sys_clkout2_clksel,
1062         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1063         .clkdm          = { .name = "cm_clkdm" },
1064         .recalc         = &omap2_clksel_recalc,
1065 };
1066
1067 /* CM OUTPUT CLOCKS */
1068
1069 static struct clk corex2_fck = {
1070         .name           = "corex2_fck",
1071         .parent         = &dpll3_m2x2_ck,
1072         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1073                                 PARENT_CONTROLS_CLOCK,
1074         .clkdm          = { .name = "cm_clkdm" },
1075         .recalc         = &followparent_recalc,
1076 };
1077
1078 /* DPLL power domain clock controls */
1079
1080 static const struct clksel_rate div4_rates[] = {
1081         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1082         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1083         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1084         { .div = 0 }
1085 };
1086
1087 static const struct clksel div4_core_clksel[] = {
1088         { .parent = &core_ck, .rates = div4_rates },
1089         { .parent = NULL }
1090 };
1091
1092 static struct clk dpll1_fck = {
1093         .name           = "dpll1_fck",
1094         .parent         = &core_ck,
1095         .init           = &omap2_init_clksel_parent,
1096         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1097         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1098         .clksel         = div4_core_clksel,
1099         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1100                                 PARENT_CONTROLS_CLOCK,
1101         .clkdm          = { .name = "cm_clkdm" },
1102         .recalc         = &omap2_clksel_recalc,
1103 };
1104
1105 /*
1106  * MPU clksel:
1107  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1108  * derives from the high-frequency bypass clock originating from DPLL3,
1109  * called 'dpll1_fck'
1110  */
1111 static const struct clksel mpu_clksel[] = {
1112         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1113         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1114         { .parent = NULL }
1115 };
1116
1117 static struct clk mpu_ck = {
1118         .name           = "mpu_ck",
1119         .parent         = &dpll1_x2m2_ck,
1120         .init           = &omap2_init_clksel_parent,
1121         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1122         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1123         .clksel         = mpu_clksel,
1124         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1125                                 PARENT_CONTROLS_CLOCK,
1126         .clkdm          = { .name = "mpu_clkdm" },
1127         .recalc         = &omap2_clksel_recalc,
1128 };
1129
1130 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1131 static const struct clksel_rate arm_fck_rates[] = {
1132         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1133         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1134         { .div = 0 },
1135 };
1136
1137 static const struct clksel arm_fck_clksel[] = {
1138         { .parent = &mpu_ck, .rates = arm_fck_rates },
1139         { .parent = NULL }
1140 };
1141
1142 static struct clk arm_fck = {
1143         .name           = "arm_fck",
1144         .parent         = &mpu_ck,
1145         .init           = &omap2_init_clksel_parent,
1146         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1147         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1148         .clksel         = arm_fck_clksel,
1149         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1150                                 PARENT_CONTROLS_CLOCK,
1151         .recalc         = &omap2_clksel_recalc,
1152 };
1153
1154 /* XXX What about neon_clkdm ? */
1155
1156 /*
1157  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1158  * although it is referenced - so this is a guess
1159  */
1160 static struct clk emu_mpu_alwon_ck = {
1161         .name           = "emu_mpu_alwon_ck",
1162         .parent         = &mpu_ck,
1163         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1164                                 PARENT_CONTROLS_CLOCK,
1165         .recalc         = &followparent_recalc,
1166 };
1167
1168 static struct clk dpll2_fck = {
1169         .name           = "dpll2_fck",
1170         .parent         = &core_ck,
1171         .init           = &omap2_init_clksel_parent,
1172         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1173         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1174         .clksel         = div4_core_clksel,
1175         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1176                                 PARENT_CONTROLS_CLOCK,
1177         .clkdm          = { .name = "cm_clkdm" },
1178         .recalc         = &omap2_clksel_recalc,
1179 };
1180
1181 /*
1182  * IVA2 clksel:
1183  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1184  * derives from the high-frequency bypass clock originating from DPLL3,
1185  * called 'dpll2_fck'
1186  */
1187
1188 static const struct clksel iva2_clksel[] = {
1189         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1190         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1191         { .parent = NULL }
1192 };
1193
1194 static struct clk iva2_ck = {
1195         .name           = "iva2_ck",
1196         .parent         = &dpll2_m2_ck,
1197         .init           = &omap2_init_clksel_parent,
1198         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1199         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1200         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1201                                           OMAP3430_CM_IDLEST_PLL),
1202         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1203         .clksel         = iva2_clksel,
1204         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1205         .clkdm          = { .name = "iva2_clkdm" },
1206         .recalc         = &omap2_clksel_recalc,
1207 };
1208
1209 /* Common interface clocks */
1210
1211 static const struct clksel div2_core_clksel[] = {
1212         { .parent = &core_ck, .rates = div2_rates },
1213         { .parent = NULL }
1214 };
1215
1216 static struct clk l3_ick = {
1217         .name           = "l3_ick",
1218         .parent         = &core_ck,
1219         .init           = &omap2_init_clksel_parent,
1220         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1221         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1222         .clksel         = div2_core_clksel,
1223         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1224                                 PARENT_CONTROLS_CLOCK,
1225         .clkdm          = { .name = "core_l3_clkdm" },
1226         .recalc         = &omap2_clksel_recalc,
1227 };
1228
1229 static const struct clksel div2_l3_clksel[] = {
1230         { .parent = &l3_ick, .rates = div2_rates },
1231         { .parent = NULL }
1232 };
1233
1234 static struct clk l4_ick = {
1235         .name           = "l4_ick",
1236         .parent         = &l3_ick,
1237         .init           = &omap2_init_clksel_parent,
1238         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1239         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1240         .clksel         = div2_l3_clksel,
1241         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1242                                 PARENT_CONTROLS_CLOCK,
1243         .clkdm          = { .name = "core_l4_clkdm" },
1244         .recalc         = &omap2_clksel_recalc,
1245
1246 };
1247
1248 static const struct clksel div2_l4_clksel[] = {
1249         { .parent = &l4_ick, .rates = div2_rates },
1250         { .parent = NULL }
1251 };
1252
1253 static struct clk rm_ick = {
1254         .name           = "rm_ick",
1255         .parent         = &l4_ick,
1256         .init           = &omap2_init_clksel_parent,
1257         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1258         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1259         .clksel         = div2_l4_clksel,
1260         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1261         .clkdm          = { .name = "cm_clkdm" },
1262         .recalc         = &omap2_clksel_recalc,
1263 };
1264
1265 /* GFX power domain */
1266
1267 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1268
1269 static const struct clksel gfx_l3_clksel[] = {
1270         { .parent = &l3_ick, .rates = gfx_l3_rates },
1271         { .parent = NULL }
1272 };
1273
1274 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1275 static struct clk gfx_l3_ck = {
1276         .name           = "gfx_l3_ck",
1277         .parent         = &l3_ick,
1278         .init           = &omap2_init_clksel_parent,
1279         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1280         .enable_bit     = OMAP_EN_GFX_SHIFT,
1281         .flags          = CLOCK_IN_OMAP3430ES1,
1282         .recalc         = &followparent_recalc,
1283 };
1284
1285 static struct clk gfx_l3_fck = {
1286         .name           = "gfx_l3_fck",
1287         .parent         = &gfx_l3_ck,
1288         .init           = &omap2_init_clksel_parent,
1289         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1290         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1291         .clksel         = gfx_l3_clksel,
1292         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1293                                 PARENT_CONTROLS_CLOCK,
1294         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1295         .recalc         = &omap2_clksel_recalc,
1296 };
1297
1298 static struct clk gfx_l3_ick = {
1299         .name           = "gfx_l3_ick",
1300         .parent         = &gfx_l3_ck,
1301         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1302         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1303         .recalc         = &followparent_recalc,
1304 };
1305
1306 static struct clk gfx_cg1_ck = {
1307         .name           = "gfx_cg1_ck",
1308         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1309         .init           = &omap2_init_clk_clkdm,
1310         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1311         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1312         .flags          = CLOCK_IN_OMAP3430ES1,
1313         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1314         .recalc         = &followparent_recalc,
1315 };
1316
1317 static struct clk gfx_cg2_ck = {
1318         .name           = "gfx_cg2_ck",
1319         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1320         .init           = &omap2_init_clk_clkdm,
1321         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1322         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1323         .flags          = CLOCK_IN_OMAP3430ES1,
1324         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1325         .recalc         = &followparent_recalc,
1326 };
1327
1328 /* SGX power domain - 3430ES2 only */
1329
1330 static const struct clksel_rate sgx_core_rates[] = {
1331         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1332         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1333         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1334         { .div = 0 },
1335 };
1336
1337 static const struct clksel_rate sgx_96m_rates[] = {
1338         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1339         { .div = 0 },
1340 };
1341
1342 static const struct clksel sgx_clksel[] = {
1343         { .parent = &core_ck,    .rates = sgx_core_rates },
1344         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1345         { .parent = NULL },
1346 };
1347
1348 static struct clk sgx_fck = {
1349         .name           = "sgx_fck",
1350         .init           = &omap2_init_clksel_parent,
1351         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1352         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1353         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1354         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1355         .clksel         = sgx_clksel,
1356         .flags          = CLOCK_IN_OMAP3430ES2,
1357         .clkdm          = { .name = "sgx_clkdm" },
1358         .recalc         = &omap2_clksel_recalc,
1359 };
1360
1361 static struct clk sgx_ick = {
1362         .name           = "sgx_ick",
1363         .parent         = &l3_ick,
1364         .init           = &omap2_init_clk_clkdm,
1365         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1366         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1367         .flags          = CLOCK_IN_OMAP3430ES2,
1368         .clkdm          = { .name = "sgx_clkdm" },
1369         .recalc         = &followparent_recalc,
1370 };
1371
1372 /* CORE power domain */
1373
1374 static struct clk d2d_26m_fck = {
1375         .name           = "d2d_26m_fck",
1376         .parent         = &sys_ck,
1377         .init           = &omap2_init_clk_clkdm,
1378         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1379         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1380         .flags          = CLOCK_IN_OMAP3430ES1,
1381         .clkdm          = { .name = "d2d_clkdm" },
1382         .recalc         = &followparent_recalc,
1383 };
1384
1385 static const struct clksel omap343x_gpt_clksel[] = {
1386         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1387         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1388         { .parent = NULL}
1389 };
1390
1391 static struct clk gpt10_fck = {
1392         .name           = "gpt10_fck",
1393         .parent         = &sys_ck,
1394         .init           = &omap2_init_clksel_parent,
1395         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1396         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1397         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1398         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1399         .clksel         = omap343x_gpt_clksel,
1400         .flags          = CLOCK_IN_OMAP343X,
1401         .clkdm          = { .name = "core_l4_clkdm" },
1402         .recalc         = &omap2_clksel_recalc,
1403 };
1404
1405 static struct clk gpt11_fck = {
1406         .name           = "gpt11_fck",
1407         .parent         = &sys_ck,
1408         .init           = &omap2_init_clksel_parent,
1409         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1410         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1411         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1412         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1413         .clksel         = omap343x_gpt_clksel,
1414         .flags          = CLOCK_IN_OMAP343X,
1415         .clkdm          = { .name = "core_l4_clkdm" },
1416         .recalc         = &omap2_clksel_recalc,
1417 };
1418
1419 static struct clk cpefuse_fck = {
1420         .name           = "cpefuse_fck",
1421         .parent         = &sys_ck,
1422         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1423         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1424         .flags          = CLOCK_IN_OMAP3430ES2,
1425         .clkdm          = { .name = "cm_clkdm" },
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk ts_fck = {
1430         .name           = "ts_fck",
1431         .parent         = &omap_32k_fck,
1432         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1433         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1434         .flags          = CLOCK_IN_OMAP3430ES2,
1435         .recalc         = &followparent_recalc,
1436 };
1437
1438 static struct clk usbtll_fck = {
1439         .name           = "usbtll_fck",
1440         .parent         = &omap_120m_fck,
1441         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1442         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1443         .flags          = CLOCK_IN_OMAP3430ES2,
1444         .recalc         = &followparent_recalc,
1445 };
1446
1447 /* CORE 96M FCLK-derived clocks */
1448
1449 static struct clk core_96m_fck = {
1450         .name           = "core_96m_fck",
1451         .parent         = &omap_96m_fck,
1452         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1453                                 PARENT_CONTROLS_CLOCK,
1454         .clkdm          = { .name = "core_l4_clkdm" },
1455         .recalc         = &followparent_recalc,
1456 };
1457
1458 static struct clk mmchs3_fck = {
1459         .name           = "mmchs_fck",
1460         .id             = 3,
1461         .parent         = &core_96m_fck,
1462         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1464         .flags          = CLOCK_IN_OMAP3430ES2,
1465         .clkdm          = { .name = "core_l4_clkdm" },
1466         .recalc         = &followparent_recalc,
1467 };
1468
1469 static struct clk mmchs2_fck = {
1470         .name           = "mmchs_fck",
1471         .id             = 2,
1472         .parent         = &core_96m_fck,
1473         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1475         .flags          = CLOCK_IN_OMAP343X,
1476         .clkdm          = { .name = "core_l4_clkdm" },
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 static struct clk mspro_fck = {
1481         .name           = "mspro_fck",
1482         .parent         = &core_96m_fck,
1483         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1484         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1485         .flags          = CLOCK_IN_OMAP343X,
1486         .clkdm          = { .name = "core_l4_clkdm" },
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 static struct clk mmchs1_fck = {
1491         .name           = "mmchs_fck",
1492         .id             = 1,
1493         .parent         = &core_96m_fck,
1494         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1495         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1496         .flags          = CLOCK_IN_OMAP343X,
1497         .clkdm          = { .name = "core_l4_clkdm" },
1498         .recalc         = &followparent_recalc,
1499 };
1500
1501 static struct clk i2c3_fck = {
1502         .name           = "i2c_fck",
1503         .id             = 3,
1504         .parent         = &core_96m_fck,
1505         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1506         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1507         .flags          = CLOCK_IN_OMAP343X,
1508         .clkdm          = { .name = "core_l4_clkdm" },
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static struct clk i2c2_fck = {
1513         .name           = "i2c_fck",
1514         .id             = 2,
1515         .parent         = &core_96m_fck,
1516         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1517         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1518         .flags          = CLOCK_IN_OMAP343X,
1519         .clkdm          = { .name = "core_l4_clkdm" },
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 static struct clk i2c1_fck = {
1524         .name           = "i2c_fck",
1525         .id             = 1,
1526         .parent         = &core_96m_fck,
1527         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1528         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1529         .flags          = CLOCK_IN_OMAP343X,
1530         .clkdm          = { .name = "core_l4_clkdm" },
1531         .recalc         = &followparent_recalc,
1532 };
1533
1534 /*
1535  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1536  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1537  */
1538 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1539         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1540         { .div = 0 }
1541 };
1542
1543 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1544         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1545         { .div = 0 }
1546 };
1547
1548 static const struct clksel mcbsp_15_clksel[] = {
1549         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1550         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1551         { .parent = NULL }
1552 };
1553
1554 static struct clk mcbsp5_fck = {
1555         .name           = "mcbsp_fck",
1556         .id             = 5,
1557         .init           = &omap2_init_clksel_parent,
1558         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1560         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1561         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1562         .clksel         = mcbsp_15_clksel,
1563         .flags          = CLOCK_IN_OMAP343X,
1564         .clkdm          = { .name = "core_l4_clkdm" },
1565         .recalc         = &omap2_clksel_recalc,
1566 };
1567
1568 static struct clk mcbsp1_fck = {
1569         .name           = "mcbsp_fck",
1570         .id             = 1,
1571         .init           = &omap2_init_clksel_parent,
1572         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1573         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1574         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1575         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1576         .clksel         = mcbsp_15_clksel,
1577         .flags          = CLOCK_IN_OMAP343X,
1578         .clkdm          = { .name = "core_l4_clkdm" },
1579         .recalc         = &omap2_clksel_recalc,
1580 };
1581
1582 /* CORE_48M_FCK-derived clocks */
1583
1584 static struct clk core_48m_fck = {
1585         .name           = "core_48m_fck",
1586         .parent         = &omap_48m_fck,
1587         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1588                                 PARENT_CONTROLS_CLOCK,
1589         .clkdm          = { .name = "core_l4_clkdm" },
1590         .recalc         = &followparent_recalc,
1591 };
1592
1593 static struct clk mcspi4_fck = {
1594         .name           = "mcspi_fck",
1595         .id             = 4,
1596         .parent         = &core_48m_fck,
1597         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1598         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1599         .flags          = CLOCK_IN_OMAP343X,
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 static struct clk mcspi3_fck = {
1604         .name           = "mcspi_fck",
1605         .id             = 3,
1606         .parent         = &core_48m_fck,
1607         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1608         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1609         .flags          = CLOCK_IN_OMAP343X,
1610         .recalc         = &followparent_recalc,
1611 };
1612
1613 static struct clk mcspi2_fck = {
1614         .name           = "mcspi_fck",
1615         .id             = 2,
1616         .parent         = &core_48m_fck,
1617         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1618         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1619         .flags          = CLOCK_IN_OMAP343X,
1620         .recalc         = &followparent_recalc,
1621 };
1622
1623 static struct clk mcspi1_fck = {
1624         .name           = "mcspi_fck",
1625         .id             = 1,
1626         .parent         = &core_48m_fck,
1627         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1628         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1629         .flags          = CLOCK_IN_OMAP343X,
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 static struct clk uart2_fck = {
1634         .name           = "uart2_fck",
1635         .parent         = &core_48m_fck,
1636         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1637         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1638         .flags          = CLOCK_IN_OMAP343X,
1639         .recalc         = &followparent_recalc,
1640 };
1641
1642 static struct clk uart1_fck = {
1643         .name           = "uart1_fck",
1644         .parent         = &core_48m_fck,
1645         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1646         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1647         .flags          = CLOCK_IN_OMAP343X,
1648         .recalc         = &followparent_recalc,
1649 };
1650
1651 static struct clk fshostusb_fck = {
1652         .name           = "fshostusb_fck",
1653         .parent         = &core_48m_fck,
1654         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1655         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1656         .flags          = CLOCK_IN_OMAP3430ES1,
1657         .recalc         = &followparent_recalc,
1658 };
1659
1660 /* CORE_12M_FCK based clocks */
1661
1662 static struct clk core_12m_fck = {
1663         .name           = "core_12m_fck",
1664         .parent         = &omap_12m_fck,
1665         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1666                                 PARENT_CONTROLS_CLOCK,
1667         .clkdm          = { .name = "core_l4_clkdm" },
1668         .recalc         = &followparent_recalc,
1669 };
1670
1671 static struct clk hdq_fck = {
1672         .name           = "hdq_fck",
1673         .parent         = &core_12m_fck,
1674         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1675         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1676         .flags          = CLOCK_IN_OMAP343X,
1677         .recalc         = &followparent_recalc,
1678 };
1679
1680 /* DPLL3-derived clock */
1681
1682 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1683         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1684         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1685         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1686         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1687         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1688         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1689         { .div = 0 }
1690 };
1691
1692 static const struct clksel ssi_ssr_clksel[] = {
1693         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1694         { .parent = NULL }
1695 };
1696
1697 static struct clk ssi_ssr_fck = {
1698         .name           = "ssi_ssr_fck",
1699         .init           = &omap2_init_clksel_parent,
1700         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1701         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1702         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1703         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1704         .clksel         = ssi_ssr_clksel,
1705         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1706         .clkdm          = { .name = "core_l4_clkdm" },
1707         .recalc         = &omap2_clksel_recalc,
1708 };
1709
1710 static struct clk ssi_sst_fck = {
1711         .name           = "ssi_sst_fck",
1712         .parent         = &ssi_ssr_fck,
1713         .fixed_div      = 2,
1714         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1715         .recalc         = &omap2_fixed_divisor_recalc,
1716 };
1717
1718
1719
1720 /* CORE_L3_ICK based clocks */
1721
1722 /*
1723  * XXX must add clk_enable/clk_disable for these if standard code won't
1724  * handle it
1725  */
1726 static struct clk core_l3_ick = {
1727         .name           = "core_l3_ick",
1728         .parent         = &l3_ick,
1729         .init           = &omap2_init_clk_clkdm,
1730         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1731                                 PARENT_CONTROLS_CLOCK,
1732         .clkdm          = { .name = "core_l3_clkdm" },
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static struct clk hsotgusb_ick = {
1737         .name           = "hsotgusb_ick",
1738         .parent         = &core_l3_ick,
1739         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1740         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1741         .flags          = CLOCK_IN_OMAP343X,
1742         .clkdm          = { .name = "core_l3_clkdm" },
1743         .recalc         = &followparent_recalc,
1744 };
1745
1746 static struct clk sdrc_ick = {
1747         .name           = "sdrc_ick",
1748         .parent         = &core_l3_ick,
1749         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1750         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1751         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1752         .clkdm          = { .name = "core_l3_clkdm" },
1753         .recalc         = &followparent_recalc,
1754 };
1755
1756 static struct clk gpmc_fck = {
1757         .name           = "gpmc_fck",
1758         .parent         = &core_l3_ick,
1759         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1760                                 ENABLE_ON_INIT,
1761         .clkdm          = { .name = "core_l3_clkdm" },
1762         .recalc         = &followparent_recalc,
1763 };
1764
1765 /* SECURITY_L3_ICK based clocks */
1766
1767 static struct clk security_l3_ick = {
1768         .name           = "security_l3_ick",
1769         .parent         = &l3_ick,
1770         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1771                                 PARENT_CONTROLS_CLOCK,
1772         .recalc         = &followparent_recalc,
1773 };
1774
1775 static struct clk pka_ick = {
1776         .name           = "pka_ick",
1777         .parent         = &security_l3_ick,
1778         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1779         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1780         .flags          = CLOCK_IN_OMAP343X,
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 /* CORE_L4_ICK based clocks */
1785
1786 static struct clk core_l4_ick = {
1787         .name           = "core_l4_ick",
1788         .parent         = &l4_ick,
1789         .init           = &omap2_init_clk_clkdm,
1790         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1791                                 PARENT_CONTROLS_CLOCK,
1792         .clkdm          = { .name = "core_l4_clkdm" },
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk usbtll_ick = {
1797         .name           = "usbtll_ick",
1798         .parent         = &core_l4_ick,
1799         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1800         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1801         .flags          = CLOCK_IN_OMAP3430ES2,
1802         .clkdm          = { .name = "core_l4_clkdm" },
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mmchs3_ick = {
1807         .name           = "mmchs_ick",
1808         .id             = 3,
1809         .parent         = &core_l4_ick,
1810         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1812         .flags          = CLOCK_IN_OMAP3430ES2,
1813         .clkdm          = { .name = "core_l4_clkdm" },
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 /* Intersystem Communication Registers - chassis mode only */
1818 static struct clk icr_ick = {
1819         .name           = "icr_ick",
1820         .parent         = &core_l4_ick,
1821         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1822         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1823         .flags          = CLOCK_IN_OMAP343X,
1824         .clkdm          = { .name = "core_l4_clkdm" },
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk aes2_ick = {
1829         .name           = "aes2_ick",
1830         .parent         = &core_l4_ick,
1831         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1833         .flags          = CLOCK_IN_OMAP343X,
1834         .clkdm          = { .name = "core_l4_clkdm" },
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk sha12_ick = {
1839         .name           = "sha12_ick",
1840         .parent         = &core_l4_ick,
1841         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1843         .flags          = CLOCK_IN_OMAP343X,
1844         .clkdm          = { .name = "core_l4_clkdm" },
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk des2_ick = {
1849         .name           = "des2_ick",
1850         .parent         = &core_l4_ick,
1851         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1852         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1853         .flags          = CLOCK_IN_OMAP343X,
1854         .clkdm          = { .name = "core_l4_clkdm" },
1855         .recalc         = &followparent_recalc,
1856 };
1857
1858 static struct clk mmchs2_ick = {
1859         .name           = "mmchs_ick",
1860         .id             = 2,
1861         .parent         = &core_l4_ick,
1862         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1863         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1864         .flags          = CLOCK_IN_OMAP343X,
1865         .clkdm          = { .name = "core_l4_clkdm" },
1866         .recalc         = &followparent_recalc,
1867 };
1868
1869 static struct clk mmchs1_ick = {
1870         .name           = "mmchs_ick",
1871         .id             = 1,
1872         .parent         = &core_l4_ick,
1873         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1874         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1875         .flags          = CLOCK_IN_OMAP343X,
1876         .clkdm          = { .name = "core_l4_clkdm" },
1877         .recalc         = &followparent_recalc,
1878 };
1879
1880 static struct clk mspro_ick = {
1881         .name           = "mspro_ick",
1882         .parent         = &core_l4_ick,
1883         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1884         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1885         .flags          = CLOCK_IN_OMAP343X,
1886         .clkdm          = { .name = "core_l4_clkdm" },
1887         .recalc         = &followparent_recalc,
1888 };
1889
1890 static struct clk hdq_ick = {
1891         .name           = "hdq_ick",
1892         .parent         = &core_l4_ick,
1893         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1894         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1895         .flags          = CLOCK_IN_OMAP343X,
1896         .clkdm          = { .name = "core_l4_clkdm" },
1897         .recalc         = &followparent_recalc,
1898 };
1899
1900 static struct clk mcspi4_ick = {
1901         .name           = "mcspi_ick",
1902         .id             = 4,
1903         .parent         = &core_l4_ick,
1904         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1905         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1906         .flags          = CLOCK_IN_OMAP343X,
1907         .clkdm          = { .name = "core_l4_clkdm" },
1908         .recalc         = &followparent_recalc,
1909 };
1910
1911 static struct clk mcspi3_ick = {
1912         .name           = "mcspi_ick",
1913         .id             = 3,
1914         .parent         = &core_l4_ick,
1915         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1917         .flags          = CLOCK_IN_OMAP343X,
1918         .clkdm          = { .name = "core_l4_clkdm" },
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk mcspi2_ick = {
1923         .name           = "mcspi_ick",
1924         .id             = 2,
1925         .parent         = &core_l4_ick,
1926         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1928         .flags          = CLOCK_IN_OMAP343X,
1929         .clkdm          = { .name = "core_l4_clkdm" },
1930         .recalc         = &followparent_recalc,
1931 };
1932
1933 static struct clk mcspi1_ick = {
1934         .name           = "mcspi_ick",
1935         .id             = 1,
1936         .parent         = &core_l4_ick,
1937         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1938         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1939         .flags          = CLOCK_IN_OMAP343X,
1940         .clkdm          = { .name = "core_l4_clkdm" },
1941         .recalc         = &followparent_recalc,
1942 };
1943
1944 static struct clk i2c3_ick = {
1945         .name           = "i2c_ick",
1946         .id             = 3,
1947         .parent         = &core_l4_ick,
1948         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1950         .flags          = CLOCK_IN_OMAP343X,
1951         .clkdm          = { .name = "core_l4_clkdm" },
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk i2c2_ick = {
1956         .name           = "i2c_ick",
1957         .id             = 2,
1958         .parent         = &core_l4_ick,
1959         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1960         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1961         .flags          = CLOCK_IN_OMAP343X,
1962         .clkdm          = { .name = "core_l4_clkdm" },
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk i2c1_ick = {
1967         .name           = "i2c_ick",
1968         .id             = 1,
1969         .parent         = &core_l4_ick,
1970         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1971         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1972         .flags          = CLOCK_IN_OMAP343X,
1973         .clkdm          = { .name = "core_l4_clkdm" },
1974         .recalc         = &followparent_recalc,
1975 };
1976
1977 static struct clk uart2_ick = {
1978         .name           = "uart2_ick",
1979         .parent         = &core_l4_ick,
1980         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1981         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1982         .flags          = CLOCK_IN_OMAP343X,
1983         .clkdm          = { .name = "core_l4_clkdm" },
1984         .recalc         = &followparent_recalc,
1985 };
1986
1987 static struct clk uart1_ick = {
1988         .name           = "uart1_ick",
1989         .parent         = &core_l4_ick,
1990         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1991         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1992         .flags          = CLOCK_IN_OMAP343X,
1993         .clkdm          = { .name = "core_l4_clkdm" },
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk gpt11_ick = {
1998         .name           = "gpt11_ick",
1999         .parent         = &core_l4_ick,
2000         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2001         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2002         .flags          = CLOCK_IN_OMAP343X,
2003         .clkdm          = { .name = "core_l4_clkdm" },
2004         .recalc         = &followparent_recalc,
2005 };
2006
2007 static struct clk gpt10_ick = {
2008         .name           = "gpt10_ick",
2009         .parent         = &core_l4_ick,
2010         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2011         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2012         .flags          = CLOCK_IN_OMAP343X,
2013         .clkdm          = { .name = "core_l4_clkdm" },
2014         .recalc         = &followparent_recalc,
2015 };
2016
2017 static struct clk mcbsp5_ick = {
2018         .name           = "mcbsp_ick",
2019         .id             = 5,
2020         .parent         = &core_l4_ick,
2021         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2022         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2023         .flags          = CLOCK_IN_OMAP343X,
2024         .clkdm          = { .name = "core_l4_clkdm" },
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 static struct clk mcbsp1_ick = {
2029         .name           = "mcbsp_ick",
2030         .id             = 1,
2031         .parent         = &core_l4_ick,
2032         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2033         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2034         .flags          = CLOCK_IN_OMAP343X,
2035         .clkdm          = { .name = "core_l4_clkdm" },
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk fac_ick = {
2040         .name           = "fac_ick",
2041         .parent         = &core_l4_ick,
2042         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2043         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2044         .flags          = CLOCK_IN_OMAP3430ES1,
2045         .clkdm          = { .name = "core_l4_clkdm" },
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 static struct clk mailboxes_ick = {
2050         .name           = "mailboxes_ick",
2051         .parent         = &core_l4_ick,
2052         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2053         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2054         .flags          = CLOCK_IN_OMAP343X,
2055         .clkdm          = { .name = "core_l4_clkdm" },
2056         .recalc         = &followparent_recalc,
2057 };
2058
2059 static struct clk omapctrl_ick = {
2060         .name           = "omapctrl_ick",
2061         .parent         = &core_l4_ick,
2062         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2063         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2064         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2065         .recalc         = &followparent_recalc,
2066 };
2067
2068 /* SSI_L4_ICK based clocks */
2069
2070 static struct clk ssi_l4_ick = {
2071         .name           = "ssi_l4_ick",
2072         .parent         = &l4_ick,
2073         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2074                                 PARENT_CONTROLS_CLOCK,
2075         .clkdm          = { .name = "core_l4_clkdm" },
2076         .recalc         = &followparent_recalc,
2077 };
2078
2079 static struct clk ssi_ick = {
2080         .name           = "ssi_ick",
2081         .parent         = &ssi_l4_ick,
2082         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2083         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2084         .flags          = CLOCK_IN_OMAP343X,
2085         .clkdm          = { .name = "core_l4_clkdm" },
2086         .recalc         = &followparent_recalc,
2087 };
2088
2089 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2090  * but l4_ick makes more sense to me */
2091
2092 static const struct clksel usb_l4_clksel[] = {
2093         { .parent = &l4_ick, .rates = div2_rates },
2094         { .parent = NULL },
2095 };
2096
2097 static struct clk usb_l4_ick = {
2098         .name           = "usb_l4_ick",
2099         .parent         = &l4_ick,
2100         .init           = &omap2_init_clksel_parent,
2101         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2102         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2103         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2104         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2105         .clksel         = usb_l4_clksel,
2106         .flags          = CLOCK_IN_OMAP3430ES1,
2107         .recalc         = &omap2_clksel_recalc,
2108 };
2109
2110 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2111
2112 /* SECURITY_L4_ICK2 based clocks */
2113
2114 static struct clk security_l4_ick2 = {
2115         .name           = "security_l4_ick2",
2116         .parent         = &l4_ick,
2117         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2118                                 PARENT_CONTROLS_CLOCK,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk aes1_ick = {
2123         .name           = "aes1_ick",
2124         .parent         = &security_l4_ick2,
2125         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2126         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2127         .flags          = CLOCK_IN_OMAP343X,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk rng_ick = {
2132         .name           = "rng_ick",
2133         .parent         = &security_l4_ick2,
2134         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2135         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2136         .flags          = CLOCK_IN_OMAP343X,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 static struct clk sha11_ick = {
2141         .name           = "sha11_ick",
2142         .parent         = &security_l4_ick2,
2143         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2144         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2145         .flags          = CLOCK_IN_OMAP343X,
2146         .recalc         = &followparent_recalc,
2147 };
2148
2149 static struct clk des1_ick = {
2150         .name           = "des1_ick",
2151         .parent         = &security_l4_ick2,
2152         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2153         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2154         .flags          = CLOCK_IN_OMAP343X,
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 /* DSS */
2159 static const struct clksel dss1_alwon_fck_clksel[] = {
2160         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2161         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2162         { .parent = NULL }
2163 };
2164
2165 static struct clk dss1_alwon_fck = {
2166         .name           = "dss1_alwon_fck",
2167         .parent         = &dpll4_m4x2_ck,
2168         .init           = &omap2_init_clksel_parent,
2169         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2170         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2171         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2172         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2173         .clksel         = dss1_alwon_fck_clksel,
2174         .flags          = CLOCK_IN_OMAP343X,
2175         .clkdm          = { .name = "dss_clkdm" },
2176         .recalc         = &omap2_clksel_recalc,
2177 };
2178
2179 static struct clk dss_tv_fck = {
2180         .name           = "dss_tv_fck",
2181         .parent         = &omap_54m_fck,
2182         .init           = &omap2_init_clk_clkdm,
2183         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2184         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2185         .flags          = CLOCK_IN_OMAP343X,
2186         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2187         .recalc         = &followparent_recalc,
2188 };
2189
2190 static struct clk dss_96m_fck = {
2191         .name           = "dss_96m_fck",
2192         .parent         = &omap_96m_fck,
2193         .init           = &omap2_init_clk_clkdm,
2194         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2195         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2196         .flags          = CLOCK_IN_OMAP343X,
2197         .clkdm          = { .name = "dss_clkdm" },
2198         .recalc         = &followparent_recalc,
2199 };
2200
2201 static struct clk dss2_alwon_fck = {
2202         .name           = "dss2_alwon_fck",
2203         .parent         = &sys_ck,
2204         .init           = &omap2_init_clk_clkdm,
2205         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2206         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2207         .flags          = CLOCK_IN_OMAP343X,
2208         .clkdm          = { .name = "dss_clkdm" },
2209         .recalc         = &followparent_recalc,
2210 };
2211
2212 static struct clk dss_ick = {
2213         /* Handles both L3 and L4 clocks */
2214         .name           = "dss_ick",
2215         .parent         = &l4_ick,
2216         .init           = &omap2_init_clk_clkdm,
2217         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2218         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2219         .flags          = CLOCK_IN_OMAP343X,
2220         .clkdm          = { .name = "dss_clkdm" },
2221         .recalc         = &followparent_recalc,
2222 };
2223
2224 /* CAM */
2225
2226 static const struct clksel cam_mclk_clksel[] = {
2227         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2228         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2229         { .parent = NULL }
2230 };
2231
2232 static struct clk cam_mclk = {
2233         .name           = "cam_mclk",
2234         .parent         = &dpll4_m5x2_ck,
2235         .init           = &omap2_init_clksel_parent,
2236         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2237         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2238         .clksel         = cam_mclk_clksel,
2239         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2240         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2241         .flags          = CLOCK_IN_OMAP343X,
2242         .clkdm          = { .name = "cam_clkdm" },
2243         .recalc         = &omap2_clksel_recalc,
2244 };
2245
2246 static struct clk cam_ick = {
2247         /* Handles both L3 and L4 clocks */
2248         .name           = "cam_ick",
2249         .parent         = &l4_ick,
2250         .init           = &omap2_init_clk_clkdm,
2251         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2252         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2253         .flags          = CLOCK_IN_OMAP343X,
2254         .clkdm          = { .name = "cam_clkdm" },
2255         .recalc         = &followparent_recalc,
2256 };
2257
2258 static struct clk csi2_96m_fck = {
2259         .name           = "csi2_96m_fck",
2260         .parent         = &core_96m_fck,
2261         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2262         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2263         .flags          = CLOCK_IN_OMAP343X,
2264         .clkdm          = { .name = "cam_clkdm" },
2265         .recalc         = &followparent_recalc,
2266 };
2267
2268 /* USBHOST - 3430ES2 only */
2269
2270 static struct clk usbhost_120m_fck = {
2271         .name           = "usbhost_120m_fck",
2272         .parent         = &omap_120m_fck,
2273         .init           = &omap2_init_clk_clkdm,
2274         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2275         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2276         .flags          = CLOCK_IN_OMAP3430ES2,
2277         .clkdm          = { .name = "usbhost_clkdm" },
2278         .recalc         = &followparent_recalc,
2279 };
2280
2281 static struct clk usbhost_48m_fck = {
2282         .name           = "usbhost_48m_fck",
2283         .parent         = &omap_48m_fck,
2284         .init           = &omap2_init_clk_clkdm,
2285         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2286         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2287         .flags          = CLOCK_IN_OMAP3430ES2,
2288         .clkdm          = { .name = "usbhost_clkdm" },
2289         .recalc         = &followparent_recalc,
2290 };
2291
2292 static struct clk usbhost_ick = {
2293         /* Handles both L3 and L4 clocks */
2294         .name           = "usbhost_ick",
2295         .parent         = &l4_ick,
2296         .init           = &omap2_init_clk_clkdm,
2297         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2298         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2299         .flags          = CLOCK_IN_OMAP3430ES2,
2300         .clkdm          = { .name = "usbhost_clkdm" },
2301         .recalc         = &followparent_recalc,
2302 };
2303
2304 /* WKUP */
2305
2306 static const struct clksel_rate usim_96m_rates[] = {
2307         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2308         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2309         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2310         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2311         { .div = 0 },
2312 };
2313
2314 static const struct clksel_rate usim_120m_rates[] = {
2315         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2316         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2317         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2318         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2319         { .div = 0 },
2320 };
2321
2322 static const struct clksel usim_clksel[] = {
2323         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2324         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2325         { .parent = &sys_ck,            .rates = div2_rates },
2326         { .parent = NULL },
2327 };
2328
2329 /* 3430ES2 only */
2330 static struct clk usim_fck = {
2331         .name           = "usim_fck",
2332         .init           = &omap2_init_clksel_parent,
2333         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2334         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2335         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2336         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2337         .clksel         = usim_clksel,
2338         .flags          = CLOCK_IN_OMAP3430ES2,
2339         .clkdm          = { .name = "prm_clkdm" },
2340         .recalc         = &omap2_clksel_recalc,
2341 };
2342
2343 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2344 static struct clk gpt1_fck = {
2345         .name           = "gpt1_fck",
2346         .init           = &omap2_init_clksel_parent,
2347         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2348         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2349         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2350         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2351         .clksel         = omap343x_gpt_clksel,
2352         .flags          = CLOCK_IN_OMAP343X,
2353         .clkdm          = { .name = "prm_clkdm" },
2354         .recalc         = &omap2_clksel_recalc,
2355 };
2356
2357 static struct clk wkup_32k_fck = {
2358         .name           = "wkup_32k_fck",
2359         .init           = &omap2_init_clk_clkdm,
2360         .parent         = &omap_32k_fck,
2361         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2362         .clkdm          = { .name = "prm_clkdm" },
2363         .recalc         = &followparent_recalc,
2364 };
2365
2366 static struct clk gpio1_fck = {
2367         .name           = "gpio1_fck",
2368         .parent         = &wkup_32k_fck,
2369         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2370         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2371         .flags          = CLOCK_IN_OMAP343X,
2372         .clkdm          = { .name = "prm_clkdm" },
2373         .recalc         = &followparent_recalc,
2374 };
2375
2376 static struct clk wdt2_fck = {
2377         .name           = "wdt2_fck",
2378         .parent         = &wkup_32k_fck,
2379         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2380         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2381         .flags          = CLOCK_IN_OMAP343X,
2382         .clkdm          = { .name = "prm_clkdm" },
2383         .recalc         = &followparent_recalc,
2384 };
2385
2386 static struct clk wkup_l4_ick = {
2387         .name           = "wkup_l4_ick",
2388         .parent         = &sys_ck,
2389         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2390         .clkdm          = { .name = "prm_clkdm" },
2391         .recalc         = &followparent_recalc,
2392 };
2393
2394 /* 3430ES2 only */
2395 /* Never specifically named in the TRM, so we have to infer a likely name */
2396 static struct clk usim_ick = {
2397         .name           = "usim_ick",
2398         .parent         = &wkup_l4_ick,
2399         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2400         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2401         .flags          = CLOCK_IN_OMAP3430ES2,
2402         .clkdm          = { .name = "prm_clkdm" },
2403         .recalc         = &followparent_recalc,
2404 };
2405
2406 static struct clk wdt2_ick = {
2407         .name           = "wdt2_ick",
2408         .parent         = &wkup_l4_ick,
2409         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2410         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2411         .flags          = CLOCK_IN_OMAP343X,
2412         .clkdm          = { .name = "prm_clkdm" },
2413         .recalc         = &followparent_recalc,
2414 };
2415
2416 static struct clk wdt1_ick = {
2417         .name           = "wdt1_ick",
2418         .parent         = &wkup_l4_ick,
2419         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2420         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2421         .flags          = CLOCK_IN_OMAP343X,
2422         .clkdm          = { .name = "prm_clkdm" },
2423         .recalc         = &followparent_recalc,
2424 };
2425
2426 static struct clk gpio1_ick = {
2427         .name           = "gpio1_ick",
2428         .parent         = &wkup_l4_ick,
2429         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2430         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2431         .flags          = CLOCK_IN_OMAP343X,
2432         .clkdm          = { .name = "prm_clkdm" },
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk omap_32ksync_ick = {
2437         .name           = "omap_32ksync_ick",
2438         .parent         = &wkup_l4_ick,
2439         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2440         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2441         .flags          = CLOCK_IN_OMAP343X,
2442         .clkdm          = { .name = "prm_clkdm" },
2443         .recalc         = &followparent_recalc,
2444 };
2445
2446 static struct clk gpt12_ick = {
2447         .name           = "gpt12_ick",
2448         .parent         = &wkup_l4_ick,
2449         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2450         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2451         .flags          = CLOCK_IN_OMAP343X,
2452         .clkdm          = { .name = "prm_clkdm" },
2453         .recalc         = &followparent_recalc,
2454 };
2455
2456 static struct clk gpt1_ick = {
2457         .name           = "gpt1_ick",
2458         .parent         = &wkup_l4_ick,
2459         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2460         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2461         .flags          = CLOCK_IN_OMAP343X,
2462         .clkdm          = { .name = "prm_clkdm" },
2463         .recalc         = &followparent_recalc,
2464 };
2465
2466
2467
2468 /* PER clock domain */
2469
2470 static struct clk per_96m_fck = {
2471         .name           = "per_96m_fck",
2472         .parent         = &omap_96m_alwon_fck,
2473         .init           = &omap2_init_clk_clkdm,
2474         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2475                                 PARENT_CONTROLS_CLOCK,
2476         .clkdm          = { .name = "per_clkdm" },
2477         .recalc         = &followparent_recalc,
2478 };
2479
2480 static struct clk per_48m_fck = {
2481         .name           = "per_48m_fck",
2482         .parent         = &omap_48m_fck,
2483         .init           = &omap2_init_clk_clkdm,
2484         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2485                                 PARENT_CONTROLS_CLOCK,
2486         .clkdm          = { .name = "per_clkdm" },
2487         .recalc         = &followparent_recalc,
2488 };
2489
2490 static struct clk uart3_fck = {
2491         .name           = "uart3_fck",
2492         .parent         = &per_48m_fck,
2493         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2494         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2495         .flags          = CLOCK_IN_OMAP343X,
2496         .clkdm          = { .name = "per_clkdm" },
2497         .recalc         = &followparent_recalc,
2498 };
2499
2500 static struct clk gpt2_fck = {
2501         .name           = "gpt2_fck",
2502         .init           = &omap2_init_clksel_parent,
2503         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2504         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2505         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2506         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2507         .clksel         = omap343x_gpt_clksel,
2508         .flags          = CLOCK_IN_OMAP343X,
2509         .clkdm          = { .name = "per_clkdm" },
2510         .recalc         = &omap2_clksel_recalc,
2511 };
2512
2513 static struct clk gpt3_fck = {
2514         .name           = "gpt3_fck",
2515         .init           = &omap2_init_clksel_parent,
2516         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2517         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2518         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2519         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2520         .clksel         = omap343x_gpt_clksel,
2521         .flags          = CLOCK_IN_OMAP343X,
2522         .clkdm          = { .name = "per_clkdm" },
2523         .recalc         = &omap2_clksel_recalc,
2524 };
2525
2526 static struct clk gpt4_fck = {
2527         .name           = "gpt4_fck",
2528         .init           = &omap2_init_clksel_parent,
2529         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2530         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2531         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2532         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2533         .clksel         = omap343x_gpt_clksel,
2534         .flags          = CLOCK_IN_OMAP343X,
2535         .clkdm          = { .name = "per_clkdm" },
2536         .recalc         = &omap2_clksel_recalc,
2537 };
2538
2539 static struct clk gpt5_fck = {
2540         .name           = "gpt5_fck",
2541         .init           = &omap2_init_clksel_parent,
2542         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2543         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2544         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2545         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2546         .clksel         = omap343x_gpt_clksel,
2547         .flags          = CLOCK_IN_OMAP343X,
2548         .clkdm          = { .name = "per_clkdm" },
2549         .recalc         = &omap2_clksel_recalc,
2550 };
2551
2552 static struct clk gpt6_fck = {
2553         .name           = "gpt6_fck",
2554         .init           = &omap2_init_clksel_parent,
2555         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2556         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2557         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2558         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2559         .clksel         = omap343x_gpt_clksel,
2560         .flags          = CLOCK_IN_OMAP343X,
2561         .clkdm          = { .name = "per_clkdm" },
2562         .recalc         = &omap2_clksel_recalc,
2563 };
2564
2565 static struct clk gpt7_fck = {
2566         .name           = "gpt7_fck",
2567         .init           = &omap2_init_clksel_parent,
2568         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2569         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2570         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2571         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2572         .clksel         = omap343x_gpt_clksel,
2573         .flags          = CLOCK_IN_OMAP343X,
2574         .clkdm          = { .name = "per_clkdm" },
2575         .recalc         = &omap2_clksel_recalc,
2576 };
2577
2578 static struct clk gpt8_fck = {
2579         .name           = "gpt8_fck",
2580         .init           = &omap2_init_clksel_parent,
2581         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2582         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2583         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2584         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2585         .clksel         = omap343x_gpt_clksel,
2586         .flags          = CLOCK_IN_OMAP343X,
2587         .clkdm          = { .name = "per_clkdm" },
2588         .recalc         = &omap2_clksel_recalc,
2589 };
2590
2591 static struct clk gpt9_fck = {
2592         .name           = "gpt9_fck",
2593         .init           = &omap2_init_clksel_parent,
2594         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2595         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2596         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2597         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2598         .clksel         = omap343x_gpt_clksel,
2599         .flags          = CLOCK_IN_OMAP343X,
2600         .clkdm          = { .name = "per_clkdm" },
2601         .recalc         = &omap2_clksel_recalc,
2602 };
2603
2604 static struct clk per_32k_alwon_fck = {
2605         .name           = "per_32k_alwon_fck",
2606         .parent         = &omap_32k_fck,
2607         .clkdm          = { .name = "per_clkdm" },
2608         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2609         .recalc         = &followparent_recalc,
2610 };
2611
2612 static struct clk gpio6_fck = {
2613         .name           = "gpio6_fck",
2614         .parent         = &per_32k_alwon_fck,
2615         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2616         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2617         .flags          = CLOCK_IN_OMAP343X,
2618         .clkdm          = { .name = "per_clkdm" },
2619         .recalc         = &followparent_recalc,
2620 };
2621
2622 static struct clk gpio5_fck = {
2623         .name           = "gpio5_fck",
2624         .parent         = &per_32k_alwon_fck,
2625         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2626         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2627         .flags          = CLOCK_IN_OMAP343X,
2628         .clkdm          = { .name = "per_clkdm" },
2629         .recalc         = &followparent_recalc,
2630 };
2631
2632 static struct clk gpio4_fck = {
2633         .name           = "gpio4_fck",
2634         .parent         = &per_32k_alwon_fck,
2635         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2636         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2637         .flags          = CLOCK_IN_OMAP343X,
2638         .clkdm          = { .name = "per_clkdm" },
2639         .recalc         = &followparent_recalc,
2640 };
2641
2642 static struct clk gpio3_fck = {
2643         .name           = "gpio3_fck",
2644         .parent         = &per_32k_alwon_fck,
2645         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2646         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2647         .flags          = CLOCK_IN_OMAP343X,
2648         .clkdm          = { .name = "per_clkdm" },
2649         .recalc         = &followparent_recalc,
2650 };
2651
2652 static struct clk gpio2_fck = {
2653         .name           = "gpio2_fck",
2654         .parent         = &per_32k_alwon_fck,
2655         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2656         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2657         .flags          = CLOCK_IN_OMAP343X,
2658         .clkdm          = { .name = "per_clkdm" },
2659         .recalc         = &followparent_recalc,
2660 };
2661
2662 static struct clk wdt3_fck = {
2663         .name           = "wdt3_fck",
2664         .parent         = &per_32k_alwon_fck,
2665         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2666         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2667         .flags          = CLOCK_IN_OMAP343X,
2668         .clkdm          = { .name = "per_clkdm" },
2669         .recalc         = &followparent_recalc,
2670 };
2671
2672 static struct clk per_l4_ick = {
2673         .name           = "per_l4_ick",
2674         .parent         = &l4_ick,
2675         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2676                                 PARENT_CONTROLS_CLOCK,
2677         .clkdm          = { .name = "per_clkdm" },
2678         .recalc         = &followparent_recalc,
2679 };
2680
2681 static struct clk gpio6_ick = {
2682         .name           = "gpio6_ick",
2683         .parent         = &per_l4_ick,
2684         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2685         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2686         .flags          = CLOCK_IN_OMAP343X,
2687         .clkdm          = { .name = "per_clkdm" },
2688         .recalc         = &followparent_recalc,
2689 };
2690
2691 static struct clk gpio5_ick = {
2692         .name           = "gpio5_ick",
2693         .parent         = &per_l4_ick,
2694         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2695         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2696         .flags          = CLOCK_IN_OMAP343X,
2697         .clkdm          = { .name = "per_clkdm" },
2698         .recalc         = &followparent_recalc,
2699 };
2700
2701 static struct clk gpio4_ick = {
2702         .name           = "gpio4_ick",
2703         .parent         = &per_l4_ick,
2704         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2705         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2706         .flags          = CLOCK_IN_OMAP343X,
2707         .clkdm          = { .name = "per_clkdm" },
2708         .recalc         = &followparent_recalc,
2709 };
2710
2711 static struct clk gpio3_ick = {
2712         .name           = "gpio3_ick",
2713         .parent         = &per_l4_ick,
2714         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2715         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2716         .flags          = CLOCK_IN_OMAP343X,
2717         .clkdm          = { .name = "per_clkdm" },
2718         .recalc         = &followparent_recalc,
2719 };
2720
2721 static struct clk gpio2_ick = {
2722         .name           = "gpio2_ick",
2723         .parent         = &per_l4_ick,
2724         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2725         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2726         .flags          = CLOCK_IN_OMAP343X,
2727         .clkdm          = { .name = "per_clkdm" },
2728         .recalc         = &followparent_recalc,
2729 };
2730
2731 static struct clk wdt3_ick = {
2732         .name           = "wdt3_ick",
2733         .parent         = &per_l4_ick,
2734         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2735         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2736         .flags          = CLOCK_IN_OMAP343X,
2737         .clkdm          = { .name = "per_clkdm" },
2738         .recalc         = &followparent_recalc,
2739 };
2740
2741 static struct clk uart3_ick = {
2742         .name           = "uart3_ick",
2743         .parent         = &per_l4_ick,
2744         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2745         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2746         .flags          = CLOCK_IN_OMAP343X,
2747         .clkdm          = { .name = "per_clkdm" },
2748         .recalc         = &followparent_recalc,
2749 };
2750
2751 static struct clk gpt9_ick = {
2752         .name           = "gpt9_ick",
2753         .parent         = &per_l4_ick,
2754         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2755         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2756         .flags          = CLOCK_IN_OMAP343X,
2757         .clkdm          = { .name = "per_clkdm" },
2758         .recalc         = &followparent_recalc,
2759 };
2760
2761 static struct clk gpt8_ick = {
2762         .name           = "gpt8_ick",
2763         .parent         = &per_l4_ick,
2764         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2765         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2766         .flags          = CLOCK_IN_OMAP343X,
2767         .clkdm          = { .name = "per_clkdm" },
2768         .recalc         = &followparent_recalc,
2769 };
2770
2771 static struct clk gpt7_ick = {
2772         .name           = "gpt7_ick",
2773         .parent         = &per_l4_ick,
2774         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2775         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2776         .flags          = CLOCK_IN_OMAP343X,
2777         .clkdm          = { .name = "per_clkdm" },
2778         .recalc         = &followparent_recalc,
2779 };
2780
2781 static struct clk gpt6_ick = {
2782         .name           = "gpt6_ick",
2783         .parent         = &per_l4_ick,
2784         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2785         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2786         .flags          = CLOCK_IN_OMAP343X,
2787         .clkdm          = { .name = "per_clkdm" },
2788         .recalc         = &followparent_recalc,
2789 };
2790
2791 static struct clk gpt5_ick = {
2792         .name           = "gpt5_ick",
2793         .parent         = &per_l4_ick,
2794         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2795         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2796         .flags          = CLOCK_IN_OMAP343X,
2797         .clkdm          = { .name = "per_clkdm" },
2798         .recalc         = &followparent_recalc,
2799 };
2800
2801 static struct clk gpt4_ick = {
2802         .name           = "gpt4_ick",
2803         .parent         = &per_l4_ick,
2804         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2805         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2806         .flags          = CLOCK_IN_OMAP343X,
2807         .clkdm          = { .name = "per_clkdm" },
2808         .recalc         = &followparent_recalc,
2809 };
2810
2811 static struct clk gpt3_ick = {
2812         .name           = "gpt3_ick",
2813         .parent         = &per_l4_ick,
2814         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2815         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2816         .flags          = CLOCK_IN_OMAP343X,
2817         .clkdm          = { .name = "per_clkdm" },
2818         .recalc         = &followparent_recalc,
2819 };
2820
2821 static struct clk gpt2_ick = {
2822         .name           = "gpt2_ick",
2823         .parent         = &per_l4_ick,
2824         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2825         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2826         .flags          = CLOCK_IN_OMAP343X,
2827         .clkdm          = { .name = "per_clkdm" },
2828         .recalc         = &followparent_recalc,
2829 };
2830
2831 static struct clk mcbsp2_ick = {
2832         .name           = "mcbsp_ick",
2833         .id             = 2,
2834         .parent         = &per_l4_ick,
2835         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2836         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2837         .flags          = CLOCK_IN_OMAP343X,
2838         .clkdm          = { .name = "per_clkdm" },
2839         .recalc         = &followparent_recalc,
2840 };
2841
2842 static struct clk mcbsp3_ick = {
2843         .name           = "mcbsp_ick",
2844         .id             = 3,
2845         .parent         = &per_l4_ick,
2846         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2847         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2848         .flags          = CLOCK_IN_OMAP343X,
2849         .clkdm          = { .name = "per_clkdm" },
2850         .recalc         = &followparent_recalc,
2851 };
2852
2853 static struct clk mcbsp4_ick = {
2854         .name           = "mcbsp_ick",
2855         .id             = 4,
2856         .parent         = &per_l4_ick,
2857         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2858         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2859         .flags          = CLOCK_IN_OMAP343X,
2860         .clkdm          = { .name = "per_clkdm" },
2861         .recalc         = &followparent_recalc,
2862 };
2863
2864 static const struct clksel mcbsp_234_clksel[] = {
2865         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2866         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2867         { .parent = NULL }
2868 };
2869
2870 static struct clk mcbsp2_fck = {
2871         .name           = "mcbsp_fck",
2872         .id             = 2,
2873         .init           = &omap2_init_clksel_parent,
2874         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2875         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2876         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2877         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2878         .clksel         = mcbsp_234_clksel,
2879         .flags          = CLOCK_IN_OMAP343X,
2880         .clkdm          = { .name = "per_clkdm" },
2881         .recalc         = &omap2_clksel_recalc,
2882 };
2883
2884 static struct clk mcbsp3_fck = {
2885         .name           = "mcbsp_fck",
2886         .id             = 3,
2887         .init           = &omap2_init_clksel_parent,
2888         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2889         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2890         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2891         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2892         .clksel         = mcbsp_234_clksel,
2893         .flags          = CLOCK_IN_OMAP343X,
2894         .clkdm          = { .name = "per_clkdm" },
2895         .recalc         = &omap2_clksel_recalc,
2896 };
2897
2898 static struct clk mcbsp4_fck = {
2899         .name           = "mcbsp_fck",
2900         .id             = 4,
2901         .init           = &omap2_init_clksel_parent,
2902         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2903         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2904         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2905         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2906         .clksel         = mcbsp_234_clksel,
2907         .flags          = CLOCK_IN_OMAP343X,
2908         .clkdm          = { .name = "per_clkdm" },
2909         .recalc         = &omap2_clksel_recalc,
2910 };
2911
2912 /* EMU clocks */
2913
2914 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2915
2916 static const struct clksel_rate emu_src_sys_rates[] = {
2917         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2918         { .div = 0 },
2919 };
2920
2921 static const struct clksel_rate emu_src_core_rates[] = {
2922         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2923         { .div = 0 },
2924 };
2925
2926 static const struct clksel_rate emu_src_per_rates[] = {
2927         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2928         { .div = 0 },
2929 };
2930
2931 static const struct clksel_rate emu_src_mpu_rates[] = {
2932         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2933         { .div = 0 },
2934 };
2935
2936 static const struct clksel emu_src_clksel[] = {
2937         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2938         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2939         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2940         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2941         { .parent = NULL },
2942 };
2943
2944 /*
2945  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2946  * to switch the source of some of the EMU clocks.
2947  * XXX Are there CLKEN bits for these EMU clks?
2948  */
2949 static struct clk emu_src_ck = {
2950         .name           = "emu_src_ck",
2951         .init           = &omap2_init_clksel_parent,
2952         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2953         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2954         .clksel         = emu_src_clksel,
2955         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2956         .clkdm          = { .name = "emu_clkdm" },
2957         .recalc         = &omap2_clksel_recalc,
2958 };
2959
2960 static const struct clksel_rate pclk_emu_rates[] = {
2961         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2962         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2963         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2964         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2965         { .div = 0 },
2966 };
2967
2968 static const struct clksel pclk_emu_clksel[] = {
2969         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2970         { .parent = NULL },
2971 };
2972
2973 static struct clk pclk_fck = {
2974         .name           = "pclk_fck",
2975         .init           = &omap2_init_clksel_parent,
2976         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2977         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2978         .clksel         = pclk_emu_clksel,
2979         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2980         .clkdm          = { .name = "emu_clkdm" },
2981         .recalc         = &omap2_clksel_recalc,
2982 };
2983
2984 static const struct clksel_rate pclkx2_emu_rates[] = {
2985         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2986         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2987         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2988         { .div = 0 },
2989 };
2990
2991 static const struct clksel pclkx2_emu_clksel[] = {
2992         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2993         { .parent = NULL },
2994 };
2995
2996 static struct clk pclkx2_fck = {
2997         .name           = "pclkx2_fck",
2998         .init           = &omap2_init_clksel_parent,
2999         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3000         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3001         .clksel         = pclkx2_emu_clksel,
3002         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3003         .clkdm          = { .name = "emu_clkdm" },
3004         .recalc         = &omap2_clksel_recalc,
3005 };
3006
3007 static const struct clksel atclk_emu_clksel[] = {
3008         { .parent = &emu_src_ck, .rates = div2_rates },
3009         { .parent = NULL },
3010 };
3011
3012 static struct clk atclk_fck = {
3013         .name           = "atclk_fck",
3014         .init           = &omap2_init_clksel_parent,
3015         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3016         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3017         .clksel         = atclk_emu_clksel,
3018         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3019         .clkdm          = { .name = "emu_clkdm" },
3020         .recalc         = &omap2_clksel_recalc,
3021 };
3022
3023 static struct clk traceclk_src_fck = {
3024         .name           = "traceclk_src_fck",
3025         .init           = &omap2_init_clksel_parent,
3026         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3027         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3028         .clksel         = emu_src_clksel,
3029         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3030         .clkdm          = { .name = "emu_clkdm" },
3031         .recalc         = &omap2_clksel_recalc,
3032 };
3033
3034 static const struct clksel_rate traceclk_rates[] = {
3035         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3036         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3037         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3038         { .div = 0 },
3039 };
3040
3041 static const struct clksel traceclk_clksel[] = {
3042         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3043         { .parent = NULL },
3044 };
3045
3046 static struct clk traceclk_fck = {
3047         .name           = "traceclk_fck",
3048         .init           = &omap2_init_clksel_parent,
3049         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3050         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3051         .clksel         = traceclk_clksel,
3052         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3053         .clkdm          = { .name = "emu_clkdm" },
3054         .recalc         = &omap2_clksel_recalc,
3055 };
3056
3057 /* SR clocks */
3058
3059 /* SmartReflex fclk (VDD1) */
3060 static struct clk sr1_fck = {
3061         .name           = "sr1_fck",
3062         .parent         = &sys_ck,
3063         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3064         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3065         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3066         .clkdm          = { .name = "prm_clkdm" },
3067         .recalc         = &followparent_recalc,
3068 };
3069
3070 /* SmartReflex fclk (VDD2) */
3071 static struct clk sr2_fck = {
3072         .name           = "sr2_fck",
3073         .parent         = &sys_ck,
3074         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3075         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3076         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3077         .clkdm          = { .name = "prm_clkdm" },
3078         .recalc         = &followparent_recalc,
3079 };
3080
3081 static struct clk sr_l4_ick = {
3082         .name           = "sr_l4_ick",
3083         .parent         = &l4_ick,
3084         .flags          = CLOCK_IN_OMAP343X,
3085         .clkdm          = { .name = "core_l4_clkdm" },
3086         .recalc         = &followparent_recalc,
3087 };
3088
3089 /* SECURE_32K_FCK clocks */
3090
3091 /* XXX This clock no longer exists in 3430 TRM rev F */
3092 static struct clk gpt12_fck = {
3093         .name           = "gpt12_fck",
3094         .parent         = &secure_32k_fck,
3095         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3096         .clkdm          = { .name = "prm_clkdm" },
3097         .recalc         = &followparent_recalc,
3098 };
3099
3100 static struct clk wdt1_fck = {
3101         .name           = "wdt1_fck",
3102         .parent         = &secure_32k_fck,
3103         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3104         .clkdm          = { .name = "prm_clkdm" },
3105         .recalc         = &followparent_recalc,
3106 };
3107
3108 static struct clk *onchip_34xx_clks[] __initdata = {
3109         &omap_32k_fck,
3110         &virt_12m_ck,
3111         &virt_13m_ck,
3112         &virt_16_8m_ck,
3113         &virt_19_2m_ck,
3114         &virt_26m_ck,
3115         &virt_38_4m_ck,
3116         &osc_sys_ck,
3117         &sys_ck,
3118         &sys_altclk,
3119         &mcbsp_clks,
3120         &sys_clkout1,
3121         &dpll1_ck,
3122         &dpll1_x2_ck,
3123         &dpll1_x2m2_ck,
3124         &dpll2_ck,
3125         &dpll2_m2_ck,
3126         &dpll3_ck,
3127         &core_ck,
3128         &dpll3_x2_ck,
3129         &dpll3_m2_ck,
3130         &dpll3_m2x2_ck,
3131         &dpll3_m3_ck,
3132         &dpll3_m3x2_ck,
3133         &emu_core_alwon_ck,
3134         &dpll4_ck,
3135         &dpll4_x2_ck,
3136         &omap_96m_alwon_fck,
3137         &omap_96m_fck,
3138         &cm_96m_fck,
3139         &virt_omap_54m_fck,
3140         &omap_54m_fck,
3141         &omap_48m_fck,
3142         &omap_12m_fck,
3143         &dpll4_m2_ck,
3144         &dpll4_m2x2_ck,
3145         &dpll4_m3_ck,
3146         &dpll4_m3x2_ck,
3147         &dpll4_m4_ck,
3148         &dpll4_m4x2_ck,
3149         &dpll4_m5_ck,
3150         &dpll4_m5x2_ck,
3151         &dpll4_m6_ck,
3152         &dpll4_m6x2_ck,
3153         &emu_per_alwon_ck,
3154         &dpll5_ck,
3155         &dpll5_m2_ck,
3156         &omap_120m_fck,
3157         &clkout2_src_ck,
3158         &sys_clkout2,
3159         &corex2_fck,
3160         &dpll1_fck,
3161         &mpu_ck,
3162         &arm_fck,
3163         &emu_mpu_alwon_ck,
3164         &dpll2_fck,
3165         &iva2_ck,
3166         &l3_ick,
3167         &l4_ick,
3168         &rm_ick,
3169         &gfx_l3_ck,
3170         &gfx_l3_fck,
3171         &gfx_l3_ick,
3172         &gfx_cg1_ck,
3173         &gfx_cg2_ck,
3174         &sgx_fck,
3175         &sgx_ick,
3176         &d2d_26m_fck,
3177         &gpt10_fck,
3178         &gpt11_fck,
3179         &cpefuse_fck,
3180         &ts_fck,
3181         &usbtll_fck,
3182         &core_96m_fck,
3183         &mmchs3_fck,
3184         &mmchs2_fck,
3185         &mspro_fck,
3186         &mmchs1_fck,
3187         &i2c3_fck,
3188         &i2c2_fck,
3189         &i2c1_fck,
3190         &mcbsp5_fck,
3191         &mcbsp1_fck,
3192         &core_48m_fck,
3193         &mcspi4_fck,
3194         &mcspi3_fck,
3195         &mcspi2_fck,
3196         &mcspi1_fck,
3197         &uart2_fck,
3198         &uart1_fck,
3199         &fshostusb_fck,
3200         &core_12m_fck,
3201         &hdq_fck,
3202         &ssi_ssr_fck,
3203         &ssi_sst_fck,
3204         &core_l3_ick,
3205         &hsotgusb_ick,
3206         &sdrc_ick,
3207         &gpmc_fck,
3208         &security_l3_ick,
3209         &pka_ick,
3210         &core_l4_ick,
3211         &usbtll_ick,
3212         &mmchs3_ick,
3213         &icr_ick,
3214         &aes2_ick,
3215         &sha12_ick,
3216         &des2_ick,
3217         &mmchs2_ick,
3218         &mmchs1_ick,
3219         &mspro_ick,
3220         &hdq_ick,
3221         &mcspi4_ick,
3222         &mcspi3_ick,
3223         &mcspi2_ick,
3224         &mcspi1_ick,
3225         &i2c3_ick,
3226         &i2c2_ick,
3227         &i2c1_ick,
3228         &uart2_ick,
3229         &uart1_ick,
3230         &gpt11_ick,
3231         &gpt10_ick,
3232         &mcbsp5_ick,
3233         &mcbsp1_ick,
3234         &fac_ick,
3235         &mailboxes_ick,
3236         &omapctrl_ick,
3237         &ssi_l4_ick,
3238         &ssi_ick,
3239         &usb_l4_ick,
3240         &security_l4_ick2,
3241         &aes1_ick,
3242         &rng_ick,
3243         &sha11_ick,
3244         &des1_ick,
3245         &dss1_alwon_fck,
3246         &dss_tv_fck,
3247         &dss_96m_fck,
3248         &dss2_alwon_fck,
3249         &dss_ick,
3250         &cam_mclk,
3251         &cam_ick,
3252         &csi2_96m_fck,
3253         &usbhost_120m_fck,
3254         &usbhost_48m_fck,
3255         &usbhost_ick,
3256         &usim_fck,
3257         &gpt1_fck,
3258         &wkup_32k_fck,
3259         &gpio1_fck,
3260         &wdt2_fck,
3261         &wkup_l4_ick,
3262         &usim_ick,
3263         &wdt2_ick,
3264         &wdt1_ick,
3265         &gpio1_ick,
3266         &omap_32ksync_ick,
3267         &gpt12_ick,
3268         &gpt1_ick,
3269         &per_96m_fck,
3270         &per_48m_fck,
3271         &uart3_fck,
3272         &gpt2_fck,
3273         &gpt3_fck,
3274         &gpt4_fck,
3275         &gpt5_fck,
3276         &gpt6_fck,
3277         &gpt7_fck,
3278         &gpt8_fck,
3279         &gpt9_fck,
3280         &per_32k_alwon_fck,
3281         &gpio6_fck,
3282         &gpio5_fck,
3283         &gpio4_fck,
3284         &gpio3_fck,
3285         &gpio2_fck,
3286         &wdt3_fck,
3287         &per_l4_ick,
3288         &gpio6_ick,
3289         &gpio5_ick,
3290         &gpio4_ick,
3291         &gpio3_ick,
3292         &gpio2_ick,
3293         &wdt3_ick,
3294         &uart3_ick,
3295         &gpt9_ick,
3296         &gpt8_ick,
3297         &gpt7_ick,
3298         &gpt6_ick,
3299         &gpt5_ick,
3300         &gpt4_ick,
3301         &gpt3_ick,
3302         &gpt2_ick,
3303         &mcbsp2_ick,
3304         &mcbsp3_ick,
3305         &mcbsp4_ick,
3306         &mcbsp2_fck,
3307         &mcbsp3_fck,
3308         &mcbsp4_fck,
3309         &emu_src_ck,
3310         &pclk_fck,
3311         &pclkx2_fck,
3312         &atclk_fck,
3313         &traceclk_src_fck,
3314         &traceclk_fck,
3315         &sr1_fck,
3316         &sr2_fck,
3317         &sr_l4_ick,
3318         &secure_32k_fck,
3319         &gpt12_fck,
3320         &wdt1_fck,
3321 };
3322
3323 #endif