2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
30 #include <mach/clock.h>
31 #include <mach/sram.h>
32 #include <asm/div64.h>
34 #include <mach/sdrc.h>
36 #include "clock34xx.h"
38 #include "prm-regbits-34xx.h"
40 #include "cm-regbits-34xx.h"
42 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
43 #define DPLL_AUTOIDLE_DISABLE 0x0
44 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
46 #define MAX_DPLL_WAIT_TRIES 1000000
49 * omap3_dpll_recalc - recalculate DPLL rate
50 * @clk: DPLL struct clk
51 * @parent_rate: rate of the DPLL's parent clock
52 * @rate_storage: flag indicating whether current or temporary rate is changing
54 * Recalculate and propagate the DPLL rate.
56 static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
61 rate = omap2_get_dpll_rate(clk, parent_rate);
63 if (rate_storage == CURRENT_RATE)
65 else if (rate_storage == TEMP_RATE)
66 clk->temp_rate = rate;
69 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
70 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
72 const struct dpll_data *dd;
77 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
78 v &= ~dd->enable_mask;
79 v |= clken_bits << __ffs(dd->enable_mask);
80 cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
83 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
84 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
86 const struct dpll_data *dd;
92 state <<= __ffs(dd->idlest_mask);
94 while (((cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg)
95 & dd->idlest_mask) != state) &&
96 i < MAX_DPLL_WAIT_TRIES) {
101 if (i == MAX_DPLL_WAIT_TRIES) {
102 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
103 clk->name, (state) ? "locked" : "bypassed");
105 pr_debug("clock: %s transition to '%s' in %d loops\n",
106 clk->name, (state) ? "locked" : "bypassed", i);
114 /* From 3430 TRM ES2 4.7.6.2 */
115 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
120 fint = clk->parent->rate / (n + 1);
122 pr_debug("clock: fint is %lu\n", fint);
124 if (fint >= 750000 && fint <= 1000000)
126 else if (fint > 1000000 && fint <= 1250000)
128 else if (fint > 1250000 && fint <= 1500000)
130 else if (fint > 1500000 && fint <= 1750000)
132 else if (fint > 1750000 && fint <= 2100000)
134 else if (fint > 7500000 && fint <= 10000000)
136 else if (fint > 10000000 && fint <= 12500000)
138 else if (fint > 12500000 && fint <= 15000000)
140 else if (fint > 15000000 && fint <= 17500000)
142 else if (fint > 17500000 && fint <= 21000000)
145 pr_debug("clock: unknown freqsel setting for %d\n", n);
150 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
153 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
154 * @clk: pointer to a DPLL struct clk
156 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
157 * readiness before returning. Will save and restore the DPLL's
158 * autoidle state across the enable, per the CDP code. If the DPLL
159 * locked successfully, return 0; if the DPLL did not lock in the time
160 * allotted, or DPLL3 was passed in, return -EINVAL.
162 static int _omap3_noncore_dpll_lock(struct clk *clk)
167 if (clk == &dpll3_ck)
170 pr_debug("clock: locking DPLL %s\n", clk->name);
172 ai = omap3_dpll_autoidle_read(clk);
174 omap3_dpll_deny_idle(clk);
176 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
178 r = _omap3_wait_dpll_status(clk, 1);
181 omap3_dpll_allow_idle(clk);
187 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
188 * @clk: pointer to a DPLL struct clk
190 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
191 * bypass mode, the DPLL's rate is set equal to its parent clock's
192 * rate. Waits for the DPLL to report readiness before returning.
193 * Will save and restore the DPLL's autoidle state across the enable,
194 * per the CDP code. If the DPLL entered bypass mode successfully,
195 * return 0; if the DPLL did not enter bypass in the time allotted, or
196 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
199 static int _omap3_noncore_dpll_bypass(struct clk *clk)
204 if (clk == &dpll3_ck)
207 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
210 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
213 ai = omap3_dpll_autoidle_read(clk);
215 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
217 r = _omap3_wait_dpll_status(clk, 0);
220 omap3_dpll_allow_idle(clk);
222 omap3_dpll_deny_idle(clk);
228 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
229 * @clk: pointer to a DPLL struct clk
231 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
232 * restore the DPLL's autoidle state across the stop, per the CDP
233 * code. If DPLL3 was passed in, or the DPLL does not support
234 * low-power stop, return -EINVAL; otherwise, return 0.
236 static int _omap3_noncore_dpll_stop(struct clk *clk)
240 if (clk == &dpll3_ck)
243 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
246 pr_debug("clock: stopping DPLL %s\n", clk->name);
248 ai = omap3_dpll_autoidle_read(clk);
250 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
253 omap3_dpll_allow_idle(clk);
255 omap3_dpll_deny_idle(clk);
261 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
262 * @clk: pointer to a DPLL struct clk
264 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
265 * The choice of modes depends on the DPLL's programmed rate: if it is
266 * the same as the DPLL's parent clock, it will enter bypass;
267 * otherwise, it will enter lock. This code will wait for the DPLL to
268 * indicate readiness before returning, unless the DPLL takes too long
269 * to enter the target state. Intended to be used as the struct clk's
270 * enable function. If DPLL3 was passed in, or the DPLL does not
271 * support low-power stop, or if the DPLL took too long to enter
272 * bypass or lock, return -EINVAL; otherwise, return 0.
274 static int omap3_noncore_dpll_enable(struct clk *clk)
277 struct dpll_data *dd;
279 if (clk == &dpll3_ck)
286 if (clk->rate == dd->bypass_clk->rate)
287 r = _omap3_noncore_dpll_bypass(clk);
289 r = _omap3_noncore_dpll_lock(clk);
295 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
296 * @clk: pointer to a DPLL struct clk
298 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
299 * The choice of modes depends on the DPLL's programmed rate: if it is
300 * the same as the DPLL's parent clock, it will enter bypass;
301 * otherwise, it will enter lock. This code will wait for the DPLL to
302 * indicate readiness before returning, unless the DPLL takes too long
303 * to enter the target state. Intended to be used as the struct clk's
304 * enable function. If DPLL3 was passed in, or the DPLL does not
305 * support low-power stop, or if the DPLL took too long to enter
306 * bypass or lock, return -EINVAL; otherwise, return 0.
308 static void omap3_noncore_dpll_disable(struct clk *clk)
310 if (clk == &dpll3_ck)
313 _omap3_noncore_dpll_stop(clk);
317 /* Non-CORE DPLL rate set code */
320 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
321 * @clk: struct clk * of DPLL to set
322 * @m: DPLL multiplier to set
323 * @n: DPLL divider to set
324 * @freqsel: FREQSEL value to set
326 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
327 * lock.. Returns -EINVAL upon error, or 0 upon success.
329 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
331 struct dpll_data *dd;
342 * According to the 12-5 CDP code from TI, "Limitation 2.5"
343 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
346 if (omap_rev() == OMAP3430_REV_ES1_0 &&
347 !strcmp("dpll4_ck", clk->name)) {
348 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
349 "silicon 'Limitation 2.5' on 3430ES1.\n");
353 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
354 _omap3_noncore_dpll_bypass(clk);
356 /* Set jitter correction */
357 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
358 v &= ~dd->freqsel_mask;
359 v |= freqsel << __ffs(dd->freqsel_mask);
360 cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
362 /* Set DPLL multiplier, divider */
363 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
364 v &= ~(dd->mult_mask | dd->div1_mask);
365 v |= m << __ffs(dd->mult_mask);
366 v |= (n - 1) << __ffs(dd->div1_mask);
367 cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg);
369 /* We let the clock framework set the other output dividers later */
371 /* REVISIT: Set ramp-up delay? */
373 _omap3_noncore_dpll_lock(clk);
379 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
380 * @clk: struct clk * of DPLL to set
381 * @rate: rounded target rate
383 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
384 * low-power bypass, and the target rate is the bypass source clock
385 * rate, then configure the DPLL for bypass. Otherwise, round the
386 * target rate if it hasn't been done already, then program and lock
387 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
389 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
392 struct dpll_data *dd;
402 if (rate == omap2_get_dpll_rate(clk, clk->parent->rate))
405 if (dd->bypass_clk->rate == rate &&
406 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
408 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
410 ret = _omap3_noncore_dpll_bypass(clk);
416 if (dd->last_rounded_rate != rate)
417 omap2_dpll_round_rate(clk, rate);
419 if (dd->last_rounded_rate == 0)
422 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
426 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
429 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
430 dd->last_rounded_n, freqsel);
442 * CORE DPLL (DPLL3) rate programming functions
444 * These call into SRAM code to do the actual CM writes, since the SDRAM
445 * is clocked from DPLL3.
449 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
450 * @clk: struct clk * of DPLL to set
451 * @rate: rounded target rate
453 * Program the DPLL M2 divider with the rounded target rate. Returns
454 * -EINVAL upon error, or 0 upon success.
456 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
459 unsigned long validrate, sdrcrate;
460 struct omap_sdrc_params *sp;
465 if (clk != &dpll3_m2_ck)
468 if (rate == clk->rate)
471 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
472 if (validrate != rate)
475 sdrcrate = sdrc_ick.rate;
476 if (rate > clk->rate)
477 sdrcrate <<= ((rate / clk->rate) - 1);
479 sdrcrate >>= ((clk->rate / rate) - 1);
481 sp = omap2_sdrc_get_params(sdrcrate);
485 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
487 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
488 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
490 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
491 WARN_ON(new_div != 1 && new_div != 2);
493 /* REVISIT: Add SDRC_MR changing to this code also */
494 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
495 sp->actim_ctrlb, new_div);
501 /* DPLL autoidle read/set code */
505 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
506 * @clk: struct clk * of the DPLL to read
508 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
509 * -EINVAL if passed a null pointer or if the struct clk does not
510 * appear to refer to a DPLL.
512 static u32 omap3_dpll_autoidle_read(struct clk *clk)
514 const struct dpll_data *dd;
517 if (!clk || !clk->dpll_data)
522 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
523 v &= dd->autoidle_mask;
524 v >>= __ffs(dd->autoidle_mask);
530 * omap3_dpll_allow_idle - enable DPLL autoidle bits
531 * @clk: struct clk * of the DPLL to operate on
533 * Enable DPLL automatic idle control. This automatic idle mode
534 * switching takes effect only when the DPLL is locked, at least on
535 * OMAP3430. The DPLL will enter low-power stop when its downstream
536 * clocks are gated. No return value.
538 static void omap3_dpll_allow_idle(struct clk *clk)
540 const struct dpll_data *dd;
543 if (!clk || !clk->dpll_data)
549 * REVISIT: CORE DPLL can optionally enter low-power bypass
550 * by writing 0x5 instead of 0x1. Add some mechanism to
551 * optionally enter this mode.
553 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
554 v &= ~dd->autoidle_mask;
555 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
556 cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
560 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
561 * @clk: struct clk * of the DPLL to operate on
563 * Disable DPLL automatic idle control. No return value.
565 static void omap3_dpll_deny_idle(struct clk *clk)
567 const struct dpll_data *dd;
570 if (!clk || !clk->dpll_data)
575 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
576 v &= ~dd->autoidle_mask;
577 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
578 cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
581 /* Clock control for DPLL outputs */
584 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
585 * @clk: DPLL output struct clk
586 * @parent_rate: rate of the parent clock of @clk
587 * @rate_storage: flag indicating whether current or temporary rate is changing
589 * Using parent clock DPLL data, look up DPLL state. If locked, set our
590 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
592 static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
595 const struct dpll_data *dd;
600 /* Walk up the parents of clk, looking for a DPLL */
602 while (pclk && !pclk->dpll_data)
605 /* clk does not have a DPLL as a parent? */
608 dd = pclk->dpll_data;
610 WARN_ON(!dd->enable_mask);
614 v = cm_read_mod_reg(pclk->prcm_mod, dd->control_reg) & dd->enable_mask;
615 v >>= __ffs(dd->enable_mask);
616 if (v == OMAP3XXX_EN_DPLL_LOCKED)
619 if (rate_storage == CURRENT_RATE)
621 else if (rate_storage == TEMP_RATE)
622 clk->temp_rate = rate;
625 /* Common clock code */
628 * As it is structured now, this will prevent an OMAP2/3 multiboot
629 * kernel from compiling. This will need further attention.
631 #if defined(CONFIG_ARCH_OMAP3)
633 static struct clk_functions omap2_clk_functions = {
634 .clk_register = omap2_clk_register,
635 .clk_enable = omap2_clk_enable,
636 .clk_disable = omap2_clk_disable,
637 .clk_round_rate = omap2_clk_round_rate,
638 .clk_set_rate = omap2_clk_set_rate,
639 .clk_set_parent = omap2_clk_set_parent,
640 .clk_get_parent = omap2_clk_get_parent,
641 .clk_disable_unused = omap2_clk_disable_unused,
645 * Set clocks for bypass mode for reboot to work.
647 void omap2_clk_prepare_for_reboot(void)
649 /* REVISIT: Not ready for 343x */
653 if (vclk == NULL || sclk == NULL)
656 rate = clk_get_rate(sclk);
657 clk_set_rate(vclk, rate);
661 /* REVISIT: Move this init stuff out into clock.c */
664 * Switch the MPU rate if specified on cmdline.
665 * We cannot do this early until cmdline is parsed.
667 static int __init omap2_clk_arch_init(void)
672 /* REVISIT: not yet ready for 343x */
674 if (clk_set_rate(&virt_prcm_set, mpurate))
675 printk(KERN_ERR "Could not find matching MPU rate\n");
678 recalculate_root_clocks();
680 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
681 "%ld.%01ld/%ld/%ld MHz\n",
682 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
683 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
687 arch_initcall(omap2_clk_arch_init);
689 int __init omap2_clk_init(void)
691 /* struct prcm_config *prcm; */
696 /* REVISIT: Ultimately this will be used for multiboot */
698 if (cpu_is_omap242x()) {
699 cpu_mask = RATE_IN_242X;
700 cpu_clkflg = CLOCK_IN_OMAP242X;
701 clkp = onchip_24xx_clks;
702 } else if (cpu_is_omap2430()) {
703 cpu_mask = RATE_IN_243X;
704 cpu_clkflg = CLOCK_IN_OMAP243X;
705 clkp = onchip_24xx_clks;
708 if (cpu_is_omap34xx()) {
709 cpu_mask = RATE_IN_343X;
710 cpu_clkflg = CLOCK_IN_OMAP343X;
711 clkp = onchip_34xx_clks;
714 * Update this if there are further clock changes between ES2
715 * and production parts
717 if (omap_rev() == OMAP3430_REV_ES1_0) {
718 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
719 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
721 cpu_mask |= RATE_IN_3430ES2;
722 cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
726 clk_init(&omap2_clk_functions);
728 for (clkp = onchip_34xx_clks;
729 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
731 if ((*clkp)->flags & cpu_clkflg)
735 /* REVISIT: Not yet ready for OMAP3 */
737 /* Check the MPU rate set by bootloader */
738 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
739 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
740 if (!(prcm->flags & cpu_mask))
742 if (prcm->xtal_speed != sys_ck.rate)
744 if (prcm->dpll_speed <= clkrate)
747 curr_prcm_set = prcm;
750 recalculate_root_clocks();
752 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
753 "%ld.%01ld/%ld/%ld MHz\n",
754 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
755 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
758 * Only enable those clocks we will need, let the drivers
759 * enable other clocks as necessary
761 clk_enable_init_clocks();
763 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
764 /* REVISIT: not yet ready for 343x */
766 vclk = clk_get(NULL, "virt_prcm_set");
767 sclk = clk_get(NULL, "sys_ck");