2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
29 #include <mach/clock.h>
30 #include <mach/sram.h>
31 #include <asm/div64.h>
32 #include <asm/bitops.h>
34 #include <mach/sdrc.h>
36 #include "clock34xx.h"
38 #include "prm-regbits-34xx.h"
40 #include "cm-regbits-34xx.h"
42 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
43 #define DPLL_AUTOIDLE_DISABLE 0x0
44 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
46 #define MAX_DPLL_WAIT_TRIES 1000000
49 * omap3_dpll_recalc - recalculate DPLL rate
50 * @clk: DPLL struct clk
52 * Recalculate and propagate the DPLL rate.
54 static void omap3_dpll_recalc(struct clk *clk)
56 clk->rate = omap2_get_dpll_rate(clk);
61 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
62 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
64 const struct dpll_data *dd;
69 v = __raw_readl(dd->control_reg);
70 v &= ~dd->enable_mask;
71 v |= clken_bits << __ffs(dd->enable_mask);
72 __raw_writel(v, dd->control_reg);
75 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
76 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
78 const struct dpll_data *dd;
84 state <<= __ffs(dd->idlest_mask);
86 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
87 i < MAX_DPLL_WAIT_TRIES) {
92 if (i == MAX_DPLL_WAIT_TRIES) {
93 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
94 clk->name, (state) ? "locked" : "bypassed");
96 pr_debug("clock: %s transition to '%s' in %d loops\n",
97 clk->name, (state) ? "locked" : "bypassed", i);
105 /* From 3430 TRM ES2 4.7.6.2 */
106 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
111 fint = clk->parent->rate / (n + 1);
113 pr_debug("clock: fint is %lu\n", fint);
115 if (fint >= 750000 && fint <= 1000000)
117 else if (fint > 1000000 && fint <= 1250000)
119 else if (fint > 1250000 && fint <= 1500000)
121 else if (fint > 1500000 && fint <= 1750000)
123 else if (fint > 1750000 && fint <= 2100000)
125 else if (fint > 7500000 && fint <= 10000000)
127 else if (fint > 10000000 && fint <= 12500000)
129 else if (fint > 12500000 && fint <= 15000000)
131 else if (fint > 15000000 && fint <= 17500000)
133 else if (fint > 17500000 && fint <= 21000000)
136 pr_debug("clock: unknown freqsel setting for %d\n", n);
141 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
144 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
145 * @clk: pointer to a DPLL struct clk
147 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
148 * readiness before returning. Will save and restore the DPLL's
149 * autoidle state across the enable, per the CDP code. If the DPLL
150 * locked successfully, return 0; if the DPLL did not lock in the time
151 * allotted, or DPLL3 was passed in, return -EINVAL.
153 static int _omap3_noncore_dpll_lock(struct clk *clk)
158 if (clk == &dpll3_ck)
161 pr_debug("clock: locking DPLL %s\n", clk->name);
163 ai = omap3_dpll_autoidle_read(clk);
165 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
169 * If no downstream clocks are enabled, CM_IDLEST bit
170 * may never become active, so don't wait for DPLL to lock.
173 omap3_dpll_allow_idle(clk);
175 r = _omap3_wait_dpll_status(clk, 1);
176 omap3_dpll_deny_idle(clk);
183 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
184 * @clk: pointer to a DPLL struct clk
186 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
187 * bypass mode, the DPLL's rate is set equal to its parent clock's
188 * rate. Waits for the DPLL to report readiness before returning.
189 * Will save and restore the DPLL's autoidle state across the enable,
190 * per the CDP code. If the DPLL entered bypass mode successfully,
191 * return 0; if the DPLL did not enter bypass in the time allotted, or
192 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
195 static int _omap3_noncore_dpll_bypass(struct clk *clk)
200 if (clk == &dpll3_ck)
203 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
206 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
209 ai = omap3_dpll_autoidle_read(clk);
211 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
213 r = _omap3_wait_dpll_status(clk, 0);
216 omap3_dpll_allow_idle(clk);
218 omap3_dpll_deny_idle(clk);
224 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
225 * @clk: pointer to a DPLL struct clk
227 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
228 * restore the DPLL's autoidle state across the stop, per the CDP
229 * code. If DPLL3 was passed in, or the DPLL does not support
230 * low-power stop, return -EINVAL; otherwise, return 0.
232 static int _omap3_noncore_dpll_stop(struct clk *clk)
236 if (clk == &dpll3_ck)
239 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
242 pr_debug("clock: stopping DPLL %s\n", clk->name);
244 ai = omap3_dpll_autoidle_read(clk);
246 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
249 omap3_dpll_allow_idle(clk);
251 omap3_dpll_deny_idle(clk);
257 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
258 * @clk: pointer to a DPLL struct clk
260 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
261 * The choice of modes depends on the DPLL's programmed rate: if it is
262 * the same as the DPLL's parent clock, it will enter bypass;
263 * otherwise, it will enter lock. This code will wait for the DPLL to
264 * indicate readiness before returning, unless the DPLL takes too long
265 * to enter the target state. Intended to be used as the struct clk's
266 * enable function. If DPLL3 was passed in, or the DPLL does not
267 * support low-power stop, or if the DPLL took too long to enter
268 * bypass or lock, return -EINVAL; otherwise, return 0.
270 static int omap3_noncore_dpll_enable(struct clk *clk)
274 if (clk == &dpll3_ck)
277 if (clk->parent->rate == omap2_get_dpll_rate(clk))
278 r = _omap3_noncore_dpll_bypass(clk);
280 r = _omap3_noncore_dpll_lock(clk);
286 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
287 * @clk: pointer to a DPLL struct clk
289 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
290 * The choice of modes depends on the DPLL's programmed rate: if it is
291 * the same as the DPLL's parent clock, it will enter bypass;
292 * otherwise, it will enter lock. This code will wait for the DPLL to
293 * indicate readiness before returning, unless the DPLL takes too long
294 * to enter the target state. Intended to be used as the struct clk's
295 * enable function. If DPLL3 was passed in, or the DPLL does not
296 * support low-power stop, or if the DPLL took too long to enter
297 * bypass or lock, return -EINVAL; otherwise, return 0.
299 static void omap3_noncore_dpll_disable(struct clk *clk)
301 if (clk == &dpll3_ck)
304 _omap3_noncore_dpll_stop(clk);
308 /* Non-CORE DPLL rate set code */
311 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
312 * @clk: struct clk * of DPLL to set
313 * @m: DPLL multiplier to set
314 * @n: DPLL divider to set
315 * @freqsel: FREQSEL value to set
317 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
318 * lock.. Returns -EINVAL upon error, or 0 upon success.
320 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
322 struct dpll_data *dd;
333 * According to the 12-5 CDP code from TI, "Limitation 2.5"
334 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
337 if (system_rev == OMAP3430_REV_ES1_0 &&
338 !strcmp("dpll4_ck", clk->name)) {
339 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
340 "silicon 'Limitation 2.5' on 3430ES1.\n");
344 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
345 _omap3_noncore_dpll_bypass(clk);
347 /* Set jitter correction */
348 v = __raw_readl(dd->control_reg);
349 v &= ~dd->freqsel_mask;
350 v |= freqsel << __ffs(dd->freqsel_mask);
351 __raw_writel(v, dd->control_reg);
353 /* Set DPLL multiplier, divider */
354 v = __raw_readl(dd->mult_div1_reg);
355 v &= ~(dd->mult_mask | dd->div1_mask);
356 v |= m << __ffs(dd->mult_mask);
357 v |= (n - 1) << __ffs(dd->div1_mask);
358 __raw_writel(v, dd->mult_div1_reg);
360 /* We let the clock framework set the other output dividers later */
362 /* REVISIT: Set ramp-up delay? */
364 _omap3_noncore_dpll_lock(clk);
370 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
371 * @clk: struct clk * of DPLL to set
372 * @rate: rounded target rate
374 * Program the DPLL with the rounded target rate. Returns -EINVAL upon
375 * error, or 0 upon success.
377 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
380 struct dpll_data *dd;
389 if (rate == omap2_get_dpll_rate(clk))
392 if (dd->last_rounded_rate != rate)
393 omap2_dpll_round_rate(clk, rate);
395 if (dd->last_rounded_rate == 0)
398 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
402 omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n,
405 omap3_dpll_recalc(clk);
412 * CORE DPLL (DPLL3) rate programming functions
414 * These call into SRAM code to do the actual CM writes, since the SDRAM
415 * is clocked from DPLL3.
419 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
420 * @clk: struct clk * of DPLL to set
421 * @rate: rounded target rate
423 * Program the DPLL M2 divider with the rounded target rate. Returns
424 * -EINVAL upon error, or 0 upon success.
426 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
429 unsigned long validrate, sdrcrate;
430 struct omap_sdrc_params *sp;
435 if (clk != &dpll3_m2_ck)
438 if (rate == clk->rate)
441 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
442 if (validrate != rate)
445 sdrcrate = sdrc_ick.rate;
446 if (rate > clk->rate)
447 sdrcrate <<= ((rate / clk->rate) - 1);
449 sdrcrate >>= ((clk->rate / rate) - 1);
451 sp = omap2_sdrc_get_params(sdrcrate);
455 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
457 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
458 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
460 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
461 WARN_ON(new_div != 1 && new_div != 2);
463 /* REVISIT: Add SDRC_MR changing to this code also */
465 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
466 sp->actim_ctrlb, new_div);
469 omap2_clksel_recalc(clk);
475 /* DPLL autoidle read/set code */
479 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
480 * @clk: struct clk * of the DPLL to read
482 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
483 * -EINVAL if passed a null pointer or if the struct clk does not
484 * appear to refer to a DPLL.
486 static u32 omap3_dpll_autoidle_read(struct clk *clk)
488 const struct dpll_data *dd;
491 if (!clk || !clk->dpll_data)
496 v = __raw_readl(dd->autoidle_reg);
497 v &= dd->autoidle_mask;
498 v >>= __ffs(dd->autoidle_mask);
504 * omap3_dpll_allow_idle - enable DPLL autoidle bits
505 * @clk: struct clk * of the DPLL to operate on
507 * Enable DPLL automatic idle control. This automatic idle mode
508 * switching takes effect only when the DPLL is locked, at least on
509 * OMAP3430. The DPLL will enter low-power stop when its downstream
510 * clocks are gated. No return value.
512 static void omap3_dpll_allow_idle(struct clk *clk)
514 const struct dpll_data *dd;
517 if (!clk || !clk->dpll_data)
523 * REVISIT: CORE DPLL can optionally enter low-power bypass
524 * by writing 0x5 instead of 0x1. Add some mechanism to
525 * optionally enter this mode.
527 v = __raw_readl(dd->autoidle_reg);
528 v &= ~dd->autoidle_mask;
529 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
530 __raw_writel(v, dd->autoidle_reg);
534 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
535 * @clk: struct clk * of the DPLL to operate on
537 * Disable DPLL automatic idle control. No return value.
539 static void omap3_dpll_deny_idle(struct clk *clk)
541 const struct dpll_data *dd;
544 if (!clk || !clk->dpll_data)
549 v = __raw_readl(dd->autoidle_reg);
550 v &= ~dd->autoidle_mask;
551 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
552 __raw_writel(v, dd->autoidle_reg);
555 /* Clock control for DPLL outputs */
558 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
559 * @clk: DPLL output struct clk
561 * Using parent clock DPLL data, look up DPLL state. If locked, set our
562 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
564 static void omap3_clkoutx2_recalc(struct clk *clk)
566 const struct dpll_data *dd;
570 /* Walk up the parents of clk, looking for a DPLL */
572 while (pclk && !pclk->dpll_data)
575 /* clk does not have a DPLL as a parent? */
578 dd = pclk->dpll_data;
580 WARN_ON(!dd->idlest_reg || !dd->idlest_mask);
582 v = __raw_readl(dd->idlest_reg) & dd->idlest_mask;
584 clk->rate = clk->parent->rate;
586 clk->rate = clk->parent->rate * 2;
588 if (clk->flags & RATE_PROPAGATES)
592 /* Common clock code */
595 * As it is structured now, this will prevent an OMAP2/3 multiboot
596 * kernel from compiling. This will need further attention.
598 #if defined(CONFIG_ARCH_OMAP3)
600 static struct clk_functions omap2_clk_functions = {
601 .clk_enable = omap2_clk_enable,
602 .clk_disable = omap2_clk_disable,
603 .clk_round_rate = omap2_clk_round_rate,
604 .clk_set_rate = omap2_clk_set_rate,
605 .clk_set_parent = omap2_clk_set_parent,
606 .clk_disable_unused = omap2_clk_disable_unused,
610 * Set clocks for bypass mode for reboot to work.
612 void omap2_clk_prepare_for_reboot(void)
614 /* REVISIT: Not ready for 343x */
618 if (vclk == NULL || sclk == NULL)
621 rate = clk_get_rate(sclk);
622 clk_set_rate(vclk, rate);
626 /* REVISIT: Move this init stuff out into clock.c */
629 * Switch the MPU rate if specified on cmdline.
630 * We cannot do this early until cmdline is parsed.
632 static int __init omap2_clk_arch_init(void)
637 /* REVISIT: not yet ready for 343x */
639 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
640 printk(KERN_ERR "Could not find matching MPU rate\n");
643 recalculate_root_clocks();
645 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
646 "%ld.%01ld/%ld/%ld MHz\n",
647 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
648 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
652 arch_initcall(omap2_clk_arch_init);
654 int __init omap2_clk_init(void)
656 /* struct prcm_config *prcm; */
661 /* REVISIT: Ultimately this will be used for multiboot */
663 if (cpu_is_omap242x()) {
664 cpu_mask = RATE_IN_242X;
665 cpu_clkflg = CLOCK_IN_OMAP242X;
666 clkp = onchip_24xx_clks;
667 } else if (cpu_is_omap2430()) {
668 cpu_mask = RATE_IN_243X;
669 cpu_clkflg = CLOCK_IN_OMAP243X;
670 clkp = onchip_24xx_clks;
673 if (cpu_is_omap34xx()) {
674 cpu_mask = RATE_IN_343X;
675 cpu_clkflg = CLOCK_IN_OMAP343X;
676 clkp = onchip_34xx_clks;
679 * Update this if there are further clock changes between ES2
680 * and production parts
682 if (system_rev == OMAP3430_REV_ES1_0) {
683 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
684 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
686 cpu_mask |= RATE_IN_3430ES2;
687 cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
691 clk_init(&omap2_clk_functions);
693 for (clkp = onchip_34xx_clks;
694 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
696 if ((*clkp)->flags & cpu_clkflg) {
698 omap2_init_clk_clkdm(*clkp);
702 /* REVISIT: Not yet ready for OMAP3 */
704 /* Check the MPU rate set by bootloader */
705 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
706 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
707 if (!(prcm->flags & cpu_mask))
709 if (prcm->xtal_speed != sys_ck.rate)
711 if (prcm->dpll_speed <= clkrate)
714 curr_prcm_set = prcm;
717 recalculate_root_clocks();
719 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
720 "%ld.%01ld/%ld/%ld MHz\n",
721 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
722 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
725 * Only enable those clocks we will need, let the drivers
726 * enable other clocks as necessary
728 clk_enable_init_clocks();
730 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
731 /* REVISIT: not yet ready for 343x */
733 vclk = clk_get(NULL, "virt_prcm_set");
734 sclk = clk_get(NULL, "sys_ck");