2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
29 #include <mach/clock.h>
30 #include <mach/sram.h>
31 #include <asm/div64.h>
32 #include <asm/bitops.h>
34 #include <mach/sdrc.h>
36 #include "clock34xx.h"
38 #include "prm-regbits-34xx.h"
40 #include "cm-regbits-34xx.h"
42 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
43 #define DPLL_AUTOIDLE_DISABLE 0x0
44 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
46 #define MAX_DPLL_WAIT_TRIES 1000000
49 * omap3_dpll_recalc - recalculate DPLL rate
50 * @clk: DPLL struct clk
52 * Recalculate and propagate the DPLL rate.
54 static void omap3_dpll_recalc(struct clk *clk)
56 clk->rate = omap2_get_dpll_rate(clk);
61 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
62 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
64 const struct dpll_data *dd;
69 v = __raw_readl(dd->control_reg);
70 v &= ~dd->enable_mask;
71 v |= clken_bits << __ffs(dd->enable_mask);
72 __raw_writel(v, dd->control_reg);
75 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
76 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
78 const struct dpll_data *dd;
85 state <<= dd->idlest_bit;
86 idlest_mask = 1 << dd->idlest_bit;
88 while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
89 i < MAX_DPLL_WAIT_TRIES) {
94 if (i == MAX_DPLL_WAIT_TRIES) {
95 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
96 clk->name, (state) ? "locked" : "bypassed");
98 pr_debug("clock: %s transition to '%s' in %d loops\n",
99 clk->name, (state) ? "locked" : "bypassed", i);
107 /* From 3430 TRM ES2 4.7.6.2 */
108 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
113 fint = clk->parent->rate / (n + 1);
115 pr_debug("clock: fint is %lu\n", fint);
117 if (fint >= 750000 && fint <= 1000000)
119 else if (fint > 1000000 && fint <= 1250000)
121 else if (fint > 1250000 && fint <= 1500000)
123 else if (fint > 1500000 && fint <= 1750000)
125 else if (fint > 1750000 && fint <= 2100000)
127 else if (fint > 7500000 && fint <= 10000000)
129 else if (fint > 10000000 && fint <= 12500000)
131 else if (fint > 12500000 && fint <= 15000000)
133 else if (fint > 15000000 && fint <= 17500000)
135 else if (fint > 17500000 && fint <= 21000000)
138 pr_debug("clock: unknown freqsel setting for %d\n", n);
143 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
146 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
147 * @clk: pointer to a DPLL struct clk
149 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
150 * readiness before returning. Will save and restore the DPLL's
151 * autoidle state across the enable, per the CDP code. If the DPLL
152 * locked successfully, return 0; if the DPLL did not lock in the time
153 * allotted, or DPLL3 was passed in, return -EINVAL.
155 static int _omap3_noncore_dpll_lock(struct clk *clk)
160 if (clk == &dpll3_ck)
163 pr_debug("clock: locking DPLL %s\n", clk->name);
165 ai = omap3_dpll_autoidle_read(clk);
167 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
171 * If no downstream clocks are enabled, CM_IDLEST bit
172 * may never become active, so don't wait for DPLL to lock.
175 omap3_dpll_allow_idle(clk);
177 r = _omap3_wait_dpll_status(clk, 1);
178 omap3_dpll_deny_idle(clk);
185 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
186 * @clk: pointer to a DPLL struct clk
188 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
189 * bypass mode, the DPLL's rate is set equal to its parent clock's
190 * rate. Waits for the DPLL to report readiness before returning.
191 * Will save and restore the DPLL's autoidle state across the enable,
192 * per the CDP code. If the DPLL entered bypass mode successfully,
193 * return 0; if the DPLL did not enter bypass in the time allotted, or
194 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
197 static int _omap3_noncore_dpll_bypass(struct clk *clk)
202 if (clk == &dpll3_ck)
205 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
208 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
211 ai = omap3_dpll_autoidle_read(clk);
213 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
215 r = _omap3_wait_dpll_status(clk, 0);
218 omap3_dpll_allow_idle(clk);
220 omap3_dpll_deny_idle(clk);
226 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
227 * @clk: pointer to a DPLL struct clk
229 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
230 * restore the DPLL's autoidle state across the stop, per the CDP
231 * code. If DPLL3 was passed in, or the DPLL does not support
232 * low-power stop, return -EINVAL; otherwise, return 0.
234 static int _omap3_noncore_dpll_stop(struct clk *clk)
238 if (clk == &dpll3_ck)
241 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
244 pr_debug("clock: stopping DPLL %s\n", clk->name);
246 ai = omap3_dpll_autoidle_read(clk);
248 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
251 omap3_dpll_allow_idle(clk);
253 omap3_dpll_deny_idle(clk);
259 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
260 * @clk: pointer to a DPLL struct clk
262 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
263 * The choice of modes depends on the DPLL's programmed rate: if it is
264 * the same as the DPLL's parent clock, it will enter bypass;
265 * otherwise, it will enter lock. This code will wait for the DPLL to
266 * indicate readiness before returning, unless the DPLL takes too long
267 * to enter the target state. Intended to be used as the struct clk's
268 * enable function. If DPLL3 was passed in, or the DPLL does not
269 * support low-power stop, or if the DPLL took too long to enter
270 * bypass or lock, return -EINVAL; otherwise, return 0.
272 static int omap3_noncore_dpll_enable(struct clk *clk)
276 if (clk == &dpll3_ck)
279 if (clk->parent->rate == omap2_get_dpll_rate(clk))
280 r = _omap3_noncore_dpll_bypass(clk);
282 r = _omap3_noncore_dpll_lock(clk);
288 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
289 * @clk: pointer to a DPLL struct clk
291 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
292 * The choice of modes depends on the DPLL's programmed rate: if it is
293 * the same as the DPLL's parent clock, it will enter bypass;
294 * otherwise, it will enter lock. This code will wait for the DPLL to
295 * indicate readiness before returning, unless the DPLL takes too long
296 * to enter the target state. Intended to be used as the struct clk's
297 * enable function. If DPLL3 was passed in, or the DPLL does not
298 * support low-power stop, or if the DPLL took too long to enter
299 * bypass or lock, return -EINVAL; otherwise, return 0.
301 static void omap3_noncore_dpll_disable(struct clk *clk)
303 if (clk == &dpll3_ck)
306 _omap3_noncore_dpll_stop(clk);
310 /* Non-CORE DPLL rate set code */
313 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
314 * @clk: struct clk * of DPLL to set
315 * @m: DPLL multiplier to set
316 * @n: DPLL divider to set
317 * @freqsel: FREQSEL value to set
319 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
320 * lock.. Returns -EINVAL upon error, or 0 upon success.
322 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
324 struct dpll_data *dd;
335 * According to the 12-5 CDP code from TI, "Limitation 2.5"
336 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
339 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
340 !strcmp("dpll4_ck", clk->name)) {
341 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
342 "silicon 'Limitation 2.5' on 3430ES1.\n");
346 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
347 _omap3_noncore_dpll_bypass(clk);
349 /* Set jitter correction */
350 v = __raw_readl(dd->control_reg);
351 v &= ~dd->freqsel_mask;
352 v |= freqsel << __ffs(dd->freqsel_mask);
353 __raw_writel(v, dd->control_reg);
355 /* Set DPLL multiplier, divider */
356 v = __raw_readl(dd->mult_div1_reg);
357 v &= ~(dd->mult_mask | dd->div1_mask);
358 v |= m << __ffs(dd->mult_mask);
359 v |= (n - 1) << __ffs(dd->div1_mask);
360 __raw_writel(v, dd->mult_div1_reg);
362 /* We let the clock framework set the other output dividers later */
364 /* REVISIT: Set ramp-up delay? */
366 _omap3_noncore_dpll_lock(clk);
372 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
373 * @clk: struct clk * of DPLL to set
374 * @rate: rounded target rate
376 * Program the DPLL with the rounded target rate. Returns -EINVAL upon
377 * error, or 0 upon success.
379 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
382 struct dpll_data *dd;
391 if (rate == omap2_get_dpll_rate(clk))
394 if (dd->last_rounded_rate != rate)
395 omap2_dpll_round_rate(clk, rate);
397 if (dd->last_rounded_rate == 0)
400 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
404 omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n,
407 omap3_dpll_recalc(clk);
414 * CORE DPLL (DPLL3) rate programming functions
416 * These call into SRAM code to do the actual CM writes, since the SDRAM
417 * is clocked from DPLL3.
421 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
422 * @clk: struct clk * of DPLL to set
423 * @rate: rounded target rate
425 * Program the DPLL M2 divider with the rounded target rate. Returns
426 * -EINVAL upon error, or 0 upon success.
428 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
431 unsigned long validrate, sdrcrate;
432 struct omap_sdrc_params *sp;
437 if (clk != &dpll3_m2_ck)
440 if (rate == clk->rate)
443 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
444 if (validrate != rate)
447 sdrcrate = sdrc_ick.rate;
448 if (rate > clk->rate)
449 sdrcrate <<= ((rate / clk->rate) - 1);
451 sdrcrate >>= ((clk->rate / rate) - 1);
453 sp = omap2_sdrc_get_params(sdrcrate);
457 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
459 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
460 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
462 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
463 WARN_ON(new_div != 1 && new_div != 2);
465 /* REVISIT: Add SDRC_MR changing to this code also */
467 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
468 sp->actim_ctrlb, new_div);
471 omap2_clksel_recalc(clk);
477 /* DPLL autoidle read/set code */
481 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
482 * @clk: struct clk * of the DPLL to read
484 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
485 * -EINVAL if passed a null pointer or if the struct clk does not
486 * appear to refer to a DPLL.
488 static u32 omap3_dpll_autoidle_read(struct clk *clk)
490 const struct dpll_data *dd;
493 if (!clk || !clk->dpll_data)
498 v = __raw_readl(dd->autoidle_reg);
499 v &= dd->autoidle_mask;
500 v >>= __ffs(dd->autoidle_mask);
506 * omap3_dpll_allow_idle - enable DPLL autoidle bits
507 * @clk: struct clk * of the DPLL to operate on
509 * Enable DPLL automatic idle control. This automatic idle mode
510 * switching takes effect only when the DPLL is locked, at least on
511 * OMAP3430. The DPLL will enter low-power stop when its downstream
512 * clocks are gated. No return value.
514 static void omap3_dpll_allow_idle(struct clk *clk)
516 const struct dpll_data *dd;
519 if (!clk || !clk->dpll_data)
525 * REVISIT: CORE DPLL can optionally enter low-power bypass
526 * by writing 0x5 instead of 0x1. Add some mechanism to
527 * optionally enter this mode.
529 v = __raw_readl(dd->autoidle_reg);
530 v &= ~dd->autoidle_mask;
531 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
532 __raw_writel(v, dd->autoidle_reg);
536 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
537 * @clk: struct clk * of the DPLL to operate on
539 * Disable DPLL automatic idle control. No return value.
541 static void omap3_dpll_deny_idle(struct clk *clk)
543 const struct dpll_data *dd;
546 if (!clk || !clk->dpll_data)
551 v = __raw_readl(dd->autoidle_reg);
552 v &= ~dd->autoidle_mask;
553 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
554 __raw_writel(v, dd->autoidle_reg);
557 /* Clock control for DPLL outputs */
560 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
561 * @clk: DPLL output struct clk
563 * Using parent clock DPLL data, look up DPLL state. If locked, set our
564 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
566 static void omap3_clkoutx2_recalc(struct clk *clk)
568 const struct dpll_data *dd;
572 /* Walk up the parents of clk, looking for a DPLL */
574 while (pclk && !pclk->dpll_data)
577 /* clk does not have a DPLL as a parent? */
580 dd = pclk->dpll_data;
582 WARN_ON(!dd->control_reg || !dd->enable_mask);
584 v = __raw_readl(dd->control_reg) & dd->enable_mask;
585 v >>= __ffs(dd->enable_mask);
586 if (v != DPLL_LOCKED)
587 clk->rate = clk->parent->rate;
589 clk->rate = clk->parent->rate * 2;
591 if (clk->flags & RATE_PROPAGATES)
595 /* Common clock code */
598 * As it is structured now, this will prevent an OMAP2/3 multiboot
599 * kernel from compiling. This will need further attention.
601 #if defined(CONFIG_ARCH_OMAP3)
603 static struct clk_functions omap2_clk_functions = {
604 .clk_enable = omap2_clk_enable,
605 .clk_disable = omap2_clk_disable,
606 .clk_round_rate = omap2_clk_round_rate,
607 .clk_set_rate = omap2_clk_set_rate,
608 .clk_set_parent = omap2_clk_set_parent,
609 .clk_disable_unused = omap2_clk_disable_unused,
613 * Set clocks for bypass mode for reboot to work.
615 void omap2_clk_prepare_for_reboot(void)
617 /* REVISIT: Not ready for 343x */
621 if (vclk == NULL || sclk == NULL)
624 rate = clk_get_rate(sclk);
625 clk_set_rate(vclk, rate);
629 /* REVISIT: Move this init stuff out into clock.c */
632 * Switch the MPU rate if specified on cmdline.
633 * We cannot do this early until cmdline is parsed.
635 static int __init omap2_clk_arch_init(void)
640 /* REVISIT: not yet ready for 343x */
642 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
643 printk(KERN_ERR "Could not find matching MPU rate\n");
646 recalculate_root_clocks();
648 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
649 "%ld.%01ld/%ld/%ld MHz\n",
650 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
651 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
655 arch_initcall(omap2_clk_arch_init);
657 int __init omap2_clk_init(void)
659 /* struct prcm_config *prcm; */
664 /* REVISIT: Ultimately this will be used for multiboot */
666 if (cpu_is_omap242x()) {
667 cpu_mask = RATE_IN_242X;
668 cpu_clkflg = CLOCK_IN_OMAP242X;
669 clkp = onchip_24xx_clks;
670 } else if (cpu_is_omap2430()) {
671 cpu_mask = RATE_IN_243X;
672 cpu_clkflg = CLOCK_IN_OMAP243X;
673 clkp = onchip_24xx_clks;
676 if (cpu_is_omap34xx()) {
677 cpu_mask = RATE_IN_343X;
678 cpu_clkflg = CLOCK_IN_OMAP343X;
679 clkp = onchip_34xx_clks;
682 * Update this if there are further clock changes between ES2
683 * and production parts
685 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
686 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
687 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
689 cpu_mask |= RATE_IN_3430ES2;
690 cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
694 clk_init(&omap2_clk_functions);
696 for (clkp = onchip_34xx_clks;
697 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
699 if ((*clkp)->flags & cpu_clkflg) {
701 omap2_init_clk_clkdm(*clkp);
705 /* REVISIT: Not yet ready for OMAP3 */
707 /* Check the MPU rate set by bootloader */
708 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
709 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
710 if (!(prcm->flags & cpu_mask))
712 if (prcm->xtal_speed != sys_ck.rate)
714 if (prcm->dpll_speed <= clkrate)
717 curr_prcm_set = prcm;
720 recalculate_root_clocks();
722 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
723 "%ld.%01ld/%ld/%ld MHz\n",
724 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
725 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
728 * Only enable those clocks we will need, let the drivers
729 * enable other clocks as necessary
731 clk_enable_init_clocks();
733 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
734 /* REVISIT: not yet ready for 343x */
736 vclk = clk_get(NULL, "virt_prcm_set");
737 sclk = clk_get(NULL, "sys_ck");