arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*
 604  * Since 2420 and 2430 have different cm_base, we use offsets only here.
 605  * Clock code will rewrite the register address as needed.
 606  */
 607 #define _CM_REG_OFFSET(module, reg)                             \
 608                         ((__force void __iomem *)(module) + (reg))
 609 #define _GR_MOD_OFFSET(reg)                                     \
 610                         ((__force void __iomem *)(OMAP24XX_GR_MOD + (reg)))
 611
 612 /*-------------------------------------------------------------------------
 613  * 24xx clock tree.
 614  *
 615  * NOTE:In many cases here we are assigning a 'default' parent. In many
 616  *      cases the parent is selectable. The get/set parent calls will also
 617  *      switch sources.
 618  *
 619  *      Many some clocks say always_enabled, but they can be auto idled for
 620  *      power savings. They will always be available upon clock request.
 621  *
 622  *      Several sources are given initial rates which may be wrong, this will
 623  *      be fixed up in the init func.
 624  *
 625  *      Things are broadly separated below by clock domains. It is
 626  *      noteworthy that most periferals have dependencies on multiple clock
 627  *      domains. Many get their interface clocks from the L4 domain, but get
 628  *      functional clocks from fixed sources or other core domain derived
 629  *      clocks.
 630  *-------------------------------------------------------------------------*/
 631
 632 /* Base external input clocks */
 633 static struct clk func_32k_ck = {
 634         .name           = "func_32k_ck",
 635         .rate           = 32000,
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 638         .clkdm          = { .name = "prm_clkdm" },
 639         .recalc         = &propagate_rate,
 640 };
 641
 642 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 643 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 644         .name           = "osc_ck",
 645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 646                                 RATE_PROPAGATES,
 647         .clkdm          = { .name = "prm_clkdm" },
 648         .enable         = &omap2_enable_osc_ck,
 649         .disable        = &omap2_disable_osc_ck,
 650         .recalc         = &omap2_osc_clk_recalc,
 651 };
 652
 653 /* Without modem likely 12MHz, with modem likely 13MHz */
 654 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 655         .name           = "sys_ck",             /* ~ ref_clk also */
 656         .parent         = &osc_ck,
 657         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 658                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 659         .clkdm          = { .name = "prm_clkdm" },
 660         .recalc         = &omap2_sys_clk_recalc,
 661 };
 662
 663 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 664         .name           = "alt_ck",
 665         .rate           = 54000000,
 666         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 667                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 668         .clkdm          = { .name = "prm_clkdm" },
 669         .recalc         = &propagate_rate,
 670 };
 671
 672 /*
 673  * Analog domain root source clocks
 674  */
 675
 676 /* dpll_ck, is broken out in to special cases through clksel */
 677 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 678  * deal with this
 679  */
 680
 681 static struct dpll_data dpll_dd = {
 682         .mult_div1_reg          = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 683         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 684         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 685         .max_multiplier         = 1024,
 686         .max_divider            = 16,
 687         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 688 };
 689
 690 /*
 691  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 692  * not just a DPLL
 693  */
 694 static struct clk dpll_ck = {
 695         .name           = "dpll_ck",
 696         .parent         = &sys_ck,              /* Can be func_32k also */
 697         .dpll_data      = &dpll_dd,
 698         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 699                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 700         .clkdm          = { .name = "prm_clkdm" },
 701         .recalc         = &omap2_dpllcore_recalc,
 702         .set_rate       = &omap2_reprogram_dpllcore,
 703 };
 704
 705 static struct clk apll96_ck = {
 706         .name           = "apll96_ck",
 707         .parent         = &sys_ck,
 708         .rate           = 96000000,
 709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 710                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 711         .clkdm          = { .name = "prm_clkdm" },
 712         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 713         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 714         .enable         = &omap2_clk_fixed_enable,
 715         .disable        = &omap2_clk_fixed_disable,
 716         .recalc         = &propagate_rate,
 717 };
 718
 719 static struct clk apll54_ck = {
 720         .name           = "apll54_ck",
 721         .parent         = &sys_ck,
 722         .rate           = 54000000,
 723         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 724                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 725         .clkdm          = { .name = "prm_clkdm" },
 726         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 727         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 728         .enable         = &omap2_clk_fixed_enable,
 729         .disable        = &omap2_clk_fixed_disable,
 730         .recalc         = &propagate_rate,
 731 };
 732
 733 /*
 734  * PRCM digital base sources
 735  */
 736
 737 /* func_54m_ck */
 738
 739 static const struct clksel_rate func_54m_apll54_rates[] = {
 740         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 741         { .div = 0 },
 742 };
 743
 744 static const struct clksel_rate func_54m_alt_rates[] = {
 745         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 746         { .div = 0 },
 747 };
 748
 749 static const struct clksel func_54m_clksel[] = {
 750         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 751         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 752         { .parent = NULL },
 753 };
 754
 755 static struct clk func_54m_ck = {
 756         .name           = "func_54m_ck",
 757         .parent         = &apll54_ck,   /* can also be alt_clk */
 758         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 759                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 760         .clkdm          = { .name = "cm_clkdm" },
 761         .init           = &omap2_init_clksel_parent,
 762         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 763         .clksel_mask    = OMAP24XX_54M_SOURCE,
 764         .clksel         = func_54m_clksel,
 765         .recalc         = &omap2_clksel_recalc,
 766 };
 767
 768 static struct clk core_ck = {
 769         .name           = "core_ck",
 770         .parent         = &dpll_ck,             /* can also be 32k */
 771         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 772                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 773         .clkdm          = { .name = "cm_clkdm" },
 774         .recalc         = &followparent_recalc,
 775 };
 776
 777 /* func_96m_ck */
 778 static const struct clksel_rate func_96m_apll96_rates[] = {
 779         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 780         { .div = 0 },
 781 };
 782
 783 static const struct clksel_rate func_96m_alt_rates[] = {
 784         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 785         { .div = 0 },
 786 };
 787
 788 static const struct clksel func_96m_clksel[] = {
 789         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 790         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 791         { .parent = NULL }
 792 };
 793
 794 /* The parent of this clock is not selectable on 2420. */
 795 static struct clk func_96m_ck = {
 796         .name           = "func_96m_ck",
 797         .parent         = &apll96_ck,
 798         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 799                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 800         .clkdm          = { .name = "cm_clkdm" },
 801         .init           = &omap2_init_clksel_parent,
 802         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 803         .clksel_mask    = OMAP2430_96M_SOURCE,
 804         .clksel         = func_96m_clksel,
 805         .recalc         = &omap2_clksel_recalc,
 806         .round_rate     = &omap2_clksel_round_rate,
 807         .set_rate       = &omap2_clksel_set_rate
 808 };
 809
 810 /* func_48m_ck */
 811
 812 static const struct clksel_rate func_48m_apll96_rates[] = {
 813         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 814         { .div = 0 },
 815 };
 816
 817 static const struct clksel_rate func_48m_alt_rates[] = {
 818         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 819         { .div = 0 },
 820 };
 821
 822 static const struct clksel func_48m_clksel[] = {
 823         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 824         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 825         { .parent = NULL }
 826 };
 827
 828 static struct clk func_48m_ck = {
 829         .name           = "func_48m_ck",
 830         .parent         = &apll96_ck,    /* 96M or Alt */
 831         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 832                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 833         .clkdm          = { .name = "cm_clkdm" },
 834         .init           = &omap2_init_clksel_parent,
 835         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 836         .clksel_mask    = OMAP24XX_48M_SOURCE,
 837         .clksel         = func_48m_clksel,
 838         .recalc         = &omap2_clksel_recalc,
 839         .round_rate     = &omap2_clksel_round_rate,
 840         .set_rate       = &omap2_clksel_set_rate
 841 };
 842
 843 static struct clk func_12m_ck = {
 844         .name           = "func_12m_ck",
 845         .parent         = &func_48m_ck,
 846         .fixed_div      = 4,
 847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 848                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 849         .clkdm          = { .name = "cm_clkdm" },
 850         .recalc         = &omap2_fixed_divisor_recalc,
 851 };
 852
 853 /* Secure timer, only available in secure mode */
 854 static struct clk wdt1_osc_ck = {
 855         .name           = "wdt1_osc_ck",
 856         .parent         = &osc_ck,
 857         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 858         .clkdm          = { .name = "prm_clkdm" },
 859         .recalc         = &followparent_recalc,
 860 };
 861
 862 /*
 863  * The common_clkout* clksel_rate structs are common to
 864  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 865  * sys_clkout2_* are 2420-only, so the
 866  * clksel_rate flags fields are inaccurate for those clocks. This is
 867  * harmless since access to those clocks are gated by the struct clk
 868  * flags fields, which mark them as 2420-only.
 869  */
 870 static const struct clksel_rate common_clkout_src_core_rates[] = {
 871         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 872         { .div = 0 }
 873 };
 874
 875 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 876         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 877         { .div = 0 }
 878 };
 879
 880 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 881         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 882         { .div = 0 }
 883 };
 884
 885 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 886         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 887         { .div = 0 }
 888 };
 889
 890 static const struct clksel common_clkout_src_clksel[] = {
 891         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 892         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 893         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 894         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 895         { .parent = NULL }
 896 };
 897
 898 static struct clk sys_clkout_src = {
 899         .name           = "sys_clkout_src",
 900         .parent         = &func_54m_ck,
 901         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 902                                 RATE_PROPAGATES | OFFSET_GR_MOD,
 903         .clkdm          = { .name = "prm_clkdm" },
 904         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 905         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 906         .init           = &omap2_init_clksel_parent,
 907         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 908         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 909         .clksel         = common_clkout_src_clksel,
 910         .recalc         = &omap2_clksel_recalc,
 911         .round_rate     = &omap2_clksel_round_rate,
 912         .set_rate       = &omap2_clksel_set_rate
 913 };
 914
 915 static const struct clksel_rate common_clkout_rates[] = {
 916         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 917         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 918         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 919         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 920         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 921         { .div = 0 },
 922 };
 923
 924 static const struct clksel sys_clkout_clksel[] = {
 925         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 926         { .parent = NULL }
 927 };
 928
 929 static struct clk sys_clkout = {
 930         .name           = "sys_clkout",
 931         .parent         = &sys_clkout_src,
 932         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 933                                 PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
 934         .clkdm          = { .name = "prm_clkdm" },
 935         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 936         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 937         .clksel         = sys_clkout_clksel,
 938         .recalc         = &omap2_clksel_recalc,
 939         .round_rate     = &omap2_clksel_round_rate,
 940         .set_rate       = &omap2_clksel_set_rate
 941 };
 942
 943 /* In 2430, new in 2420 ES2 */
 944 static struct clk sys_clkout2_src = {
 945         .name           = "sys_clkout2_src",
 946         .parent         = &func_54m_ck,
 947         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
 948         .clkdm          = { .name = "cm_clkdm" },
 949         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 950         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 951         .init           = &omap2_init_clksel_parent,
 952         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 953         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 954         .clksel         = common_clkout_src_clksel,
 955         .recalc         = &omap2_clksel_recalc,
 956         .round_rate     = &omap2_clksel_round_rate,
 957         .set_rate       = &omap2_clksel_set_rate
 958 };
 959
 960 static const struct clksel sys_clkout2_clksel[] = {
 961         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 962         { .parent = NULL }
 963 };
 964
 965 /* In 2430, new in 2420 ES2 */
 966 static struct clk sys_clkout2 = {
 967         .name           = "sys_clkout2",
 968         .parent         = &sys_clkout2_src,
 969         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
 970                                 OFFSET_GR_MOD,
 971         .clkdm          = { .name = "cm_clkdm" },
 972         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 973         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 974         .clksel         = sys_clkout2_clksel,
 975         .recalc         = &omap2_clksel_recalc,
 976         .round_rate     = &omap2_clksel_round_rate,
 977         .set_rate       = &omap2_clksel_set_rate
 978 };
 979
 980 static struct clk emul_ck = {
 981         .name           = "emul_ck",
 982         .parent         = &func_54m_ck,
 983         .flags          = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
 984         .clkdm          = { .name = "cm_clkdm" },
 985         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
 986         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 987         .recalc         = &followparent_recalc,
 988
 989 };
 990
 991 /*
 992  * MPU clock domain
 993  *      Clocks:
 994  *              MPU_FCLK, MPU_ICLK
 995  *              INT_M_FCLK, INT_M_I_CLK
 996  *
 997  * - Individual clocks are hardware managed.
 998  * - Base divider comes from: CM_CLKSEL_MPU
 999  *
1000  */
1001 static const struct clksel_rate mpu_core_rates[] = {
1002         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1003         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1004         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1005         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1006         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1007         { .div = 0 },
1008 };
1009
1010 static const struct clksel mpu_clksel[] = {
1011         { .parent = &core_ck, .rates = mpu_core_rates },
1012         { .parent = NULL }
1013 };
1014
1015 static struct clk mpu_ck = {    /* Control cpu */
1016         .name           = "mpu_ck",
1017         .parent         = &core_ck,
1018         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1019                                 ALWAYS_ENABLED | DELAYED_APP |
1020                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1021         .clkdm          = { .name = "mpu_clkdm" },
1022         .init           = &omap2_init_clksel_parent,
1023         .clksel_reg     = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL),
1024         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1025         .clksel         = mpu_clksel,
1026         .recalc         = &omap2_clksel_recalc,
1027         .round_rate     = &omap2_clksel_round_rate,
1028         .set_rate       = &omap2_clksel_set_rate
1029 };
1030
1031 /*
1032  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1033  * Clocks:
1034  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1035  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1036  *
1037  * Won't be too specific here. The core clock comes into this block
1038  * it is divided then tee'ed. One branch goes directly to xyz enable
1039  * controls. The other branch gets further divided by 2 then possibly
1040  * routed into a synchronizer and out of clocks abc.
1041  */
1042 static const struct clksel_rate dsp_fck_core_rates[] = {
1043         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1044         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1045         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1046         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1047         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1048         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1049         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1050         { .div = 0 },
1051 };
1052
1053 static const struct clksel dsp_fck_clksel[] = {
1054         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1055         { .parent = NULL }
1056 };
1057
1058 static struct clk dsp_fck = {
1059         .name           = "dsp_fck",
1060         .parent         = &core_ck,
1061         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1062                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1063         .clkdm          = { .name = "dsp_clkdm" },
1064         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1065         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1066         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1067         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1068         .clksel         = dsp_fck_clksel,
1069         .recalc         = &omap2_clksel_recalc,
1070         .round_rate     = &omap2_clksel_round_rate,
1071         .set_rate       = &omap2_clksel_set_rate
1072 };
1073
1074 /* DSP interface clock */
1075 static const struct clksel_rate dsp_irate_ick_rates[] = {
1076         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1077         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1078         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1079         { .div = 0 },
1080 };
1081
1082 static const struct clksel dsp_irate_ick_clksel[] = {
1083         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1084         { .parent = NULL }
1085 };
1086
1087 /* This clock does not exist as such in the TRM. */
1088 static struct clk dsp_irate_ick = {
1089         .name           = "dsp_irate_ick",
1090         .parent         = &dsp_fck,
1091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1092                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1093         .clkdm          = { .name = "dsp_clkdm" },
1094         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1095         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1096         .clksel         = dsp_irate_ick_clksel,
1097         .recalc         = &omap2_clksel_recalc,
1098         .round_rate     = &omap2_clksel_round_rate,
1099         .set_rate       = &omap2_clksel_set_rate
1100 };
1101
1102 /* 2420 only */
1103 static struct clk dsp_ick = {
1104         .name           = "dsp_ick",     /* apparently ipi and isp */
1105         .parent         = &dsp_irate_ick,
1106         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1107         .clkdm          = { .name = "dsp_clkdm" },
1108         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
1109         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1110 };
1111
1112 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1113 static struct clk iva2_1_ick = {
1114         .name           = "iva2_1_ick",
1115         .parent         = &dsp_irate_ick,
1116         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1117         .clkdm          = { .name = "dsp_clkdm" },
1118         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1119         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1120 };
1121
1122 /*
1123  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1124  * the C54x, but which is contained in the DSP powerdomain.  Does not
1125  * exist on later OMAPs.
1126  */
1127 static struct clk iva1_ifck = {
1128         .name           = "iva1_ifck",
1129         .parent         = &core_ck,
1130         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1131                                 RATE_PROPAGATES | DELAYED_APP,
1132         .clkdm          = { .name = "iva1_clkdm" },
1133         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1134         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1135         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1136         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1137         .clksel         = dsp_fck_clksel,
1138         .recalc         = &omap2_clksel_recalc,
1139         .round_rate     = &omap2_clksel_round_rate,
1140         .set_rate       = &omap2_clksel_set_rate
1141 };
1142
1143 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1144 static struct clk iva1_mpu_int_ifck = {
1145         .name           = "iva1_mpu_int_ifck",
1146         .parent         = &iva1_ifck,
1147         .flags          = CLOCK_IN_OMAP242X,
1148         .clkdm          = { .name = "iva1_clkdm" },
1149         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1150         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1151         .fixed_div      = 2,
1152         .recalc         = &omap2_fixed_divisor_recalc,
1153 };
1154
1155 /*
1156  * L3 clock domain
1157  * L3 clocks are used for both interface and functional clocks to
1158  * multiple entities. Some of these clocks are completely managed
1159  * by hardware, and some others allow software control. Hardware
1160  * managed ones general are based on directly CLK_REQ signals and
1161  * various auto idle settings. The functional spec sets many of these
1162  * as 'tie-high' for their enables.
1163  *
1164  * I-CLOCKS:
1165  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1166  *      CAM, HS-USB.
1167  * F-CLOCK
1168  *      SSI.
1169  *
1170  * GPMC memories and SDRC have timing and clock sensitive registers which
1171  * may very well need notification when the clock changes. Currently for low
1172  * operating points, these are taken care of in sleep.S.
1173  */
1174 static const struct clksel_rate core_l3_core_rates[] = {
1175         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1176         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1177         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1178         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1179         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1180         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1181         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1182         { .div = 0 }
1183 };
1184
1185 static const struct clksel core_l3_clksel[] = {
1186         { .parent = &core_ck, .rates = core_l3_core_rates },
1187         { .parent = NULL }
1188 };
1189
1190 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1191         .name           = "core_l3_ck",
1192         .parent         = &core_ck,
1193         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1194                                 ALWAYS_ENABLED | DELAYED_APP |
1195                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1196         .clkdm          = { .name = "core_l3_clkdm" },
1197         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1198         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1199         .clksel         = core_l3_clksel,
1200         .recalc         = &omap2_clksel_recalc,
1201         .round_rate     = &omap2_clksel_round_rate,
1202         .set_rate       = &omap2_clksel_set_rate
1203 };
1204
1205 /* usb_l4_ick */
1206 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1207         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1208         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1209         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1210         { .div = 0 }
1211 };
1212
1213 static const struct clksel usb_l4_ick_clksel[] = {
1214         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1215         { .parent = NULL },
1216 };
1217
1218 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1219 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1220         .name           = "usb_l4_ick",
1221         .parent         = &core_l3_ck,
1222         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1223                                 DELAYED_APP | CONFIG_PARTICIPANT,
1224         .clkdm          = { .name = "core_l4_clkdm" },
1225         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1226         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1227         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1228         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1229         .clksel         = usb_l4_ick_clksel,
1230         .recalc         = &omap2_clksel_recalc,
1231         .round_rate     = &omap2_clksel_round_rate,
1232         .set_rate       = &omap2_clksel_set_rate
1233 };
1234
1235 /*
1236  * L4 clock management domain
1237  *
1238  * This domain contains lots of interface clocks from the L4 interface, some
1239  * functional clocks.   Fixed APLL functional source clocks are managed in
1240  * this domain.
1241  */
1242 static const struct clksel_rate l4_core_l3_rates[] = {
1243         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1244         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1245         { .div = 0 }
1246 };
1247
1248 static const struct clksel l4_clksel[] = {
1249         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1250         { .parent = NULL }
1251 };
1252
1253 static struct clk l4_ck = {             /* used both as an ick and fck */
1254         .name           = "l4_ck",
1255         .parent         = &core_l3_ck,
1256         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1257                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1258         .clkdm          = { .name = "core_l4_clkdm" },
1259         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1260         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1261         .clksel         = l4_clksel,
1262         .recalc         = &omap2_clksel_recalc,
1263         .round_rate     = &omap2_clksel_round_rate,
1264         .set_rate       = &omap2_clksel_set_rate
1265 };
1266
1267 /*
1268  * SSI is in L3 management domain, its direct parent is core not l3,
1269  * many core power domain entities are grouped into the L3 clock
1270  * domain.
1271  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1272  *
1273  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1274  */
1275 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1276         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1277         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1278         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1279         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1280         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1281         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1282         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1283         { .div = 0 }
1284 };
1285
1286 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1287         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1288         { .parent = NULL }
1289 };
1290
1291 static struct clk ssi_ssr_sst_fck = {
1292         .name           = "ssi_fck",
1293         .parent         = &core_ck,
1294         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1295                                 DELAYED_APP,
1296         .clkdm          = { .name = "core_l3_clkdm" },
1297         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1298         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1299         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1300         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1301         .clksel         = ssi_ssr_sst_fck_clksel,
1302         .recalc         = &omap2_clksel_recalc,
1303         .round_rate     = &omap2_clksel_round_rate,
1304         .set_rate       = &omap2_clksel_set_rate
1305 };
1306
1307 /*
1308  * Presumably this is the same as SSI_ICLK.
1309  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1310  */
1311 static struct clk ssi_l4_ick = {
1312         .name           = "ssi_l4_ick",
1313         .parent         = &l4_ck,
1314         .clkdm          = { .name = "core_l4_clkdm" },
1315         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1316         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1317         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1318         .recalc         = &followparent_recalc,
1319 };
1320
1321
1322 /*
1323  * GFX clock domain
1324  *      Clocks:
1325  * GFX_FCLK, GFX_ICLK
1326  * GFX_CG1(2d), GFX_CG2(3d)
1327  *
1328  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1329  * The 2d and 3d clocks run at a hardware determined
1330  * divided value of fclk.
1331  *
1332  */
1333 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1334
1335 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1336 static const struct clksel gfx_fck_clksel[] = {
1337         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1338         { .parent = NULL },
1339 };
1340
1341 static struct clk gfx_3d_fck = {
1342         .name           = "gfx_3d_fck",
1343         .parent         = &core_l3_ck,
1344         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1345         .clkdm          = { .name = "gfx_clkdm" },
1346         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1347         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1348         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1349         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1350         .clksel         = gfx_fck_clksel,
1351         .recalc         = &omap2_clksel_recalc,
1352         .round_rate     = &omap2_clksel_round_rate,
1353         .set_rate       = &omap2_clksel_set_rate
1354 };
1355
1356 static struct clk gfx_2d_fck = {
1357         .name           = "gfx_2d_fck",
1358         .parent         = &core_l3_ck,
1359         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1360         .clkdm          = { .name = "gfx_clkdm" },
1361         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1362         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1363         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1364         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1365         .clksel         = gfx_fck_clksel,
1366         .recalc         = &omap2_clksel_recalc,
1367         .round_rate     = &omap2_clksel_round_rate,
1368         .set_rate       = &omap2_clksel_set_rate
1369 };
1370
1371 static struct clk gfx_ick = {
1372         .name           = "gfx_ick",            /* From l3 */
1373         .parent         = &core_l3_ck,
1374         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1375         .clkdm          = { .name = "gfx_clkdm" },
1376         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
1377         .enable_bit     = OMAP_EN_GFX_SHIFT,
1378         .recalc         = &followparent_recalc,
1379 };
1380
1381 /*
1382  * Modem clock domain (2430)
1383  *      CLOCKS:
1384  *              MDM_OSC_CLK
1385  *              MDM_ICLK
1386  * These clocks are usable in chassis mode only.
1387  */
1388 static const struct clksel_rate mdm_ick_core_rates[] = {
1389         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1390         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1391         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1392         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1393         { .div = 0 }
1394 };
1395
1396 static const struct clksel mdm_ick_clksel[] = {
1397         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1398         { .parent = NULL }
1399 };
1400
1401 static struct clk mdm_ick = {           /* used both as a ick and fck */
1402         .name           = "mdm_ick",
1403         .parent         = &core_ck,
1404         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1405         .clkdm          = { .name = "mdm_clkdm" },
1406         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
1407         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1408         .clksel_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL),
1409         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1410         .clksel         = mdm_ick_clksel,
1411         .recalc         = &omap2_clksel_recalc,
1412         .round_rate     = &omap2_clksel_round_rate,
1413         .set_rate       = &omap2_clksel_set_rate
1414 };
1415
1416 static struct clk mdm_osc_ck = {
1417         .name           = "mdm_osc_ck",
1418         .parent         = &osc_ck,
1419         .flags          = CLOCK_IN_OMAP243X,
1420         .clkdm          = { .name = "mdm_clkdm" },
1421         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
1422         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1423         .recalc         = &followparent_recalc,
1424 };
1425
1426 /*
1427  * DSS clock domain
1428  * CLOCKs:
1429  * DSS_L4_ICLK, DSS_L3_ICLK,
1430  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1431  *
1432  * DSS is both initiator and target.
1433  */
1434 /* XXX Add RATE_NOT_VALIDATED */
1435
1436 static const struct clksel_rate dss1_fck_sys_rates[] = {
1437         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1438         { .div = 0 }
1439 };
1440
1441 static const struct clksel_rate dss1_fck_core_rates[] = {
1442         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1443         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1444         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1445         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1446         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1447         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1448         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1449         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1450         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1451         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1452         { .div = 0 }
1453 };
1454
1455 static const struct clksel dss1_fck_clksel[] = {
1456         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1457         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1458         { .parent = NULL },
1459 };
1460
1461 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1462         .name           = "dss_ick",
1463         .parent         = &l4_ck,       /* really both l3 and l4 */
1464         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1465         .clkdm          = { .name = "dss_clkdm" },
1466         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1467         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 static struct clk dss1_fck = {
1472         .name           = "dss1_fck",
1473         .parent         = &core_ck,             /* Core or sys */
1474         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1475                                 DELAYED_APP,
1476         .clkdm          = { .name = "dss_clkdm" },
1477         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1478         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1479         .init           = &omap2_init_clksel_parent,
1480         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1481         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1482         .clksel         = dss1_fck_clksel,
1483         .recalc         = &omap2_clksel_recalc,
1484         .round_rate     = &omap2_clksel_round_rate,
1485         .set_rate       = &omap2_clksel_set_rate
1486 };
1487
1488 static const struct clksel_rate dss2_fck_sys_rates[] = {
1489         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1490         { .div = 0 }
1491 };
1492
1493 static const struct clksel_rate dss2_fck_48m_rates[] = {
1494         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1495         { .div = 0 }
1496 };
1497
1498 static const struct clksel dss2_fck_clksel[] = {
1499         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1500         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1501         { .parent = NULL }
1502 };
1503
1504 static struct clk dss2_fck = {          /* Alt clk used in power management */
1505         .name           = "dss2_fck",
1506         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1507         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1508                                 DELAYED_APP,
1509         .clkdm          = { .name = "dss_clkdm" },
1510         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1511         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1512         .init           = &omap2_init_clksel_parent,
1513         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1514         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1515         .clksel         = dss2_fck_clksel,
1516         .recalc         = &followparent_recalc,
1517 };
1518
1519 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1520         .name           = "dss_54m_fck",        /* 54m tv clk */
1521         .parent         = &func_54m_ck,
1522         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523         .clkdm          = { .name = "dss_clkdm" },
1524         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1525         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1526         .recalc         = &followparent_recalc,
1527 };
1528
1529 /*
1530  * CORE power domain ICLK & FCLK defines.
1531  * Many of the these can have more than one possible parent. Entries
1532  * here will likely have an L4 interface parent, and may have multiple
1533  * functional clock parents.
1534  */
1535 static const struct clksel_rate gpt_alt_rates[] = {
1536         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1537         { .div = 0 }
1538 };
1539
1540 static const struct clksel omap24xx_gpt_clksel[] = {
1541         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1542         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1543         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1544         { .parent = NULL },
1545 };
1546
1547 static struct clk gpt1_ick = {
1548         .name           = "gpt1_ick",
1549         .parent         = &l4_ck,
1550         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1551         .clkdm          = { .name = "core_l4_clkdm" },
1552         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
1553         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1554         .recalc         = &followparent_recalc,
1555 };
1556
1557 static struct clk gpt1_fck = {
1558         .name           = "gpt1_fck",
1559         .parent         = &func_32k_ck,
1560         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1561         .clkdm          = { .name = "core_l4_clkdm" },
1562         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
1563         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1564         .init           = &omap2_init_clksel_parent,
1565         .clksel_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_CLKSEL1),
1566         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1567         .clksel         = omap24xx_gpt_clksel,
1568         .recalc         = &omap2_clksel_recalc,
1569         .round_rate     = &omap2_clksel_round_rate,
1570         .set_rate       = &omap2_clksel_set_rate
1571 };
1572
1573 static struct clk gpt2_ick = {
1574         .name           = "gpt2_ick",
1575         .parent         = &l4_ck,
1576         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1577         .clkdm          = { .name = "core_l4_clkdm" },
1578         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1579         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk gpt2_fck = {
1584         .name           = "gpt2_fck",
1585         .parent         = &func_32k_ck,
1586         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1587         .clkdm          = { .name = "core_l4_clkdm" },
1588         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1589         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1590         .init           = &omap2_init_clksel_parent,
1591         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1592         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1593         .clksel         = omap24xx_gpt_clksel,
1594         .recalc         = &omap2_clksel_recalc,
1595 };
1596
1597 static struct clk gpt3_ick = {
1598         .name           = "gpt3_ick",
1599         .parent         = &l4_ck,
1600         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1601         .clkdm          = { .name = "core_l4_clkdm" },
1602         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1603         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1604         .recalc         = &followparent_recalc,
1605 };
1606
1607 static struct clk gpt3_fck = {
1608         .name           = "gpt3_fck",
1609         .parent         = &func_32k_ck,
1610         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1611         .clkdm          = { .name = "core_l4_clkdm" },
1612         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1613         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1614         .init           = &omap2_init_clksel_parent,
1615         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1616         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1617         .clksel         = omap24xx_gpt_clksel,
1618         .recalc         = &omap2_clksel_recalc,
1619 };
1620
1621 static struct clk gpt4_ick = {
1622         .name           = "gpt4_ick",
1623         .parent         = &l4_ck,
1624         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1625         .clkdm          = { .name = "core_l4_clkdm" },
1626         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1627         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1628         .recalc         = &followparent_recalc,
1629 };
1630
1631 static struct clk gpt4_fck = {
1632         .name           = "gpt4_fck",
1633         .parent         = &func_32k_ck,
1634         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1635         .clkdm          = { .name = "core_l4_clkdm" },
1636         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1637         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1638         .init           = &omap2_init_clksel_parent,
1639         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1640         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1641         .clksel         = omap24xx_gpt_clksel,
1642         .recalc         = &omap2_clksel_recalc,
1643 };
1644
1645 static struct clk gpt5_ick = {
1646         .name           = "gpt5_ick",
1647         .parent         = &l4_ck,
1648         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1649         .clkdm          = { .name = "core_l4_clkdm" },
1650         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1651         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk gpt5_fck = {
1656         .name           = "gpt5_fck",
1657         .parent         = &func_32k_ck,
1658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1659         .clkdm          = { .name = "core_l4_clkdm" },
1660         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1661         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1662         .init           = &omap2_init_clksel_parent,
1663         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1664         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1665         .clksel         = omap24xx_gpt_clksel,
1666         .recalc         = &omap2_clksel_recalc,
1667 };
1668
1669 static struct clk gpt6_ick = {
1670         .name           = "gpt6_ick",
1671         .parent         = &l4_ck,
1672         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1673         .clkdm          = { .name = "core_l4_clkdm" },
1674         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1675         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1676         .recalc         = &followparent_recalc,
1677 };
1678
1679 static struct clk gpt6_fck = {
1680         .name           = "gpt6_fck",
1681         .parent         = &func_32k_ck,
1682         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1683         .clkdm          = { .name = "core_l4_clkdm" },
1684         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1685         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1686         .init           = &omap2_init_clksel_parent,
1687         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1688         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1689         .clksel         = omap24xx_gpt_clksel,
1690         .recalc         = &omap2_clksel_recalc,
1691 };
1692
1693 static struct clk gpt7_ick = {
1694         .name           = "gpt7_ick",
1695         .parent         = &l4_ck,
1696         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1697         .clkdm          = { .name = "core_l4_clkdm" },
1698         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1699         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1700         .recalc         = &followparent_recalc,
1701 };
1702
1703 static struct clk gpt7_fck = {
1704         .name           = "gpt7_fck",
1705         .parent         = &func_32k_ck,
1706         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1707         .clkdm          = { .name = "core_l4_clkdm" },
1708         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1709         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1710         .init           = &omap2_init_clksel_parent,
1711         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1712         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1713         .clksel         = omap24xx_gpt_clksel,
1714         .recalc         = &omap2_clksel_recalc,
1715 };
1716
1717 static struct clk gpt8_ick = {
1718         .name           = "gpt8_ick",
1719         .parent         = &l4_ck,
1720         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1721         .clkdm          = { .name = "core_l4_clkdm" },
1722         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1723         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1724         .recalc         = &followparent_recalc,
1725 };
1726
1727 static struct clk gpt8_fck = {
1728         .name           = "gpt8_fck",
1729         .parent         = &func_32k_ck,
1730         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1731         .clkdm          = { .name = "core_l4_clkdm" },
1732         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1733         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1734         .init           = &omap2_init_clksel_parent,
1735         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1736         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1737         .clksel         = omap24xx_gpt_clksel,
1738         .recalc         = &omap2_clksel_recalc,
1739 };
1740
1741 static struct clk gpt9_ick = {
1742         .name           = "gpt9_ick",
1743         .parent         = &l4_ck,
1744         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1745         .clkdm          = { .name = "core_l4_clkdm" },
1746         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1747         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 static struct clk gpt9_fck = {
1752         .name           = "gpt9_fck",
1753         .parent         = &func_32k_ck,
1754         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1755         .clkdm          = { .name = "core_l4_clkdm" },
1756         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1757         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1758         .init           = &omap2_init_clksel_parent,
1759         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1760         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1761         .clksel         = omap24xx_gpt_clksel,
1762         .recalc         = &omap2_clksel_recalc,
1763 };
1764
1765 static struct clk gpt10_ick = {
1766         .name           = "gpt10_ick",
1767         .parent         = &l4_ck,
1768         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1769         .clkdm          = { .name = "core_l4_clkdm" },
1770         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1771         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1772         .recalc         = &followparent_recalc,
1773 };
1774
1775 static struct clk gpt10_fck = {
1776         .name           = "gpt10_fck",
1777         .parent         = &func_32k_ck,
1778         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1779         .clkdm          = { .name = "core_l4_clkdm" },
1780         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1781         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1782         .init           = &omap2_init_clksel_parent,
1783         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1784         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1785         .clksel         = omap24xx_gpt_clksel,
1786         .recalc         = &omap2_clksel_recalc,
1787 };
1788
1789 static struct clk gpt11_ick = {
1790         .name           = "gpt11_ick",
1791         .parent         = &l4_ck,
1792         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1793         .clkdm          = { .name = "core_l4_clkdm" },
1794         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1795         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1796         .recalc         = &followparent_recalc,
1797 };
1798
1799 static struct clk gpt11_fck = {
1800         .name           = "gpt11_fck",
1801         .parent         = &func_32k_ck,
1802         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1803         .clkdm          = { .name = "core_l4_clkdm" },
1804         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1805         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1806         .init           = &omap2_init_clksel_parent,
1807         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1808         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1809         .clksel         = omap24xx_gpt_clksel,
1810         .recalc         = &omap2_clksel_recalc,
1811 };
1812
1813 static struct clk gpt12_ick = {
1814         .name           = "gpt12_ick",
1815         .parent         = &l4_ck,
1816         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1817         .clkdm          = { .name = "core_l4_clkdm" },
1818         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1819         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1820         .recalc         = &followparent_recalc,
1821 };
1822
1823 static struct clk gpt12_fck = {
1824         .name           = "gpt12_fck",
1825         .parent         = &func_32k_ck,
1826         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1827         .clkdm          = { .name = "core_l4_clkdm" },
1828         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1829         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1830         .init           = &omap2_init_clksel_parent,
1831         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1832         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1833         .clksel         = omap24xx_gpt_clksel,
1834         .recalc         = &omap2_clksel_recalc,
1835 };
1836
1837 static struct clk mcbsp1_ick = {
1838         .name           = "mcbsp_ick",
1839         .id             = 1,
1840         .parent         = &l4_ck,
1841         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1842         .clkdm          = { .name = "core_l4_clkdm" },
1843         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1844         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcbsp1_fck = {
1849         .name           = "mcbsp_fck",
1850         .id             = 1,
1851         .parent         = &func_96m_ck,
1852         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1853         .clkdm          = { .name = "core_l4_clkdm" },
1854         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1855         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk mcbsp2_ick = {
1860         .name           = "mcbsp_ick",
1861         .id             = 2,
1862         .parent         = &l4_ck,
1863         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1864         .clkdm          = { .name = "core_l4_clkdm" },
1865         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1866         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk mcbsp2_fck = {
1871         .name           = "mcbsp_fck",
1872         .id             = 2,
1873         .parent         = &func_96m_ck,
1874         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1875         .clkdm          = { .name = "core_l4_clkdm" },
1876         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1877         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk mcbsp3_ick = {
1882         .name           = "mcbsp_ick",
1883         .id             = 3,
1884         .parent         = &l4_ck,
1885         .flags          = CLOCK_IN_OMAP243X,
1886         .clkdm          = { .name = "core_l4_clkdm" },
1887         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1888         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk mcbsp3_fck = {
1893         .name           = "mcbsp_fck",
1894         .id             = 3,
1895         .parent         = &func_96m_ck,
1896         .flags          = CLOCK_IN_OMAP243X,
1897         .clkdm          = { .name = "core_l4_clkdm" },
1898         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1899         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1900         .recalc         = &followparent_recalc,
1901 };
1902
1903 static struct clk mcbsp4_ick = {
1904         .name           = "mcbsp_ick",
1905         .id             = 4,
1906         .parent         = &l4_ck,
1907         .flags          = CLOCK_IN_OMAP243X,
1908         .clkdm          = { .name = "core_l4_clkdm" },
1909         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1910         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1911         .recalc         = &followparent_recalc,
1912 };
1913
1914 static struct clk mcbsp4_fck = {
1915         .name           = "mcbsp_fck",
1916         .id             = 4,
1917         .parent         = &func_96m_ck,
1918         .flags          = CLOCK_IN_OMAP243X,
1919         .clkdm          = { .name = "core_l4_clkdm" },
1920         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1921         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1922         .recalc         = &followparent_recalc,
1923 };
1924
1925 static struct clk mcbsp5_ick = {
1926         .name           = "mcbsp_ick",
1927         .id             = 5,
1928         .parent         = &l4_ck,
1929         .flags          = CLOCK_IN_OMAP243X,
1930         .clkdm          = { .name = "core_l4_clkdm" },
1931         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1932         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1933         .recalc         = &followparent_recalc,
1934 };
1935
1936 static struct clk mcbsp5_fck = {
1937         .name           = "mcbsp_fck",
1938         .id             = 5,
1939         .parent         = &func_96m_ck,
1940         .flags          = CLOCK_IN_OMAP243X,
1941         .clkdm          = { .name = "core_l4_clkdm" },
1942         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1943         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1944         .recalc         = &followparent_recalc,
1945 };
1946
1947 static struct clk mcspi1_ick = {
1948         .name           = "mcspi_ick",
1949         .id             = 1,
1950         .parent         = &l4_ck,
1951         .clkdm          = { .name = "core_l4_clkdm" },
1952         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1953         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1954         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1955         .recalc         = &followparent_recalc,
1956 };
1957
1958 static struct clk mcspi1_fck = {
1959         .name           = "mcspi_fck",
1960         .id             = 1,
1961         .parent         = &func_48m_ck,
1962         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1963         .clkdm          = { .name = "core_l4_clkdm" },
1964         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1965         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1966         .recalc         = &followparent_recalc,
1967 };
1968
1969 static struct clk mcspi2_ick = {
1970         .name           = "mcspi_ick",
1971         .id             = 2,
1972         .parent         = &l4_ck,
1973         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1974         .clkdm          = { .name = "core_l4_clkdm" },
1975         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1976         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1977         .recalc         = &followparent_recalc,
1978 };
1979
1980 static struct clk mcspi2_fck = {
1981         .name           = "mcspi_fck",
1982         .id             = 2,
1983         .parent         = &func_48m_ck,
1984         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1985         .clkdm          = { .name = "core_l4_clkdm" },
1986         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1987         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1988         .recalc         = &followparent_recalc,
1989 };
1990
1991 static struct clk mcspi3_ick = {
1992         .name           = "mcspi_ick",
1993         .id             = 3,
1994         .parent         = &l4_ck,
1995         .flags          = CLOCK_IN_OMAP243X,
1996         .clkdm          = { .name = "core_l4_clkdm" },
1997         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1998         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1999         .recalc         = &followparent_recalc,
2000 };
2001
2002 static struct clk mcspi3_fck = {
2003         .name           = "mcspi_fck",
2004         .id             = 3,
2005         .parent         = &func_48m_ck,
2006         .flags          = CLOCK_IN_OMAP243X,
2007         .clkdm          = { .name = "core_l4_clkdm" },
2008         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2009         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2010         .recalc         = &followparent_recalc,
2011 };
2012
2013 static struct clk uart1_ick = {
2014         .name           = "uart1_ick",
2015         .parent         = &l4_ck,
2016         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2017         .clkdm          = { .name = "core_l4_clkdm" },
2018         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2019         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2020         .recalc         = &followparent_recalc,
2021 };
2022
2023 static struct clk uart1_fck = {
2024         .name           = "uart1_fck",
2025         .parent         = &func_48m_ck,
2026         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2027         .clkdm          = { .name = "core_l4_clkdm" },
2028         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2029         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2030         .recalc         = &followparent_recalc,
2031 };
2032
2033 static struct clk uart2_ick = {
2034         .name           = "uart2_ick",
2035         .parent         = &l4_ck,
2036         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2037         .clkdm          = { .name = "core_l4_clkdm" },
2038         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2039         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2040         .recalc         = &followparent_recalc,
2041 };
2042
2043 static struct clk uart2_fck = {
2044         .name           = "uart2_fck",
2045         .parent         = &func_48m_ck,
2046         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2047         .clkdm          = { .name = "core_l4_clkdm" },
2048         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2049         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2050         .recalc         = &followparent_recalc,
2051 };
2052
2053 static struct clk uart3_ick = {
2054         .name           = "uart3_ick",
2055         .parent         = &l4_ck,
2056         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2057         .clkdm          = { .name = "core_l4_clkdm" },
2058         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2059         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2060         .recalc         = &followparent_recalc,
2061 };
2062
2063 static struct clk uart3_fck = {
2064         .name           = "uart3_fck",
2065         .parent         = &func_48m_ck,
2066         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2067         .clkdm          = { .name = "core_l4_clkdm" },
2068         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2069         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2070         .recalc         = &followparent_recalc,
2071 };
2072
2073 static struct clk gpios_ick = {
2074         .name           = "gpios_ick",
2075         .parent         = &l4_ck,
2076         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2077         .clkdm          = { .name = "core_l4_clkdm" },
2078         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2079         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2080         .recalc         = &followparent_recalc,
2081 };
2082
2083 static struct clk gpios_fck = {
2084         .name           = "gpios_fck",
2085         .parent         = &func_32k_ck,
2086         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2087         .clkdm          = { .name = "prm_clkdm" },
2088         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2089         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2090         .recalc         = &followparent_recalc,
2091 };
2092
2093 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2094 static struct clk mpu_wdt_ick = {
2095         .name           = "mpu_wdt_ick",
2096         .parent         = &l4_ck,
2097         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2098         .clkdm          = { .name = "prm_clkdm" },
2099         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2100         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2101         .recalc         = &followparent_recalc,
2102 };
2103
2104 /* aka WDT2 */
2105 static struct clk mpu_wdt_fck = {
2106         .name           = "mpu_wdt_fck",
2107         .parent         = &func_32k_ck,
2108         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2109         .clkdm          = { .name = "prm_clkdm" },
2110         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2111         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2112         .recalc         = &followparent_recalc,
2113 };
2114
2115 static struct clk sync_32k_ick = {
2116         .name           = "sync_32k_ick",
2117         .parent         = &l4_ck,
2118         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2119                                 ENABLE_ON_INIT,
2120         .clkdm          = { .name = "core_l4_clkdm" },
2121         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2122         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2123         .recalc         = &followparent_recalc,
2124 };
2125
2126 /* REVISIT: parent is really wu_l4_iclk */
2127 static struct clk wdt1_ick = {
2128         .name           = "wdt1_ick",
2129         .parent         = &l4_ck,
2130         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2131         .clkdm          = { .name = "prm_clkdm" },
2132         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2133         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2134         .recalc         = &followparent_recalc,
2135 };
2136
2137 static struct clk omapctrl_ick = {
2138         .name           = "omapctrl_ick",
2139         .parent         = &l4_ck,
2140         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2141                                 ENABLE_ON_INIT,
2142         .clkdm          = { .name = "core_l4_clkdm" },
2143         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2144         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2145         .recalc         = &followparent_recalc,
2146 };
2147
2148 static struct clk icr_ick = {
2149         .name           = "icr_ick",
2150         .parent         = &l4_ck,
2151         .flags          = CLOCK_IN_OMAP243X,
2152         .clkdm          = { .name = "core_l4_clkdm" },
2153         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2154         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 static struct clk cam_ick = {
2159         .name           = "cam_ick",
2160         .parent         = &l4_ck,
2161         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2162         .clkdm          = { .name = "core_l4_clkdm" },
2163         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2164         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2165         .recalc         = &followparent_recalc,
2166 };
2167
2168 /*
2169  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2170  * split into two separate clocks, since the parent clocks are different
2171  * and the clockdomains are also different.
2172  */
2173 static struct clk cam_fck = {
2174         .name           = "cam_fck",
2175         .parent         = &func_96m_ck,
2176         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2177         .clkdm          = { .name = "core_l3_clkdm" },
2178         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2179         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk mailboxes_ick = {
2184         .name           = "mailboxes_ick",
2185         .parent         = &l4_ck,
2186         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2187         .clkdm          = { .name = "core_l4_clkdm" },
2188         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2189         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk wdt4_ick = {
2194         .name           = "wdt4_ick",
2195         .parent         = &l4_ck,
2196         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2197         .clkdm          = { .name = "core_l4_clkdm" },
2198         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2199         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk wdt4_fck = {
2204         .name           = "wdt4_fck",
2205         .parent         = &func_32k_ck,
2206         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2207         .clkdm          = { .name = "core_l4_clkdm" },
2208         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2209         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 static struct clk wdt3_ick = {
2214         .name           = "wdt3_ick",
2215         .parent         = &l4_ck,
2216         .flags          = CLOCK_IN_OMAP242X,
2217         .clkdm          = { .name = "core_l4_clkdm" },
2218         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2219         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk wdt3_fck = {
2224         .name           = "wdt3_fck",
2225         .parent         = &func_32k_ck,
2226         .flags          = CLOCK_IN_OMAP242X,
2227         .clkdm          = { .name = "core_l4_clkdm" },
2228         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2229         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2230         .recalc         = &followparent_recalc,
2231 };
2232
2233 static struct clk mspro_ick = {
2234         .name           = "mspro_ick",
2235         .parent         = &l4_ck,
2236         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2237         .clkdm          = { .name = "core_l4_clkdm" },
2238         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2239         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk mspro_fck = {
2244         .name           = "mspro_fck",
2245         .parent         = &func_96m_ck,
2246         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2247         .clkdm          = { .name = "core_l4_clkdm" },
2248         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2249         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2250         .recalc         = &followparent_recalc,
2251 };
2252
2253 static struct clk mmc_ick = {
2254         .name           = "mmc_ick",
2255         .parent         = &l4_ck,
2256         .flags          = CLOCK_IN_OMAP242X,
2257         .clkdm          = { .name = "core_l4_clkdm" },
2258         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2259         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk mmc_fck = {
2264         .name           = "mmc_fck",
2265         .parent         = &func_96m_ck,
2266         .flags          = CLOCK_IN_OMAP242X,
2267         .clkdm          = { .name = "core_l4_clkdm" },
2268         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2269         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk fac_ick = {
2274         .name           = "fac_ick",
2275         .parent         = &l4_ck,
2276         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2277         .clkdm          = { .name = "core_l4_clkdm" },
2278         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2279         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk fac_fck = {
2284         .name           = "fac_fck",
2285         .parent         = &func_12m_ck,
2286         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2287         .clkdm          = { .name = "core_l4_clkdm" },
2288         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2289         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2290         .recalc         = &followparent_recalc,
2291 };
2292
2293 static struct clk eac_ick = {
2294         .name           = "eac_ick",
2295         .parent         = &l4_ck,
2296         .flags          = CLOCK_IN_OMAP242X,
2297         .clkdm          = { .name = "core_l4_clkdm" },
2298         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2299         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2300         .recalc         = &followparent_recalc,
2301 };
2302
2303 static struct clk eac_fck = {
2304         .name           = "eac_fck",
2305         .parent         = &func_96m_ck,
2306         .flags          = CLOCK_IN_OMAP242X,
2307         .clkdm          = { .name = "core_l4_clkdm" },
2308         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2309         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2310         .recalc         = &followparent_recalc,
2311 };
2312
2313 static struct clk hdq_ick = {
2314         .name           = "hdq_ick",
2315         .parent         = &l4_ck,
2316         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2317         .clkdm          = { .name = "core_l4_clkdm" },
2318         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2319         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2320         .recalc         = &followparent_recalc,
2321 };
2322
2323 static struct clk hdq_fck = {
2324         .name           = "hdq_fck",
2325         .parent         = &func_12m_ck,
2326         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2327         .clkdm          = { .name = "core_l4_clkdm" },
2328         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2329         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2330         .recalc         = &followparent_recalc,
2331 };
2332
2333 static struct clk i2c2_ick = {
2334         .name           = "i2c_ick",
2335         .id             = 2,
2336         .parent         = &l4_ck,
2337         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2338         .clkdm          = { .name = "core_l4_clkdm" },
2339         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2340         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2341         .recalc         = &followparent_recalc,
2342 };
2343
2344 static struct clk i2c2_fck = {
2345         .name           = "i2c_fck",
2346         .id             = 2,
2347         .parent         = &func_12m_ck,
2348         .flags          = CLOCK_IN_OMAP242X,
2349         .clkdm          = { .name = "core_l4_clkdm" },
2350         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2351         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk i2chs2_fck = {
2356         .name           = "i2chs_fck",
2357         .id             = 2,
2358         .parent         = &func_96m_ck,
2359         .flags          = CLOCK_IN_OMAP243X,
2360         .clkdm          = { .name = "core_l4_clkdm" },
2361         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2362         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2363         .recalc         = &followparent_recalc,
2364 };
2365
2366 static struct clk i2c1_ick = {
2367         .name           = "i2c_ick",
2368         .id             = 1,
2369         .parent         = &l4_ck,
2370         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2371         .clkdm          = { .name = "core_l4_clkdm" },
2372         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2373         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2374         .recalc         = &followparent_recalc,
2375 };
2376
2377 static struct clk i2c1_fck = {
2378         .name           = "i2c_fck",
2379         .id             = 1,
2380         .parent         = &func_12m_ck,
2381         .flags          = CLOCK_IN_OMAP242X,
2382         .clkdm          = { .name = "core_l4_clkdm" },
2383         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2384         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk i2chs1_fck = {
2389         .name           = "i2chs_fck",
2390         .id             = 1,
2391         .parent         = &func_96m_ck,
2392         .flags          = CLOCK_IN_OMAP243X,
2393         .clkdm          = { .name = "core_l4_clkdm" },
2394         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2395         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2396         .recalc         = &followparent_recalc,
2397 };
2398
2399 static struct clk gpmc_fck = {
2400         .name           = "gpmc_fck",
2401         .parent         = &core_l3_ck,
2402         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2403                                 ENABLE_ON_INIT,
2404         .clkdm          = { .name = "core_l3_clkdm" },
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk sdma_fck = {
2409         .name           = "sdma_fck",
2410         .parent         = &core_l3_ck,
2411         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2412         .clkdm          = { .name = "core_l3_clkdm" },
2413         .recalc         = &followparent_recalc,
2414 };
2415
2416 static struct clk sdma_ick = {
2417         .name           = "sdma_ick",
2418         .parent         = &l4_ck,
2419         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2420         .clkdm          = { .name = "core_l3_clkdm" },
2421         .recalc         = &followparent_recalc,
2422 };
2423
2424 static struct clk vlynq_ick = {
2425         .name           = "vlynq_ick",
2426         .parent         = &core_l3_ck,
2427         .flags          = CLOCK_IN_OMAP242X,
2428         .clkdm          = { .name = "core_l3_clkdm" },
2429         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2430         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2431         .recalc         = &followparent_recalc,
2432 };
2433
2434 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2435         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2436         { .div = 0 }
2437 };
2438
2439 static const struct clksel_rate vlynq_fck_core_rates[] = {
2440         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2441         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2442         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2443         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2444         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2445         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2446         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2447         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2448         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2449         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2450         { .div = 0 }
2451 };
2452
2453 static const struct clksel vlynq_fck_clksel[] = {
2454         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2455         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2456         { .parent = NULL }
2457 };
2458
2459 static struct clk vlynq_fck = {
2460         .name           = "vlynq_fck",
2461         .parent         = &func_96m_ck,
2462         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2463         .clkdm          = { .name = "core_l3_clkdm" },
2464         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2465         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2466         .init           = &omap2_init_clksel_parent,
2467         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
2468         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2469         .clksel         = vlynq_fck_clksel,
2470         .recalc         = &omap2_clksel_recalc,
2471         .round_rate     = &omap2_clksel_round_rate,
2472         .set_rate       = &omap2_clksel_set_rate
2473 };
2474
2475 static struct clk sdrc_ick = {
2476         .name           = "sdrc_ick",
2477         .parent         = &l4_ck,
2478         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2479         .clkdm          = { .name = "core_l4_clkdm" },
2480         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
2481         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2482         .recalc         = &followparent_recalc,
2483 };
2484
2485 static struct clk des_ick = {
2486         .name           = "des_ick",
2487         .parent         = &l4_ck,
2488         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2489         .clkdm          = { .name = "core_l4_clkdm" },
2490         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2491         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2492         .recalc         = &followparent_recalc,
2493 };
2494
2495 static struct clk sha_ick = {
2496         .name           = "sha_ick",
2497         .parent         = &l4_ck,
2498         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2499         .clkdm          = { .name = "core_l4_clkdm" },
2500         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2501         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2502         .recalc         = &followparent_recalc,
2503 };
2504
2505 static struct clk rng_ick = {
2506         .name           = "rng_ick",
2507         .parent         = &l4_ck,
2508         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2509         .clkdm          = { .name = "core_l4_clkdm" },
2510         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2511         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2512         .recalc         = &followparent_recalc,
2513 };
2514
2515 static struct clk aes_ick = {
2516         .name           = "aes_ick",
2517         .parent         = &l4_ck,
2518         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2519         .clkdm          = { .name = "core_l4_clkdm" },
2520         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2521         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2522         .recalc         = &followparent_recalc,
2523 };
2524
2525 static struct clk pka_ick = {
2526         .name           = "pka_ick",
2527         .parent         = &l4_ck,
2528         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2529         .clkdm          = { .name = "core_l4_clkdm" },
2530         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2531         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2532         .recalc         = &followparent_recalc,
2533 };
2534
2535 static struct clk usb_fck = {
2536         .name           = "usb_fck",
2537         .parent         = &func_48m_ck,
2538         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2539         .clkdm          = { .name = "core_l3_clkdm" },
2540         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2541         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2542         .recalc         = &followparent_recalc,
2543 };
2544
2545 static struct clk usbhs_ick = {
2546         .name           = "usbhs_ick",
2547         .parent         = &core_l3_ck,
2548         .flags          = CLOCK_IN_OMAP243X,
2549         .clkdm          = { .name = "core_l3_clkdm" },
2550         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2551         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2552         .recalc         = &followparent_recalc,
2553 };
2554
2555 static struct clk mmchs1_ick = {
2556         .name           = "mmchs_ick",
2557         .id             = 1,
2558         .parent         = &l4_ck,
2559         .flags          = CLOCK_IN_OMAP243X,
2560         .clkdm          = { .name = "core_l4_clkdm" },
2561         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2562         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2563         .recalc         = &followparent_recalc,
2564 };
2565
2566 static struct clk mmchs1_fck = {
2567         .name           = "mmchs_fck",
2568         .id             = 1,
2569         .parent         = &func_96m_ck,
2570         .flags          = CLOCK_IN_OMAP243X,
2571         .clkdm          = { .name = "core_l3_clkdm" },
2572         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2573         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2574         .recalc         = &followparent_recalc,
2575 };
2576
2577 static struct clk mmchs2_ick = {
2578         .name           = "mmchs_ick",
2579         .id             = 2,
2580         .parent         = &l4_ck,
2581         .flags          = CLOCK_IN_OMAP243X,
2582         .clkdm          = { .name = "core_l4_clkdm" },
2583         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2584         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2585         .recalc         = &followparent_recalc,
2586 };
2587
2588 static struct clk mmchs2_fck = {
2589         .name           = "mmchs_fck",
2590         .id             = 2,
2591         .parent         = &func_96m_ck,
2592         .flags          = CLOCK_IN_OMAP243X,
2593         .clkdm          = { .name = "core_l4_clkdm" },
2594         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2595         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2596         .recalc         = &followparent_recalc,
2597 };
2598
2599 static struct clk gpio5_ick = {
2600         .name           = "gpio5_ick",
2601         .parent         = &l4_ck,
2602         .flags          = CLOCK_IN_OMAP243X,
2603         .clkdm          = { .name = "core_l4_clkdm" },
2604         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2605         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2606         .recalc         = &followparent_recalc,
2607 };
2608
2609 static struct clk gpio5_fck = {
2610         .name           = "gpio5_fck",
2611         .parent         = &func_32k_ck,
2612         .flags          = CLOCK_IN_OMAP243X,
2613         .clkdm          = { .name = "core_l4_clkdm" },
2614         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2615         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2616         .recalc         = &followparent_recalc,
2617 };
2618
2619 static struct clk mdm_intc_ick = {
2620         .name           = "mdm_intc_ick",
2621         .parent         = &l4_ck,
2622         .flags          = CLOCK_IN_OMAP243X,
2623         .clkdm          = { .name = "core_l4_clkdm" },
2624         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2625         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2626         .recalc         = &followparent_recalc,
2627 };
2628
2629 static struct clk mmchsdb1_fck = {
2630         .name           = "mmchsdb_fck",
2631         .id             = 1,
2632         .parent         = &func_32k_ck,
2633         .flags          = CLOCK_IN_OMAP243X,
2634         .clkdm          = { .name = "core_l4_clkdm" },
2635         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2636         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2637         .recalc         = &followparent_recalc,
2638 };
2639
2640 static struct clk mmchsdb2_fck = {
2641         .name           = "mmchsdb_fck",
2642         .id             = 2,
2643         .parent         = &func_32k_ck,
2644         .flags          = CLOCK_IN_OMAP243X,
2645         .clkdm          = { .name = "core_l4_clkdm" },
2646         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2647         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2648         .recalc         = &followparent_recalc,
2649 };
2650
2651 /*
2652  * This clock is a composite clock which does entire set changes then
2653  * forces a rebalance. It keys on the MPU speed, but it really could
2654  * be any key speed part of a set in the rate table.
2655  *
2656  * to really change a set, you need memory table sets which get changed
2657  * in sram, pre-notifiers & post notifiers, changing the top set, without
2658  * having low level display recalc's won't work... this is why dpm notifiers
2659  * work, isr's off, walk a list of clocks already _off_ and not messing with
2660  * the bus.
2661  *
2662  * This clock should have no parent. It embodies the entire upper level
2663  * active set. A parent will mess up some of the init also.
2664  */
2665 static struct clk virt_prcm_set = {
2666         .name           = "virt_prcm_set",
2667         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2668                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2669         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2670         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2671         .set_rate       = &omap2_select_table_rate,
2672         .round_rate     = &omap2_round_to_table_rate,
2673 };
2674
2675 static struct clk *onchip_24xx_clks[] __initdata = {
2676         /* external root sources */
2677         &func_32k_ck,
2678         &osc_ck,
2679         &sys_ck,
2680         &alt_ck,
2681         /* internal analog sources */
2682         &dpll_ck,
2683         &apll96_ck,
2684         &apll54_ck,
2685         /* internal prcm root sources */
2686         &func_54m_ck,
2687         &core_ck,
2688         &func_96m_ck,
2689         &func_48m_ck,
2690         &func_12m_ck,
2691         &wdt1_osc_ck,
2692         &sys_clkout_src,
2693         &sys_clkout,
2694         &sys_clkout2_src,
2695         &sys_clkout2,
2696         &emul_ck,
2697         /* mpu domain clocks */
2698         &mpu_ck,
2699         /* dsp domain clocks */
2700         &dsp_fck,
2701         &dsp_irate_ick,
2702         &dsp_ick,               /* 242x */
2703         &iva2_1_ick,            /* 243x */
2704         &iva1_ifck,             /* 242x */
2705         &iva1_mpu_int_ifck,     /* 242x */
2706         /* GFX domain clocks */
2707         &gfx_3d_fck,
2708         &gfx_2d_fck,
2709         &gfx_ick,
2710         /* Modem domain clocks */
2711         &mdm_ick,
2712         &mdm_osc_ck,
2713         /* DSS domain clocks */
2714         &dss_ick,
2715         &dss1_fck,
2716         &dss2_fck,
2717         &dss_54m_fck,
2718         /* L3 domain clocks */
2719         &core_l3_ck,
2720         &ssi_ssr_sst_fck,
2721         &usb_l4_ick,
2722         /* L4 domain clocks */
2723         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2724         &ssi_l4_ick,
2725         /* virtual meta-group clock */
2726         &virt_prcm_set,
2727         /* general l4 interface ck, multi-parent functional clk */
2728         &gpt1_ick,
2729         &gpt1_fck,
2730         &gpt2_ick,
2731         &gpt2_fck,
2732         &gpt3_ick,
2733         &gpt3_fck,
2734         &gpt4_ick,
2735         &gpt4_fck,
2736         &gpt5_ick,
2737         &gpt5_fck,
2738         &gpt6_ick,
2739         &gpt6_fck,
2740         &gpt7_ick,
2741         &gpt7_fck,
2742         &gpt8_ick,
2743         &gpt8_fck,
2744         &gpt9_ick,
2745         &gpt9_fck,
2746         &gpt10_ick,
2747         &gpt10_fck,
2748         &gpt11_ick,
2749         &gpt11_fck,
2750         &gpt12_ick,
2751         &gpt12_fck,
2752         &mcbsp1_ick,
2753         &mcbsp1_fck,
2754         &mcbsp2_ick,
2755         &mcbsp2_fck,
2756         &mcbsp3_ick,
2757         &mcbsp3_fck,
2758         &mcbsp4_ick,
2759         &mcbsp4_fck,
2760         &mcbsp5_ick,
2761         &mcbsp5_fck,
2762         &mcspi1_ick,
2763         &mcspi1_fck,
2764         &mcspi2_ick,
2765         &mcspi2_fck,
2766         &mcspi3_ick,
2767         &mcspi3_fck,
2768         &uart1_ick,
2769         &uart1_fck,
2770         &uart2_ick,
2771         &uart2_fck,
2772         &uart3_ick,
2773         &uart3_fck,
2774         &gpios_ick,
2775         &gpios_fck,
2776         &mpu_wdt_ick,
2777         &mpu_wdt_fck,
2778         &sync_32k_ick,
2779         &wdt1_ick,
2780         &omapctrl_ick,
2781         &icr_ick,
2782         &cam_fck,
2783         &cam_ick,
2784         &mailboxes_ick,
2785         &wdt4_ick,
2786         &wdt4_fck,
2787         &wdt3_ick,
2788         &wdt3_fck,
2789         &mspro_ick,
2790         &mspro_fck,
2791         &mmc_ick,
2792         &mmc_fck,
2793         &fac_ick,
2794         &fac_fck,
2795         &eac_ick,
2796         &eac_fck,
2797         &hdq_ick,
2798         &hdq_fck,
2799         &i2c1_ick,
2800         &i2c1_fck,
2801         &i2chs1_fck,
2802         &i2c2_ick,
2803         &i2c2_fck,
2804         &i2chs2_fck,
2805         &gpmc_fck,
2806         &sdma_fck,
2807         &sdma_ick,
2808         &vlynq_ick,
2809         &vlynq_fck,
2810         &sdrc_ick,
2811         &des_ick,
2812         &sha_ick,
2813         &rng_ick,
2814         &aes_ick,
2815         &pka_ick,
2816         &usb_fck,
2817         &usbhs_ick,
2818         &mmchs1_ick,
2819         &mmchs1_fck,
2820         &mmchs2_ick,
2821         &mmchs2_fck,
2822         &gpio5_ick,
2823         &gpio5_fck,
2824         &mdm_intc_ick,
2825         &mmchsdb1_fck,
2826         &mmchsdb2_fck,
2827 };
2828
2829 #endif
2830