arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  23
  24 #include "clock.h"
  25
  26 #include "prm.h"
  27 #include "cm.h"
  28 #include "prm_regbits_24xx.h"
  29 #include "cm_regbits_24xx.h"
  30 #include "sdrc.h"
  31
  32 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  33  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  34  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  35  */
  36 struct prcm_config {
  37         unsigned long xtal_speed;       /* crystal rate */
  38         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  39         unsigned long mpu_speed;        /* speed of MPU */
  40         unsigned long cm_clksel_mpu;    /* mpu divider */
  41         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  42         unsigned long cm_clksel_gfx;    /* gfx dividers */
  43         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  44         unsigned long cm_clksel1_pll;   /* m,n */
  45         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  46         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  47         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  48         unsigned char flags;
  49 };
  50
  51 /*
  52  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  53  * These configurations are characterized by voltage and speed for clocks.
  54  * The device is only validated for certain combinations. One way to express
  55  * these combinations is via the 'ratio's' which the clocks operate with
  56  * respect to each other. These ratio sets are for a given voltage/DPLL
  57  * setting. All configurations can be described by a DPLL setting and a ratio
  58  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  59  *
  60  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  61  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  62  * 2430 (iva2.1, NOdsp, mdm)
  63  */
  64
  65 /* Core fields for cm_clksel, not ratio governed */
  66 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  67 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  68 #define RX_CLKSEL_SSI                   (0x5 << 20)
  69
  70 /*-------------------------------------------------------------------------
  71  * Voltage/DPLL ratios
  72  *-------------------------------------------------------------------------*/
  73
  74 /* 2430 Ratio's, 2430-Ratio Config 1 */
  75 #define R1_CLKSEL_L3                    (4 << 0)
  76 #define R1_CLKSEL_L4                    (2 << 5)
  77 #define R1_CLKSEL_USB                   (4 << 25)
  78 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  79                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  80                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  81 #define R1_CLKSEL_MPU                   (2 << 0)
  82 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  83 #define R1_CLKSEL_DSP                   (2 << 0)
  84 #define R1_CLKSEL_DSP_IF                (2 << 5)
  85 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  86 #define R1_CLKSEL_GFX                   (2 << 0)
  87 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  88 #define R1_CLKSEL_MDM                   (4 << 0)
  89 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  90
  91 /* 2430-Ratio Config 2 */
  92 #define R2_CLKSEL_L3                    (6 << 0)
  93 #define R2_CLKSEL_L4                    (2 << 5)
  94 #define R2_CLKSEL_USB                   (2 << 25)
  95 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
  96                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  97                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
  98 #define R2_CLKSEL_MPU                   (2 << 0)
  99 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 100 #define R2_CLKSEL_DSP                   (2 << 0)
 101 #define R2_CLKSEL_DSP_IF                (3 << 5)
 102 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 103 #define R2_CLKSEL_GFX                   (2 << 0)
 104 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 105 #define R2_CLKSEL_MDM                   (6 << 0)
 106 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 107
 108 /* 2430-Ratio Bootm (BYPASS) */
 109 #define RB_CLKSEL_L3                    (1 << 0)
 110 #define RB_CLKSEL_L4                    (1 << 5)
 111 #define RB_CLKSEL_USB                   (1 << 25)
 112 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 113                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 114                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 115 #define RB_CLKSEL_MPU                   (1 << 0)
 116 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 117 #define RB_CLKSEL_DSP                   (1 << 0)
 118 #define RB_CLKSEL_DSP_IF                (1 << 5)
 119 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 120 #define RB_CLKSEL_GFX                   (1 << 0)
 121 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 122 #define RB_CLKSEL_MDM                   (1 << 0)
 123 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 124
 125 /* 2420 Ratio Equivalents */
 126 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 127 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 128
 129 /* 2420-PRCM III 532MHz core */
 130 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 131 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 132 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 133 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 134                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 135                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 136                                         RIII_CLKSEL_L3
 137 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 138 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 139 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 140 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 141 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 142 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 143 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 144 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 145                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 146                                         RIII_CLKSEL_DSP
 147 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 148 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 149
 150 /* 2420-PRCM II 600MHz core */
 151 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 152 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 153 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 154 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 155                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 156                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 157                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 158 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 159 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 160 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 161 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 162 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 163 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 164 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 165 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 166                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 167                                         RII_CLKSEL_DSP
 168 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 169 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 170
 171 /* 2420-PRCM I 660MHz core */
 172 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 173 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 174 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 175 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 176                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 177                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 178                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 179 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 180 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 181 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 182 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 183 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 184 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 185 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 186 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 187                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 188                                         RI_CLKSEL_DSP
 189 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 190 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 191
 192 /* 2420-PRCM VII (boot) */
 193 #define RVII_CLKSEL_L3                  (1 << 0)
 194 #define RVII_CLKSEL_L4                  (1 << 5)
 195 #define RVII_CLKSEL_DSS1                (1 << 8)
 196 #define RVII_CLKSEL_DSS2                (0 << 13)
 197 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 198 #define RVII_CLKSEL_SSI                 (1 << 20)
 199 #define RVII_CLKSEL_USB                 (1 << 25)
 200
 201 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 202                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 203                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 204
 205 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 206 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 207
 208 #define RVII_CLKSEL_DSP                 (1 << 0)
 209 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 210 #define RVII_SYNC_DSP                   (0 << 7)
 211 #define RVII_CLKSEL_IVA                 (1 << 8)
 212 #define RVII_SYNC_IVA                   (0 << 13)
 213 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 214                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 215
 216 #define RVII_CLKSEL_GFX                 (1 << 0)
 217 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 218
 219 /*-------------------------------------------------------------------------
 220  * 2430 Target modes: Along with each configuration the CPU has several
 221  * modes which goes along with them. Modes mainly are the addition of
 222  * describe DPLL combinations to go along with a ratio.
 223  *-------------------------------------------------------------------------*/
 224
 225 /* Hardware governed */
 226 #define MX_48M_SRC                      (0 << 3)
 227 #define MX_54M_SRC                      (0 << 5)
 228 #define MX_APLLS_CLIKIN_12              (3 << 23)
 229 #define MX_APLLS_CLIKIN_13              (2 << 23)
 230 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 231
 232 /*
 233  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 234  * #2   (ratio1) baseport-target
 235  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 236  */
 237 #define M5A_DPLL_MULT_12                (133 << 12)
 238 #define M5A_DPLL_DIV_12                 (5 << 8)
 239 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 240                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 241                                         MX_APLLS_CLIKIN_12
 242 #define M5A_DPLL_MULT_13                (266 << 12)
 243 #define M5A_DPLL_DIV_13                 (12 << 8)
 244 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 245                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 246                                         MX_APLLS_CLIKIN_13
 247 #define M5A_DPLL_MULT_19                (180 << 12)
 248 #define M5A_DPLL_DIV_19                 (12 << 8)
 249 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 250                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 251                                         MX_APLLS_CLIKIN_19_2
 252 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 253 #define M5B_DPLL_MULT_12                (50 << 12)
 254 #define M5B_DPLL_DIV_12                 (2 << 8)
 255 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 256                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 257                                         MX_APLLS_CLIKIN_12
 258 #define M5B_DPLL_MULT_13                (200 << 12)
 259 #define M5B_DPLL_DIV_13                 (12 << 8)
 260
 261 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 262                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 263                                         MX_APLLS_CLIKIN_13
 264 #define M5B_DPLL_MULT_19                (125 << 12)
 265 #define M5B_DPLL_DIV_19                 (31 << 8)
 266 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 267                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 268                                         MX_APLLS_CLIKIN_19_2
 269 /*
 270  * #4   (ratio2)
 271  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 272  */
 273 #define M3_DPLL_MULT_12                 (55 << 12)
 274 #define M3_DPLL_DIV_12                  (1 << 8)
 275 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 276                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 277                                         MX_APLLS_CLIKIN_12
 278 #define M3_DPLL_MULT_13                 (330 << 12)
 279 #define M3_DPLL_DIV_13                  (12 << 8)
 280 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 281                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 282                                         MX_APLLS_CLIKIN_13
 283 #define M3_DPLL_MULT_19                 (275 << 12)
 284 #define M3_DPLL_DIV_19                  (15 << 8)
 285 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 286                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 287                                         MX_APLLS_CLIKIN_19_2
 288 /* boot (boot) */
 289 #define MB_DPLL_MULT                    (1 << 12)
 290 #define MB_DPLL_DIV                     (0 << 8)
 291 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 292                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 293
 294 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 295                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 296
 297 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 298                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 299
 300 /*
 301  * 2430 - chassis (sedna)
 302  * 165 (ratio1) same as above #2
 303  * 150 (ratio1)
 304  * 133 (ratio2) same as above #4
 305  * 110 (ratio2) same as above #3
 306  * 104 (ratio2)
 307  * boot (boot)
 308  */
 309
 310 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 311 #define MI_DPLL_MULT_12                 (55 << 12)
 312 #define MI_DPLL_DIV_12                  (1 << 8)
 313 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 314                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 315                                         MX_APLLS_CLIKIN_12
 316
 317 /*
 318  * 2420 Equivalent - mode registers
 319  * PRCM II , target DPLL = 2*300MHz = 600MHz
 320  */
 321 #define MII_DPLL_MULT_12                (50 << 12)
 322 #define MII_DPLL_DIV_12                 (1 << 8)
 323 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 324                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 325                                         MX_APLLS_CLIKIN_12
 326 #define MII_DPLL_MULT_13                (300 << 12)
 327 #define MII_DPLL_DIV_13                 (12 << 8)
 328 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 329                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 330                                         MX_APLLS_CLIKIN_13
 331
 332 /* PRCM III target DPLL = 2*266 = 532MHz*/
 333 #define MIII_DPLL_MULT_12               (133 << 12)
 334 #define MIII_DPLL_DIV_12                (5 << 8)
 335 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 336                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 337                                         MX_APLLS_CLIKIN_12
 338 #define MIII_DPLL_MULT_13               (266 << 12)
 339 #define MIII_DPLL_DIV_13                (12 << 8)
 340 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 341                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 342                                         MX_APLLS_CLIKIN_13
 343
 344 /* PRCM VII (boot bypass) */
 345 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 346 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 347
 348 /* High and low operation value */
 349 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 350 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 351
 352 /* MPU speed defines */
 353 #define S12M    12000000
 354 #define S13M    13000000
 355 #define S19M    19200000
 356 #define S26M    26000000
 357 #define S100M   100000000
 358 #define S133M   133000000
 359 #define S150M   150000000
 360 #define S165M   165000000
 361 #define S200M   200000000
 362 #define S266M   266000000
 363 #define S300M   300000000
 364 #define S330M   330000000
 365 #define S400M   400000000
 366 #define S532M   532000000
 367 #define S600M   600000000
 368 #define S660M   660000000
 369
 370 /*-------------------------------------------------------------------------
 371  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 372  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 373  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 374  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 375  *
 376  * Filling in table based on H4 boards and 2430-SDPs variants available.
 377  * There are quite a few more rates combinations which could be defined.
 378  *
 379  * When multiple values are defined the start up will try and choose the
 380  * fastest one. If a 'fast' value is defined, then automatically, the /2
 381  * one should be included as it can be used.    Generally having more that
 382  * one fast set does not make sense, as static timings need to be changed
 383  * to change the set.    The exception is the bypass setting which is
 384  * availble for low power bypass.
 385  *
 386  * Note: This table needs to be sorted, fastest to slowest.
 387  *-------------------------------------------------------------------------*/
 388 static struct prcm_config rate_table[] = {
 389         /* PRCM I - FAST */
 390         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 391                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 392                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 393                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 394                 RATE_IN_242X},
 395
 396         /* PRCM II - FAST */
 397         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 398                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 399                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 400                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 401                 RATE_IN_242X},
 402
 403         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 404                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 405                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 406                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 407                 RATE_IN_242X},
 408
 409         /* PRCM III - FAST */
 410         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 411                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 412                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 413                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 414                 RATE_IN_242X},
 415
 416         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 417                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 418                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 419                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 420                 RATE_IN_242X},
 421
 422         /* PRCM II - SLOW */
 423         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 424                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 425                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 426                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 427                 RATE_IN_242X},
 428
 429         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 430                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 431                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 432                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 433                 RATE_IN_242X},
 434
 435         /* PRCM III - SLOW */
 436         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 437                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 438                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 439                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 440                 RATE_IN_242X},
 441
 442         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 443                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 444                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 445                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 446                 RATE_IN_242X},
 447
 448         /* PRCM-VII (boot-bypass) */
 449         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 450                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 451                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 452                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 453                 RATE_IN_242X},
 454
 455         /* PRCM-VII (boot-bypass) */
 456         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 457                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 458                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 459                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 460                 RATE_IN_242X},
 461
 462         /* PRCM #3 - ratio2 (ES2) - FAST */
 463         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 464                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 465                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 466                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 467                 SDRC_RFR_CTRL_110MHz,
 468                 RATE_IN_243X},
 469
 470         /* PRCM #5a - ratio1 - FAST */
 471         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 472                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 473                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 474                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 475                 SDRC_RFR_CTRL_133MHz,
 476                 RATE_IN_243X},
 477
 478         /* PRCM #5b - ratio1 - FAST */
 479         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 480                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 481                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 482                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 483                 SDRC_RFR_CTRL_100MHz,
 484                 RATE_IN_243X},
 485
 486         /* PRCM #3 - ratio2 (ES2) - SLOW */
 487         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 488                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 489                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 491                 SDRC_RFR_CTRL_110MHz,
 492                 RATE_IN_243X},
 493
 494         /* PRCM #5a - ratio1 - SLOW */
 495         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 496                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 497                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 498                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 499                 SDRC_RFR_CTRL_133MHz,
 500                 RATE_IN_243X},
 501
 502         /* PRCM #5b - ratio1 - SLOW*/
 503         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 504                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 505                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 506                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 507                 SDRC_RFR_CTRL_100MHz,
 508                 RATE_IN_243X},
 509
 510         /* PRCM-boot/bypass */
 511         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 512                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 513                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 514                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 515                 SDRC_RFR_CTRL_BYPASS,
 516                 RATE_IN_243X},
 517
 518         /* PRCM-boot/bypass */
 519         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 520                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 521                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 522                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 523                 SDRC_RFR_CTRL_BYPASS,
 524                 RATE_IN_243X},
 525
 526         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 527 };
 528
 529 /*-------------------------------------------------------------------------
 530  * 24xx clock tree.
 531  *
 532  * NOTE:In many cases here we are assigning a 'default' parent. In many
 533  *      cases the parent is selectable. The get/set parent calls will also
 534  *      switch sources.
 535  *
 536  *      Many some clocks say always_enabled, but they can be auto idled for
 537  *      power savings. They will always be available upon clock request.
 538  *
 539  *      Several sources are given initial rates which may be wrong, this will
 540  *      be fixed up in the init func.
 541  *
 542  *      Things are broadly separated below by clock domains. It is
 543  *      noteworthy that most periferals have dependencies on multiple clock
 544  *      domains. Many get their interface clocks from the L4 domain, but get
 545  *      functional clocks from fixed sources or other core domain derived
 546  *      clocks.
 547  *-------------------------------------------------------------------------*/
 548
 549 /* Base external input clocks */
 550 static struct clk func_32k_ck = {
 551         .name           = "func_32k_ck",
 552         .rate           = 32000,
 553         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 554                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 555         .recalc         = &propagate_rate,
 556 };
 557
 558 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 559 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 560         .name           = "osc_ck",
 561         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 562                                 RATE_PROPAGATES,
 563         .enable         = &omap2_enable_osc_ck,
 564         .disable        = &omap2_disable_osc_ck,
 565         .recalc         = &omap2_osc_clk_recalc,
 566 };
 567
 568 /* With out modem likely 12MHz, with modem likely 13MHz */
 569 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 570         .name           = "sys_ck",             /* ~ ref_clk also */
 571         .parent         = &osc_ck,
 572         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 573                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 574         .recalc         = &omap2_sys_clk_recalc,
 575 };
 576
 577 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 578         .name           = "alt_ck",
 579         .rate           = 54000000,
 580         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 581                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 582         .recalc         = &propagate_rate,
 583 };
 584
 585 /*
 586  * Analog domain root source clocks
 587  */
 588
 589 /* dpll_ck, is broken out in to special cases through clksel */
 590 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 591  * deal with this
 592  */
 593
 594 static const struct dpll_data dpll_dd = {
 595         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 596         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 597         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 598         .auto_idle_mask         = OMAP24XX_AUTO_DPLL_MASK,
 599         .auto_idle_val          = 0x3, /* stop DPLL upon idle */
 600 };
 601
 602 static struct clk dpll_ck = {
 603         .name           = "dpll_ck",
 604         .parent         = &sys_ck,              /* Can be func_32k also */
 605         .dpll_data      = &dpll_dd,
 606         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 607                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 608         .recalc         = &omap2_dpll_recalc,
 609         .set_rate       = &omap2_reprogram_dpll,
 610 };
 611
 612 static struct clk apll96_ck = {
 613         .name           = "apll96_ck",
 614         .parent         = &sys_ck,
 615         .rate           = 96000000,
 616         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 617                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 618         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 619         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 620         .enable         = &omap2_clk_fixed_enable,
 621         .disable        = &omap2_clk_fixed_disable,
 622         .recalc         = &propagate_rate,
 623 };
 624
 625 static struct clk apll54_ck = {
 626         .name           = "apll54_ck",
 627         .parent         = &sys_ck,
 628         .rate           = 54000000,
 629         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 630                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 631         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 632         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 633         .enable         = &omap2_clk_fixed_enable,
 634         .disable        = &omap2_clk_fixed_disable,
 635         .recalc         = &propagate_rate,
 636 };
 637
 638 /*
 639  * PRCM digital base sources
 640  */
 641
 642 /* func_54m_ck */
 643
 644 static const struct clksel_rate func_54m_apll54_rates[] = {
 645         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 646         { .div = 0 },
 647 };
 648
 649 static const struct clksel_rate func_54m_alt_rates[] = {
 650         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 651         { .div = 0 },
 652 };
 653
 654 static const struct clksel func_54m_clksel[] = {
 655         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 656         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 657         { .parent = NULL },
 658 };
 659
 660 static struct clk func_54m_ck = {
 661         .name           = "func_54m_ck",
 662         .parent         = &apll54_ck,   /* can also be alt_clk */
 663         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 664                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 665         .init           = &omap2_init_clksel_parent,
 666         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 667         .clksel_mask    = OMAP24XX_54M_SOURCE,
 668         .clksel         = func_54m_clksel,
 669         .recalc         = &omap2_clksel_recalc,
 670 };
 671
 672 static struct clk core_ck = {
 673         .name           = "core_ck",
 674         .parent         = &dpll_ck,             /* can also be 32k */
 675         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 676                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 677         .recalc         = &followparent_recalc,
 678 };
 679
 680 /* func_96m_ck */
 681 static const struct clksel_rate func_96m_apll96_rates[] = {
 682         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 683         { .div = 0 },
 684 };
 685
 686 static const struct clksel_rate func_96m_alt_rates[] = {
 687         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 688         { .div = 0 },
 689 };
 690
 691 static const struct clksel func_96m_clksel[] = {
 692         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 693         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 694         { .parent = NULL }
 695 };
 696
 697 /* The parent of this clock is not selectable on 2420. */
 698 static struct clk func_96m_ck = {
 699         .name           = "func_96m_ck",
 700         .parent         = &apll96_ck,
 701         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 702                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 703         .init           = &omap2_init_clksel_parent,
 704         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 705         .clksel_mask    = OMAP2430_96M_SOURCE,
 706         .clksel         = func_96m_clksel,
 707         .recalc         = &omap2_clksel_recalc,
 708         .round_rate     = &omap2_clksel_round_rate,
 709         .set_rate       = &omap2_clksel_set_rate
 710 };
 711
 712 /* func_48m_ck */
 713
 714 static const struct clksel_rate func_48m_apll96_rates[] = {
 715         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 716         { .div = 0 },
 717 };
 718
 719 static const struct clksel_rate func_48m_alt_rates[] = {
 720         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 721         { .div = 0 },
 722 };
 723
 724 static const struct clksel func_48m_clksel[] = {
 725         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 726         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 727         { .parent = NULL }
 728 };
 729
 730 static struct clk func_48m_ck = {
 731         .name           = "func_48m_ck",
 732         .parent         = &apll96_ck,    /* 96M or Alt */
 733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 734                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 735         .init           = &omap2_init_clksel_parent,
 736         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 737         .clksel_mask    = OMAP24XX_48M_SOURCE,
 738         .clksel         = func_48m_clksel,
 739         .recalc         = &omap2_clksel_recalc,
 740         .round_rate     = &omap2_clksel_round_rate,
 741         .set_rate       = &omap2_clksel_set_rate
 742 };
 743
 744 static struct clk func_12m_ck = {
 745         .name           = "func_12m_ck",
 746         .parent         = &func_48m_ck,
 747         .fixed_div      = 4,
 748         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 749                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 750         .recalc         = &omap2_fixed_divisor_recalc,
 751 };
 752
 753 /* Secure timer, only available in secure mode */
 754 static struct clk wdt1_osc_ck = {
 755         .name           = "ck_wdt1_osc",
 756         .parent         = &osc_ck,
 757         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 758         .recalc         = &followparent_recalc,
 759 };
 760
 761 /*
 762  * The common_clkout* clksel_rate structs are common to
 763  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 764  * sys_clkout2_* are 2420-only, so the
 765  * clksel_rate flags fields are inaccurate for those clocks. This is
 766  * harmless since access to those clocks are gated by the struct clk
 767  * flags fields, which mark them as 2420-only.
 768  */
 769 static const struct clksel_rate common_clkout_src_core_rates[] = {
 770         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 771         { .div = 0 }
 772 };
 773
 774 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 775         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 776         { .div = 0 }
 777 };
 778
 779 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 780         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 781         { .div = 0 }
 782 };
 783
 784 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 785         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 786         { .div = 0 }
 787 };
 788
 789 static const struct clksel common_clkout_src_clksel[] = {
 790         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 791         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 792         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 793         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 794         { .parent = NULL }
 795 };
 796
 797 static struct clk sys_clkout_src = {
 798         .name           = "sys_clkout_src",
 799         .parent         = &func_54m_ck,
 800         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 801                                 RATE_PROPAGATES,
 802         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 803         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 804         .init           = &omap2_init_clksel_parent,
 805         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 806         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 807         .clksel         = common_clkout_src_clksel,
 808         .recalc         = &omap2_clksel_recalc,
 809         .round_rate     = &omap2_clksel_round_rate,
 810         .set_rate       = &omap2_clksel_set_rate
 811 };
 812
 813 static const struct clksel_rate common_clkout_rates[] = {
 814         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 815         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 816         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 817         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 818         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 819         { .div = 0 },
 820 };
 821
 822 static const struct clksel sys_clkout_clksel[] = {
 823         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 824         { .parent = NULL }
 825 };
 826
 827 static struct clk sys_clkout = {
 828         .name           = "sys_clkout",
 829         .parent         = &sys_clkout_src,
 830         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 831                                 PARENT_CONTROLS_CLOCK,
 832         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 833         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 834         .clksel         = sys_clkout_clksel,
 835         .recalc         = &omap2_clksel_recalc,
 836         .round_rate     = &omap2_clksel_round_rate,
 837         .set_rate       = &omap2_clksel_set_rate
 838 };
 839
 840 /* In 2430, new in 2420 ES2 */
 841 static struct clk sys_clkout2_src = {
 842         .name           = "sys_clkout2_src",
 843         .parent         = &func_54m_ck,
 844         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 845         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 846         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 847         .init           = &omap2_init_clksel_parent,
 848         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 849         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 850         .clksel         = common_clkout_src_clksel,
 851         .recalc         = &omap2_clksel_recalc,
 852         .round_rate     = &omap2_clksel_round_rate,
 853         .set_rate       = &omap2_clksel_set_rate
 854 };
 855
 856 static const struct clksel sys_clkout2_clksel[] = {
 857         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 858         { .parent = NULL }
 859 };
 860
 861 /* In 2430, new in 2420 ES2 */
 862 static struct clk sys_clkout2 = {
 863         .name           = "sys_clkout2",
 864         .parent         = &sys_clkout2_src,
 865         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 866         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 867         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 868         .clksel         = sys_clkout2_clksel,
 869         .recalc         = &omap2_clksel_recalc,
 870         .round_rate     = &omap2_clksel_round_rate,
 871         .set_rate       = &omap2_clksel_set_rate
 872 };
 873
 874 static struct clk emul_ck = {
 875         .name           = "emul_ck",
 876         .parent         = &func_54m_ck,
 877         .flags          = CLOCK_IN_OMAP242X,
 878         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 879         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 880         .recalc         = &followparent_recalc,
 881
 882 };
 883
 884 /*
 885  * MPU clock domain
 886  *      Clocks:
 887  *              MPU_FCLK, MPU_ICLK
 888  *              INT_M_FCLK, INT_M_I_CLK
 889  *
 890  * - Individual clocks are hardware managed.
 891  * - Base divider comes from: CM_CLKSEL_MPU
 892  *
 893  */
 894 static const struct clksel_rate mpu_core_rates[] = {
 895         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 896         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 897         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 898         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 899         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 900         { .div = 0 },
 901 };
 902
 903 static const struct clksel mpu_clksel[] = {
 904         { .parent = &core_ck, .rates = mpu_core_rates },
 905         { .parent = NULL }
 906 };
 907
 908 static struct clk mpu_ck = {    /* Control cpu */
 909         .name           = "mpu_ck",
 910         .parent         = &core_ck,
 911         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 912                                 ALWAYS_ENABLED | DELAYED_APP |
 913                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 914         .init           = &omap2_init_clksel_parent,
 915         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 916         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 917         .clksel         = mpu_clksel,
 918         .recalc         = &omap2_clksel_recalc,
 919         .round_rate     = &omap2_clksel_round_rate,
 920         .set_rate       = &omap2_clksel_set_rate
 921 };
 922
 923 /*
 924  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 925  * Clocks:
 926  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 927  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 928  */
 929 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 930  * they should just be treated as such.
 931  */
 932
 933 /* iva2_1_fck */
 934 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 935         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 936         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 937         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 938         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 939         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 940         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 941         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 942         { .div = 0 },
 943 };
 944
 945 static const struct clksel iva2_1_fck_clksel[] = {
 946         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 947         { .parent = NULL }
 948 };
 949
 950 static struct clk iva2_1_fck = {
 951         .name           = "iva2_1_fck",
 952         .parent         = &core_ck,
 953         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
 954                                 CONFIG_PARTICIPANT,
 955         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 956         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 957         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 958         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 959         .clksel         = iva2_1_fck_clksel,
 960         .recalc         = &omap2_clksel_recalc,
 961         .round_rate     = &omap2_clksel_round_rate,
 962         .set_rate       = &omap2_clksel_set_rate
 963 };
 964
 965 /* iva2_1_ick */
 966 static const struct clksel_rate iva2_1_ick_core_rates[] = {
 967         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 968         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 969         { .div = 3, .val = 3, .flags = RATE_IN_243X },
 970         { .div = 0 },
 971 };
 972
 973 static const struct clksel iva2_1_ick_clksel[] = {
 974         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
 975         { .parent = NULL }
 976 };
 977
 978 static struct clk iva2_1_ick = {
 979         .name           = "iva2_1_ick",
 980         .parent         = &iva2_1_fck,
 981         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
 982         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 983         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
 984         .clksel         = iva2_1_ick_clksel,
 985         .recalc         = &omap2_clksel_recalc,
 986         .round_rate     = &omap2_clksel_round_rate,
 987         .set_rate       = &omap2_clksel_set_rate
 988 };
 989
 990 /*
 991  * Won't be too specific here. The core clock comes into this block
 992  * it is divided then tee'ed. One branch goes directly to xyz enable
 993  * controls. The other branch gets further divided by 2 then possibly
 994  * routed into a synchronizer and out of clocks abc.
 995  */
 996 static const struct clksel_rate dsp_fck_core_rates[] = {
 997         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 998         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 999         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1000         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1001         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1002         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1003         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1004         { .div = 0 },
1005 };
1006
1007 static const struct clksel dsp_fck_clksel[] = {
1008         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1009         { .parent = NULL }
1010 };
1011
1012 static struct clk dsp_fck = {
1013         .name           = "dsp_fck",
1014         .parent         = &core_ck,
1015         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP |
1016                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1017         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1018         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1019         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1020         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1021         .clksel         = dsp_fck_clksel,
1022         .recalc         = &omap2_clksel_recalc,
1023         .round_rate     = &omap2_clksel_round_rate,
1024         .set_rate       = &omap2_clksel_set_rate
1025 };
1026
1027 static const struct clksel_rate dsp_ick_core_rates[] = {
1028         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1029         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1030         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1031         { .div = 0 },
1032 };
1033
1034 static const struct clksel dsp_ick_clksel[] = {
1035         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1036         { .parent = NULL }
1037 };
1038
1039 static struct clk dsp_ick = {
1040         .name           = "dsp_ick",     /* apparently ipi and isp */
1041         .parent         = &core_ck,
1042         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1043         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1044         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1045         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1046         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1047         .clksel         = dsp_ick_clksel,
1048         .recalc         = &omap2_clksel_recalc,
1049 };
1050
1051 static const struct clksel_rate iva1_ifck_core_rates[] = {
1052         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1053         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1054         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1055         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1056         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1057         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1058         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1059         { .div = 0 },
1060 };
1061
1062 static const struct clksel iva1_ifck_clksel[] = {
1063         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1064         { .parent = NULL }
1065 };
1066
1067 static struct clk iva1_ifck = {
1068         .name           = "iva1_ifck",
1069         .parent         = &core_ck,
1070         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1071                                 RATE_PROPAGATES | DELAYED_APP,
1072         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1073         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1074         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1075         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1076         .clksel         = iva1_ifck_clksel,
1077         .recalc         = &omap2_clksel_recalc,
1078         .round_rate     = &omap2_clksel_round_rate,
1079         .set_rate       = &omap2_clksel_set_rate
1080 };
1081
1082 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1083 static struct clk iva1_mpu_int_ifck = {
1084         .name           = "iva1_mpu_int_ifck",
1085         .parent         = &iva1_ifck,
1086         .flags          = CLOCK_IN_OMAP242X,
1087         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1088         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1089         .fixed_div      = 2,
1090         .recalc         = &omap2_fixed_divisor_recalc,
1091 };
1092
1093 /*
1094  * L3 clock domain
1095  * L3 clocks are used for both interface and functional clocks to
1096  * multiple entities. Some of these clocks are completely managed
1097  * by hardware, and some others allow software control. Hardware
1098  * managed ones general are based on directly CLK_REQ signals and
1099  * various auto idle settings. The functional spec sets many of these
1100  * as 'tie-high' for their enables.
1101  *
1102  * I-CLOCKS:
1103  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1104  *      CAM, HS-USB.
1105  * F-CLOCK
1106  *      SSI.
1107  *
1108  * GPMC memories and SDRC have timing and clock sensitive registers which
1109  * may very well need notification when the clock changes. Currently for low
1110  * operating points, these are taken care of in sleep.S.
1111  */
1112 static const struct clksel_rate core_l3_core_rates[] = {
1113         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1114         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1115         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1116         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1117         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1118         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1119         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1120         { .div = 0 }
1121 };
1122
1123 static const struct clksel core_l3_clksel[] = {
1124         { .parent = &core_ck, .rates = core_l3_core_rates },
1125         { .parent = NULL }
1126 };
1127
1128 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1129         .name           = "core_l3_ck",
1130         .parent         = &core_ck,
1131         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1132                                 ALWAYS_ENABLED | DELAYED_APP |
1133                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1134         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1135         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1136         .clksel         = core_l3_clksel,
1137         .recalc         = &omap2_clksel_recalc,
1138         .round_rate     = &omap2_clksel_round_rate,
1139         .set_rate       = &omap2_clksel_set_rate
1140 };
1141
1142 /* usb_l4_ick */
1143 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1144         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1145         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1146         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1147         { .div = 0 }
1148 };
1149
1150 static const struct clksel usb_l4_ick_clksel[] = {
1151         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1152         { .parent = NULL },
1153 };
1154
1155 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1156         .name           = "usb_l4_ick",
1157         .parent         = &core_l3_ck,
1158         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1159                                 DELAYED_APP | CONFIG_PARTICIPANT,
1160         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1161         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1162         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1163         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1164         .clksel         = usb_l4_ick_clksel,
1165         .recalc         = &omap2_clksel_recalc,
1166         .round_rate     = &omap2_clksel_round_rate,
1167         .set_rate       = &omap2_clksel_set_rate
1168 };
1169
1170 /*
1171  * SSI is in L3 management domain, its direct parent is core not l3,
1172  * many core power domain entities are grouped into the L3 clock
1173  * domain.
1174  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1175  *
1176  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1177  */
1178 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1179         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1180         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1181         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1182         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1183         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1184         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1185         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1186         { .div = 0 }
1187 };
1188
1189 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1190         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1191         { .parent = NULL }
1192 };
1193
1194 static struct clk ssi_ssr_sst_fck = {
1195         .name           = "ssi_fck",
1196         .parent         = &core_ck,
1197         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1198                                 DELAYED_APP,
1199         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1200         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1201         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1202         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1203         .clksel         = ssi_ssr_sst_fck_clksel,
1204         .recalc         = &omap2_clksel_recalc,
1205         .round_rate     = &omap2_clksel_round_rate,
1206         .set_rate       = &omap2_clksel_set_rate
1207 };
1208
1209 /*
1210  * GFX clock domain
1211  *      Clocks:
1212  * GFX_FCLK, GFX_ICLK
1213  * GFX_CG1(2d), GFX_CG2(3d)
1214  *
1215  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1216  * The 2d and 3d clocks run at a hardware determined
1217  * divided value of fclk.
1218  *
1219  */
1220 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1221
1222 /*
1223  * These clksel_rate/clksel structs are shared between gfx_3d_fck and
1224  * gfx_2d_fck
1225  */
1226 static const struct clksel_rate gfx_fck_core_l3_rates[] = {
1227         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1228         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1229         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1230         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1231         { .div = 0 }
1232 };
1233
1234 static const struct clksel gfx_fck_clksel[] = {
1235         { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
1236         { .parent = NULL },
1237 };
1238
1239 static struct clk gfx_3d_fck = {
1240         .name           = "gfx_3d_fck",
1241         .parent         = &core_l3_ck,
1242         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1243         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1244         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1245         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1246         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1247         .clksel         = gfx_fck_clksel,
1248         .recalc         = &omap2_clksel_recalc,
1249         .round_rate     = &omap2_clksel_round_rate,
1250         .set_rate       = &omap2_clksel_set_rate
1251 };
1252
1253 static struct clk gfx_2d_fck = {
1254         .name           = "gfx_2d_fck",
1255         .parent         = &core_l3_ck,
1256         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1257         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1258         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1259         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1260         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1261         .clksel         = gfx_fck_clksel,
1262         .recalc         = &omap2_clksel_recalc,
1263         .round_rate     = &omap2_clksel_round_rate,
1264         .set_rate       = &omap2_clksel_set_rate
1265 };
1266
1267 static struct clk gfx_ick = {
1268         .name           = "gfx_ick",            /* From l3 */
1269         .parent         = &core_l3_ck,
1270         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1271         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1272         .enable_bit     = OMAP_EN_GFX_SHIFT,
1273         .recalc         = &followparent_recalc,
1274 };
1275
1276 /*
1277  * Modem clock domain (2430)
1278  *      CLOCKS:
1279  *              MDM_OSC_CLK
1280  *              MDM_ICLK
1281  * These clocks are usable in chassis mode only.
1282  */
1283 static const struct clksel_rate mdm_ick_core_rates[] = {
1284         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1285         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1286         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1287         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1288         { .div = 0 }
1289 };
1290
1291 static const struct clksel mdm_ick_clksel[] = {
1292         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1293         { .parent = NULL }
1294 };
1295
1296 static struct clk mdm_ick = {           /* used both as a ick and fck */
1297         .name           = "mdm_ick",
1298         .parent         = &core_ck,
1299         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1300         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1301         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1302         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1303         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1304         .clksel         = mdm_ick_clksel,
1305         .recalc         = &omap2_clksel_recalc,
1306         .round_rate     = &omap2_clksel_round_rate,
1307         .set_rate       = &omap2_clksel_set_rate
1308 };
1309
1310 static struct clk mdm_osc_ck = {
1311         .name           = "mdm_osc_ck",
1312         .parent         = &osc_ck,
1313         .flags          = CLOCK_IN_OMAP243X,
1314         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
1315         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 /*
1320  * L4 clock management domain
1321  *
1322  * This domain contains lots of interface clocks from the L4 interface, some
1323  * functional clocks.   Fixed APLL functional source clocks are managed in
1324  * this domain.
1325  */
1326 static const struct clksel_rate l4_core_l3_rates[] = {
1327         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1328         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1329         { .div = 0 }
1330 };
1331
1332 static const struct clksel l4_clksel[] = {
1333         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1334         { .parent = NULL }
1335 };
1336
1337 static struct clk l4_ck = {             /* used both as an ick and fck */
1338         .name           = "l4_ck",
1339         .parent         = &core_l3_ck,
1340         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1341                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1342         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1343         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1344         .clksel         = l4_clksel,
1345         .recalc         = &omap2_clksel_recalc,
1346         .round_rate     = &omap2_clksel_round_rate,
1347         .set_rate       = &omap2_clksel_set_rate
1348 };
1349
1350 static struct clk ssi_l4_ick = {
1351         .name           = "ssi_l4_ick",
1352         .parent         = &l4_ck,
1353         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1354         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1355         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1356         .recalc         = &followparent_recalc,
1357 };
1358
1359 /*
1360  * DSS clock domain
1361  * CLOCKs:
1362  * DSS_L4_ICLK, DSS_L3_ICLK,
1363  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1364  *
1365  * DSS is both initiator and target.
1366  */
1367 /* XXX Add RATE_NOT_VALIDATED */
1368
1369 static const struct clksel_rate dss1_fck_sys_rates[] = {
1370         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1371         { .div = 0 }
1372 };
1373
1374 static const struct clksel_rate dss1_fck_core_rates[] = {
1375         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1376         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1377         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1378         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1379         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1380         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1381         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1382         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1383         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1384         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1385         { .div = 0 }
1386 };
1387
1388 static const struct clksel dss1_fck_clksel[] = {
1389         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1390         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1391         { .parent = NULL },
1392 };
1393
1394 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1395         .name           = "dss_ick",
1396         .parent         = &l4_ck,       /* really both l3 and l4 */
1397         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1398         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1399         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1400         .recalc         = &followparent_recalc,
1401 };
1402
1403 static struct clk dss1_fck = {
1404         .name           = "dss1_fck",
1405         .parent         = &core_ck,             /* Core or sys */
1406         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1407                                 DELAYED_APP,
1408         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1409         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1410         .init           = &omap2_init_clksel_parent,
1411         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1412         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1413         .clksel         = dss1_fck_clksel,
1414         .recalc         = &omap2_clksel_recalc,
1415         .round_rate     = &omap2_clksel_round_rate,
1416         .set_rate       = &omap2_clksel_set_rate
1417 };
1418
1419 static const struct clksel_rate dss2_fck_sys_rates[] = {
1420         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1421         { .div = 0 }
1422 };
1423
1424 static const struct clksel_rate dss2_fck_48m_rates[] = {
1425         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1426         { .div = 0 }
1427 };
1428
1429 static const struct clksel dss2_fck_clksel[] = {
1430         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1431         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1432         { .parent = NULL }
1433 };
1434
1435 static struct clk dss2_fck = {          /* Alt clk used in power management */
1436         .name           = "dss2_fck",
1437         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1438         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1439                                 DELAYED_APP,
1440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1442         .init           = &omap2_init_clksel_parent,
1443         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1444         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1445         .clksel         = dss2_fck_clksel,
1446         .recalc         = &followparent_recalc,
1447 };
1448
1449 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1450         .name           = "dss_54m_fck",        /* 54m tv clk */
1451         .parent         = &func_54m_ck,
1452         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1453         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1455         .recalc         = &followparent_recalc,
1456 };
1457
1458 /*
1459  * CORE power domain ICLK & FCLK defines.
1460  * Many of the these can have more than one possible parent. Entries
1461  * here will likely have an L4 interface parent, and may have multiple
1462  * functional clock parents.
1463  */
1464 static const struct clksel_rate gpt_32k_rates[] = {
1465         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1466         { .div = 0 }
1467 };
1468
1469 static const struct clksel_rate gpt_sys_rates[] = {
1470         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1471         { .div = 0 }
1472 };
1473
1474 static const struct clksel_rate gpt_alt_rates[] = {
1475         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1476         { .div = 0 }
1477 };
1478
1479 static const struct clksel gpt_clksel[] = {
1480         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1481         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1482         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1483         { .parent = NULL },
1484 };
1485
1486 static struct clk gpt1_ick = {
1487         .name           = "gpt1_ick",
1488         .parent         = &l4_ck,
1489         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1490         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1491         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1492         .recalc         = &followparent_recalc,
1493 };
1494
1495 static struct clk gpt1_fck = {
1496         .name           = "gpt1_fck",
1497         .parent         = &func_32k_ck,
1498         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1499         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1500         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1501         .init           = &omap2_init_clksel_parent,
1502         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1503         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1504         .clksel         = gpt_clksel,
1505         .recalc         = &omap2_clksel_recalc,
1506         .round_rate     = &omap2_clksel_round_rate,
1507         .set_rate       = &omap2_clksel_set_rate
1508 };
1509
1510 static struct clk gpt2_ick = {
1511         .name           = "gpt2_ick",
1512         .parent         = &l4_ck,
1513         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1514         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1515         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1516         .recalc         = &followparent_recalc,
1517 };
1518
1519 static struct clk gpt2_fck = {
1520         .name           = "gpt2_fck",
1521         .parent         = &func_32k_ck,
1522         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1525         .init           = &omap2_init_clksel_parent,
1526         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1527         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1528         .clksel         = gpt_clksel,
1529         .recalc         = &omap2_clksel_recalc,
1530 };
1531
1532 static struct clk gpt3_ick = {
1533         .name           = "gpt3_ick",
1534         .parent         = &l4_ck,
1535         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1537         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk gpt3_fck = {
1542         .name           = "gpt3_fck",
1543         .parent         = &func_32k_ck,
1544         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1545         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1546         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1547         .init           = &omap2_init_clksel_parent,
1548         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1549         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1550         .clksel         = gpt_clksel,
1551         .recalc         = &omap2_clksel_recalc,
1552 };
1553
1554 static struct clk gpt4_ick = {
1555         .name           = "gpt4_ick",
1556         .parent         = &l4_ck,
1557         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1558         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1559         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 static struct clk gpt4_fck = {
1564         .name           = "gpt4_fck",
1565         .parent         = &func_32k_ck,
1566         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1567         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1568         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1569         .init           = &omap2_init_clksel_parent,
1570         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1571         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1572         .clksel         = gpt_clksel,
1573         .recalc         = &omap2_clksel_recalc,
1574 };
1575
1576 static struct clk gpt5_ick = {
1577         .name           = "gpt5_ick",
1578         .parent         = &l4_ck,
1579         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1581         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk gpt5_fck = {
1586         .name           = "gpt5_fck",
1587         .parent         = &func_32k_ck,
1588         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1589         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1591         .init           = &omap2_init_clksel_parent,
1592         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1593         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1594         .clksel         = gpt_clksel,
1595         .recalc         = &omap2_clksel_recalc,
1596 };
1597
1598 static struct clk gpt6_ick = {
1599         .name           = "gpt6_ick",
1600         .parent         = &l4_ck,
1601         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1602         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1604         .recalc         = &followparent_recalc,
1605 };
1606
1607 static struct clk gpt6_fck = {
1608         .name           = "gpt6_fck",
1609         .parent         = &func_32k_ck,
1610         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1611         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1612         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1613         .init           = &omap2_init_clksel_parent,
1614         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1615         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1616         .clksel         = gpt_clksel,
1617         .recalc         = &omap2_clksel_recalc,
1618 };
1619
1620 static struct clk gpt7_ick = {
1621         .name           = "gpt7_ick",
1622         .parent         = &l4_ck,
1623         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1624         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1625         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1626         .recalc         = &followparent_recalc,
1627 };
1628
1629 static struct clk gpt7_fck = {
1630         .name           = "gpt7_fck",
1631         .parent         = &func_32k_ck,
1632         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1633         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1634         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1635         .init           = &omap2_init_clksel_parent,
1636         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1637         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1638         .clksel         = gpt_clksel,
1639         .recalc         = &omap2_clksel_recalc,
1640 };
1641
1642 static struct clk gpt8_ick = {
1643         .name           = "gpt8_ick",
1644         .parent         = &l4_ck,
1645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1647         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1648         .recalc         = &followparent_recalc,
1649 };
1650
1651 static struct clk gpt8_fck = {
1652         .name           = "gpt8_fck",
1653         .parent         = &func_32k_ck,
1654         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1656         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1657         .init           = &omap2_init_clksel_parent,
1658         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1659         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1660         .clksel         = gpt_clksel,
1661         .recalc         = &omap2_clksel_recalc,
1662 };
1663
1664 static struct clk gpt9_ick = {
1665         .name           = "gpt9_ick",
1666         .parent         = &l4_ck,
1667         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1668         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1669         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1670         .recalc         = &followparent_recalc,
1671 };
1672
1673 static struct clk gpt9_fck = {
1674         .name           = "gpt9_fck",
1675         .parent         = &func_32k_ck,
1676         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1677         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1678         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1679         .init           = &omap2_init_clksel_parent,
1680         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1681         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1682         .clksel         = gpt_clksel,
1683         .recalc         = &omap2_clksel_recalc,
1684 };
1685
1686 static struct clk gpt10_ick = {
1687         .name           = "gpt10_ick",
1688         .parent         = &l4_ck,
1689         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1690         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1691         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1692         .recalc         = &followparent_recalc,
1693 };
1694
1695 static struct clk gpt10_fck = {
1696         .name           = "gpt10_fck",
1697         .parent         = &func_32k_ck,
1698         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1699         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1700         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1701         .init           = &omap2_init_clksel_parent,
1702         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1703         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1704         .clksel         = gpt_clksel,
1705         .recalc         = &omap2_clksel_recalc,
1706 };
1707
1708 static struct clk gpt11_ick = {
1709         .name           = "gpt11_ick",
1710         .parent         = &l4_ck,
1711         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1712         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1713         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1714         .recalc         = &followparent_recalc,
1715 };
1716
1717 static struct clk gpt11_fck = {
1718         .name           = "gpt11_fck",
1719         .parent         = &func_32k_ck,
1720         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1721         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1722         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1723         .init           = &omap2_init_clksel_parent,
1724         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1725         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1726         .clksel         = gpt_clksel,
1727         .recalc         = &omap2_clksel_recalc,
1728 };
1729
1730 static struct clk gpt12_ick = {
1731         .name           = "gpt12_ick",
1732         .parent         = &l4_ck,
1733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1735         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1736         .recalc         = &followparent_recalc,
1737 };
1738
1739 static struct clk gpt12_fck = {
1740         .name           = "gpt12_fck",
1741         .parent         = &func_32k_ck,
1742         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1743         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1744         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1745         .init           = &omap2_init_clksel_parent,
1746         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1747         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1748         .clksel         = gpt_clksel,
1749         .recalc         = &omap2_clksel_recalc,
1750 };
1751
1752 static struct clk mcbsp1_ick = {
1753         .name           = "mcbsp1_ick",
1754         .parent         = &l4_ck,
1755         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1757         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1758         .recalc         = &followparent_recalc,
1759 };
1760
1761 static struct clk mcbsp1_fck = {
1762         .name           = "mcbsp1_fck",
1763         .parent         = &func_96m_ck,
1764         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1765         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1766         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1767         .recalc         = &followparent_recalc,
1768 };
1769
1770 static struct clk mcbsp2_ick = {
1771         .name           = "mcbsp2_ick",
1772         .parent         = &l4_ck,
1773         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1775         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1776         .recalc         = &followparent_recalc,
1777 };
1778
1779 static struct clk mcbsp2_fck = {
1780         .name           = "mcbsp2_fck",
1781         .parent         = &func_96m_ck,
1782         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1783         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1784         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk mcbsp3_ick = {
1789         .name           = "mcbsp3_ick",
1790         .parent         = &l4_ck,
1791         .flags          = CLOCK_IN_OMAP243X,
1792         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1793         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1794         .recalc         = &followparent_recalc,
1795 };
1796
1797 static struct clk mcbsp3_fck = {
1798         .name           = "mcbsp3_fck",
1799         .parent         = &func_96m_ck,
1800         .flags          = CLOCK_IN_OMAP243X,
1801         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1802         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mcbsp4_ick = {
1807         .name           = "mcbsp4_ick",
1808         .parent         = &l4_ck,
1809         .flags          = CLOCK_IN_OMAP243X,
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1811         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mcbsp4_fck = {
1816         .name           = "mcbsp4_fck",
1817         .parent         = &func_96m_ck,
1818         .flags          = CLOCK_IN_OMAP243X,
1819         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1820         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk mcbsp5_ick = {
1825         .name           = "mcbsp5_ick",
1826         .parent         = &l4_ck,
1827         .flags          = CLOCK_IN_OMAP243X,
1828         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1829         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1830         .recalc         = &followparent_recalc,
1831 };
1832
1833 static struct clk mcbsp5_fck = {
1834         .name           = "mcbsp5_fck",
1835         .parent         = &func_96m_ck,
1836         .flags          = CLOCK_IN_OMAP243X,
1837         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1838         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1839         .recalc         = &followparent_recalc,
1840 };
1841
1842 static struct clk mcspi1_ick = {
1843         .name           = "mcspi_ick",
1844         .id             = 1,
1845         .parent         = &l4_ck,
1846         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1847         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1849         .recalc         = &followparent_recalc,
1850 };
1851
1852 static struct clk mcspi1_fck = {
1853         .name           = "mcspi_fck",
1854         .id             = 1,
1855         .parent         = &func_48m_ck,
1856         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1857         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1858         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1859         .recalc         = &followparent_recalc,
1860 };
1861
1862 static struct clk mcspi2_ick = {
1863         .name           = "mcspi_ick",
1864         .id             = 2,
1865         .parent         = &l4_ck,
1866         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1867         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1868         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk mcspi2_fck = {
1873         .name           = "mcspi_fck",
1874         .id             = 2,
1875         .parent         = &func_48m_ck,
1876         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1877         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1878         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk mcspi3_ick = {
1883         .name           = "mcspi_ick",
1884         .id             = 3,
1885         .parent         = &l4_ck,
1886         .flags          = CLOCK_IN_OMAP243X,
1887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1888         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk mcspi3_fck = {
1893         .name           = "mcspi_fck",
1894         .id             = 3,
1895         .parent         = &func_48m_ck,
1896         .flags          = CLOCK_IN_OMAP243X,
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1898         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk uart1_ick = {
1903         .name           = "uart1_ick",
1904         .parent         = &l4_ck,
1905         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1908         .recalc         = &followparent_recalc,
1909 };
1910
1911 static struct clk uart1_fck = {
1912         .name           = "uart1_fck",
1913         .parent         = &func_48m_ck,
1914         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1916         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk uart2_ick = {
1921         .name           = "uart2_ick",
1922         .parent         = &l4_ck,
1923         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1924         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk uart2_fck = {
1930         .name           = "uart2_fck",
1931         .parent         = &func_48m_ck,
1932         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1933         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1934         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk uart3_ick = {
1939         .name           = "uart3_ick",
1940         .parent         = &l4_ck,
1941         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1942         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1943         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1944         .recalc         = &followparent_recalc,
1945 };
1946
1947 static struct clk uart3_fck = {
1948         .name           = "uart3_fck",
1949         .parent         = &func_48m_ck,
1950         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1951         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1952         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk gpios_ick = {
1957         .name           = "gpios_ick",
1958         .parent         = &l4_ck,
1959         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1960         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1961         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk gpios_fck = {
1966         .name           = "gpios_fck",
1967         .parent         = &func_32k_ck,
1968         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1969         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1970         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1971         .recalc         = &followparent_recalc,
1972 };
1973
1974 static struct clk mpu_wdt_ick = {
1975         .name           = "mpu_wdt_ick",
1976         .parent         = &l4_ck,
1977         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1978         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1979         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1980         .recalc         = &followparent_recalc,
1981 };
1982
1983 static struct clk mpu_wdt_fck = {
1984         .name           = "mpu_wdt_fck",
1985         .parent         = &func_32k_ck,
1986         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1987         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1988         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1989         .recalc         = &followparent_recalc,
1990 };
1991
1992 static struct clk sync_32k_ick = {
1993         .name           = "sync_32k_ick",
1994         .parent         = &l4_ck,
1995         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1996         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1997         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1998         .recalc         = &followparent_recalc,
1999 };
2000 static struct clk wdt1_ick = {
2001         .name           = "wdt1_ick",
2002         .parent         = &l4_ck,
2003         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2004         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2005         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2006         .recalc         = &followparent_recalc,
2007 };
2008 static struct clk omapctrl_ick = {
2009         .name           = "omapctrl_ick",
2010         .parent         = &l4_ck,
2011         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2012         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2013         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2014         .recalc         = &followparent_recalc,
2015 };
2016 static struct clk icr_ick = {
2017         .name           = "icr_ick",
2018         .parent         = &l4_ck,
2019         .flags          = CLOCK_IN_OMAP243X,
2020         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2021         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2022         .recalc         = &followparent_recalc,
2023 };
2024
2025 static struct clk cam_ick = {
2026         .name           = "cam_ick",
2027         .parent         = &l4_ck,
2028         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2029         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2030         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2031         .recalc         = &followparent_recalc,
2032 };
2033
2034 static struct clk cam_fck = {
2035         .name           = "cam_fck",
2036         .parent         = &func_96m_ck,
2037         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2039         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2040         .recalc         = &followparent_recalc,
2041 };
2042
2043 static struct clk mailboxes_ick = {
2044         .name           = "mailboxes_ick",
2045         .parent         = &l4_ck,
2046         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2047         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2048         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2049         .recalc         = &followparent_recalc,
2050 };
2051
2052 static struct clk wdt4_ick = {
2053         .name           = "wdt4_ick",
2054         .parent         = &l4_ck,
2055         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2056         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2057         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2058         .recalc         = &followparent_recalc,
2059 };
2060
2061 static struct clk wdt4_fck = {
2062         .name           = "wdt4_fck",
2063         .parent         = &func_32k_ck,
2064         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2065         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2066         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2067         .recalc         = &followparent_recalc,
2068 };
2069
2070 static struct clk wdt3_ick = {
2071         .name           = "wdt3_ick",
2072         .parent         = &l4_ck,
2073         .flags          = CLOCK_IN_OMAP242X,
2074         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2075         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2076         .recalc         = &followparent_recalc,
2077 };
2078
2079 static struct clk wdt3_fck = {
2080         .name           = "wdt3_fck",
2081         .parent         = &func_32k_ck,
2082         .flags          = CLOCK_IN_OMAP242X,
2083         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2084         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2085         .recalc         = &followparent_recalc,
2086 };
2087
2088 static struct clk mspro_ick = {
2089         .name           = "mspro_ick",
2090         .parent         = &l4_ck,
2091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2092         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2093         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2094         .recalc         = &followparent_recalc,
2095 };
2096
2097 static struct clk mspro_fck = {
2098         .name           = "mspro_fck",
2099         .parent         = &func_96m_ck,
2100         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2101         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2102         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk mmc_ick = {
2107         .name           = "mmc_ick",
2108         .parent         = &l4_ck,
2109         .flags          = CLOCK_IN_OMAP242X,
2110         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2111         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2112         .recalc         = &followparent_recalc,
2113 };
2114
2115 static struct clk mmc_fck = {
2116         .name           = "mmc_fck",
2117         .parent         = &func_96m_ck,
2118         .flags          = CLOCK_IN_OMAP242X,
2119         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2120         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 static struct clk fac_ick = {
2125         .name           = "fac_ick",
2126         .parent         = &l4_ck,
2127         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2128         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2129         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2130         .recalc         = &followparent_recalc,
2131 };
2132
2133 static struct clk fac_fck = {
2134         .name           = "fac_fck",
2135         .parent         = &func_12m_ck,
2136         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2137         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2138         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2139         .recalc         = &followparent_recalc,
2140 };
2141
2142 static struct clk eac_ick = {
2143         .name           = "eac_ick",
2144         .parent         = &l4_ck,
2145         .flags          = CLOCK_IN_OMAP242X,
2146         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2147         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2148         .recalc         = &followparent_recalc,
2149 };
2150
2151 static struct clk eac_fck = {
2152         .name           = "eac_fck",
2153         .parent         = &func_96m_ck,
2154         .flags          = CLOCK_IN_OMAP242X,
2155         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2156         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2157         .recalc         = &followparent_recalc,
2158 };
2159
2160 static struct clk hdq_ick = {
2161         .name           = "hdq_ick",
2162         .parent         = &l4_ck,
2163         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2164         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2165         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2166         .recalc         = &followparent_recalc,
2167 };
2168
2169 static struct clk hdq_fck = {
2170         .name           = "hdq_fck",
2171         .parent         = &func_12m_ck,
2172         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2173         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2174         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2175         .recalc         = &followparent_recalc,
2176 };
2177
2178 static struct clk i2c2_ick = {
2179         .name           = "i2c_ick",
2180         .id             = 2,
2181         .parent         = &l4_ck,
2182         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2183         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2184         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2185         .recalc         = &followparent_recalc,
2186 };
2187
2188 static struct clk i2c2_fck = {
2189         .name           = "i2c_fck",
2190         .id             = 2,
2191         .parent         = &func_12m_ck,
2192         .flags          = CLOCK_IN_OMAP242X,
2193         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2194         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk i2chs2_fck = {
2199         .name           = "i2chs_fck",
2200         .id             = 2,
2201         .parent         = &func_96m_ck,
2202         .flags          = CLOCK_IN_OMAP243X,
2203         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2204         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2205         .recalc         = &followparent_recalc,
2206 };
2207
2208 static struct clk i2c1_ick = {
2209         .name           = "i2c_ick",
2210         .id             = 1,
2211         .parent         = &l4_ck,
2212         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2213         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2214         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 static struct clk i2c1_fck = {
2219         .name           = "i2c_fck",
2220         .id             = 1,
2221         .parent         = &func_12m_ck,
2222         .flags          = CLOCK_IN_OMAP242X,
2223         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2224         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2225         .recalc         = &followparent_recalc,
2226 };
2227
2228 static struct clk i2chs1_fck = {
2229         .name           = "i2chs_fck",
2230         .id             = 1,
2231         .parent         = &func_96m_ck,
2232         .flags          = CLOCK_IN_OMAP243X,
2233         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2234         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2235         .recalc         = &followparent_recalc,
2236 };
2237
2238 static struct clk gpmc_fck = {
2239         .name           = "gpmc_fck",
2240         .parent         = &core_l3_ck,
2241         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk sdma_fck = {
2246         .name           = "sdma_fck",
2247         .parent         = &core_l3_ck,
2248         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk sdma_ick = {
2253         .name           = "sdma_ick",
2254         .parent         = &l4_ck,
2255         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2256         .recalc         = &followparent_recalc,
2257 };
2258
2259 static struct clk vlynq_ick = {
2260         .name           = "vlynq_ick",
2261         .parent         = &core_l3_ck,
2262         .flags          = CLOCK_IN_OMAP242X,
2263         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2264         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2265         .recalc         = &followparent_recalc,
2266 };
2267
2268 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2269         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2270         { .div = 0 }
2271 };
2272
2273 static const struct clksel_rate vlynq_fck_core_rates[] = {
2274         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2275         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2276         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2277         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2278         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2279         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2280         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2281         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2282         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2283         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2284         { .div = 0 }
2285 };
2286
2287 static const struct clksel vlynq_fck_clksel[] = {
2288         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2289         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2290         { .parent = NULL }
2291 };
2292
2293 static struct clk vlynq_fck = {
2294         .name           = "vlynq_fck",
2295         .parent         = &func_96m_ck,
2296         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2297         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2298         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2299         .init           = &omap2_init_clksel_parent,
2300         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2301         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2302         .clksel         = vlynq_fck_clksel,
2303         .recalc         = &omap2_clksel_recalc,
2304         .round_rate     = &omap2_clksel_round_rate,
2305         .set_rate       = &omap2_clksel_set_rate
2306 };
2307
2308 static struct clk sdrc_ick = {
2309         .name           = "sdrc_ick",
2310         .parent         = &l4_ck,
2311         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2312         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2313         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2314         .recalc         = &followparent_recalc,
2315 };
2316
2317 static struct clk des_ick = {
2318         .name           = "des_ick",
2319         .parent         = &l4_ck,
2320         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2321         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2322         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2323         .recalc         = &followparent_recalc,
2324 };
2325
2326 static struct clk sha_ick = {
2327         .name           = "sha_ick",
2328         .parent         = &l4_ck,
2329         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2330         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2331         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2332         .recalc         = &followparent_recalc,
2333 };
2334
2335 static struct clk rng_ick = {
2336         .name           = "rng_ick",
2337         .parent         = &l4_ck,
2338         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2339         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2340         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2341         .recalc         = &followparent_recalc,
2342 };
2343
2344 static struct clk aes_ick = {
2345         .name           = "aes_ick",
2346         .parent         = &l4_ck,
2347         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2348         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2349         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2350         .recalc         = &followparent_recalc,
2351 };
2352
2353 static struct clk pka_ick = {
2354         .name           = "pka_ick",
2355         .parent         = &l4_ck,
2356         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2357         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2358         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk usb_fck = {
2363         .name           = "usb_fck",
2364         .parent         = &func_48m_ck,
2365         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2366         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2367         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2368         .recalc         = &followparent_recalc,
2369 };
2370
2371 static struct clk usbhs_ick = {
2372         .name           = "usbhs_ick",
2373         .parent         = &core_l3_ck,
2374         .flags          = CLOCK_IN_OMAP243X,
2375         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2376         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2377         .recalc         = &followparent_recalc,
2378 };
2379
2380 static struct clk mmchs1_ick = {
2381         .name           = "mmchs1_ick",
2382         .parent         = &l4_ck,
2383         .flags          = CLOCK_IN_OMAP243X,
2384         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2385         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2386         .recalc         = &followparent_recalc,
2387 };
2388
2389 static struct clk mmchs1_fck = {
2390         .name           = "mmchs1_fck",
2391         .parent         = &func_96m_ck,
2392         .flags          = CLOCK_IN_OMAP243X,
2393         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2394         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static struct clk mmchs2_ick = {
2399         .name           = "mmchs2_ick",
2400         .parent         = &l4_ck,
2401         .flags          = CLOCK_IN_OMAP243X,
2402         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2403         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2404         .recalc         = &followparent_recalc,
2405 };
2406
2407 static struct clk mmchs2_fck = {
2408         .name           = "mmchs2_fck",
2409         .parent         = &func_96m_ck,
2410         .flags          = CLOCK_IN_OMAP243X,
2411         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2412         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2413         .recalc         = &followparent_recalc,
2414 };
2415
2416 static struct clk gpio5_ick = {
2417         .name           = "gpio5_ick",
2418         .parent         = &l4_ck,
2419         .flags          = CLOCK_IN_OMAP243X,
2420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2421         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2422         .recalc         = &followparent_recalc,
2423 };
2424
2425 static struct clk gpio5_fck = {
2426         .name           = "gpio5_fck",
2427         .parent         = &func_32k_ck,
2428         .flags          = CLOCK_IN_OMAP243X,
2429         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2430         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2431         .recalc         = &followparent_recalc,
2432 };
2433
2434 static struct clk mdm_intc_ick = {
2435         .name           = "mdm_intc_ick",
2436         .parent         = &l4_ck,
2437         .flags          = CLOCK_IN_OMAP243X,
2438         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2439         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2440         .recalc         = &followparent_recalc,
2441 };
2442
2443 static struct clk mmchsdb1_fck = {
2444         .name           = "mmchsdb1_fck",
2445         .parent         = &func_32k_ck,
2446         .flags          = CLOCK_IN_OMAP243X,
2447         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2448         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2449         .recalc         = &followparent_recalc,
2450 };
2451
2452 static struct clk mmchsdb2_fck = {
2453         .name           = "mmchsdb2_fck",
2454         .parent         = &func_32k_ck,
2455         .flags          = CLOCK_IN_OMAP243X,
2456         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2457         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2458         .recalc         = &followparent_recalc,
2459 };
2460
2461 /*
2462  * This clock is a composite clock which does entire set changes then
2463  * forces a rebalance. It keys on the MPU speed, but it really could
2464  * be any key speed part of a set in the rate table.
2465  *
2466  * to really change a set, you need memory table sets which get changed
2467  * in sram, pre-notifiers & post notifiers, changing the top set, without
2468  * having low level display recalc's won't work... this is why dpm notifiers
2469  * work, isr's off, walk a list of clocks already _off_ and not messing with
2470  * the bus.
2471  *
2472  * This clock should have no parent. It embodies the entire upper level
2473  * active set. A parent will mess up some of the init also.
2474  */
2475 static struct clk virt_prcm_set = {
2476         .name           = "virt_prcm_set",
2477         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2478                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2479         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2480         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2481         .set_rate       = &omap2_select_table_rate,
2482         .round_rate     = &omap2_round_to_table_rate,
2483 };
2484
2485 static struct clk *onchip_clks[] __initdata = {
2486         /* external root sources */
2487         &func_32k_ck,
2488         &osc_ck,
2489         &sys_ck,
2490         &alt_ck,
2491         /* internal analog sources */
2492         &dpll_ck,
2493         &apll96_ck,
2494         &apll54_ck,
2495         /* internal prcm root sources */
2496         &func_54m_ck,
2497         &core_ck,
2498         &func_96m_ck,
2499         &func_48m_ck,
2500         &func_12m_ck,
2501         &wdt1_osc_ck,
2502         &sys_clkout_src,
2503         &sys_clkout,
2504         &sys_clkout2_src,
2505         &sys_clkout2,
2506         &emul_ck,
2507         /* mpu domain clocks */
2508         &mpu_ck,
2509         /* dsp domain clocks */
2510         &iva2_1_fck,            /* 2430 */
2511         &iva2_1_ick,
2512         &dsp_ick,               /* 2420 */
2513         &dsp_fck,
2514         &iva1_ifck,
2515         &iva1_mpu_int_ifck,
2516         /* GFX domain clocks */
2517         &gfx_3d_fck,
2518         &gfx_2d_fck,
2519         &gfx_ick,
2520         /* Modem domain clocks */
2521         &mdm_ick,
2522         &mdm_osc_ck,
2523         /* DSS domain clocks */
2524         &dss_ick,
2525         &dss1_fck,
2526         &dss2_fck,
2527         &dss_54m_fck,
2528         /* L3 domain clocks */
2529         &core_l3_ck,
2530         &ssi_ssr_sst_fck,
2531         &usb_l4_ick,
2532         /* L4 domain clocks */
2533         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2534         &ssi_l4_ick,
2535         /* virtual meta-group clock */
2536         &virt_prcm_set,
2537         /* general l4 interface ck, multi-parent functional clk */
2538         &gpt1_ick,
2539         &gpt1_fck,
2540         &gpt2_ick,
2541         &gpt2_fck,
2542         &gpt3_ick,
2543         &gpt3_fck,
2544         &gpt4_ick,
2545         &gpt4_fck,
2546         &gpt5_ick,
2547         &gpt5_fck,
2548         &gpt6_ick,
2549         &gpt6_fck,
2550         &gpt7_ick,
2551         &gpt7_fck,
2552         &gpt8_ick,
2553         &gpt8_fck,
2554         &gpt9_ick,
2555         &gpt9_fck,
2556         &gpt10_ick,
2557         &gpt10_fck,
2558         &gpt11_ick,
2559         &gpt11_fck,
2560         &gpt12_ick,
2561         &gpt12_fck,
2562         &mcbsp1_ick,
2563         &mcbsp1_fck,
2564         &mcbsp2_ick,
2565         &mcbsp2_fck,
2566         &mcbsp3_ick,
2567         &mcbsp3_fck,
2568         &mcbsp4_ick,
2569         &mcbsp4_fck,
2570         &mcbsp5_ick,
2571         &mcbsp5_fck,
2572         &mcspi1_ick,
2573         &mcspi1_fck,
2574         &mcspi2_ick,
2575         &mcspi2_fck,
2576         &mcspi3_ick,
2577         &mcspi3_fck,
2578         &uart1_ick,
2579         &uart1_fck,
2580         &uart2_ick,
2581         &uart2_fck,
2582         &uart3_ick,
2583         &uart3_fck,
2584         &gpios_ick,
2585         &gpios_fck,
2586         &mpu_wdt_ick,
2587         &mpu_wdt_fck,
2588         &sync_32k_ick,
2589         &wdt1_ick,
2590         &omapctrl_ick,
2591         &icr_ick,
2592         &cam_fck,
2593         &cam_ick,
2594         &mailboxes_ick,
2595         &wdt4_ick,
2596         &wdt4_fck,
2597         &wdt3_ick,
2598         &wdt3_fck,
2599         &mspro_ick,
2600         &mspro_fck,
2601         &mmc_ick,
2602         &mmc_fck,
2603         &fac_ick,
2604         &fac_fck,
2605         &eac_ick,
2606         &eac_fck,
2607         &hdq_ick,
2608         &hdq_fck,
2609         &i2c1_ick,
2610         &i2c1_fck,
2611         &i2chs1_fck,
2612         &i2c2_ick,
2613         &i2c2_fck,
2614         &i2chs2_fck,
2615         &gpmc_fck,
2616         &sdma_fck,
2617         &sdma_ick,
2618         &vlynq_ick,
2619         &vlynq_fck,
2620         &sdrc_ick,
2621         &des_ick,
2622         &sha_ick,
2623         &rng_ick,
2624         &aes_ick,
2625         &pka_ick,
2626         &usb_fck,
2627         &usbhs_ick,
2628         &mmchs1_ick,
2629         &mmchs1_fck,
2630         &mmchs2_ick,
2631         &mmchs2_fck,
2632         &gpio5_ick,
2633         &gpio5_fck,
2634         &mdm_intc_ick,
2635         &mmchsdb1_fck,
2636         &mmchsdb2_fck,
2637 };
2638
2639 #endif
2640