arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*
 604  * Since 2420 and 2430 have different cm_base, we use offsets only here.
 605  * Clock code will rewrite the register address as needed.
 606  */
 607 #define _CM_REG_OFFSET(module, reg)     ((void __iomem *)(module) + (reg))
 608 #define _GR_MOD_OFFSET(reg)     ((void __iomem *)(OMAP24XX_GR_MOD + (reg)))
 609
 610 /*-------------------------------------------------------------------------
 611  * 24xx clock tree.
 612  *
 613  * NOTE:In many cases here we are assigning a 'default' parent. In many
 614  *      cases the parent is selectable. The get/set parent calls will also
 615  *      switch sources.
 616  *
 617  *      Many some clocks say always_enabled, but they can be auto idled for
 618  *      power savings. They will always be available upon clock request.
 619  *
 620  *      Several sources are given initial rates which may be wrong, this will
 621  *      be fixed up in the init func.
 622  *
 623  *      Things are broadly separated below by clock domains. It is
 624  *      noteworthy that most periferals have dependencies on multiple clock
 625  *      domains. Many get their interface clocks from the L4 domain, but get
 626  *      functional clocks from fixed sources or other core domain derived
 627  *      clocks.
 628  *-------------------------------------------------------------------------*/
 629
 630 /* Base external input clocks */
 631 static struct clk func_32k_ck = {
 632         .name           = "func_32k_ck",
 633         .rate           = 32000,
 634         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 635                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 636         .clkdm_name     = "wkup_clkdm",
 637         .recalc         = &propagate_rate,
 638 };
 639
 640 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 641 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 642         .name           = "osc_ck",
 643         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 644                                 RATE_PROPAGATES,
 645         .clkdm_name     = "wkup_clkdm",
 646         .enable         = &omap2_enable_osc_ck,
 647         .disable        = &omap2_disable_osc_ck,
 648         .recalc         = &omap2_osc_clk_recalc,
 649 };
 650
 651 /* Without modem likely 12MHz, with modem likely 13MHz */
 652 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 653         .name           = "sys_ck",             /* ~ ref_clk also */
 654         .parent         = &osc_ck,
 655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 656                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 657         .clkdm_name     = "wkup_clkdm",
 658         .recalc         = &omap2_sys_clk_recalc,
 659 };
 660
 661 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 662         .name           = "alt_ck",
 663         .rate           = 54000000,
 664         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 665                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 666         .clkdm_name     = "wkup_clkdm",
 667         .recalc         = &propagate_rate,
 668 };
 669
 670 /*
 671  * Analog domain root source clocks
 672  */
 673
 674 /* dpll_ck, is broken out in to special cases through clksel */
 675 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 676  * deal with this
 677  */
 678
 679 static struct dpll_data dpll_dd = {
 680         .mult_div1_reg          = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 681         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 682         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 683         .max_multiplier         = 1024,
 684         .max_divider            = 16,
 685         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 686 };
 687
 688 /*
 689  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 690  * not just a DPLL
 691  */
 692 static struct clk dpll_ck = {
 693         .name           = "dpll_ck",
 694         .parent         = &sys_ck,              /* Can be func_32k also */
 695         .dpll_data      = &dpll_dd,
 696         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 697                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 698         .clkdm_name     = "wkup_clkdm",
 699         .recalc         = &omap2_dpllcore_recalc,
 700         .set_rate       = &omap2_reprogram_dpllcore,
 701 };
 702
 703 static struct clk apll96_ck = {
 704         .name           = "apll96_ck",
 705         .parent         = &sys_ck,
 706         .rate           = 96000000,
 707         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 708                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 709         .clkdm_name     = "wkup_clkdm",
 710         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 711         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 712         .enable         = &omap2_clk_fixed_enable,
 713         .disable        = &omap2_clk_fixed_disable,
 714         .recalc         = &propagate_rate,
 715 };
 716
 717 static struct clk apll54_ck = {
 718         .name           = "apll54_ck",
 719         .parent         = &sys_ck,
 720         .rate           = 54000000,
 721         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 722                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 723         .clkdm_name     = "wkup_clkdm",
 724         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 725         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 726         .enable         = &omap2_clk_fixed_enable,
 727         .disable        = &omap2_clk_fixed_disable,
 728         .recalc         = &propagate_rate,
 729 };
 730
 731 /*
 732  * PRCM digital base sources
 733  */
 734
 735 /* func_54m_ck */
 736
 737 static const struct clksel_rate func_54m_apll54_rates[] = {
 738         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 739         { .div = 0 },
 740 };
 741
 742 static const struct clksel_rate func_54m_alt_rates[] = {
 743         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 744         { .div = 0 },
 745 };
 746
 747 static const struct clksel func_54m_clksel[] = {
 748         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 749         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 750         { .parent = NULL },
 751 };
 752
 753 static struct clk func_54m_ck = {
 754         .name           = "func_54m_ck",
 755         .parent         = &apll54_ck,   /* can also be alt_clk */
 756         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 757                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 758         .clkdm_name     = "wkup_clkdm",
 759         .init           = &omap2_init_clksel_parent,
 760         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 761         .clksel_mask    = OMAP24XX_54M_SOURCE,
 762         .clksel         = func_54m_clksel,
 763         .recalc         = &omap2_clksel_recalc,
 764 };
 765
 766 static struct clk core_ck = {
 767         .name           = "core_ck",
 768         .parent         = &dpll_ck,             /* can also be 32k */
 769         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 770                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 771         .clkdm_name     = "wkup_clkdm",
 772         .recalc         = &followparent_recalc,
 773 };
 774
 775 /* func_96m_ck */
 776 static const struct clksel_rate func_96m_apll96_rates[] = {
 777         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 778         { .div = 0 },
 779 };
 780
 781 static const struct clksel_rate func_96m_alt_rates[] = {
 782         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 783         { .div = 0 },
 784 };
 785
 786 static const struct clksel func_96m_clksel[] = {
 787         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 788         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 789         { .parent = NULL }
 790 };
 791
 792 /* The parent of this clock is not selectable on 2420. */
 793 static struct clk func_96m_ck = {
 794         .name           = "func_96m_ck",
 795         .parent         = &apll96_ck,
 796         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 797                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 798         .clkdm_name     = "wkup_clkdm",
 799         .init           = &omap2_init_clksel_parent,
 800         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 801         .clksel_mask    = OMAP2430_96M_SOURCE,
 802         .clksel         = func_96m_clksel,
 803         .recalc         = &omap2_clksel_recalc,
 804         .round_rate     = &omap2_clksel_round_rate,
 805         .set_rate       = &omap2_clksel_set_rate
 806 };
 807
 808 /* func_48m_ck */
 809
 810 static const struct clksel_rate func_48m_apll96_rates[] = {
 811         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 812         { .div = 0 },
 813 };
 814
 815 static const struct clksel_rate func_48m_alt_rates[] = {
 816         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 817         { .div = 0 },
 818 };
 819
 820 static const struct clksel func_48m_clksel[] = {
 821         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 822         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 823         { .parent = NULL }
 824 };
 825
 826 static struct clk func_48m_ck = {
 827         .name           = "func_48m_ck",
 828         .parent         = &apll96_ck,    /* 96M or Alt */
 829         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 830                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 831         .clkdm_name     = "wkup_clkdm",
 832         .init           = &omap2_init_clksel_parent,
 833         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 834         .clksel_mask    = OMAP24XX_48M_SOURCE,
 835         .clksel         = func_48m_clksel,
 836         .recalc         = &omap2_clksel_recalc,
 837         .round_rate     = &omap2_clksel_round_rate,
 838         .set_rate       = &omap2_clksel_set_rate
 839 };
 840
 841 static struct clk func_12m_ck = {
 842         .name           = "func_12m_ck",
 843         .parent         = &func_48m_ck,
 844         .fixed_div      = 4,
 845         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 846                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 847         .clkdm_name     = "wkup_clkdm",
 848         .recalc         = &omap2_fixed_divisor_recalc,
 849 };
 850
 851 /* Secure timer, only available in secure mode */
 852 static struct clk wdt1_osc_ck = {
 853         .name           = "ck_wdt1_osc",
 854         .parent         = &osc_ck,
 855         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 856         .recalc         = &followparent_recalc,
 857 };
 858
 859 /*
 860  * The common_clkout* clksel_rate structs are common to
 861  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 862  * sys_clkout2_* are 2420-only, so the
 863  * clksel_rate flags fields are inaccurate for those clocks. This is
 864  * harmless since access to those clocks are gated by the struct clk
 865  * flags fields, which mark them as 2420-only.
 866  */
 867 static const struct clksel_rate common_clkout_src_core_rates[] = {
 868         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 869         { .div = 0 }
 870 };
 871
 872 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 873         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 874         { .div = 0 }
 875 };
 876
 877 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 878         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 879         { .div = 0 }
 880 };
 881
 882 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 883         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 884         { .div = 0 }
 885 };
 886
 887 static const struct clksel common_clkout_src_clksel[] = {
 888         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 889         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 890         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 891         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 892         { .parent = NULL }
 893 };
 894
 895 static struct clk sys_clkout_src = {
 896         .name           = "sys_clkout_src",
 897         .parent         = &func_54m_ck,
 898         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 899                                 RATE_PROPAGATES | OFFSET_GR_MOD,
 900         .clkdm_name     = "wkup_clkdm",
 901         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 902         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 903         .init           = &omap2_init_clksel_parent,
 904         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 905         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 906         .clksel         = common_clkout_src_clksel,
 907         .recalc         = &omap2_clksel_recalc,
 908         .round_rate     = &omap2_clksel_round_rate,
 909         .set_rate       = &omap2_clksel_set_rate
 910 };
 911
 912 static const struct clksel_rate common_clkout_rates[] = {
 913         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 914         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 915         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 916         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 917         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 918         { .div = 0 },
 919 };
 920
 921 static const struct clksel sys_clkout_clksel[] = {
 922         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 923         { .parent = NULL }
 924 };
 925
 926 static struct clk sys_clkout = {
 927         .name           = "sys_clkout",
 928         .parent         = &sys_clkout_src,
 929         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 930                                 PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
 931         .clkdm_name     = "wkup_clkdm",
 932         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 933         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 934         .clksel         = sys_clkout_clksel,
 935         .recalc         = &omap2_clksel_recalc,
 936         .round_rate     = &omap2_clksel_round_rate,
 937         .set_rate       = &omap2_clksel_set_rate
 938 };
 939
 940 /* In 2430, new in 2420 ES2 */
 941 static struct clk sys_clkout2_src = {
 942         .name           = "sys_clkout2_src",
 943         .parent         = &func_54m_ck,
 944         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
 945         .clkdm_name     = "wkup_clkdm",
 946         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 947         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 948         .init           = &omap2_init_clksel_parent,
 949         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 950         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 951         .clksel         = common_clkout_src_clksel,
 952         .recalc         = &omap2_clksel_recalc,
 953         .round_rate     = &omap2_clksel_round_rate,
 954         .set_rate       = &omap2_clksel_set_rate
 955 };
 956
 957 static const struct clksel sys_clkout2_clksel[] = {
 958         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 959         { .parent = NULL }
 960 };
 961
 962 /* In 2430, new in 2420 ES2 */
 963 static struct clk sys_clkout2 = {
 964         .name           = "sys_clkout2",
 965         .parent         = &sys_clkout2_src,
 966         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
 967                                 OFFSET_GR_MOD,
 968         .clkdm_name     = "wkup_clkdm",
 969         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 970         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 971         .clksel         = sys_clkout2_clksel,
 972         .recalc         = &omap2_clksel_recalc,
 973         .round_rate     = &omap2_clksel_round_rate,
 974         .set_rate       = &omap2_clksel_set_rate
 975 };
 976
 977 static struct clk emul_ck = {
 978         .name           = "emul_ck",
 979         .parent         = &func_54m_ck,
 980         .flags          = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
 981         .clkdm_name     = "wkup_clkdm",
 982         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
 983         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 984         .recalc         = &followparent_recalc,
 985
 986 };
 987
 988 /*
 989  * MPU clock domain
 990  *      Clocks:
 991  *              MPU_FCLK, MPU_ICLK
 992  *              INT_M_FCLK, INT_M_I_CLK
 993  *
 994  * - Individual clocks are hardware managed.
 995  * - Base divider comes from: CM_CLKSEL_MPU
 996  *
 997  */
 998 static const struct clksel_rate mpu_core_rates[] = {
 999         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1000         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1001         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1002         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1003         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1004         { .div = 0 },
1005 };
1006
1007 static const struct clksel mpu_clksel[] = {
1008         { .parent = &core_ck, .rates = mpu_core_rates },
1009         { .parent = NULL }
1010 };
1011
1012 static struct clk mpu_ck = {    /* Control cpu */
1013         .name           = "mpu_ck",
1014         .parent         = &core_ck,
1015         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1016                                 ALWAYS_ENABLED | DELAYED_APP |
1017                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1018         .clkdm_name     = "mpu_clkdm",
1019         .init           = &omap2_init_clksel_parent,
1020         .clksel_reg     = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL),
1021         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1022         .clksel         = mpu_clksel,
1023         .recalc         = &omap2_clksel_recalc,
1024         .round_rate     = &omap2_clksel_round_rate,
1025         .set_rate       = &omap2_clksel_set_rate
1026 };
1027
1028 /*
1029  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1030  * Clocks:
1031  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1032  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1033  *
1034  * Won't be too specific here. The core clock comes into this block
1035  * it is divided then tee'ed. One branch goes directly to xyz enable
1036  * controls. The other branch gets further divided by 2 then possibly
1037  * routed into a synchronizer and out of clocks abc.
1038  */
1039 static const struct clksel_rate dsp_fck_core_rates[] = {
1040         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1041         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1042         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1043         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1044         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1045         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1046         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1047         { .div = 0 },
1048 };
1049
1050 static const struct clksel dsp_fck_clksel[] = {
1051         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1052         { .parent = NULL }
1053 };
1054
1055 static struct clk dsp_fck = {
1056         .name           = "dsp_fck",
1057         .parent         = &core_ck,
1058         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1059                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1060         .clkdm_name     = "dsp_clkdm",
1061         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1062         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1063         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1064         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1065         .clksel         = dsp_fck_clksel,
1066         .recalc         = &omap2_clksel_recalc,
1067         .round_rate     = &omap2_clksel_round_rate,
1068         .set_rate       = &omap2_clksel_set_rate
1069 };
1070
1071 /* DSP interface clock */
1072 static const struct clksel_rate dsp_irate_ick_rates[] = {
1073         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1074         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1075         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1076         { .div = 0 },
1077 };
1078
1079 static const struct clksel dsp_irate_ick_clksel[] = {
1080         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1081         { .parent = NULL }
1082 };
1083
1084 /* This clock does not exist as such in the TRM. */
1085 static struct clk dsp_irate_ick = {
1086         .name           = "dsp_irate_ick",
1087         .parent         = &dsp_fck,
1088         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1089                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1090         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1091         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1092         .clksel         = dsp_irate_ick_clksel,
1093         .recalc         = &omap2_clksel_recalc,
1094         .round_rate     = &omap2_clksel_round_rate,
1095         .set_rate             = &omap2_clksel_set_rate
1096 };
1097
1098 /* 2420 only */
1099 static struct clk dsp_ick = {
1100         .name           = "dsp_ick",     /* apparently ipi and isp */
1101         .parent         = &dsp_irate_ick,
1102         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1103         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
1104         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1105 };
1106
1107 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1108 static struct clk iva2_1_ick = {
1109         .name           = "iva2_1_ick",
1110         .parent         = &dsp_irate_ick,
1111         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1112         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1113         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1114 };
1115
1116 /*
1117  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1118  * the C54x, but which is contained in the DSP powerdomain.  Does not
1119  * exist on later OMAPs.
1120  */
1121 static struct clk iva1_ifck = {
1122         .name           = "iva1_ifck",
1123         .parent         = &core_ck,
1124         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1125                                 RATE_PROPAGATES | DELAYED_APP,
1126         .clkdm_name     = "iva1_clkdm",
1127         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1128         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1129         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1130         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1131         .clksel         = dsp_fck_clksel,
1132         .recalc         = &omap2_clksel_recalc,
1133         .round_rate     = &omap2_clksel_round_rate,
1134         .set_rate       = &omap2_clksel_set_rate
1135 };
1136
1137 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1138 static struct clk iva1_mpu_int_ifck = {
1139         .name           = "iva1_mpu_int_ifck",
1140         .parent         = &iva1_ifck,
1141         .flags          = CLOCK_IN_OMAP242X,
1142         .clkdm_name     = "iva1_clkdm",
1143         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1144         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1145         .fixed_div      = 2,
1146         .recalc         = &omap2_fixed_divisor_recalc,
1147 };
1148
1149 /*
1150  * L3 clock domain
1151  * L3 clocks are used for both interface and functional clocks to
1152  * multiple entities. Some of these clocks are completely managed
1153  * by hardware, and some others allow software control. Hardware
1154  * managed ones general are based on directly CLK_REQ signals and
1155  * various auto idle settings. The functional spec sets many of these
1156  * as 'tie-high' for their enables.
1157  *
1158  * I-CLOCKS:
1159  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1160  *      CAM, HS-USB.
1161  * F-CLOCK
1162  *      SSI.
1163  *
1164  * GPMC memories and SDRC have timing and clock sensitive registers which
1165  * may very well need notification when the clock changes. Currently for low
1166  * operating points, these are taken care of in sleep.S.
1167  */
1168 static const struct clksel_rate core_l3_core_rates[] = {
1169         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1170         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1171         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1172         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1173         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1174         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1175         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1176         { .div = 0 }
1177 };
1178
1179 static const struct clksel core_l3_clksel[] = {
1180         { .parent = &core_ck, .rates = core_l3_core_rates },
1181         { .parent = NULL }
1182 };
1183
1184 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1185         .name           = "core_l3_ck",
1186         .parent         = &core_ck,
1187         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1188                                 ALWAYS_ENABLED | DELAYED_APP |
1189                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1190         .clkdm_name     = "core_l3_clkdm",
1191         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1192         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1193         .clksel         = core_l3_clksel,
1194         .recalc         = &omap2_clksel_recalc,
1195         .round_rate     = &omap2_clksel_round_rate,
1196         .set_rate       = &omap2_clksel_set_rate
1197 };
1198
1199 /* usb_l4_ick */
1200 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1201         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1202         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1203         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1204         { .div = 0 }
1205 };
1206
1207 static const struct clksel usb_l4_ick_clksel[] = {
1208         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1209         { .parent = NULL },
1210 };
1211
1212 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1213 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1214         .name           = "usb_l4_ick",
1215         .parent         = &core_l3_ck,
1216         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1217                                 DELAYED_APP | CONFIG_PARTICIPANT,
1218         .clkdm_name     = "core_l4_clkdm",
1219         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1220         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1221         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1222         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1223         .clksel         = usb_l4_ick_clksel,
1224         .recalc         = &omap2_clksel_recalc,
1225         .round_rate     = &omap2_clksel_round_rate,
1226         .set_rate       = &omap2_clksel_set_rate
1227 };
1228
1229 /*
1230  * L4 clock management domain
1231  *
1232  * This domain contains lots of interface clocks from the L4 interface, some
1233  * functional clocks.   Fixed APLL functional source clocks are managed in
1234  * this domain.
1235  */
1236 static const struct clksel_rate l4_core_l3_rates[] = {
1237         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1238         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1239         { .div = 0 }
1240 };
1241
1242 static const struct clksel l4_clksel[] = {
1243         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1244         { .parent = NULL }
1245 };
1246
1247 static struct clk l4_ck = {             /* used both as an ick and fck */
1248         .name           = "l4_ck",
1249         .parent         = &core_l3_ck,
1250         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1251                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1252         .clkdm_name     = "core_l4_clkdm",
1253         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1254         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1255         .clksel         = l4_clksel,
1256         .recalc         = &omap2_clksel_recalc,
1257         .round_rate     = &omap2_clksel_round_rate,
1258         .set_rate       = &omap2_clksel_set_rate
1259 };
1260
1261 /*
1262  * SSI is in L3 management domain, its direct parent is core not l3,
1263  * many core power domain entities are grouped into the L3 clock
1264  * domain.
1265  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1266  *
1267  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1268  */
1269 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1270         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1271         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1272         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1273         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1274         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1275         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1276         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1277         { .div = 0 }
1278 };
1279
1280 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1281         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1282         { .parent = NULL }
1283 };
1284
1285 static struct clk ssi_ssr_sst_fck = {
1286         .name           = "ssi_fck",
1287         .parent         = &core_ck,
1288         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1289                                 DELAYED_APP,
1290         .clkdm_name     = "core_l3_clkdm",
1291         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1292         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1293         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1294         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1295         .clksel         = ssi_ssr_sst_fck_clksel,
1296         .recalc         = &omap2_clksel_recalc,
1297         .round_rate     = &omap2_clksel_round_rate,
1298         .set_rate       = &omap2_clksel_set_rate
1299 };
1300
1301 /*
1302  * Presumably this is the same as SSI_ICLK.
1303  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1304  */
1305 static struct clk ssi_l4_ick = {
1306         .name           = "ssi_l4_ick",
1307         .parent         = &l4_ck,
1308         .clkdm_name     = "core_l4_clkdm",
1309         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1310         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1311         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315
1316 /*
1317  * GFX clock domain
1318  *      Clocks:
1319  * GFX_FCLK, GFX_ICLK
1320  * GFX_CG1(2d), GFX_CG2(3d)
1321  *
1322  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1323  * The 2d and 3d clocks run at a hardware determined
1324  * divided value of fclk.
1325  *
1326  */
1327 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1328
1329 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1330 static const struct clksel gfx_fck_clksel[] = {
1331         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1332         { .parent = NULL },
1333 };
1334
1335 static struct clk gfx_3d_fck = {
1336         .name           = "gfx_3d_fck",
1337         .parent         = &core_l3_ck,
1338         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1339         .clkdm_name     = "gfx_clkdm",
1340         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1341         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1342         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1343         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1344         .clksel         = gfx_fck_clksel,
1345         .recalc         = &omap2_clksel_recalc,
1346         .round_rate     = &omap2_clksel_round_rate,
1347         .set_rate       = &omap2_clksel_set_rate
1348 };
1349
1350 static struct clk gfx_2d_fck = {
1351         .name           = "gfx_2d_fck",
1352         .parent         = &core_l3_ck,
1353         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1354         .clkdm_name     = "gfx_clkdm",
1355         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1356         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1357         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1358         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1359         .clksel         = gfx_fck_clksel,
1360         .recalc         = &omap2_clksel_recalc,
1361         .round_rate     = &omap2_clksel_round_rate,
1362         .set_rate       = &omap2_clksel_set_rate
1363 };
1364
1365 static struct clk gfx_ick = {
1366         .name           = "gfx_ick",            /* From l3 */
1367         .parent         = &core_l3_ck,
1368         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1369         .clkdm_name     = "gfx_clkdm",
1370         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
1371         .enable_bit     = OMAP_EN_GFX_SHIFT,
1372         .recalc         = &followparent_recalc,
1373 };
1374
1375 /*
1376  * Modem clock domain (2430)
1377  *      CLOCKS:
1378  *              MDM_OSC_CLK
1379  *              MDM_ICLK
1380  * These clocks are usable in chassis mode only.
1381  */
1382 static const struct clksel_rate mdm_ick_core_rates[] = {
1383         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1384         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1385         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1386         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1387         { .div = 0 }
1388 };
1389
1390 static const struct clksel mdm_ick_clksel[] = {
1391         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1392         { .parent = NULL }
1393 };
1394
1395 static struct clk mdm_ick = {           /* used both as a ick and fck */
1396         .name           = "mdm_ick",
1397         .parent         = &core_ck,
1398         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1399         .clkdm_name     = "mdm_clkdm",
1400         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
1401         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1402         .clksel_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL),
1403         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1404         .clksel         = mdm_ick_clksel,
1405         .recalc         = &omap2_clksel_recalc,
1406         .round_rate     = &omap2_clksel_round_rate,
1407         .set_rate       = &omap2_clksel_set_rate
1408 };
1409
1410 static struct clk mdm_osc_ck = {
1411         .name           = "mdm_osc_ck",
1412         .parent         = &osc_ck,
1413         .flags          = CLOCK_IN_OMAP243X,
1414         .clkdm_name     = "mdm_clkdm",
1415         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
1416         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 /*
1421  * DSS clock domain
1422  * CLOCKs:
1423  * DSS_L4_ICLK, DSS_L3_ICLK,
1424  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1425  *
1426  * DSS is both initiator and target.
1427  */
1428 /* XXX Add RATE_NOT_VALIDATED */
1429
1430 static const struct clksel_rate dss1_fck_sys_rates[] = {
1431         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1432         { .div = 0 }
1433 };
1434
1435 static const struct clksel_rate dss1_fck_core_rates[] = {
1436         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1437         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1438         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1439         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1440         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1441         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1442         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1443         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1444         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1445         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1446         { .div = 0 }
1447 };
1448
1449 static const struct clksel dss1_fck_clksel[] = {
1450         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1451         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1452         { .parent = NULL },
1453 };
1454
1455 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1456         .name           = "dss_ick",
1457         .parent         = &l4_ck,       /* really both l3 and l4 */
1458         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1459         .clkdm_name     = "dss_clkdm",
1460         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1461         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1462         .recalc         = &followparent_recalc,
1463 };
1464
1465 static struct clk dss1_fck = {
1466         .name           = "dss1_fck",
1467         .parent         = &core_ck,             /* Core or sys */
1468         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1469                                 DELAYED_APP,
1470         .clkdm_name     = "dss_clkdm",
1471         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1472         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1473         .init           = &omap2_init_clksel_parent,
1474         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1475         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1476         .clksel         = dss1_fck_clksel,
1477         .recalc         = &omap2_clksel_recalc,
1478         .round_rate     = &omap2_clksel_round_rate,
1479         .set_rate       = &omap2_clksel_set_rate
1480 };
1481
1482 static const struct clksel_rate dss2_fck_sys_rates[] = {
1483         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1484         { .div = 0 }
1485 };
1486
1487 static const struct clksel_rate dss2_fck_48m_rates[] = {
1488         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1489         { .div = 0 }
1490 };
1491
1492 static const struct clksel dss2_fck_clksel[] = {
1493         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1494         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1495         { .parent = NULL }
1496 };
1497
1498 static struct clk dss2_fck = {          /* Alt clk used in power management */
1499         .name           = "dss2_fck",
1500         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1501         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1502                                 DELAYED_APP,
1503         .clkdm_name     = "dss_clkdm",
1504         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1505         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1506         .init           = &omap2_init_clksel_parent,
1507         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1508         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1509         .clksel         = dss2_fck_clksel,
1510         .recalc         = &followparent_recalc,
1511 };
1512
1513 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1514         .name           = "dss_54m_fck",        /* 54m tv clk */
1515         .parent         = &func_54m_ck,
1516         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1517         .clkdm_name     = "dss_clkdm",
1518         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1519         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 /*
1524  * CORE power domain ICLK & FCLK defines.
1525  * Many of the these can have more than one possible parent. Entries
1526  * here will likely have an L4 interface parent, and may have multiple
1527  * functional clock parents.
1528  */
1529 static const struct clksel_rate gpt_alt_rates[] = {
1530         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1531         { .div = 0 }
1532 };
1533
1534 static const struct clksel omap24xx_gpt_clksel[] = {
1535         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1536         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1537         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1538         { .parent = NULL },
1539 };
1540
1541 static struct clk gpt1_ick = {
1542         .name           = "gpt1_ick",
1543         .parent         = &l4_ck,
1544         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1545         .clkdm_name     = "core_l4_clkdm",
1546         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
1547         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk gpt1_fck = {
1552         .name           = "gpt1_fck",
1553         .parent         = &func_32k_ck,
1554         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1555         .clkdm_name     = "core_l4_clkdm",
1556         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
1557         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1558         .init           = &omap2_init_clksel_parent,
1559         .clksel_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_CLKSEL1),
1560         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1561         .clksel         = omap24xx_gpt_clksel,
1562         .recalc         = &omap2_clksel_recalc,
1563         .round_rate     = &omap2_clksel_round_rate,
1564         .set_rate       = &omap2_clksel_set_rate
1565 };
1566
1567 static struct clk gpt2_ick = {
1568         .name           = "gpt2_ick",
1569         .parent         = &l4_ck,
1570         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1571         .clkdm_name     = "core_l4_clkdm",
1572         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1573         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1574         .recalc         = &followparent_recalc,
1575 };
1576
1577 static struct clk gpt2_fck = {
1578         .name           = "gpt2_fck",
1579         .parent         = &func_32k_ck,
1580         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1581         .clkdm_name     = "core_l4_clkdm",
1582         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1583         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1584         .init           = &omap2_init_clksel_parent,
1585         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1586         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1587         .clksel         = omap24xx_gpt_clksel,
1588         .recalc         = &omap2_clksel_recalc,
1589 };
1590
1591 static struct clk gpt3_ick = {
1592         .name           = "gpt3_ick",
1593         .parent         = &l4_ck,
1594         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1595         .clkdm_name     = "core_l4_clkdm",
1596         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1597         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1598         .recalc         = &followparent_recalc,
1599 };
1600
1601 static struct clk gpt3_fck = {
1602         .name           = "gpt3_fck",
1603         .parent         = &func_32k_ck,
1604         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1605         .clkdm_name     = "core_l4_clkdm",
1606         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1607         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1608         .init           = &omap2_init_clksel_parent,
1609         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1610         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1611         .clksel         = omap24xx_gpt_clksel,
1612         .recalc         = &omap2_clksel_recalc,
1613 };
1614
1615 static struct clk gpt4_ick = {
1616         .name           = "gpt4_ick",
1617         .parent         = &l4_ck,
1618         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1619         .clkdm_name     = "core_l4_clkdm",
1620         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1621         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1622         .recalc         = &followparent_recalc,
1623 };
1624
1625 static struct clk gpt4_fck = {
1626         .name           = "gpt4_fck",
1627         .parent         = &func_32k_ck,
1628         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1629         .clkdm_name     = "core_l4_clkdm",
1630         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1631         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1632         .init           = &omap2_init_clksel_parent,
1633         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1634         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1635         .clksel         = omap24xx_gpt_clksel,
1636         .recalc         = &omap2_clksel_recalc,
1637 };
1638
1639 static struct clk gpt5_ick = {
1640         .name           = "gpt5_ick",
1641         .parent         = &l4_ck,
1642         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1643         .clkdm_name     = "core_l4_clkdm",
1644         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1645         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1646         .recalc         = &followparent_recalc,
1647 };
1648
1649 static struct clk gpt5_fck = {
1650         .name           = "gpt5_fck",
1651         .parent         = &func_32k_ck,
1652         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653         .clkdm_name     = "core_l4_clkdm",
1654         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1655         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1656         .init           = &omap2_init_clksel_parent,
1657         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1658         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1659         .clksel         = omap24xx_gpt_clksel,
1660         .recalc         = &omap2_clksel_recalc,
1661 };
1662
1663 static struct clk gpt6_ick = {
1664         .name           = "gpt6_ick",
1665         .parent         = &l4_ck,
1666         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1667         .clkdm_name     = "core_l4_clkdm",
1668         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1669         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1670         .recalc         = &followparent_recalc,
1671 };
1672
1673 static struct clk gpt6_fck = {
1674         .name           = "gpt6_fck",
1675         .parent         = &func_32k_ck,
1676         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1677         .clkdm_name     = "core_l4_clkdm",
1678         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1679         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1680         .init           = &omap2_init_clksel_parent,
1681         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1682         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1683         .clksel         = omap24xx_gpt_clksel,
1684         .recalc         = &omap2_clksel_recalc,
1685 };
1686
1687 static struct clk gpt7_ick = {
1688         .name           = "gpt7_ick",
1689         .parent         = &l4_ck,
1690         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1691         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1692         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 static struct clk gpt7_fck = {
1697         .name           = "gpt7_fck",
1698         .parent         = &func_32k_ck,
1699         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1700         .clkdm_name     = "core_l4_clkdm",
1701         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1702         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1703         .init           = &omap2_init_clksel_parent,
1704         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1705         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1706         .clksel         = omap24xx_gpt_clksel,
1707         .recalc         = &omap2_clksel_recalc,
1708 };
1709
1710 static struct clk gpt8_ick = {
1711         .name           = "gpt8_ick",
1712         .parent         = &l4_ck,
1713         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1714         .clkdm_name     = "core_l4_clkdm",
1715         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1716         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1717         .recalc         = &followparent_recalc,
1718 };
1719
1720 static struct clk gpt8_fck = {
1721         .name           = "gpt8_fck",
1722         .parent         = &func_32k_ck,
1723         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1724         .clkdm_name     = "core_l4_clkdm",
1725         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1726         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1727         .init           = &omap2_init_clksel_parent,
1728         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1729         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1730         .clksel         = omap24xx_gpt_clksel,
1731         .recalc         = &omap2_clksel_recalc,
1732 };
1733
1734 static struct clk gpt9_ick = {
1735         .name           = "gpt9_ick",
1736         .parent         = &l4_ck,
1737         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1738         .clkdm_name     = "core_l4_clkdm",
1739         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1740         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1741         .recalc         = &followparent_recalc,
1742 };
1743
1744 static struct clk gpt9_fck = {
1745         .name           = "gpt9_fck",
1746         .parent         = &func_32k_ck,
1747         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1748         .clkdm_name     = "core_l4_clkdm",
1749         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1750         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1751         .init           = &omap2_init_clksel_parent,
1752         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1753         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1754         .clksel         = omap24xx_gpt_clksel,
1755         .recalc         = &omap2_clksel_recalc,
1756 };
1757
1758 static struct clk gpt10_ick = {
1759         .name           = "gpt10_ick",
1760         .parent         = &l4_ck,
1761         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1762         .clkdm_name     = "core_l4_clkdm",
1763         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1764         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1765         .recalc         = &followparent_recalc,
1766 };
1767
1768 static struct clk gpt10_fck = {
1769         .name           = "gpt10_fck",
1770         .parent         = &func_32k_ck,
1771         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1772         .clkdm_name     = "core_l4_clkdm",
1773         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1774         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1775         .init           = &omap2_init_clksel_parent,
1776         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1777         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1778         .clksel         = omap24xx_gpt_clksel,
1779         .recalc         = &omap2_clksel_recalc,
1780 };
1781
1782 static struct clk gpt11_ick = {
1783         .name           = "gpt11_ick",
1784         .parent         = &l4_ck,
1785         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1786         .clkdm_name     = "core_l4_clkdm",
1787         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1788         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1789         .recalc         = &followparent_recalc,
1790 };
1791
1792 static struct clk gpt11_fck = {
1793         .name           = "gpt11_fck",
1794         .parent         = &func_32k_ck,
1795         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1796         .clkdm_name     = "core_l4_clkdm",
1797         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1798         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1799         .init           = &omap2_init_clksel_parent,
1800         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1801         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1802         .clksel         = omap24xx_gpt_clksel,
1803         .recalc         = &omap2_clksel_recalc,
1804 };
1805
1806 static struct clk gpt12_ick = {
1807         .name           = "gpt12_ick",
1808         .parent         = &l4_ck,
1809         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1810         .clkdm_name     = "core_l4_clkdm",
1811         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1812         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk gpt12_fck = {
1817         .name           = "gpt12_fck",
1818         .parent         = &func_32k_ck,
1819         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1820         .clkdm_name     = "core_l4_clkdm",
1821         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1822         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1823         .init           = &omap2_init_clksel_parent,
1824         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1825         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1826         .clksel         = omap24xx_gpt_clksel,
1827         .recalc         = &omap2_clksel_recalc,
1828 };
1829
1830 static struct clk mcbsp1_ick = {
1831         .name           = "mcbsp_ick",
1832         .id             = 1,
1833         .parent         = &l4_ck,
1834         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1835         .clkdm_name     = "core_l4_clkdm",
1836         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1837         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1838         .recalc         = &followparent_recalc,
1839 };
1840
1841 static struct clk mcbsp1_fck = {
1842         .name           = "mcbsp_fck",
1843         .id             = 1,
1844         .parent         = &func_96m_ck,
1845         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846         .clkdm_name     = "core_l4_clkdm",
1847         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1848         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1849         .recalc         = &followparent_recalc,
1850 };
1851
1852 static struct clk mcbsp2_ick = {
1853         .name           = "mcbsp_ick",
1854         .id             = 2,
1855         .parent         = &l4_ck,
1856         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1857         .clkdm_name     = "core_l4_clkdm",
1858         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1859         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1860         .recalc         = &followparent_recalc,
1861 };
1862
1863 static struct clk mcbsp2_fck = {
1864         .name           = "mcbsp_fck",
1865         .id             = 2,
1866         .parent         = &func_96m_ck,
1867         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1868         .clkdm_name     = "core_l4_clkdm",
1869         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1870         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1871         .recalc         = &followparent_recalc,
1872 };
1873
1874 static struct clk mcbsp3_ick = {
1875         .name           = "mcbsp_ick",
1876         .id             = 3,
1877         .parent         = &l4_ck,
1878         .flags          = CLOCK_IN_OMAP243X,
1879         .clkdm_name     = "core_l4_clkdm",
1880         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1881         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk mcbsp3_fck = {
1886         .name           = "mcbsp_fck",
1887         .id             = 3,
1888         .parent         = &func_96m_ck,
1889         .flags          = CLOCK_IN_OMAP243X,
1890         .clkdm_name     = "core_l4_clkdm",
1891         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1892         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mcbsp4_ick = {
1897         .name           = "mcbsp_ick",
1898         .id             = 4,
1899         .parent         = &l4_ck,
1900         .flags          = CLOCK_IN_OMAP243X,
1901         .clkdm_name     = "core_l4_clkdm",
1902         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1903         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mcbsp4_fck = {
1908         .name           = "mcbsp_fck",
1909         .id             = 4,
1910         .parent         = &func_96m_ck,
1911         .flags          = CLOCK_IN_OMAP243X,
1912         .clkdm_name     = "core_l4_clkdm",
1913         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1914         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk mcbsp5_ick = {
1919         .name           = "mcbsp_ick",
1920         .id             = 5,
1921         .parent         = &l4_ck,
1922         .flags          = CLOCK_IN_OMAP243X,
1923         .clkdm_name     = "core_l4_clkdm",
1924         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1925         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk mcbsp5_fck = {
1930         .name           = "mcbsp_fck",
1931         .id             = 5,
1932         .parent         = &func_96m_ck,
1933         .flags          = CLOCK_IN_OMAP243X,
1934         .clkdm_name     = "core_l4_clkdm",
1935         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1936         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 static struct clk mcspi1_ick = {
1941         .name           = "mcspi_ick",
1942         .id             = 1,
1943         .parent         = &l4_ck,
1944         .clkdm_name     = "core_l4_clkdm",
1945         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1946         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1947         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1948         .recalc         = &followparent_recalc,
1949 };
1950
1951 static struct clk mcspi1_fck = {
1952         .name           = "mcspi_fck",
1953         .id             = 1,
1954         .parent         = &func_48m_ck,
1955         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956         .clkdm_name     = "core_l4_clkdm",
1957         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1958         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1959         .recalc         = &followparent_recalc,
1960 };
1961
1962 static struct clk mcspi2_ick = {
1963         .name           = "mcspi_ick",
1964         .id             = 2,
1965         .parent         = &l4_ck,
1966         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1967         .clkdm_name     = "core_l4_clkdm",
1968         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1969         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1970         .recalc         = &followparent_recalc,
1971 };
1972
1973 static struct clk mcspi2_fck = {
1974         .name           = "mcspi_fck",
1975         .id             = 2,
1976         .parent         = &func_48m_ck,
1977         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1978         .clkdm_name     = "core_l4_clkdm",
1979         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1980         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1981         .recalc         = &followparent_recalc,
1982 };
1983
1984 static struct clk mcspi3_ick = {
1985         .name           = "mcspi_ick",
1986         .id             = 3,
1987         .parent         = &l4_ck,
1988         .flags          = CLOCK_IN_OMAP243X,
1989         .clkdm_name     = "core_l4_clkdm",
1990         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1991         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1992         .recalc         = &followparent_recalc,
1993 };
1994
1995 static struct clk mcspi3_fck = {
1996         .name           = "mcspi_fck",
1997         .id             = 3,
1998         .parent         = &func_48m_ck,
1999         .flags          = CLOCK_IN_OMAP243X,
2000         .clkdm_name     = "core_l4_clkdm",
2001         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2002         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 static struct clk uart1_ick = {
2007         .name           = "uart1_ick",
2008         .parent         = &l4_ck,
2009         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2010         .clkdm_name     = "core_l4_clkdm",
2011         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2012         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2013         .recalc         = &followparent_recalc,
2014 };
2015
2016 static struct clk uart1_fck = {
2017         .name           = "uart1_fck",
2018         .parent         = &func_48m_ck,
2019         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2020         .clkdm_name     = "core_l4_clkdm",
2021         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2022         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2023         .recalc         = &followparent_recalc,
2024 };
2025
2026 static struct clk uart2_ick = {
2027         .name           = "uart2_ick",
2028         .parent         = &l4_ck,
2029         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2030         .clkdm_name     = "core_l4_clkdm",
2031         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2032         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2033         .recalc         = &followparent_recalc,
2034 };
2035
2036 static struct clk uart2_fck = {
2037         .name           = "uart2_fck",
2038         .parent         = &func_48m_ck,
2039         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2040         .clkdm_name     = "core_l4_clkdm",
2041         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2042         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static struct clk uart3_ick = {
2047         .name           = "uart3_ick",
2048         .parent         = &l4_ck,
2049         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2050         .clkdm_name     = "core_l4_clkdm",
2051         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2052         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2053         .recalc         = &followparent_recalc,
2054 };
2055
2056 static struct clk uart3_fck = {
2057         .name           = "uart3_fck",
2058         .parent         = &func_48m_ck,
2059         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2060         .clkdm_name     = "core_l4_clkdm",
2061         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2062         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk gpios_ick = {
2067         .name           = "gpios_ick",
2068         .parent         = &l4_ck,
2069         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2070         .clkdm_name     = "core_l4_clkdm",
2071         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2072         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2073         .recalc         = &followparent_recalc,
2074 };
2075
2076 static struct clk gpios_fck = {
2077         .name           = "gpios_fck",
2078         .parent         = &func_32k_ck,
2079         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2080         .clkdm_name     = "wkup_clkdm",
2081         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2082         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2083         .recalc         = &followparent_recalc,
2084 };
2085
2086 static struct clk mpu_wdt_ick = {
2087         .name           = "mpu_wdt_ick",
2088         .parent         = &l4_ck,
2089         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2090         .clkdm_name     = "core_l4_clkdm",
2091         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2092         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2093         .recalc         = &followparent_recalc,
2094 };
2095
2096 static struct clk mpu_wdt_fck = {
2097         .name           = "mpu_wdt_fck",
2098         .parent         = &func_32k_ck,
2099         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2100         .clkdm_name     = "wkup_clkdm",
2101         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2102         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk sync_32k_ick = {
2107         .name           = "sync_32k_ick",
2108         .parent         = &l4_ck,
2109         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2110                                 ENABLE_ON_INIT,
2111         .clkdm_name     = "core_l4_clkdm",
2112         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2113         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk wdt1_ick = {
2118         .name           = "wdt1_ick",
2119         .parent         = &l4_ck,
2120         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2121         .clkdm_name     = "core_l4_clkdm",
2122         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2123         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2124         .recalc         = &followparent_recalc,
2125 };
2126
2127 static struct clk omapctrl_ick = {
2128         .name           = "omapctrl_ick",
2129         .parent         = &l4_ck,
2130         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2131                                 ENABLE_ON_INIT,
2132         .clkdm_name     = "core_l4_clkdm",
2133         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2134         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2135         .recalc         = &followparent_recalc,
2136 };
2137
2138 static struct clk icr_ick = {
2139         .name           = "icr_ick",
2140         .parent         = &l4_ck,
2141         .flags          = CLOCK_IN_OMAP243X,
2142         .clkdm_name     = "core_l4_clkdm",
2143         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2144         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2145         .recalc         = &followparent_recalc,
2146 };
2147
2148 static struct clk cam_ick = {
2149         .name           = "cam_ick",
2150         .parent         = &l4_ck,
2151         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2152         .clkdm_name     = "core_l4_clkdm",
2153         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2154         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 /*
2159  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2160  * split into two separate clocks, since the parent clocks are different
2161  * and the clockdomains are also different.
2162  */
2163 static struct clk cam_fck = {
2164         .name           = "cam_fck",
2165         .parent         = &func_96m_ck,
2166         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2167         .clkdm_name     = "core_l3_clkdm",
2168         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2169         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk mailboxes_ick = {
2174         .name           = "mailboxes_ick",
2175         .parent         = &l4_ck,
2176         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2177         .clkdm_name     = "core_l4_clkdm",
2178         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2179         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk wdt4_ick = {
2184         .name           = "wdt4_ick",
2185         .parent         = &l4_ck,
2186         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2187         .clkdm_name     = "core_l4_clkdm",
2188         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2189         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk wdt4_fck = {
2194         .name           = "wdt4_fck",
2195         .parent         = &func_32k_ck,
2196         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2197         .clkdm_name     = "core_l4_clkdm",
2198         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2199         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk wdt3_ick = {
2204         .name           = "wdt3_ick",
2205         .parent         = &l4_ck,
2206         .flags          = CLOCK_IN_OMAP242X,
2207         .clkdm_name     = "core_l4_clkdm",
2208         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2209         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 static struct clk wdt3_fck = {
2214         .name           = "wdt3_fck",
2215         .parent         = &func_32k_ck,
2216         .flags          = CLOCK_IN_OMAP242X,
2217         .clkdm_name     = "core_l4_clkdm",
2218         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2219         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk mspro_ick = {
2224         .name           = "mspro_ick",
2225         .parent         = &l4_ck,
2226         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2227         .clkdm_name     = "core_l4_clkdm",
2228         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2229         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2230         .recalc         = &followparent_recalc,
2231 };
2232
2233 static struct clk mspro_fck = {
2234         .name           = "mspro_fck",
2235         .parent         = &func_96m_ck,
2236         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2237         .clkdm_name     = "core_l4_clkdm",
2238         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2239         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk mmc_ick = {
2244         .name           = "mmc_ick",
2245         .parent         = &l4_ck,
2246         .flags          = CLOCK_IN_OMAP242X,
2247         .clkdm_name     = "core_l4_clkdm",
2248         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2249         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2250         .recalc         = &followparent_recalc,
2251 };
2252
2253 static struct clk mmc_fck = {
2254         .name           = "mmc_fck",
2255         .parent         = &func_96m_ck,
2256         .flags          = CLOCK_IN_OMAP242X,
2257         .clkdm_name     = "core_l4_clkdm",
2258         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2259         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk fac_ick = {
2264         .name           = "fac_ick",
2265         .parent         = &l4_ck,
2266         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2267         .clkdm_name     = "core_l4_clkdm",
2268         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2269         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk fac_fck = {
2274         .name           = "fac_fck",
2275         .parent         = &func_12m_ck,
2276         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2277         .clkdm_name     = "core_l4_clkdm",
2278         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2279         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk eac_ick = {
2284         .name           = "eac_ick",
2285         .parent         = &l4_ck,
2286         .flags          = CLOCK_IN_OMAP242X,
2287         .clkdm_name     = "core_l4_clkdm",
2288         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2289         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2290         .recalc         = &followparent_recalc,
2291 };
2292
2293 static struct clk eac_fck = {
2294         .name           = "eac_fck",
2295         .parent         = &func_96m_ck,
2296         .flags          = CLOCK_IN_OMAP242X,
2297         .clkdm_name     = "core_l4_clkdm",
2298         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2299         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2300         .recalc         = &followparent_recalc,
2301 };
2302
2303 static struct clk hdq_ick = {
2304         .name           = "hdq_ick",
2305         .parent         = &l4_ck,
2306         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2307         .clkdm_name     = "core_l4_clkdm",
2308         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2309         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2310         .recalc         = &followparent_recalc,
2311 };
2312
2313 static struct clk hdq_fck = {
2314         .name           = "hdq_fck",
2315         .parent         = &func_12m_ck,
2316         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2317         .clkdm_name     = "core_l4_clkdm",
2318         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2319         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2320         .recalc         = &followparent_recalc,
2321 };
2322
2323 static struct clk i2c2_ick = {
2324         .name           = "i2c_ick",
2325         .id             = 2,
2326         .parent         = &l4_ck,
2327         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2328         .clkdm_name     = "core_l4_clkdm",
2329         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2330         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2331         .recalc         = &followparent_recalc,
2332 };
2333
2334 static struct clk i2c2_fck = {
2335         .name           = "i2c_fck",
2336         .id             = 2,
2337         .parent         = &func_12m_ck,
2338         .flags          = CLOCK_IN_OMAP242X,
2339         .clkdm_name     = "core_l4_clkdm",
2340         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2341         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2342         .recalc         = &followparent_recalc,
2343 };
2344
2345 static struct clk i2chs2_fck = {
2346         .name           = "i2chs_fck",
2347         .id             = 2,
2348         .parent         = &func_96m_ck,
2349         .flags          = CLOCK_IN_OMAP243X,
2350         .clkdm_name     = "core_l4_clkdm",
2351         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2352         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2353         .recalc         = &followparent_recalc,
2354 };
2355
2356 static struct clk i2c1_ick = {
2357         .name           = "i2c_ick",
2358         .id             = 1,
2359         .parent         = &l4_ck,
2360         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2361         .clkdm_name     = "core_l4_clkdm",
2362         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2363         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2364         .recalc         = &followparent_recalc,
2365 };
2366
2367 static struct clk i2c1_fck = {
2368         .name           = "i2c_fck",
2369         .id             = 1,
2370         .parent         = &func_12m_ck,
2371         .flags          = CLOCK_IN_OMAP242X,
2372         .clkdm_name     = "core_l4_clkdm",
2373         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2374         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2375         .recalc         = &followparent_recalc,
2376 };
2377
2378 static struct clk i2chs1_fck = {
2379         .name           = "i2chs_fck",
2380         .id             = 1,
2381         .parent         = &func_96m_ck,
2382         .flags          = CLOCK_IN_OMAP243X,
2383         .clkdm_name     = "core_l4_clkdm",
2384         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2385         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2386         .recalc         = &followparent_recalc,
2387 };
2388
2389 static struct clk gpmc_fck = {
2390         .name           = "gpmc_fck",
2391         .parent         = &core_l3_ck,
2392         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2393                                 ENABLE_ON_INIT,
2394         .clkdm_name     = "core_l3_clkdm",
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static struct clk sdma_fck = {
2399         .name           = "sdma_fck",
2400         .parent         = &core_l3_ck,
2401         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2402         .clkdm_name     = "core_l3_clkdm",
2403         .recalc         = &followparent_recalc,
2404 };
2405
2406 static struct clk sdma_ick = {
2407         .name           = "sdma_ick",
2408         .parent         = &l4_ck,
2409         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2410         .clkdm_name     = "core_l3_clkdm",
2411         .recalc         = &followparent_recalc,
2412 };
2413
2414 static struct clk vlynq_ick = {
2415         .name           = "vlynq_ick",
2416         .parent         = &core_l3_ck,
2417         .flags          = CLOCK_IN_OMAP242X,
2418         .clkdm_name     = "core_l3_clkdm",
2419         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2420         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2421         .recalc         = &followparent_recalc,
2422 };
2423
2424 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2425         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2426         { .div = 0 }
2427 };
2428
2429 static const struct clksel_rate vlynq_fck_core_rates[] = {
2430         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2431         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2432         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2433         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2434         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2435         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2436         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2437         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2438         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2439         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2440         { .div = 0 }
2441 };
2442
2443 static const struct clksel vlynq_fck_clksel[] = {
2444         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2445         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2446         { .parent = NULL }
2447 };
2448
2449 static struct clk vlynq_fck = {
2450         .name           = "vlynq_fck",
2451         .parent         = &func_96m_ck,
2452         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2453         .clkdm_name     = "core_l3_clkdm",
2454         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2455         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2456         .init           = &omap2_init_clksel_parent,
2457         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
2458         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2459         .clksel         = vlynq_fck_clksel,
2460         .recalc         = &omap2_clksel_recalc,
2461         .round_rate     = &omap2_clksel_round_rate,
2462         .set_rate       = &omap2_clksel_set_rate
2463 };
2464
2465 static struct clk sdrc_ick = {
2466         .name           = "sdrc_ick",
2467         .parent         = &l4_ck,
2468         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2469         .clkdm_name     = "core_l4_clkdm",
2470         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
2471         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2472         .recalc         = &followparent_recalc,
2473 };
2474
2475 static struct clk des_ick = {
2476         .name           = "des_ick",
2477         .parent         = &l4_ck,
2478         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2479         .clkdm_name     = "core_l4_clkdm",
2480         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2481         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2482         .recalc         = &followparent_recalc,
2483 };
2484
2485 static struct clk sha_ick = {
2486         .name           = "sha_ick",
2487         .parent         = &l4_ck,
2488         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2489         .clkdm_name     = "core_l4_clkdm",
2490         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2491         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2492         .recalc         = &followparent_recalc,
2493 };
2494
2495 static struct clk rng_ick = {
2496         .name           = "rng_ick",
2497         .parent         = &l4_ck,
2498         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2499         .clkdm_name     = "core_l4_clkdm",
2500         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2501         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2502         .recalc         = &followparent_recalc,
2503 };
2504
2505 static struct clk aes_ick = {
2506         .name           = "aes_ick",
2507         .parent         = &l4_ck,
2508         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2509         .clkdm_name     = "core_l4_clkdm",
2510         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2511         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2512         .recalc         = &followparent_recalc,
2513 };
2514
2515 static struct clk pka_ick = {
2516         .name           = "pka_ick",
2517         .parent         = &l4_ck,
2518         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2519         .clkdm_name     = "core_l4_clkdm",
2520         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2521         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2522         .recalc         = &followparent_recalc,
2523 };
2524
2525 static struct clk usb_fck = {
2526         .name           = "usb_fck",
2527         .parent         = &func_48m_ck,
2528         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2529         .clkdm_name     = "core_l3_clkdm",
2530         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2531         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2532         .recalc         = &followparent_recalc,
2533 };
2534
2535 static struct clk usbhs_ick = {
2536         .name           = "usbhs_ick",
2537         .parent         = &core_l3_ck,
2538         .flags          = CLOCK_IN_OMAP243X,
2539         .clkdm_name     = "core_l3_clkdm",
2540         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2541         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2542         .recalc         = &followparent_recalc,
2543 };
2544
2545 static struct clk mmchs1_ick = {
2546         .name           = "mmchs_ick",
2547         .id             = 1,
2548         .parent         = &l4_ck,
2549         .flags          = CLOCK_IN_OMAP243X,
2550         .clkdm_name     = "core_l4_clkdm",
2551         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2552         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2553         .recalc         = &followparent_recalc,
2554 };
2555
2556 static struct clk mmchs1_fck = {
2557         .name           = "mmchs_fck",
2558         .id             = 1,
2559         .parent         = &func_96m_ck,
2560         .flags          = CLOCK_IN_OMAP243X,
2561         .clkdm_name     = "core_l3_clkdm",
2562         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2563         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2564         .recalc         = &followparent_recalc,
2565 };
2566
2567 static struct clk mmchs2_ick = {
2568         .name           = "mmchs_ick",
2569         .id             = 2,
2570         .parent         = &l4_ck,
2571         .flags          = CLOCK_IN_OMAP243X,
2572         .clkdm_name     = "core_l4_clkdm",
2573         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2574         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2575         .recalc         = &followparent_recalc,
2576 };
2577
2578 static struct clk mmchs2_fck = {
2579         .name           = "mmchs_fck",
2580         .id             = 2,
2581         .parent         = &func_96m_ck,
2582         .flags          = CLOCK_IN_OMAP243X,
2583         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2584         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2585         .recalc         = &followparent_recalc,
2586 };
2587
2588 static struct clk gpio5_ick = {
2589         .name           = "gpio5_ick",
2590         .parent         = &l4_ck,
2591         .flags          = CLOCK_IN_OMAP243X,
2592         .clkdm_name     = "core_l4_clkdm",
2593         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2594         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2595         .recalc         = &followparent_recalc,
2596 };
2597
2598 static struct clk gpio5_fck = {
2599         .name           = "gpio5_fck",
2600         .parent         = &func_32k_ck,
2601         .flags          = CLOCK_IN_OMAP243X,
2602         .clkdm_name     = "core_l4_clkdm",
2603         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2604         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2605         .recalc         = &followparent_recalc,
2606 };
2607
2608 static struct clk mdm_intc_ick = {
2609         .name           = "mdm_intc_ick",
2610         .parent         = &l4_ck,
2611         .flags          = CLOCK_IN_OMAP243X,
2612         .clkdm_name     = "core_l4_clkdm",
2613         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2614         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk mmchsdb1_fck = {
2619         .name           = "mmchsdb_fck",
2620         .id             = 1,
2621         .parent         = &func_32k_ck,
2622         .flags          = CLOCK_IN_OMAP243X,
2623         .clkdm_name     = "core_l4_clkdm",
2624         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2625         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2626         .recalc         = &followparent_recalc,
2627 };
2628
2629 static struct clk mmchsdb2_fck = {
2630         .name           = "mmchsdb_fck",
2631         .id             = 2,
2632         .parent         = &func_32k_ck,
2633         .flags          = CLOCK_IN_OMAP243X,
2634         .clkdm_name     = "core_l4_clkdm",
2635         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2636         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2637         .recalc         = &followparent_recalc,
2638 };
2639
2640 /*
2641  * This clock is a composite clock which does entire set changes then
2642  * forces a rebalance. It keys on the MPU speed, but it really could
2643  * be any key speed part of a set in the rate table.
2644  *
2645  * to really change a set, you need memory table sets which get changed
2646  * in sram, pre-notifiers & post notifiers, changing the top set, without
2647  * having low level display recalc's won't work... this is why dpm notifiers
2648  * work, isr's off, walk a list of clocks already _off_ and not messing with
2649  * the bus.
2650  *
2651  * This clock should have no parent. It embodies the entire upper level
2652  * active set. A parent will mess up some of the init also.
2653  */
2654 static struct clk virt_prcm_set = {
2655         .name           = "virt_prcm_set",
2656         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2657                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2658         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2659         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2660         .set_rate       = &omap2_select_table_rate,
2661         .round_rate     = &omap2_round_to_table_rate,
2662 };
2663
2664 static struct clk *onchip_24xx_clks[] __initdata = {
2665         /* external root sources */
2666         &func_32k_ck,
2667         &osc_ck,
2668         &sys_ck,
2669         &alt_ck,
2670         /* internal analog sources */
2671         &dpll_ck,
2672         &apll96_ck,
2673         &apll54_ck,
2674         /* internal prcm root sources */
2675         &func_54m_ck,
2676         &core_ck,
2677         &func_96m_ck,
2678         &func_48m_ck,
2679         &func_12m_ck,
2680         &wdt1_osc_ck,
2681         &sys_clkout_src,
2682         &sys_clkout,
2683         &sys_clkout2_src,
2684         &sys_clkout2,
2685         &emul_ck,
2686         /* mpu domain clocks */
2687         &mpu_ck,
2688         /* dsp domain clocks */
2689         &dsp_fck,
2690         &dsp_irate_ick,
2691         &dsp_ick,               /* 242x */
2692         &iva2_1_ick,            /* 243x */
2693         &iva1_ifck,             /* 242x */
2694         &iva1_mpu_int_ifck,     /* 242x */
2695         /* GFX domain clocks */
2696         &gfx_3d_fck,
2697         &gfx_2d_fck,
2698         &gfx_ick,
2699         /* Modem domain clocks */
2700         &mdm_ick,
2701         &mdm_osc_ck,
2702         /* DSS domain clocks */
2703         &dss_ick,
2704         &dss1_fck,
2705         &dss2_fck,
2706         &dss_54m_fck,
2707         /* L3 domain clocks */
2708         &core_l3_ck,
2709         &ssi_ssr_sst_fck,
2710         &usb_l4_ick,
2711         /* L4 domain clocks */
2712         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2713         &ssi_l4_ick,
2714         /* virtual meta-group clock */
2715         &virt_prcm_set,
2716         /* general l4 interface ck, multi-parent functional clk */
2717         &gpt1_ick,
2718         &gpt1_fck,
2719         &gpt2_ick,
2720         &gpt2_fck,
2721         &gpt3_ick,
2722         &gpt3_fck,
2723         &gpt4_ick,
2724         &gpt4_fck,
2725         &gpt5_ick,
2726         &gpt5_fck,
2727         &gpt6_ick,
2728         &gpt6_fck,
2729         &gpt7_ick,
2730         &gpt7_fck,
2731         &gpt8_ick,
2732         &gpt8_fck,
2733         &gpt9_ick,
2734         &gpt9_fck,
2735         &gpt10_ick,
2736         &gpt10_fck,
2737         &gpt11_ick,
2738         &gpt11_fck,
2739         &gpt12_ick,
2740         &gpt12_fck,
2741         &mcbsp1_ick,
2742         &mcbsp1_fck,
2743         &mcbsp2_ick,
2744         &mcbsp2_fck,
2745         &mcbsp3_ick,
2746         &mcbsp3_fck,
2747         &mcbsp4_ick,
2748         &mcbsp4_fck,
2749         &mcbsp5_ick,
2750         &mcbsp5_fck,
2751         &mcspi1_ick,
2752         &mcspi1_fck,
2753         &mcspi2_ick,
2754         &mcspi2_fck,
2755         &mcspi3_ick,
2756         &mcspi3_fck,
2757         &uart1_ick,
2758         &uart1_fck,
2759         &uart2_ick,
2760         &uart2_fck,
2761         &uart3_ick,
2762         &uart3_fck,
2763         &gpios_ick,
2764         &gpios_fck,
2765         &mpu_wdt_ick,
2766         &mpu_wdt_fck,
2767         &sync_32k_ick,
2768         &wdt1_ick,
2769         &omapctrl_ick,
2770         &icr_ick,
2771         &cam_fck,
2772         &cam_ick,
2773         &mailboxes_ick,
2774         &wdt4_ick,
2775         &wdt4_fck,
2776         &wdt3_ick,
2777         &wdt3_fck,
2778         &mspro_ick,
2779         &mspro_fck,
2780         &mmc_ick,
2781         &mmc_fck,
2782         &fac_ick,
2783         &fac_fck,
2784         &eac_ick,
2785         &eac_fck,
2786         &hdq_ick,
2787         &hdq_fck,
2788         &i2c1_ick,
2789         &i2c1_fck,
2790         &i2chs1_fck,
2791         &i2c2_ick,
2792         &i2c2_fck,
2793         &i2chs2_fck,
2794         &gpmc_fck,
2795         &sdma_fck,
2796         &sdma_ick,
2797         &vlynq_ick,
2798         &vlynq_fck,
2799         &sdrc_ick,
2800         &des_ick,
2801         &sha_ick,
2802         &rng_ick,
2803         &aes_ick,
2804         &pka_ick,
2805         &usb_fck,
2806         &usbhs_ick,
2807         &mmchs1_ick,
2808         &mmchs1_fck,
2809         &mmchs2_ick,
2810         &mmchs2_fck,
2811         &gpio5_ick,
2812         &gpio5_fck,
2813         &mdm_intc_ick,
2814         &mmchsdb1_fck,
2815         &mmchsdb2_fck,
2816 };
2817
2818 #endif
2819