arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*
 604  * Since 2420 and 2430 have different cm_base, we use offsets only here.
 605  * Clock code will rewrite the register address as needed.
 606  */
 607 #define _CM_REG_OFFSET(module, reg)                             \
 608                         ((__force void __iomem *)(module) + (reg))
 609 #define _GR_MOD_OFFSET(reg)                                     \
 610                         ((__force void __iomem *)(OMAP24XX_GR_MOD + (reg)))
 611
 612 /*-------------------------------------------------------------------------
 613  * 24xx clock tree.
 614  *
 615  * NOTE:In many cases here we are assigning a 'default' parent. In many
 616  *      cases the parent is selectable. The get/set parent calls will also
 617  *      switch sources.
 618  *
 619  *      Many some clocks say always_enabled, but they can be auto idled for
 620  *      power savings. They will always be available upon clock request.
 621  *
 622  *      Several sources are given initial rates which may be wrong, this will
 623  *      be fixed up in the init func.
 624  *
 625  *      Things are broadly separated below by clock domains. It is
 626  *      noteworthy that most periferals have dependencies on multiple clock
 627  *      domains. Many get their interface clocks from the L4 domain, but get
 628  *      functional clocks from fixed sources or other core domain derived
 629  *      clocks.
 630  *-------------------------------------------------------------------------*/
 631
 632 /* Base external input clocks */
 633 static struct clk func_32k_ck = {
 634         .name           = "func_32k_ck",
 635         .rate           = 32000,
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 638         .clkdm          = { .name = "prm_clkdm" },
 639         .recalc         = &propagate_rate,
 640 };
 641
 642 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 643 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 644         .name           = "osc_ck",
 645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 646                                 RATE_PROPAGATES,
 647         .clkdm          = { .name = "prm_clkdm" },
 648         .enable         = &omap2_enable_osc_ck,
 649         .disable        = &omap2_disable_osc_ck,
 650         .recalc         = &omap2_osc_clk_recalc,
 651 };
 652
 653 /* Without modem likely 12MHz, with modem likely 13MHz */
 654 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 655         .name           = "sys_ck",             /* ~ ref_clk also */
 656         .parent         = &osc_ck,
 657         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 658                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 659         .clkdm          = { .name = "prm_clkdm" },
 660         .recalc         = &omap2_sys_clk_recalc,
 661 };
 662
 663 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 664         .name           = "alt_ck",
 665         .rate           = 54000000,
 666         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 667                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 668         .clkdm          = { .name = "prm_clkdm" },
 669         .recalc         = &propagate_rate,
 670 };
 671
 672 /*
 673  * Analog domain root source clocks
 674  */
 675
 676 /* dpll_ck, is broken out in to special cases through clksel */
 677 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 678  * deal with this
 679  */
 680
 681 static struct dpll_data dpll_dd = {
 682         .mult_div1_reg          = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 683         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 684         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 685         .max_multiplier         = 1024,
 686         .max_divider            = 16,
 687         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 688 };
 689
 690 /*
 691  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 692  * not just a DPLL
 693  */
 694 static struct clk dpll_ck = {
 695         .name           = "dpll_ck",
 696         .parent         = &sys_ck,              /* Can be func_32k also */
 697         .dpll_data      = &dpll_dd,
 698         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 699                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 700         .clkdm          = { .name = "prm_clkdm" },
 701         .recalc         = &omap2_dpllcore_recalc,
 702         .set_rate       = &omap2_reprogram_dpllcore,
 703 };
 704
 705 static struct clk apll96_ck = {
 706         .name           = "apll96_ck",
 707         .parent         = &sys_ck,
 708         .rate           = 96000000,
 709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 710                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 711         .clkdm          = { .name = "prm_clkdm" },
 712         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 713         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 714         .enable         = &omap2_clk_fixed_enable,
 715         .disable        = &omap2_clk_fixed_disable,
 716         .recalc         = &propagate_rate,
 717 };
 718
 719 static struct clk apll54_ck = {
 720         .name           = "apll54_ck",
 721         .parent         = &sys_ck,
 722         .rate           = 54000000,
 723         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 724                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 725         .clkdm          = { .name = "prm_clkdm" },
 726         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 727         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 728         .enable         = &omap2_clk_fixed_enable,
 729         .disable        = &omap2_clk_fixed_disable,
 730         .recalc         = &propagate_rate,
 731 };
 732
 733 /*
 734  * PRCM digital base sources
 735  */
 736
 737 /* func_54m_ck */
 738
 739 static const struct clksel_rate func_54m_apll54_rates[] = {
 740         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 741         { .div = 0 },
 742 };
 743
 744 static const struct clksel_rate func_54m_alt_rates[] = {
 745         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 746         { .div = 0 },
 747 };
 748
 749 static const struct clksel func_54m_clksel[] = {
 750         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 751         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 752         { .parent = NULL },
 753 };
 754
 755 static struct clk func_54m_ck = {
 756         .name           = "func_54m_ck",
 757         .parent         = &apll54_ck,   /* can also be alt_clk */
 758         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 759                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 760         .clkdm          = { .name = "cm_clkdm" },
 761         .init           = &omap2_init_clksel_parent,
 762         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 763         .clksel_mask    = OMAP24XX_54M_SOURCE,
 764         .clksel         = func_54m_clksel,
 765         .recalc         = &omap2_clksel_recalc,
 766 };
 767
 768 static struct clk core_ck = {
 769         .name           = "core_ck",
 770         .parent         = &dpll_ck,             /* can also be 32k */
 771         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 772                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 773         .clkdm          = { .name = "cm_clkdm" },
 774         .recalc         = &followparent_recalc,
 775 };
 776
 777 /* func_96m_ck */
 778 static const struct clksel_rate func_96m_apll96_rates[] = {
 779         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 780         { .div = 0 },
 781 };
 782
 783 static const struct clksel_rate func_96m_alt_rates[] = {
 784         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 785         { .div = 0 },
 786 };
 787
 788 static const struct clksel func_96m_clksel[] = {
 789         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 790         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 791         { .parent = NULL }
 792 };
 793
 794 /* The parent of this clock is not selectable on 2420. */
 795 static struct clk func_96m_ck = {
 796         .name           = "func_96m_ck",
 797         .parent         = &apll96_ck,
 798         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 799                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 800         .clkdm          = { .name = "cm_clkdm" },
 801         .init           = &omap2_init_clksel_parent,
 802         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 803         .clksel_mask    = OMAP2430_96M_SOURCE,
 804         .clksel         = func_96m_clksel,
 805         .recalc         = &omap2_clksel_recalc,
 806         .round_rate     = &omap2_clksel_round_rate,
 807         .set_rate       = &omap2_clksel_set_rate
 808 };
 809
 810 /* func_48m_ck */
 811
 812 static const struct clksel_rate func_48m_apll96_rates[] = {
 813         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 814         { .div = 0 },
 815 };
 816
 817 static const struct clksel_rate func_48m_alt_rates[] = {
 818         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 819         { .div = 0 },
 820 };
 821
 822 static const struct clksel func_48m_clksel[] = {
 823         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 824         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 825         { .parent = NULL }
 826 };
 827
 828 static struct clk func_48m_ck = {
 829         .name           = "func_48m_ck",
 830         .parent         = &apll96_ck,    /* 96M or Alt */
 831         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 832                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 833         .clkdm          = { .name = "cm_clkdm" },
 834         .init           = &omap2_init_clksel_parent,
 835         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 836         .clksel_mask    = OMAP24XX_48M_SOURCE,
 837         .clksel         = func_48m_clksel,
 838         .recalc         = &omap2_clksel_recalc,
 839         .round_rate     = &omap2_clksel_round_rate,
 840         .set_rate       = &omap2_clksel_set_rate
 841 };
 842
 843 static struct clk func_12m_ck = {
 844         .name           = "func_12m_ck",
 845         .parent         = &func_48m_ck,
 846         .fixed_div      = 4,
 847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 848                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 849         .clkdm          = { .name = "cm_clkdm" },
 850         .recalc         = &omap2_fixed_divisor_recalc,
 851 };
 852
 853 /* Secure timer, only available in secure mode */
 854 static struct clk wdt1_osc_ck = {
 855         .name           = "wdt1_osc_ck",
 856         .parent         = &osc_ck,
 857         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 858         .clkdm          = { .name = "prm_clkdm" },
 859         .recalc         = &followparent_recalc,
 860 };
 861
 862 /*
 863  * The common_clkout* clksel_rate structs are common to
 864  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 865  * sys_clkout2_* are 2420-only, so the
 866  * clksel_rate flags fields are inaccurate for those clocks. This is
 867  * harmless since access to those clocks are gated by the struct clk
 868  * flags fields, which mark them as 2420-only.
 869  */
 870 static const struct clksel_rate common_clkout_src_core_rates[] = {
 871         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 872         { .div = 0 }
 873 };
 874
 875 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 876         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 877         { .div = 0 }
 878 };
 879
 880 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 881         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 882         { .div = 0 }
 883 };
 884
 885 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 886         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 887         { .div = 0 }
 888 };
 889
 890 static const struct clksel common_clkout_src_clksel[] = {
 891         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 892         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 893         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 894         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 895         { .parent = NULL }
 896 };
 897
 898 static struct clk sys_clkout_src = {
 899         .name           = "sys_clkout_src",
 900         .parent         = &func_54m_ck,
 901         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 902                                 RATE_PROPAGATES | OFFSET_GR_MOD,
 903         .clkdm          = { .name = "prm_clkdm" },
 904         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 905         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 906         .init           = &omap2_init_clksel_parent,
 907         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 908         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 909         .clksel         = common_clkout_src_clksel,
 910         .recalc         = &omap2_clksel_recalc,
 911         .round_rate     = &omap2_clksel_round_rate,
 912         .set_rate       = &omap2_clksel_set_rate
 913 };
 914
 915 static const struct clksel_rate common_clkout_rates[] = {
 916         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 917         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 918         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 919         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 920         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 921         { .div = 0 },
 922 };
 923
 924 static const struct clksel sys_clkout_clksel[] = {
 925         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 926         { .parent = NULL }
 927 };
 928
 929 static struct clk sys_clkout = {
 930         .name           = "sys_clkout",
 931         .parent         = &sys_clkout_src,
 932         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 933                                 PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
 934         .clkdm          = { .name = "prm_clkdm" },
 935         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 936         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 937         .clksel         = sys_clkout_clksel,
 938         .recalc         = &omap2_clksel_recalc,
 939         .round_rate     = &omap2_clksel_round_rate,
 940         .set_rate       = &omap2_clksel_set_rate
 941 };
 942
 943 /* In 2430, new in 2420 ES2 */
 944 static struct clk sys_clkout2_src = {
 945         .name           = "sys_clkout2_src",
 946         .parent         = &func_54m_ck,
 947         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
 948         .clkdm          = { .name = "cm_clkdm" },
 949         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 950         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 951         .init           = &omap2_init_clksel_parent,
 952         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 953         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 954         .clksel         = common_clkout_src_clksel,
 955         .recalc         = &omap2_clksel_recalc,
 956         .round_rate     = &omap2_clksel_round_rate,
 957         .set_rate       = &omap2_clksel_set_rate
 958 };
 959
 960 static const struct clksel sys_clkout2_clksel[] = {
 961         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 962         { .parent = NULL }
 963 };
 964
 965 /* In 2430, new in 2420 ES2 */
 966 static struct clk sys_clkout2 = {
 967         .name           = "sys_clkout2",
 968         .parent         = &sys_clkout2_src,
 969         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
 970                                 OFFSET_GR_MOD,
 971         .clkdm          = { .name = "cm_clkdm" },
 972         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 973         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 974         .clksel         = sys_clkout2_clksel,
 975         .recalc         = &omap2_clksel_recalc,
 976         .round_rate     = &omap2_clksel_round_rate,
 977         .set_rate       = &omap2_clksel_set_rate
 978 };
 979
 980 static struct clk emul_ck = {
 981         .name           = "emul_ck",
 982         .parent         = &func_54m_ck,
 983         .flags          = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
 984         .clkdm          = { .name = "cm_clkdm" },
 985         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
 986         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 987         .recalc         = &followparent_recalc,
 988
 989 };
 990
 991 /*
 992  * MPU clock domain
 993  *      Clocks:
 994  *              MPU_FCLK, MPU_ICLK
 995  *              INT_M_FCLK, INT_M_I_CLK
 996  *
 997  * - Individual clocks are hardware managed.
 998  * - Base divider comes from: CM_CLKSEL_MPU
 999  *
1000  */
1001 static const struct clksel_rate mpu_core_rates[] = {
1002         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1003         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1004         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1005         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1006         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1007         { .div = 0 },
1008 };
1009
1010 static const struct clksel mpu_clksel[] = {
1011         { .parent = &core_ck, .rates = mpu_core_rates },
1012         { .parent = NULL }
1013 };
1014
1015 static struct clk mpu_ck = {    /* Control cpu */
1016         .name           = "mpu_ck",
1017         .parent         = &core_ck,
1018         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1019                                 ALWAYS_ENABLED | DELAYED_APP |
1020                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1021         .clkdm          = { .name = "mpu_clkdm" },
1022         .init           = &omap2_init_clksel_parent,
1023         .clksel_reg     = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL),
1024         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1025         .clksel         = mpu_clksel,
1026         .recalc         = &omap2_clksel_recalc,
1027         .round_rate     = &omap2_clksel_round_rate,
1028         .set_rate       = &omap2_clksel_set_rate
1029 };
1030
1031 /*
1032  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1033  * Clocks:
1034  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1035  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1036  *
1037  * Won't be too specific here. The core clock comes into this block
1038  * it is divided then tee'ed. One branch goes directly to xyz enable
1039  * controls. The other branch gets further divided by 2 then possibly
1040  * routed into a synchronizer and out of clocks abc.
1041  */
1042 static const struct clksel_rate dsp_fck_core_rates[] = {
1043         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1044         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1045         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1046         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1047         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1048         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1049         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1050         { .div = 0 },
1051 };
1052
1053 static const struct clksel dsp_fck_clksel[] = {
1054         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1055         { .parent = NULL }
1056 };
1057
1058 static struct clk dsp_fck = {
1059         .name           = "dsp_fck",
1060         .parent         = &core_ck,
1061         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1062                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1063         .clkdm          = { .name = "dsp_clkdm" },
1064         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1065         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1066         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1067         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1068         .clksel         = dsp_fck_clksel,
1069         .recalc         = &omap2_clksel_recalc,
1070         .round_rate     = &omap2_clksel_round_rate,
1071         .set_rate       = &omap2_clksel_set_rate
1072 };
1073
1074 /* DSP interface clock */
1075 static const struct clksel_rate dsp_irate_ick_rates[] = {
1076         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1077         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1078         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1079         { .div = 0 },
1080 };
1081
1082 static const struct clksel dsp_irate_ick_clksel[] = {
1083         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1084         { .parent = NULL }
1085 };
1086
1087 /* This clock does not exist as such in the TRM. */
1088 static struct clk dsp_irate_ick = {
1089         .name           = "dsp_irate_ick",
1090         .parent         = &dsp_fck,
1091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1092                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1093         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1094         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1095         .clksel         = dsp_irate_ick_clksel,
1096         .recalc         = &omap2_clksel_recalc,
1097         .round_rate     = &omap2_clksel_round_rate,
1098         .set_rate             = &omap2_clksel_set_rate
1099 };
1100
1101 /* 2420 only */
1102 static struct clk dsp_ick = {
1103         .name           = "dsp_ick",     /* apparently ipi and isp */
1104         .parent         = &dsp_irate_ick,
1105         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1106         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
1107         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1108 };
1109
1110 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1111 static struct clk iva2_1_ick = {
1112         .name           = "iva2_1_ick",
1113         .parent         = &dsp_irate_ick,
1114         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1115         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1116         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1117 };
1118
1119 /*
1120  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1121  * the C54x, but which is contained in the DSP powerdomain.  Does not
1122  * exist on later OMAPs.
1123  */
1124 static struct clk iva1_ifck = {
1125         .name           = "iva1_ifck",
1126         .parent         = &core_ck,
1127         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1128                                 RATE_PROPAGATES | DELAYED_APP,
1129         .clkdm          = { .name = "iva1_clkdm" },
1130         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1131         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1132         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1133         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1134         .clksel         = dsp_fck_clksel,
1135         .recalc         = &omap2_clksel_recalc,
1136         .round_rate     = &omap2_clksel_round_rate,
1137         .set_rate       = &omap2_clksel_set_rate
1138 };
1139
1140 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1141 static struct clk iva1_mpu_int_ifck = {
1142         .name           = "iva1_mpu_int_ifck",
1143         .parent         = &iva1_ifck,
1144         .flags          = CLOCK_IN_OMAP242X,
1145         .clkdm          = { .name = "iva1_clkdm" },
1146         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1147         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1148         .fixed_div      = 2,
1149         .recalc         = &omap2_fixed_divisor_recalc,
1150 };
1151
1152 /*
1153  * L3 clock domain
1154  * L3 clocks are used for both interface and functional clocks to
1155  * multiple entities. Some of these clocks are completely managed
1156  * by hardware, and some others allow software control. Hardware
1157  * managed ones general are based on directly CLK_REQ signals and
1158  * various auto idle settings. The functional spec sets many of these
1159  * as 'tie-high' for their enables.
1160  *
1161  * I-CLOCKS:
1162  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1163  *      CAM, HS-USB.
1164  * F-CLOCK
1165  *      SSI.
1166  *
1167  * GPMC memories and SDRC have timing and clock sensitive registers which
1168  * may very well need notification when the clock changes. Currently for low
1169  * operating points, these are taken care of in sleep.S.
1170  */
1171 static const struct clksel_rate core_l3_core_rates[] = {
1172         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1173         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1174         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1175         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1176         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1177         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1178         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1179         { .div = 0 }
1180 };
1181
1182 static const struct clksel core_l3_clksel[] = {
1183         { .parent = &core_ck, .rates = core_l3_core_rates },
1184         { .parent = NULL }
1185 };
1186
1187 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1188         .name           = "core_l3_ck",
1189         .parent         = &core_ck,
1190         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1191                                 ALWAYS_ENABLED | DELAYED_APP |
1192                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1193         .clkdm          = { .name = "core_l3_clkdm" },
1194         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1195         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1196         .clksel         = core_l3_clksel,
1197         .recalc         = &omap2_clksel_recalc,
1198         .round_rate     = &omap2_clksel_round_rate,
1199         .set_rate       = &omap2_clksel_set_rate
1200 };
1201
1202 /* usb_l4_ick */
1203 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1204         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1205         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1206         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1207         { .div = 0 }
1208 };
1209
1210 static const struct clksel usb_l4_ick_clksel[] = {
1211         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1212         { .parent = NULL },
1213 };
1214
1215 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1216 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1217         .name           = "usb_l4_ick",
1218         .parent         = &core_l3_ck,
1219         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1220                                 DELAYED_APP | CONFIG_PARTICIPANT,
1221         .clkdm          = { .name = "core_l4_clkdm" },
1222         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1223         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1224         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1225         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1226         .clksel         = usb_l4_ick_clksel,
1227         .recalc         = &omap2_clksel_recalc,
1228         .round_rate     = &omap2_clksel_round_rate,
1229         .set_rate       = &omap2_clksel_set_rate
1230 };
1231
1232 /*
1233  * L4 clock management domain
1234  *
1235  * This domain contains lots of interface clocks from the L4 interface, some
1236  * functional clocks.   Fixed APLL functional source clocks are managed in
1237  * this domain.
1238  */
1239 static const struct clksel_rate l4_core_l3_rates[] = {
1240         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1241         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1242         { .div = 0 }
1243 };
1244
1245 static const struct clksel l4_clksel[] = {
1246         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1247         { .parent = NULL }
1248 };
1249
1250 static struct clk l4_ck = {             /* used both as an ick and fck */
1251         .name           = "l4_ck",
1252         .parent         = &core_l3_ck,
1253         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1254                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1255         .clkdm          = { .name = "core_l4_clkdm" },
1256         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1257         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1258         .clksel         = l4_clksel,
1259         .recalc         = &omap2_clksel_recalc,
1260         .round_rate     = &omap2_clksel_round_rate,
1261         .set_rate       = &omap2_clksel_set_rate
1262 };
1263
1264 /*
1265  * SSI is in L3 management domain, its direct parent is core not l3,
1266  * many core power domain entities are grouped into the L3 clock
1267  * domain.
1268  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1269  *
1270  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1271  */
1272 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1273         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1274         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1275         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1276         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1277         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1278         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1279         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1280         { .div = 0 }
1281 };
1282
1283 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1284         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1285         { .parent = NULL }
1286 };
1287
1288 static struct clk ssi_ssr_sst_fck = {
1289         .name           = "ssi_fck",
1290         .parent         = &core_ck,
1291         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1292                                 DELAYED_APP,
1293         .clkdm          = { .name = "core_l3_clkdm" },
1294         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1295         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1296         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1297         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1298         .clksel         = ssi_ssr_sst_fck_clksel,
1299         .recalc         = &omap2_clksel_recalc,
1300         .round_rate     = &omap2_clksel_round_rate,
1301         .set_rate       = &omap2_clksel_set_rate
1302 };
1303
1304 /*
1305  * Presumably this is the same as SSI_ICLK.
1306  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1307  */
1308 static struct clk ssi_l4_ick = {
1309         .name           = "ssi_l4_ick",
1310         .parent         = &l4_ck,
1311         .clkdm          = { .name = "core_l4_clkdm" },
1312         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1313         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1314         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1315         .recalc         = &followparent_recalc,
1316 };
1317
1318
1319 /*
1320  * GFX clock domain
1321  *      Clocks:
1322  * GFX_FCLK, GFX_ICLK
1323  * GFX_CG1(2d), GFX_CG2(3d)
1324  *
1325  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1326  * The 2d and 3d clocks run at a hardware determined
1327  * divided value of fclk.
1328  *
1329  */
1330 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1331
1332 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1333 static const struct clksel gfx_fck_clksel[] = {
1334         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1335         { .parent = NULL },
1336 };
1337
1338 static struct clk gfx_3d_fck = {
1339         .name           = "gfx_3d_fck",
1340         .parent         = &core_l3_ck,
1341         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1342         .clkdm          = { .name = "gfx_clkdm" },
1343         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1344         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1345         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1346         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1347         .clksel         = gfx_fck_clksel,
1348         .recalc         = &omap2_clksel_recalc,
1349         .round_rate     = &omap2_clksel_round_rate,
1350         .set_rate       = &omap2_clksel_set_rate
1351 };
1352
1353 static struct clk gfx_2d_fck = {
1354         .name           = "gfx_2d_fck",
1355         .parent         = &core_l3_ck,
1356         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1357         .clkdm          = { .name = "gfx_clkdm" },
1358         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1359         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1360         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1361         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1362         .clksel         = gfx_fck_clksel,
1363         .recalc         = &omap2_clksel_recalc,
1364         .round_rate     = &omap2_clksel_round_rate,
1365         .set_rate       = &omap2_clksel_set_rate
1366 };
1367
1368 static struct clk gfx_ick = {
1369         .name           = "gfx_ick",            /* From l3 */
1370         .parent         = &core_l3_ck,
1371         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1372         .clkdm          = { .name = "gfx_clkdm" },
1373         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
1374         .enable_bit     = OMAP_EN_GFX_SHIFT,
1375         .recalc         = &followparent_recalc,
1376 };
1377
1378 /*
1379  * Modem clock domain (2430)
1380  *      CLOCKS:
1381  *              MDM_OSC_CLK
1382  *              MDM_ICLK
1383  * These clocks are usable in chassis mode only.
1384  */
1385 static const struct clksel_rate mdm_ick_core_rates[] = {
1386         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1387         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1388         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1389         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1390         { .div = 0 }
1391 };
1392
1393 static const struct clksel mdm_ick_clksel[] = {
1394         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1395         { .parent = NULL }
1396 };
1397
1398 static struct clk mdm_ick = {           /* used both as a ick and fck */
1399         .name           = "mdm_ick",
1400         .parent         = &core_ck,
1401         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1402         .clkdm          = { .name = "mdm_clkdm" },
1403         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
1404         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1405         .clksel_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL),
1406         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1407         .clksel         = mdm_ick_clksel,
1408         .recalc         = &omap2_clksel_recalc,
1409         .round_rate     = &omap2_clksel_round_rate,
1410         .set_rate       = &omap2_clksel_set_rate
1411 };
1412
1413 static struct clk mdm_osc_ck = {
1414         .name           = "mdm_osc_ck",
1415         .parent         = &osc_ck,
1416         .flags          = CLOCK_IN_OMAP243X,
1417         .clkdm          = { .name = "mdm_clkdm" },
1418         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
1419         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1420         .recalc         = &followparent_recalc,
1421 };
1422
1423 /*
1424  * DSS clock domain
1425  * CLOCKs:
1426  * DSS_L4_ICLK, DSS_L3_ICLK,
1427  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1428  *
1429  * DSS is both initiator and target.
1430  */
1431 /* XXX Add RATE_NOT_VALIDATED */
1432
1433 static const struct clksel_rate dss1_fck_sys_rates[] = {
1434         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1435         { .div = 0 }
1436 };
1437
1438 static const struct clksel_rate dss1_fck_core_rates[] = {
1439         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1440         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1441         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1442         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1443         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1444         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1445         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1446         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1447         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1448         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1449         { .div = 0 }
1450 };
1451
1452 static const struct clksel dss1_fck_clksel[] = {
1453         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1454         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1455         { .parent = NULL },
1456 };
1457
1458 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1459         .name           = "dss_ick",
1460         .parent         = &l4_ck,       /* really both l3 and l4 */
1461         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1462         .clkdm          = { .name = "dss_clkdm" },
1463         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1464         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1465         .recalc         = &followparent_recalc,
1466 };
1467
1468 static struct clk dss1_fck = {
1469         .name           = "dss1_fck",
1470         .parent         = &core_ck,             /* Core or sys */
1471         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1472                                 DELAYED_APP,
1473         .clkdm          = { .name = "dss_clkdm" },
1474         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1475         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1476         .init           = &omap2_init_clksel_parent,
1477         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1478         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1479         .clksel         = dss1_fck_clksel,
1480         .recalc         = &omap2_clksel_recalc,
1481         .round_rate     = &omap2_clksel_round_rate,
1482         .set_rate       = &omap2_clksel_set_rate
1483 };
1484
1485 static const struct clksel_rate dss2_fck_sys_rates[] = {
1486         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1487         { .div = 0 }
1488 };
1489
1490 static const struct clksel_rate dss2_fck_48m_rates[] = {
1491         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1492         { .div = 0 }
1493 };
1494
1495 static const struct clksel dss2_fck_clksel[] = {
1496         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1497         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1498         { .parent = NULL }
1499 };
1500
1501 static struct clk dss2_fck = {          /* Alt clk used in power management */
1502         .name           = "dss2_fck",
1503         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1504         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1505                                 DELAYED_APP,
1506         .clkdm          = { .name = "dss_clkdm" },
1507         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1508         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1509         .init           = &omap2_init_clksel_parent,
1510         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1511         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1512         .clksel         = dss2_fck_clksel,
1513         .recalc         = &followparent_recalc,
1514 };
1515
1516 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1517         .name           = "dss_54m_fck",        /* 54m tv clk */
1518         .parent         = &func_54m_ck,
1519         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1520         .clkdm          = { .name = "dss_clkdm" },
1521         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1522         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1523         .recalc         = &followparent_recalc,
1524 };
1525
1526 /*
1527  * CORE power domain ICLK & FCLK defines.
1528  * Many of the these can have more than one possible parent. Entries
1529  * here will likely have an L4 interface parent, and may have multiple
1530  * functional clock parents.
1531  */
1532 static const struct clksel_rate gpt_alt_rates[] = {
1533         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1534         { .div = 0 }
1535 };
1536
1537 static const struct clksel omap24xx_gpt_clksel[] = {
1538         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1539         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1540         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1541         { .parent = NULL },
1542 };
1543
1544 static struct clk gpt1_ick = {
1545         .name           = "gpt1_ick",
1546         .parent         = &l4_ck,
1547         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1548         .clkdm          = { .name = "core_l4_clkdm" },
1549         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
1550         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk gpt1_fck = {
1555         .name           = "gpt1_fck",
1556         .parent         = &func_32k_ck,
1557         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1558         .clkdm          = { .name = "core_l4_clkdm" },
1559         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
1560         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1561         .init           = &omap2_init_clksel_parent,
1562         .clksel_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_CLKSEL1),
1563         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1564         .clksel         = omap24xx_gpt_clksel,
1565         .recalc         = &omap2_clksel_recalc,
1566         .round_rate     = &omap2_clksel_round_rate,
1567         .set_rate       = &omap2_clksel_set_rate
1568 };
1569
1570 static struct clk gpt2_ick = {
1571         .name           = "gpt2_ick",
1572         .parent         = &l4_ck,
1573         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1574         .clkdm          = { .name = "core_l4_clkdm" },
1575         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1576         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1577         .recalc         = &followparent_recalc,
1578 };
1579
1580 static struct clk gpt2_fck = {
1581         .name           = "gpt2_fck",
1582         .parent         = &func_32k_ck,
1583         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1584         .clkdm          = { .name = "core_l4_clkdm" },
1585         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1586         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1587         .init           = &omap2_init_clksel_parent,
1588         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1589         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1590         .clksel         = omap24xx_gpt_clksel,
1591         .recalc         = &omap2_clksel_recalc,
1592 };
1593
1594 static struct clk gpt3_ick = {
1595         .name           = "gpt3_ick",
1596         .parent         = &l4_ck,
1597         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1598         .clkdm          = { .name = "core_l4_clkdm" },
1599         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1600         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1601         .recalc         = &followparent_recalc,
1602 };
1603
1604 static struct clk gpt3_fck = {
1605         .name           = "gpt3_fck",
1606         .parent         = &func_32k_ck,
1607         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1608         .clkdm          = { .name = "core_l4_clkdm" },
1609         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1610         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1611         .init           = &omap2_init_clksel_parent,
1612         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1613         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1614         .clksel         = omap24xx_gpt_clksel,
1615         .recalc         = &omap2_clksel_recalc,
1616 };
1617
1618 static struct clk gpt4_ick = {
1619         .name           = "gpt4_ick",
1620         .parent         = &l4_ck,
1621         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1622         .clkdm          = { .name = "core_l4_clkdm" },
1623         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1624         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1625         .recalc         = &followparent_recalc,
1626 };
1627
1628 static struct clk gpt4_fck = {
1629         .name           = "gpt4_fck",
1630         .parent         = &func_32k_ck,
1631         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1632         .clkdm          = { .name = "core_l4_clkdm" },
1633         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1634         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1635         .init           = &omap2_init_clksel_parent,
1636         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1637         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1638         .clksel         = omap24xx_gpt_clksel,
1639         .recalc         = &omap2_clksel_recalc,
1640 };
1641
1642 static struct clk gpt5_ick = {
1643         .name           = "gpt5_ick",
1644         .parent         = &l4_ck,
1645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1646         .clkdm          = { .name = "core_l4_clkdm" },
1647         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1648         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1649         .recalc         = &followparent_recalc,
1650 };
1651
1652 static struct clk gpt5_fck = {
1653         .name           = "gpt5_fck",
1654         .parent         = &func_32k_ck,
1655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1656         .clkdm          = { .name = "core_l4_clkdm" },
1657         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1658         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1659         .init           = &omap2_init_clksel_parent,
1660         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1661         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1662         .clksel         = omap24xx_gpt_clksel,
1663         .recalc         = &omap2_clksel_recalc,
1664 };
1665
1666 static struct clk gpt6_ick = {
1667         .name           = "gpt6_ick",
1668         .parent         = &l4_ck,
1669         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1670         .clkdm          = { .name = "core_l4_clkdm" },
1671         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1672         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1673         .recalc         = &followparent_recalc,
1674 };
1675
1676 static struct clk gpt6_fck = {
1677         .name           = "gpt6_fck",
1678         .parent         = &func_32k_ck,
1679         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1680         .clkdm          = { .name = "core_l4_clkdm" },
1681         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1682         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1683         .init           = &omap2_init_clksel_parent,
1684         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1685         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1686         .clksel         = omap24xx_gpt_clksel,
1687         .recalc         = &omap2_clksel_recalc,
1688 };
1689
1690 static struct clk gpt7_ick = {
1691         .name           = "gpt7_ick",
1692         .parent         = &l4_ck,
1693         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1694         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1695         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1696         .recalc         = &followparent_recalc,
1697 };
1698
1699 static struct clk gpt7_fck = {
1700         .name           = "gpt7_fck",
1701         .parent         = &func_32k_ck,
1702         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1703         .clkdm          = { .name = "core_l4_clkdm" },
1704         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1705         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1706         .init           = &omap2_init_clksel_parent,
1707         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1708         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1709         .clksel         = omap24xx_gpt_clksel,
1710         .recalc         = &omap2_clksel_recalc,
1711 };
1712
1713 static struct clk gpt8_ick = {
1714         .name           = "gpt8_ick",
1715         .parent         = &l4_ck,
1716         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1717         .clkdm          = { .name = "core_l4_clkdm" },
1718         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1719         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1720         .recalc         = &followparent_recalc,
1721 };
1722
1723 static struct clk gpt8_fck = {
1724         .name           = "gpt8_fck",
1725         .parent         = &func_32k_ck,
1726         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1727         .clkdm          = { .name = "core_l4_clkdm" },
1728         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1729         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1730         .init           = &omap2_init_clksel_parent,
1731         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1732         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1733         .clksel         = omap24xx_gpt_clksel,
1734         .recalc         = &omap2_clksel_recalc,
1735 };
1736
1737 static struct clk gpt9_ick = {
1738         .name           = "gpt9_ick",
1739         .parent         = &l4_ck,
1740         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1741         .clkdm          = { .name = "core_l4_clkdm" },
1742         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1743         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1744         .recalc         = &followparent_recalc,
1745 };
1746
1747 static struct clk gpt9_fck = {
1748         .name           = "gpt9_fck",
1749         .parent         = &func_32k_ck,
1750         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1751         .clkdm          = { .name = "core_l4_clkdm" },
1752         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1753         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1754         .init           = &omap2_init_clksel_parent,
1755         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1756         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1757         .clksel         = omap24xx_gpt_clksel,
1758         .recalc         = &omap2_clksel_recalc,
1759 };
1760
1761 static struct clk gpt10_ick = {
1762         .name           = "gpt10_ick",
1763         .parent         = &l4_ck,
1764         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1765         .clkdm          = { .name = "core_l4_clkdm" },
1766         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1767         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1768         .recalc         = &followparent_recalc,
1769 };
1770
1771 static struct clk gpt10_fck = {
1772         .name           = "gpt10_fck",
1773         .parent         = &func_32k_ck,
1774         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1775         .clkdm          = { .name = "core_l4_clkdm" },
1776         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1777         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1778         .init           = &omap2_init_clksel_parent,
1779         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1780         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1781         .clksel         = omap24xx_gpt_clksel,
1782         .recalc         = &omap2_clksel_recalc,
1783 };
1784
1785 static struct clk gpt11_ick = {
1786         .name           = "gpt11_ick",
1787         .parent         = &l4_ck,
1788         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1789         .clkdm          = { .name = "core_l4_clkdm" },
1790         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1791         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1792         .recalc         = &followparent_recalc,
1793 };
1794
1795 static struct clk gpt11_fck = {
1796         .name           = "gpt11_fck",
1797         .parent         = &func_32k_ck,
1798         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1799         .clkdm          = { .name = "core_l4_clkdm" },
1800         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1801         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1802         .init           = &omap2_init_clksel_parent,
1803         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1804         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1805         .clksel         = omap24xx_gpt_clksel,
1806         .recalc         = &omap2_clksel_recalc,
1807 };
1808
1809 static struct clk gpt12_ick = {
1810         .name           = "gpt12_ick",
1811         .parent         = &l4_ck,
1812         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1813         .clkdm          = { .name = "core_l4_clkdm" },
1814         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1815         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 static struct clk gpt12_fck = {
1820         .name           = "gpt12_fck",
1821         .parent         = &func_32k_ck,
1822         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1823         .clkdm          = { .name = "core_l4_clkdm" },
1824         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1825         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1826         .init           = &omap2_init_clksel_parent,
1827         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1828         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1829         .clksel         = omap24xx_gpt_clksel,
1830         .recalc         = &omap2_clksel_recalc,
1831 };
1832
1833 static struct clk mcbsp1_ick = {
1834         .name           = "mcbsp_ick",
1835         .id             = 1,
1836         .parent         = &l4_ck,
1837         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1838         .clkdm          = { .name = "core_l4_clkdm" },
1839         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1840         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 static struct clk mcbsp1_fck = {
1845         .name           = "mcbsp_fck",
1846         .id             = 1,
1847         .parent         = &func_96m_ck,
1848         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1849         .clkdm          = { .name = "core_l4_clkdm" },
1850         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1851         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk mcbsp2_ick = {
1856         .name           = "mcbsp_ick",
1857         .id             = 2,
1858         .parent         = &l4_ck,
1859         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1860         .clkdm          = { .name = "core_l4_clkdm" },
1861         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1862         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 static struct clk mcbsp2_fck = {
1867         .name           = "mcbsp_fck",
1868         .id             = 2,
1869         .parent         = &func_96m_ck,
1870         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1871         .clkdm          = { .name = "core_l4_clkdm" },
1872         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1873         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1874         .recalc         = &followparent_recalc,
1875 };
1876
1877 static struct clk mcbsp3_ick = {
1878         .name           = "mcbsp_ick",
1879         .id             = 3,
1880         .parent         = &l4_ck,
1881         .flags          = CLOCK_IN_OMAP243X,
1882         .clkdm          = { .name = "core_l4_clkdm" },
1883         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1884         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1885         .recalc         = &followparent_recalc,
1886 };
1887
1888 static struct clk mcbsp3_fck = {
1889         .name           = "mcbsp_fck",
1890         .id             = 3,
1891         .parent         = &func_96m_ck,
1892         .flags          = CLOCK_IN_OMAP243X,
1893         .clkdm          = { .name = "core_l4_clkdm" },
1894         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1895         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1896         .recalc         = &followparent_recalc,
1897 };
1898
1899 static struct clk mcbsp4_ick = {
1900         .name           = "mcbsp_ick",
1901         .id             = 4,
1902         .parent         = &l4_ck,
1903         .flags          = CLOCK_IN_OMAP243X,
1904         .clkdm          = { .name = "core_l4_clkdm" },
1905         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1906         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1907         .recalc         = &followparent_recalc,
1908 };
1909
1910 static struct clk mcbsp4_fck = {
1911         .name           = "mcbsp_fck",
1912         .id             = 4,
1913         .parent         = &func_96m_ck,
1914         .flags          = CLOCK_IN_OMAP243X,
1915         .clkdm          = { .name = "core_l4_clkdm" },
1916         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1917         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1918         .recalc         = &followparent_recalc,
1919 };
1920
1921 static struct clk mcbsp5_ick = {
1922         .name           = "mcbsp_ick",
1923         .id             = 5,
1924         .parent         = &l4_ck,
1925         .flags          = CLOCK_IN_OMAP243X,
1926         .clkdm          = { .name = "core_l4_clkdm" },
1927         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1928         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk mcbsp5_fck = {
1933         .name           = "mcbsp_fck",
1934         .id             = 5,
1935         .parent         = &func_96m_ck,
1936         .flags          = CLOCK_IN_OMAP243X,
1937         .clkdm          = { .name = "core_l4_clkdm" },
1938         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1939         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk mcspi1_ick = {
1944         .name           = "mcspi_ick",
1945         .id             = 1,
1946         .parent         = &l4_ck,
1947         .clkdm          = { .name = "core_l4_clkdm" },
1948         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1949         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1950         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1951         .recalc         = &followparent_recalc,
1952 };
1953
1954 static struct clk mcspi1_fck = {
1955         .name           = "mcspi_fck",
1956         .id             = 1,
1957         .parent         = &func_48m_ck,
1958         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1959         .clkdm          = { .name = "core_l4_clkdm" },
1960         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1961         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk mcspi2_ick = {
1966         .name           = "mcspi_ick",
1967         .id             = 2,
1968         .parent         = &l4_ck,
1969         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1970         .clkdm          = { .name = "core_l4_clkdm" },
1971         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1972         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk mcspi2_fck = {
1977         .name           = "mcspi_fck",
1978         .id             = 2,
1979         .parent         = &func_48m_ck,
1980         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1981         .clkdm          = { .name = "core_l4_clkdm" },
1982         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1983         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1984         .recalc         = &followparent_recalc,
1985 };
1986
1987 static struct clk mcspi3_ick = {
1988         .name           = "mcspi_ick",
1989         .id             = 3,
1990         .parent         = &l4_ck,
1991         .flags          = CLOCK_IN_OMAP243X,
1992         .clkdm          = { .name = "core_l4_clkdm" },
1993         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1994         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1995         .recalc         = &followparent_recalc,
1996 };
1997
1998 static struct clk mcspi3_fck = {
1999         .name           = "mcspi_fck",
2000         .id             = 3,
2001         .parent         = &func_48m_ck,
2002         .flags          = CLOCK_IN_OMAP243X,
2003         .clkdm          = { .name = "core_l4_clkdm" },
2004         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2005         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2006         .recalc         = &followparent_recalc,
2007 };
2008
2009 static struct clk uart1_ick = {
2010         .name           = "uart1_ick",
2011         .parent         = &l4_ck,
2012         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2013         .clkdm          = { .name = "core_l4_clkdm" },
2014         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2015         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2016         .recalc         = &followparent_recalc,
2017 };
2018
2019 static struct clk uart1_fck = {
2020         .name           = "uart1_fck",
2021         .parent         = &func_48m_ck,
2022         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2023         .clkdm          = { .name = "core_l4_clkdm" },
2024         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2025         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2026         .recalc         = &followparent_recalc,
2027 };
2028
2029 static struct clk uart2_ick = {
2030         .name           = "uart2_ick",
2031         .parent         = &l4_ck,
2032         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2033         .clkdm          = { .name = "core_l4_clkdm" },
2034         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2035         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk uart2_fck = {
2040         .name           = "uart2_fck",
2041         .parent         = &func_48m_ck,
2042         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2043         .clkdm          = { .name = "core_l4_clkdm" },
2044         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2045         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 static struct clk uart3_ick = {
2050         .name           = "uart3_ick",
2051         .parent         = &l4_ck,
2052         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2053         .clkdm          = { .name = "core_l4_clkdm" },
2054         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2055         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2056         .recalc         = &followparent_recalc,
2057 };
2058
2059 static struct clk uart3_fck = {
2060         .name           = "uart3_fck",
2061         .parent         = &func_48m_ck,
2062         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2063         .clkdm          = { .name = "core_l4_clkdm" },
2064         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2065         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2066         .recalc         = &followparent_recalc,
2067 };
2068
2069 static struct clk gpios_ick = {
2070         .name           = "gpios_ick",
2071         .parent         = &l4_ck,
2072         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2073         .clkdm          = { .name = "core_l4_clkdm" },
2074         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2075         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2076         .recalc         = &followparent_recalc,
2077 };
2078
2079 static struct clk gpios_fck = {
2080         .name           = "gpios_fck",
2081         .parent         = &func_32k_ck,
2082         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2083         .clkdm          = { .name = "prm_clkdm" },
2084         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2085         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2086         .recalc         = &followparent_recalc,
2087 };
2088
2089 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2090 static struct clk mpu_wdt_ick = {
2091         .name           = "mpu_wdt_ick",
2092         .parent         = &l4_ck,
2093         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2094         .clkdm          = { .name = "prm_clkdm" },
2095         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2096         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2097         .recalc         = &followparent_recalc,
2098 };
2099
2100 /* aka WDT2 */
2101 static struct clk mpu_wdt_fck = {
2102         .name           = "mpu_wdt_fck",
2103         .parent         = &func_32k_ck,
2104         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2105         .clkdm          = { .name = "prm_clkdm" },
2106         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2107         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2108         .recalc         = &followparent_recalc,
2109 };
2110
2111 static struct clk sync_32k_ick = {
2112         .name           = "sync_32k_ick",
2113         .parent         = &l4_ck,
2114         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2115                                 ENABLE_ON_INIT,
2116         .clkdm          = { .name = "core_l4_clkdm" },
2117         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2118         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 /* REVISIT: parent is really wu_l4_iclk */
2123 static struct clk wdt1_ick = {
2124         .name           = "wdt1_ick",
2125         .parent         = &l4_ck,
2126         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2127         .clkdm          = { .name = "prm_clkdm" },
2128         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2129         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2130         .recalc         = &followparent_recalc,
2131 };
2132
2133 static struct clk omapctrl_ick = {
2134         .name           = "omapctrl_ick",
2135         .parent         = &l4_ck,
2136         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2137                                 ENABLE_ON_INIT,
2138         .clkdm          = { .name = "core_l4_clkdm" },
2139         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2140         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 static struct clk icr_ick = {
2145         .name           = "icr_ick",
2146         .parent         = &l4_ck,
2147         .flags          = CLOCK_IN_OMAP243X,
2148         .clkdm          = { .name = "core_l4_clkdm" },
2149         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2150         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2151         .recalc         = &followparent_recalc,
2152 };
2153
2154 static struct clk cam_ick = {
2155         .name           = "cam_ick",
2156         .parent         = &l4_ck,
2157         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2158         .clkdm          = { .name = "core_l4_clkdm" },
2159         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2160         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 /*
2165  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2166  * split into two separate clocks, since the parent clocks are different
2167  * and the clockdomains are also different.
2168  */
2169 static struct clk cam_fck = {
2170         .name           = "cam_fck",
2171         .parent         = &func_96m_ck,
2172         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2173         .clkdm          = { .name = "core_l3_clkdm" },
2174         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2175         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2176         .recalc         = &followparent_recalc,
2177 };
2178
2179 static struct clk mailboxes_ick = {
2180         .name           = "mailboxes_ick",
2181         .parent         = &l4_ck,
2182         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2183         .clkdm          = { .name = "core_l4_clkdm" },
2184         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2185         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2186         .recalc         = &followparent_recalc,
2187 };
2188
2189 static struct clk wdt4_ick = {
2190         .name           = "wdt4_ick",
2191         .parent         = &l4_ck,
2192         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2193         .clkdm          = { .name = "core_l4_clkdm" },
2194         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2195         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2196         .recalc         = &followparent_recalc,
2197 };
2198
2199 static struct clk wdt4_fck = {
2200         .name           = "wdt4_fck",
2201         .parent         = &func_32k_ck,
2202         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2203         .clkdm          = { .name = "core_l4_clkdm" },
2204         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2205         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2206         .recalc         = &followparent_recalc,
2207 };
2208
2209 static struct clk wdt3_ick = {
2210         .name           = "wdt3_ick",
2211         .parent         = &l4_ck,
2212         .flags          = CLOCK_IN_OMAP242X,
2213         .clkdm          = { .name = "core_l4_clkdm" },
2214         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2215         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2216         .recalc         = &followparent_recalc,
2217 };
2218
2219 static struct clk wdt3_fck = {
2220         .name           = "wdt3_fck",
2221         .parent         = &func_32k_ck,
2222         .flags          = CLOCK_IN_OMAP242X,
2223         .clkdm          = { .name = "core_l4_clkdm" },
2224         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2225         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2226         .recalc         = &followparent_recalc,
2227 };
2228
2229 static struct clk mspro_ick = {
2230         .name           = "mspro_ick",
2231         .parent         = &l4_ck,
2232         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2233         .clkdm          = { .name = "core_l4_clkdm" },
2234         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2235         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2236         .recalc         = &followparent_recalc,
2237 };
2238
2239 static struct clk mspro_fck = {
2240         .name           = "mspro_fck",
2241         .parent         = &func_96m_ck,
2242         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2243         .clkdm          = { .name = "core_l4_clkdm" },
2244         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2245         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2246         .recalc         = &followparent_recalc,
2247 };
2248
2249 static struct clk mmc_ick = {
2250         .name           = "mmc_ick",
2251         .parent         = &l4_ck,
2252         .flags          = CLOCK_IN_OMAP242X,
2253         .clkdm          = { .name = "core_l4_clkdm" },
2254         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2255         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2256         .recalc         = &followparent_recalc,
2257 };
2258
2259 static struct clk mmc_fck = {
2260         .name           = "mmc_fck",
2261         .parent         = &func_96m_ck,
2262         .flags          = CLOCK_IN_OMAP242X,
2263         .clkdm          = { .name = "core_l4_clkdm" },
2264         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2265         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2266         .recalc         = &followparent_recalc,
2267 };
2268
2269 static struct clk fac_ick = {
2270         .name           = "fac_ick",
2271         .parent         = &l4_ck,
2272         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2273         .clkdm          = { .name = "core_l4_clkdm" },
2274         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2275         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2276         .recalc         = &followparent_recalc,
2277 };
2278
2279 static struct clk fac_fck = {
2280         .name           = "fac_fck",
2281         .parent         = &func_12m_ck,
2282         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2283         .clkdm          = { .name = "core_l4_clkdm" },
2284         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2285         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2286         .recalc         = &followparent_recalc,
2287 };
2288
2289 static struct clk eac_ick = {
2290         .name           = "eac_ick",
2291         .parent         = &l4_ck,
2292         .flags          = CLOCK_IN_OMAP242X,
2293         .clkdm          = { .name = "core_l4_clkdm" },
2294         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2295         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2296         .recalc         = &followparent_recalc,
2297 };
2298
2299 static struct clk eac_fck = {
2300         .name           = "eac_fck",
2301         .parent         = &func_96m_ck,
2302         .flags          = CLOCK_IN_OMAP242X,
2303         .clkdm          = { .name = "core_l4_clkdm" },
2304         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2305         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2306         .recalc         = &followparent_recalc,
2307 };
2308
2309 static struct clk hdq_ick = {
2310         .name           = "hdq_ick",
2311         .parent         = &l4_ck,
2312         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2313         .clkdm          = { .name = "core_l4_clkdm" },
2314         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2315         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2316         .recalc         = &followparent_recalc,
2317 };
2318
2319 static struct clk hdq_fck = {
2320         .name           = "hdq_fck",
2321         .parent         = &func_12m_ck,
2322         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2323         .clkdm          = { .name = "core_l4_clkdm" },
2324         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2325         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2326         .recalc         = &followparent_recalc,
2327 };
2328
2329 static struct clk i2c2_ick = {
2330         .name           = "i2c_ick",
2331         .id             = 2,
2332         .parent         = &l4_ck,
2333         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2334         .clkdm          = { .name = "core_l4_clkdm" },
2335         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2336         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2337         .recalc         = &followparent_recalc,
2338 };
2339
2340 static struct clk i2c2_fck = {
2341         .name           = "i2c_fck",
2342         .id             = 2,
2343         .parent         = &func_12m_ck,
2344         .flags          = CLOCK_IN_OMAP242X,
2345         .clkdm          = { .name = "core_l4_clkdm" },
2346         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2347         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2348         .recalc         = &followparent_recalc,
2349 };
2350
2351 static struct clk i2chs2_fck = {
2352         .name           = "i2chs_fck",
2353         .id             = 2,
2354         .parent         = &func_96m_ck,
2355         .flags          = CLOCK_IN_OMAP243X,
2356         .clkdm          = { .name = "core_l4_clkdm" },
2357         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2358         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk i2c1_ick = {
2363         .name           = "i2c_ick",
2364         .id             = 1,
2365         .parent         = &l4_ck,
2366         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2367         .clkdm          = { .name = "core_l4_clkdm" },
2368         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2369         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk i2c1_fck = {
2374         .name           = "i2c_fck",
2375         .id             = 1,
2376         .parent         = &func_12m_ck,
2377         .flags          = CLOCK_IN_OMAP242X,
2378         .clkdm          = { .name = "core_l4_clkdm" },
2379         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2380         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2381         .recalc         = &followparent_recalc,
2382 };
2383
2384 static struct clk i2chs1_fck = {
2385         .name           = "i2chs_fck",
2386         .id             = 1,
2387         .parent         = &func_96m_ck,
2388         .flags          = CLOCK_IN_OMAP243X,
2389         .clkdm          = { .name = "core_l4_clkdm" },
2390         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2391         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2392         .recalc         = &followparent_recalc,
2393 };
2394
2395 static struct clk gpmc_fck = {
2396         .name           = "gpmc_fck",
2397         .parent         = &core_l3_ck,
2398         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2399                                 ENABLE_ON_INIT,
2400         .clkdm          = { .name = "core_l3_clkdm" },
2401         .recalc         = &followparent_recalc,
2402 };
2403
2404 static struct clk sdma_fck = {
2405         .name           = "sdma_fck",
2406         .parent         = &core_l3_ck,
2407         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2408         .clkdm          = { .name = "core_l3_clkdm" },
2409         .recalc         = &followparent_recalc,
2410 };
2411
2412 static struct clk sdma_ick = {
2413         .name           = "sdma_ick",
2414         .parent         = &l4_ck,
2415         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2416         .clkdm          = { .name = "core_l3_clkdm" },
2417         .recalc         = &followparent_recalc,
2418 };
2419
2420 static struct clk vlynq_ick = {
2421         .name           = "vlynq_ick",
2422         .parent         = &core_l3_ck,
2423         .flags          = CLOCK_IN_OMAP242X,
2424         .clkdm          = { .name = "core_l3_clkdm" },
2425         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2426         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2431         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2432         { .div = 0 }
2433 };
2434
2435 static const struct clksel_rate vlynq_fck_core_rates[] = {
2436         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2437         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2438         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2439         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2440         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2441         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2442         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2443         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2444         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2445         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2446         { .div = 0 }
2447 };
2448
2449 static const struct clksel vlynq_fck_clksel[] = {
2450         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2451         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2452         { .parent = NULL }
2453 };
2454
2455 static struct clk vlynq_fck = {
2456         .name           = "vlynq_fck",
2457         .parent         = &func_96m_ck,
2458         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2459         .clkdm          = { .name = "core_l3_clkdm" },
2460         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2461         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2462         .init           = &omap2_init_clksel_parent,
2463         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
2464         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2465         .clksel         = vlynq_fck_clksel,
2466         .recalc         = &omap2_clksel_recalc,
2467         .round_rate     = &omap2_clksel_round_rate,
2468         .set_rate       = &omap2_clksel_set_rate
2469 };
2470
2471 static struct clk sdrc_ick = {
2472         .name           = "sdrc_ick",
2473         .parent         = &l4_ck,
2474         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2475         .clkdm          = { .name = "core_l4_clkdm" },
2476         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
2477         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2478         .recalc         = &followparent_recalc,
2479 };
2480
2481 static struct clk des_ick = {
2482         .name           = "des_ick",
2483         .parent         = &l4_ck,
2484         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2485         .clkdm          = { .name = "core_l4_clkdm" },
2486         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2487         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2488         .recalc         = &followparent_recalc,
2489 };
2490
2491 static struct clk sha_ick = {
2492         .name           = "sha_ick",
2493         .parent         = &l4_ck,
2494         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2495         .clkdm          = { .name = "core_l4_clkdm" },
2496         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2497         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2498         .recalc         = &followparent_recalc,
2499 };
2500
2501 static struct clk rng_ick = {
2502         .name           = "rng_ick",
2503         .parent         = &l4_ck,
2504         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2505         .clkdm          = { .name = "core_l4_clkdm" },
2506         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2507         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2508         .recalc         = &followparent_recalc,
2509 };
2510
2511 static struct clk aes_ick = {
2512         .name           = "aes_ick",
2513         .parent         = &l4_ck,
2514         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2515         .clkdm          = { .name = "core_l4_clkdm" },
2516         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2517         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2518         .recalc         = &followparent_recalc,
2519 };
2520
2521 static struct clk pka_ick = {
2522         .name           = "pka_ick",
2523         .parent         = &l4_ck,
2524         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2525         .clkdm          = { .name = "core_l4_clkdm" },
2526         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2527         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2528         .recalc         = &followparent_recalc,
2529 };
2530
2531 static struct clk usb_fck = {
2532         .name           = "usb_fck",
2533         .parent         = &func_48m_ck,
2534         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2535         .clkdm          = { .name = "core_l3_clkdm" },
2536         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2537         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2538         .recalc         = &followparent_recalc,
2539 };
2540
2541 static struct clk usbhs_ick = {
2542         .name           = "usbhs_ick",
2543         .parent         = &core_l3_ck,
2544         .flags          = CLOCK_IN_OMAP243X,
2545         .clkdm          = { .name = "core_l3_clkdm" },
2546         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2547         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2548         .recalc         = &followparent_recalc,
2549 };
2550
2551 static struct clk mmchs1_ick = {
2552         .name           = "mmchs_ick",
2553         .id             = 1,
2554         .parent         = &l4_ck,
2555         .flags          = CLOCK_IN_OMAP243X,
2556         .clkdm          = { .name = "core_l4_clkdm" },
2557         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2558         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2559         .recalc         = &followparent_recalc,
2560 };
2561
2562 static struct clk mmchs1_fck = {
2563         .name           = "mmchs_fck",
2564         .id             = 1,
2565         .parent         = &func_96m_ck,
2566         .flags          = CLOCK_IN_OMAP243X,
2567         .clkdm          = { .name = "core_l3_clkdm" },
2568         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2569         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2570         .recalc         = &followparent_recalc,
2571 };
2572
2573 static struct clk mmchs2_ick = {
2574         .name           = "mmchs_ick",
2575         .id             = 2,
2576         .parent         = &l4_ck,
2577         .flags          = CLOCK_IN_OMAP243X,
2578         .clkdm          = { .name = "core_l4_clkdm" },
2579         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2580         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2581         .recalc         = &followparent_recalc,
2582 };
2583
2584 static struct clk mmchs2_fck = {
2585         .name           = "mmchs_fck",
2586         .id             = 2,
2587         .parent         = &func_96m_ck,
2588         .flags          = CLOCK_IN_OMAP243X,
2589         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2590         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2591         .recalc         = &followparent_recalc,
2592 };
2593
2594 static struct clk gpio5_ick = {
2595         .name           = "gpio5_ick",
2596         .parent         = &l4_ck,
2597         .flags          = CLOCK_IN_OMAP243X,
2598         .clkdm          = { .name = "core_l4_clkdm" },
2599         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2600         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2601         .recalc         = &followparent_recalc,
2602 };
2603
2604 static struct clk gpio5_fck = {
2605         .name           = "gpio5_fck",
2606         .parent         = &func_32k_ck,
2607         .flags          = CLOCK_IN_OMAP243X,
2608         .clkdm          = { .name = "core_l4_clkdm" },
2609         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2610         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2611         .recalc         = &followparent_recalc,
2612 };
2613
2614 static struct clk mdm_intc_ick = {
2615         .name           = "mdm_intc_ick",
2616         .parent         = &l4_ck,
2617         .flags          = CLOCK_IN_OMAP243X,
2618         .clkdm          = { .name = "core_l4_clkdm" },
2619         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2620         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2621         .recalc         = &followparent_recalc,
2622 };
2623
2624 static struct clk mmchsdb1_fck = {
2625         .name           = "mmchsdb_fck",
2626         .id             = 1,
2627         .parent         = &func_32k_ck,
2628         .flags          = CLOCK_IN_OMAP243X,
2629         .clkdm          = { .name = "core_l4_clkdm" },
2630         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2631         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2632         .recalc         = &followparent_recalc,
2633 };
2634
2635 static struct clk mmchsdb2_fck = {
2636         .name           = "mmchsdb_fck",
2637         .id             = 2,
2638         .parent         = &func_32k_ck,
2639         .flags          = CLOCK_IN_OMAP243X,
2640         .clkdm          = { .name = "core_l4_clkdm" },
2641         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2642         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2643         .recalc         = &followparent_recalc,
2644 };
2645
2646 /*
2647  * This clock is a composite clock which does entire set changes then
2648  * forces a rebalance. It keys on the MPU speed, but it really could
2649  * be any key speed part of a set in the rate table.
2650  *
2651  * to really change a set, you need memory table sets which get changed
2652  * in sram, pre-notifiers & post notifiers, changing the top set, without
2653  * having low level display recalc's won't work... this is why dpm notifiers
2654  * work, isr's off, walk a list of clocks already _off_ and not messing with
2655  * the bus.
2656  *
2657  * This clock should have no parent. It embodies the entire upper level
2658  * active set. A parent will mess up some of the init also.
2659  */
2660 static struct clk virt_prcm_set = {
2661         .name           = "virt_prcm_set",
2662         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2663                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2664         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2665         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2666         .set_rate       = &omap2_select_table_rate,
2667         .round_rate     = &omap2_round_to_table_rate,
2668 };
2669
2670 static struct clk *onchip_24xx_clks[] __initdata = {
2671         /* external root sources */
2672         &func_32k_ck,
2673         &osc_ck,
2674         &sys_ck,
2675         &alt_ck,
2676         /* internal analog sources */
2677         &dpll_ck,
2678         &apll96_ck,
2679         &apll54_ck,
2680         /* internal prcm root sources */
2681         &func_54m_ck,
2682         &core_ck,
2683         &func_96m_ck,
2684         &func_48m_ck,
2685         &func_12m_ck,
2686         &wdt1_osc_ck,
2687         &sys_clkout_src,
2688         &sys_clkout,
2689         &sys_clkout2_src,
2690         &sys_clkout2,
2691         &emul_ck,
2692         /* mpu domain clocks */
2693         &mpu_ck,
2694         /* dsp domain clocks */
2695         &dsp_fck,
2696         &dsp_irate_ick,
2697         &dsp_ick,               /* 242x */
2698         &iva2_1_ick,            /* 243x */
2699         &iva1_ifck,             /* 242x */
2700         &iva1_mpu_int_ifck,     /* 242x */
2701         /* GFX domain clocks */
2702         &gfx_3d_fck,
2703         &gfx_2d_fck,
2704         &gfx_ick,
2705         /* Modem domain clocks */
2706         &mdm_ick,
2707         &mdm_osc_ck,
2708         /* DSS domain clocks */
2709         &dss_ick,
2710         &dss1_fck,
2711         &dss2_fck,
2712         &dss_54m_fck,
2713         /* L3 domain clocks */
2714         &core_l3_ck,
2715         &ssi_ssr_sst_fck,
2716         &usb_l4_ick,
2717         /* L4 domain clocks */
2718         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2719         &ssi_l4_ick,
2720         /* virtual meta-group clock */
2721         &virt_prcm_set,
2722         /* general l4 interface ck, multi-parent functional clk */
2723         &gpt1_ick,
2724         &gpt1_fck,
2725         &gpt2_ick,
2726         &gpt2_fck,
2727         &gpt3_ick,
2728         &gpt3_fck,
2729         &gpt4_ick,
2730         &gpt4_fck,
2731         &gpt5_ick,
2732         &gpt5_fck,
2733         &gpt6_ick,
2734         &gpt6_fck,
2735         &gpt7_ick,
2736         &gpt7_fck,
2737         &gpt8_ick,
2738         &gpt8_fck,
2739         &gpt9_ick,
2740         &gpt9_fck,
2741         &gpt10_ick,
2742         &gpt10_fck,
2743         &gpt11_ick,
2744         &gpt11_fck,
2745         &gpt12_ick,
2746         &gpt12_fck,
2747         &mcbsp1_ick,
2748         &mcbsp1_fck,
2749         &mcbsp2_ick,
2750         &mcbsp2_fck,
2751         &mcbsp3_ick,
2752         &mcbsp3_fck,
2753         &mcbsp4_ick,
2754         &mcbsp4_fck,
2755         &mcbsp5_ick,
2756         &mcbsp5_fck,
2757         &mcspi1_ick,
2758         &mcspi1_fck,
2759         &mcspi2_ick,
2760         &mcspi2_fck,
2761         &mcspi3_ick,
2762         &mcspi3_fck,
2763         &uart1_ick,
2764         &uart1_fck,
2765         &uart2_ick,
2766         &uart2_fck,
2767         &uart3_ick,
2768         &uart3_fck,
2769         &gpios_ick,
2770         &gpios_fck,
2771         &mpu_wdt_ick,
2772         &mpu_wdt_fck,
2773         &sync_32k_ick,
2774         &wdt1_ick,
2775         &omapctrl_ick,
2776         &icr_ick,
2777         &cam_fck,
2778         &cam_ick,
2779         &mailboxes_ick,
2780         &wdt4_ick,
2781         &wdt4_fck,
2782         &wdt3_ick,
2783         &wdt3_fck,
2784         &mspro_ick,
2785         &mspro_fck,
2786         &mmc_ick,
2787         &mmc_fck,
2788         &fac_ick,
2789         &fac_fck,
2790         &eac_ick,
2791         &eac_fck,
2792         &hdq_ick,
2793         &hdq_fck,
2794         &i2c1_ick,
2795         &i2c1_fck,
2796         &i2chs1_fck,
2797         &i2c2_ick,
2798         &i2c2_fck,
2799         &i2chs2_fck,
2800         &gpmc_fck,
2801         &sdma_fck,
2802         &sdma_ick,
2803         &vlynq_ick,
2804         &vlynq_fck,
2805         &sdrc_ick,
2806         &des_ick,
2807         &sha_ick,
2808         &rng_ick,
2809         &aes_ick,
2810         &pka_ick,
2811         &usb_fck,
2812         &usbhs_ick,
2813         &mmchs1_ick,
2814         &mmchs1_fck,
2815         &mmchs2_ick,
2816         &mmchs2_fck,
2817         &gpio5_ick,
2818         &gpio5_fck,
2819         &mdm_intc_ick,
2820         &mmchsdb1_fck,
2821         &mmchsdb2_fck,
2822 };
2823
2824 #endif
2825