arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  23
  24 #include "clock.h"
  25
  26 #include "prm.h"
  27 #include "cm.h"
  28 #include "prm_regbits_24xx.h"
  29 #include "cm_regbits_24xx.h"
  30 #include "sdrc.h"
  31
  32 static void omap2_table_mpu_recalc(struct clk *clk);
  33 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  34 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  35 static void omap2_sys_clk_recalc(struct clk *clk);
  36 static void omap2_osc_clk_recalc(struct clk *clk);
  37 static void omap2_sys_clk_recalc(struct clk *clk);
  38 static void omap2_dpll_recalc(struct clk *clk);
  39 static int omap2_clk_fixed_enable(struct clk *clk);
  40 static void omap2_clk_fixed_disable(struct clk *clk);
  41 static int omap2_enable_osc_ck(struct clk *clk);
  42 static void omap2_disable_osc_ck(struct clk *clk);
  43 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
  44
  45 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  46  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  47  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  48  */
  49 struct prcm_config {
  50         unsigned long xtal_speed;       /* crystal rate */
  51         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  52         unsigned long mpu_speed;        /* speed of MPU */
  53         unsigned long cm_clksel_mpu;    /* mpu divider */
  54         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  55         unsigned long cm_clksel_gfx;    /* gfx dividers */
  56         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  57         unsigned long cm_clksel1_pll;   /* m,n */
  58         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  59         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  60         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  61         unsigned char flags;
  62 };
  63
  64 /*
  65  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  66  * These configurations are characterized by voltage and speed for clocks.
  67  * The device is only validated for certain combinations. One way to express
  68  * these combinations is via the 'ratio's' which the clocks operate with
  69  * respect to each other. These ratio sets are for a given voltage/DPLL
  70  * setting. All configurations can be described by a DPLL setting and a ratio
  71  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  72  *
  73  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  74  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  75  * 2430 (iva2.1, NOdsp, mdm)
  76  */
  77
  78 /* Core fields for cm_clksel, not ratio governed */
  79 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  80 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  81 #define RX_CLKSEL_SSI                   (0x5 << 20)
  82
  83 /*-------------------------------------------------------------------------
  84  * Voltage/DPLL ratios
  85  *-------------------------------------------------------------------------*/
  86
  87 /* 2430 Ratio's, 2430-Ratio Config 1 */
  88 #define R1_CLKSEL_L3                    (4 << 0)
  89 #define R1_CLKSEL_L4                    (2 << 5)
  90 #define R1_CLKSEL_USB                   (4 << 25)
  91 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  92                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  93                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  94 #define R1_CLKSEL_MPU                   (2 << 0)
  95 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  96 #define R1_CLKSEL_DSP                   (2 << 0)
  97 #define R1_CLKSEL_DSP_IF                (2 << 5)
  98 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  99 #define R1_CLKSEL_GFX                   (2 << 0)
 100 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 101 #define R1_CLKSEL_MDM                   (4 << 0)
 102 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 103
 104 /* 2430-Ratio Config 2 */
 105 #define R2_CLKSEL_L3                    (6 << 0)
 106 #define R2_CLKSEL_L4                    (2 << 5)
 107 #define R2_CLKSEL_USB                   (2 << 25)
 108 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 109                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 110                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 111 #define R2_CLKSEL_MPU                   (2 << 0)
 112 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 113 #define R2_CLKSEL_DSP                   (2 << 0)
 114 #define R2_CLKSEL_DSP_IF                (3 << 5)
 115 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 116 #define R2_CLKSEL_GFX                   (2 << 0)
 117 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 118 #define R2_CLKSEL_MDM                   (6 << 0)
 119 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 120
 121 /* 2430-Ratio Bootm (BYPASS) */
 122 #define RB_CLKSEL_L3                    (1 << 0)
 123 #define RB_CLKSEL_L4                    (1 << 5)
 124 #define RB_CLKSEL_USB                   (1 << 25)
 125 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 126                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 127                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 128 #define RB_CLKSEL_MPU                   (1 << 0)
 129 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 130 #define RB_CLKSEL_DSP                   (1 << 0)
 131 #define RB_CLKSEL_DSP_IF                (1 << 5)
 132 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 133 #define RB_CLKSEL_GFX                   (1 << 0)
 134 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 135 #define RB_CLKSEL_MDM                   (1 << 0)
 136 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 137
 138 /* 2420 Ratio Equivalents */
 139 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 140 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 141
 142 /* 2420-PRCM III 532MHz core */
 143 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 144 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 145 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 146 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 147                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 148                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 149                                         RIII_CLKSEL_L3
 150 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 151 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 152 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 153 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 154 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 155 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 156 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 157 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 158                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 159                                         RIII_CLKSEL_DSP
 160 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 161 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 162
 163 /* 2420-PRCM II 600MHz core */
 164 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 165 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 166 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 167 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 168                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 169                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 170                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 171 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 172 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 173 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 174 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 175 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 176 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 177 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 178 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 179                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 180                                         RII_CLKSEL_DSP
 181 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 182 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 183
 184 /* 2420-PRCM I 660MHz core */
 185 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 186 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 187 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 188 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 189                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 190                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 191                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 192 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 193 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 194 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 195 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 196 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 197 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 198 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 199 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 200                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 201                                         RI_CLKSEL_DSP
 202 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 203 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 204
 205 /* 2420-PRCM VII (boot) */
 206 #define RVII_CLKSEL_L3                  (1 << 0)
 207 #define RVII_CLKSEL_L4                  (1 << 5)
 208 #define RVII_CLKSEL_DSS1                (1 << 8)
 209 #define RVII_CLKSEL_DSS2                (0 << 13)
 210 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 211 #define RVII_CLKSEL_SSI                 (1 << 20)
 212 #define RVII_CLKSEL_USB                 (1 << 25)
 213
 214 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 215                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 216                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 217
 218 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 219 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 220
 221 #define RVII_CLKSEL_DSP                 (1 << 0)
 222 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 223 #define RVII_SYNC_DSP                   (0 << 7)
 224 #define RVII_CLKSEL_IVA                 (1 << 8)
 225 #define RVII_SYNC_IVA                   (0 << 13)
 226 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 227                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 228
 229 #define RVII_CLKSEL_GFX                 (1 << 0)
 230 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 231
 232 /*-------------------------------------------------------------------------
 233  * 2430 Target modes: Along with each configuration the CPU has several
 234  * modes which goes along with them. Modes mainly are the addition of
 235  * describe DPLL combinations to go along with a ratio.
 236  *-------------------------------------------------------------------------*/
 237
 238 /* Hardware governed */
 239 #define MX_48M_SRC                      (0 << 3)
 240 #define MX_54M_SRC                      (0 << 5)
 241 #define MX_APLLS_CLIKIN_12              (3 << 23)
 242 #define MX_APLLS_CLIKIN_13              (2 << 23)
 243 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 244
 245 /*
 246  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 247  * #2   (ratio1) baseport-target
 248  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 249  */
 250 #define M5A_DPLL_MULT_12                (133 << 12)
 251 #define M5A_DPLL_DIV_12                 (5 << 8)
 252 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 253                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 254                                         MX_APLLS_CLIKIN_12
 255 #define M5A_DPLL_MULT_13                (266 << 12)
 256 #define M5A_DPLL_DIV_13                 (12 << 8)
 257 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 258                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 259                                         MX_APLLS_CLIKIN_13
 260 #define M5A_DPLL_MULT_19                (180 << 12)
 261 #define M5A_DPLL_DIV_19                 (12 << 8)
 262 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 264                                         MX_APLLS_CLIKIN_19_2
 265 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 266 #define M5B_DPLL_MULT_12                (50 << 12)
 267 #define M5B_DPLL_DIV_12                 (2 << 8)
 268 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 270                                         MX_APLLS_CLIKIN_12
 271 #define M5B_DPLL_MULT_13                (200 << 12)
 272 #define M5B_DPLL_DIV_13                 (12 << 8)
 273
 274 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 275                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 276                                         MX_APLLS_CLIKIN_13
 277 #define M5B_DPLL_MULT_19                (125 << 12)
 278 #define M5B_DPLL_DIV_19                 (31 << 8)
 279 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 280                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 281                                         MX_APLLS_CLIKIN_19_2
 282 /*
 283  * #4   (ratio2)
 284  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 285  */
 286 #define M3_DPLL_MULT_12                 (55 << 12)
 287 #define M3_DPLL_DIV_12                  (1 << 8)
 288 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 289                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 290                                         MX_APLLS_CLIKIN_12
 291 #define M3_DPLL_MULT_13                 (330 << 12)
 292 #define M3_DPLL_DIV_13                  (12 << 8)
 293 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 295                                         MX_APLLS_CLIKIN_13
 296 #define M3_DPLL_MULT_19                 (275 << 12)
 297 #define M3_DPLL_DIV_19                  (15 << 8)
 298 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 299                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 300                                         MX_APLLS_CLIKIN_19_2
 301 /* boot (boot) */
 302 #define MB_DPLL_MULT                    (1 << 12)
 303 #define MB_DPLL_DIV                     (0 << 8)
 304 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 305                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 306
 307 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 308                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 309
 310 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 311                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 312
 313 /*
 314  * 2430 - chassis (sedna)
 315  * 165 (ratio1) same as above #2
 316  * 150 (ratio1)
 317  * 133 (ratio2) same as above #4
 318  * 110 (ratio2) same as above #3
 319  * 104 (ratio2)
 320  * boot (boot)
 321  */
 322
 323 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 324 #define MI_DPLL_MULT_12                 (55 << 12)
 325 #define MI_DPLL_DIV_12                  (1 << 8)
 326 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 327                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 328                                         MX_APLLS_CLIKIN_12
 329
 330 /*
 331  * 2420 Equivalent - mode registers
 332  * PRCM II , target DPLL = 2*300MHz = 600MHz
 333  */
 334 #define MII_DPLL_MULT_12                (50 << 12)
 335 #define MII_DPLL_DIV_12                 (1 << 8)
 336 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 337                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 338                                         MX_APLLS_CLIKIN_12
 339 #define MII_DPLL_MULT_13                (300 << 12)
 340 #define MII_DPLL_DIV_13                 (12 << 8)
 341 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 342                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 343                                         MX_APLLS_CLIKIN_13
 344
 345 /* PRCM III target DPLL = 2*266 = 532MHz*/
 346 #define MIII_DPLL_MULT_12               (133 << 12)
 347 #define MIII_DPLL_DIV_12                (5 << 8)
 348 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 349                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 350                                         MX_APLLS_CLIKIN_12
 351 #define MIII_DPLL_MULT_13               (266 << 12)
 352 #define MIII_DPLL_DIV_13                (12 << 8)
 353 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 354                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 355                                         MX_APLLS_CLIKIN_13
 356
 357 /* PRCM VII (boot bypass) */
 358 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 359 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 360
 361 /* High and low operation value */
 362 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 363 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 364
 365 /* MPU speed defines */
 366 #define S12M    12000000
 367 #define S13M    13000000
 368 #define S19M    19200000
 369 #define S26M    26000000
 370 #define S100M   100000000
 371 #define S133M   133000000
 372 #define S150M   150000000
 373 #define S165M   165000000
 374 #define S200M   200000000
 375 #define S266M   266000000
 376 #define S300M   300000000
 377 #define S330M   330000000
 378 #define S400M   400000000
 379 #define S532M   532000000
 380 #define S600M   600000000
 381 #define S660M   660000000
 382
 383 /*-------------------------------------------------------------------------
 384  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 385  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 386  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 387  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 388  *
 389  * Filling in table based on H4 boards and 2430-SDPs variants available.
 390  * There are quite a few more rates combinations which could be defined.
 391  *
 392  * When multiple values are defined the start up will try and choose the
 393  * fastest one. If a 'fast' value is defined, then automatically, the /2
 394  * one should be included as it can be used.    Generally having more that
 395  * one fast set does not make sense, as static timings need to be changed
 396  * to change the set.    The exception is the bypass setting which is
 397  * availble for low power bypass.
 398  *
 399  * Note: This table needs to be sorted, fastest to slowest.
 400  *-------------------------------------------------------------------------*/
 401 static struct prcm_config rate_table[] = {
 402         /* PRCM I - FAST */
 403         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 404                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 405                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 406                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 407                 RATE_IN_242X},
 408
 409         /* PRCM II - FAST */
 410         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 411                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 412                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 413                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 414                 RATE_IN_242X},
 415
 416         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 417                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 418                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 419                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 420                 RATE_IN_242X},
 421
 422         /* PRCM III - FAST */
 423         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 424                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 425                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 426                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 427                 RATE_IN_242X},
 428
 429         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 430                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 431                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 432                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 433                 RATE_IN_242X},
 434
 435         /* PRCM II - SLOW */
 436         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 437                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 438                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 439                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 440                 RATE_IN_242X},
 441
 442         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 443                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 444                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 445                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 446                 RATE_IN_242X},
 447
 448         /* PRCM III - SLOW */
 449         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 450                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 451                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 452                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 453                 RATE_IN_242X},
 454
 455         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 456                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 457                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 459                 RATE_IN_242X},
 460
 461         /* PRCM-VII (boot-bypass) */
 462         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 463                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 464                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 465                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 466                 RATE_IN_242X},
 467
 468         /* PRCM-VII (boot-bypass) */
 469         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 470                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 471                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 472                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 473                 RATE_IN_242X},
 474
 475         /* PRCM #3 - ratio2 (ES2) - FAST */
 476         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 477                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 478                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 479                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 480                 SDRC_RFR_CTRL_110MHz,
 481                 RATE_IN_243X},
 482
 483         /* PRCM #5a - ratio1 - FAST */
 484         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 485                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 486                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 487                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 488                 SDRC_RFR_CTRL_133MHz,
 489                 RATE_IN_243X},
 490
 491         /* PRCM #5b - ratio1 - FAST */
 492         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 493                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 494                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 495                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 496                 SDRC_RFR_CTRL_100MHz,
 497                 RATE_IN_243X},
 498
 499         /* PRCM #3 - ratio2 (ES2) - SLOW */
 500         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 501                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 502                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 504                 SDRC_RFR_CTRL_110MHz,
 505                 RATE_IN_243X},
 506
 507         /* PRCM #5a - ratio1 - SLOW */
 508         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 509                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 510                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 511                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 512                 SDRC_RFR_CTRL_133MHz,
 513                 RATE_IN_243X},
 514
 515         /* PRCM #5b - ratio1 - SLOW*/
 516         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 517                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 518                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 519                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 520                 SDRC_RFR_CTRL_100MHz,
 521                 RATE_IN_243X},
 522
 523         /* PRCM-boot/bypass */
 524         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 525                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 526                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 527                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 528                 SDRC_RFR_CTRL_BYPASS,
 529                 RATE_IN_243X},
 530
 531         /* PRCM-boot/bypass */
 532         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 533                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 534                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 535                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 536                 SDRC_RFR_CTRL_BYPASS,
 537                 RATE_IN_243X},
 538
 539         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 540 };
 541
 542 /*-------------------------------------------------------------------------
 543  * 24xx clock tree.
 544  *
 545  * NOTE:In many cases here we are assigning a 'default' parent. In many
 546  *      cases the parent is selectable. The get/set parent calls will also
 547  *      switch sources.
 548  *
 549  *      Many some clocks say always_enabled, but they can be auto idled for
 550  *      power savings. They will always be available upon clock request.
 551  *
 552  *      Several sources are given initial rates which may be wrong, this will
 553  *      be fixed up in the init func.
 554  *
 555  *      Things are broadly separated below by clock domains. It is
 556  *      noteworthy that most periferals have dependencies on multiple clock
 557  *      domains. Many get their interface clocks from the L4 domain, but get
 558  *      functional clocks from fixed sources or other core domain derived
 559  *      clocks.
 560  *-------------------------------------------------------------------------*/
 561
 562 /* Base external input clocks */
 563 static struct clk func_32k_ck = {
 564         .name           = "func_32k_ck",
 565         .rate           = 32000,
 566         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 567                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 568         .recalc         = &propagate_rate,
 569 };
 570
 571 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 572 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 573         .name           = "osc_ck",
 574         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 575                                 RATE_PROPAGATES,
 576         .enable         = &omap2_enable_osc_ck,
 577         .disable        = &omap2_disable_osc_ck,
 578         .recalc         = &omap2_osc_clk_recalc,
 579 };
 580
 581 /* With out modem likely 12MHz, with modem likely 13MHz */
 582 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 583         .name           = "sys_ck",             /* ~ ref_clk also */
 584         .parent         = &osc_ck,
 585         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 586                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 587         .recalc         = &omap2_sys_clk_recalc,
 588 };
 589
 590 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 591         .name           = "alt_ck",
 592         .rate           = 54000000,
 593         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 594                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 595         .recalc         = &propagate_rate,
 596 };
 597
 598 /*
 599  * Analog domain root source clocks
 600  */
 601
 602 /* dpll_ck, is broken out in to special cases through clksel */
 603 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 604  * deal with this
 605  */
 606
 607 static const struct dpll_data dpll_dd = {
 608         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 609         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 610         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 611         .auto_idle_mask         = OMAP24XX_AUTO_DPLL_MASK,
 612         .auto_idle_val          = 0x3, /* stop DPLL upon idle */
 613 };
 614
 615 static struct clk dpll_ck = {
 616         .name           = "dpll_ck",
 617         .parent         = &sys_ck,              /* Can be func_32k also */
 618         .dpll_data      = &dpll_dd,
 619         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 620                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 621         .recalc         = &omap2_dpll_recalc,
 622         .set_rate       = &omap2_reprogram_dpll,
 623 };
 624
 625 static struct clk apll96_ck = {
 626         .name           = "apll96_ck",
 627         .parent         = &sys_ck,
 628         .rate           = 96000000,
 629         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 630                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 631         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 632         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 633         .enable         = &omap2_clk_fixed_enable,
 634         .disable        = &omap2_clk_fixed_disable,
 635         .recalc         = &propagate_rate,
 636 };
 637
 638 static struct clk apll54_ck = {
 639         .name           = "apll54_ck",
 640         .parent         = &sys_ck,
 641         .rate           = 54000000,
 642         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 643                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 644         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 645         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 646         .enable         = &omap2_clk_fixed_enable,
 647         .disable        = &omap2_clk_fixed_disable,
 648         .recalc         = &propagate_rate,
 649 };
 650
 651 /*
 652  * PRCM digital base sources
 653  */
 654
 655 /* func_54m_ck */
 656
 657 static const struct clksel_rate func_54m_apll54_rates[] = {
 658         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 659         { .div = 0 },
 660 };
 661
 662 static const struct clksel_rate func_54m_alt_rates[] = {
 663         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 664         { .div = 0 },
 665 };
 666
 667 static const struct clksel func_54m_clksel[] = {
 668         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 669         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 670         { .parent = NULL },
 671 };
 672
 673 static struct clk func_54m_ck = {
 674         .name           = "func_54m_ck",
 675         .parent         = &apll54_ck,   /* can also be alt_clk */
 676         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 677                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 678         .init           = &omap2_init_clksel_parent,
 679         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 680         .clksel_mask    = OMAP24XX_54M_SOURCE,
 681         .clksel         = func_54m_clksel,
 682         .recalc         = &omap2_clksel_recalc,
 683 };
 684
 685 static struct clk core_ck = {
 686         .name           = "core_ck",
 687         .parent         = &dpll_ck,             /* can also be 32k */
 688         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 689                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 690         .recalc         = &followparent_recalc,
 691 };
 692
 693 /* func_96m_ck */
 694 static const struct clksel_rate func_96m_apll96_rates[] = {
 695         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 696         { .div = 0 },
 697 };
 698
 699 static const struct clksel_rate func_96m_alt_rates[] = {
 700         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 701         { .div = 0 },
 702 };
 703
 704 static const struct clksel func_96m_clksel[] = {
 705         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 706         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 707         { .parent = NULL }
 708 };
 709
 710 /* The parent of this clock is not selectable on 2420. */
 711 static struct clk func_96m_ck = {
 712         .name           = "func_96m_ck",
 713         .parent         = &apll96_ck,
 714         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 715                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 716         .init           = &omap2_init_clksel_parent,
 717         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 718         .clksel_mask    = OMAP2430_96M_SOURCE,
 719         .clksel         = func_96m_clksel,
 720         .recalc         = &omap2_clksel_recalc,
 721         .round_rate     = &omap2_clksel_round_rate,
 722         .set_rate       = &omap2_clksel_set_rate
 723 };
 724
 725 /* func_48m_ck */
 726
 727 static const struct clksel_rate func_48m_apll96_rates[] = {
 728         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 729         { .div = 0 },
 730 };
 731
 732 static const struct clksel_rate func_48m_alt_rates[] = {
 733         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 734         { .div = 0 },
 735 };
 736
 737 static const struct clksel func_48m_clksel[] = {
 738         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 739         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 740         { .parent = NULL }
 741 };
 742
 743 static struct clk func_48m_ck = {
 744         .name           = "func_48m_ck",
 745         .parent         = &apll96_ck,    /* 96M or Alt */
 746         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 747                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 748         .init           = &omap2_init_clksel_parent,
 749         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 750         .clksel_mask    = OMAP24XX_48M_SOURCE,
 751         .clksel         = func_48m_clksel,
 752         .recalc         = &omap2_clksel_recalc,
 753         .round_rate     = &omap2_clksel_round_rate,
 754         .set_rate       = &omap2_clksel_set_rate
 755 };
 756
 757 static struct clk func_12m_ck = {
 758         .name           = "func_12m_ck",
 759         .parent         = &func_48m_ck,
 760         .fixed_div      = 4,
 761         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 762                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 763         .recalc         = &omap2_fixed_divisor_recalc,
 764 };
 765
 766 /* Secure timer, only available in secure mode */
 767 static struct clk wdt1_osc_ck = {
 768         .name           = "ck_wdt1_osc",
 769         .parent         = &osc_ck,
 770         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 771         .recalc         = &followparent_recalc,
 772 };
 773
 774 /*
 775  * The common_clkout* clksel_rate structs are common to
 776  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 777  * sys_clkout2_* are 2420-only, so the
 778  * clksel_rate flags fields are inaccurate for those clocks. This is
 779  * harmless since access to those clocks are gated by the struct clk
 780  * flags fields, which mark them as 2420-only.
 781  */
 782 static const struct clksel_rate common_clkout_src_core_rates[] = {
 783         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 784         { .div = 0 }
 785 };
 786
 787 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 788         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 789         { .div = 0 }
 790 };
 791
 792 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 793         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 794         { .div = 0 }
 795 };
 796
 797 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 798         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 799         { .div = 0 }
 800 };
 801
 802 static const struct clksel common_clkout_src_clksel[] = {
 803         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 804         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 805         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 806         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 807         { .parent = NULL }
 808 };
 809
 810 static struct clk sys_clkout_src = {
 811         .name           = "sys_clkout_src",
 812         .parent         = &func_54m_ck,
 813         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 814                                 RATE_PROPAGATES,
 815         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 816         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 817         .init           = &omap2_init_clksel_parent,
 818         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 819         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 820         .clksel         = common_clkout_src_clksel,
 821         .recalc         = &omap2_clksel_recalc,
 822         .round_rate     = &omap2_clksel_round_rate,
 823         .set_rate       = &omap2_clksel_set_rate
 824 };
 825
 826 static const struct clksel_rate common_clkout_rates[] = {
 827         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 828         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 829         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 830         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 831         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 832         { .div = 0 },
 833 };
 834
 835 static const struct clksel sys_clkout_clksel[] = {
 836         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 837         { .parent = NULL }
 838 };
 839
 840 static struct clk sys_clkout = {
 841         .name           = "sys_clkout",
 842         .parent         = &sys_clkout_src,
 843         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 844                                 PARENT_CONTROLS_CLOCK,
 845         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 846         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 847         .clksel         = sys_clkout_clksel,
 848         .recalc         = &omap2_clksel_recalc,
 849         .round_rate     = &omap2_clksel_round_rate,
 850         .set_rate       = &omap2_clksel_set_rate
 851 };
 852
 853 /* In 2430, new in 2420 ES2 */
 854 static struct clk sys_clkout2_src = {
 855         .name           = "sys_clkout2_src",
 856         .parent         = &func_54m_ck,
 857         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 858         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 859         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 860         .init           = &omap2_init_clksel_parent,
 861         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 862         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 863         .clksel         = common_clkout_src_clksel,
 864         .recalc         = &omap2_clksel_recalc,
 865         .round_rate     = &omap2_clksel_round_rate,
 866         .set_rate       = &omap2_clksel_set_rate
 867 };
 868
 869 static const struct clksel sys_clkout2_clksel[] = {
 870         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 871         { .parent = NULL }
 872 };
 873
 874 /* In 2430, new in 2420 ES2 */
 875 static struct clk sys_clkout2 = {
 876         .name           = "sys_clkout2",
 877         .parent         = &sys_clkout2_src,
 878         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 879         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 880         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 881         .clksel         = sys_clkout2_clksel,
 882         .recalc         = &omap2_clksel_recalc,
 883         .round_rate     = &omap2_clksel_round_rate,
 884         .set_rate       = &omap2_clksel_set_rate
 885 };
 886
 887 static struct clk emul_ck = {
 888         .name           = "emul_ck",
 889         .parent         = &func_54m_ck,
 890         .flags          = CLOCK_IN_OMAP242X,
 891         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 892         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 893         .recalc         = &followparent_recalc,
 894
 895 };
 896
 897 /*
 898  * MPU clock domain
 899  *      Clocks:
 900  *              MPU_FCLK, MPU_ICLK
 901  *              INT_M_FCLK, INT_M_I_CLK
 902  *
 903  * - Individual clocks are hardware managed.
 904  * - Base divider comes from: CM_CLKSEL_MPU
 905  *
 906  */
 907 static const struct clksel_rate mpu_core_rates[] = {
 908         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 909         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 910         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 911         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 912         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 913         { .div = 0 },
 914 };
 915
 916 static const struct clksel mpu_clksel[] = {
 917         { .parent = &core_ck, .rates = mpu_core_rates },
 918         { .parent = NULL }
 919 };
 920
 921 static struct clk mpu_ck = {    /* Control cpu */
 922         .name           = "mpu_ck",
 923         .parent         = &core_ck,
 924         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 925                                 ALWAYS_ENABLED | DELAYED_APP |
 926                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 927         .init           = &omap2_init_clksel_parent,
 928         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 929         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 930         .clksel         = mpu_clksel,
 931         .recalc         = &omap2_clksel_recalc,
 932         .round_rate     = &omap2_clksel_round_rate,
 933         .set_rate       = &omap2_clksel_set_rate
 934 };
 935
 936 /*
 937  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 938  * Clocks:
 939  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 940  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 941  */
 942 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 943  * they should just be treated as such.
 944  */
 945
 946 /* iva2_1_fck */
 947 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 948         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 949         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 950         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 951         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 952         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 953         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 954         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 955         { .div = 0 },
 956 };
 957
 958 static const struct clksel iva2_1_fck_clksel[] = {
 959         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 960         { .parent = NULL }
 961 };
 962
 963 static struct clk iva2_1_fck = {
 964         .name           = "iva2_1_fck",
 965         .parent         = &core_ck,
 966         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
 967                                 CONFIG_PARTICIPANT,
 968         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 969         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 970         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 971         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 972         .clksel         = iva2_1_fck_clksel,
 973         .recalc         = &omap2_clksel_recalc,
 974         .round_rate     = &omap2_clksel_round_rate,
 975         .set_rate       = &omap2_clksel_set_rate
 976 };
 977
 978 /* iva2_1_ick */
 979 static const struct clksel_rate iva2_1_ick_core_rates[] = {
 980         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 981         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 982         { .div = 3, .val = 3, .flags = RATE_IN_243X },
 983         { .div = 0 },
 984 };
 985
 986 static const struct clksel iva2_1_ick_clksel[] = {
 987         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
 988         { .parent = NULL }
 989 };
 990
 991 static struct clk iva2_1_ick = {
 992         .name           = "iva2_1_ick",
 993         .parent         = &iva2_1_fck,
 994         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
 995         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 996         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
 997         .clksel         = iva2_1_ick_clksel,
 998         .recalc         = &omap2_clksel_recalc,
 999         .round_rate     = &omap2_clksel_round_rate,
1000         .set_rate       = &omap2_clksel_set_rate
1001 };
1002
1003 /*
1004  * Won't be too specific here. The core clock comes into this block
1005  * it is divided then tee'ed. One branch goes directly to xyz enable
1006  * controls. The other branch gets further divided by 2 then possibly
1007  * routed into a synchronizer and out of clocks abc.
1008  */
1009 static const struct clksel_rate dsp_fck_core_rates[] = {
1010         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1011         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1012         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1013         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1014         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1015         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1016         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1017         { .div = 0 },
1018 };
1019
1020 static const struct clksel dsp_fck_clksel[] = {
1021         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1022         { .parent = NULL }
1023 };
1024
1025 static struct clk dsp_fck = {
1026         .name           = "dsp_fck",
1027         .parent         = &core_ck,
1028         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP |
1029                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1030         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1031         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1032         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1033         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1034         .clksel         = dsp_fck_clksel,
1035         .recalc         = &omap2_clksel_recalc,
1036         .round_rate     = &omap2_clksel_round_rate,
1037         .set_rate       = &omap2_clksel_set_rate
1038 };
1039
1040 static const struct clksel_rate dsp_ick_core_rates[] = {
1041         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1042         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1043         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1044         { .div = 0 },
1045 };
1046
1047 static const struct clksel dsp_ick_clksel[] = {
1048         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1049         { .parent = NULL }
1050 };
1051
1052 static struct clk dsp_ick = {
1053         .name           = "dsp_ick",     /* apparently ipi and isp */
1054         .parent         = &core_ck,
1055         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1056         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1057         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1058         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1059         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1060         .clksel         = dsp_ick_clksel,
1061         .recalc         = &omap2_clksel_recalc,
1062 };
1063
1064 static const struct clksel_rate iva1_ifck_core_rates[] = {
1065         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1066         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1067         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1068         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1069         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1070         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1071         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1072         { .div = 0 },
1073 };
1074
1075 static const struct clksel iva1_ifck_clksel[] = {
1076         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1077         { .parent = NULL }
1078 };
1079
1080 static struct clk iva1_ifck = {
1081         .name           = "iva1_ifck",
1082         .parent         = &core_ck,
1083         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1084                                 RATE_PROPAGATES | DELAYED_APP,
1085         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1086         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1087         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1088         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1089         .clksel         = iva1_ifck_clksel,
1090         .recalc         = &omap2_clksel_recalc,
1091         .round_rate     = &omap2_clksel_round_rate,
1092         .set_rate       = &omap2_clksel_set_rate
1093 };
1094
1095 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1096 static struct clk iva1_mpu_int_ifck = {
1097         .name           = "iva1_mpu_int_ifck",
1098         .parent         = &iva1_ifck,
1099         .flags          = CLOCK_IN_OMAP242X,
1100         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1101         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1102         .fixed_div      = 2,
1103         .recalc         = &omap2_fixed_divisor_recalc,
1104 };
1105
1106 /*
1107  * L3 clock domain
1108  * L3 clocks are used for both interface and functional clocks to
1109  * multiple entities. Some of these clocks are completely managed
1110  * by hardware, and some others allow software control. Hardware
1111  * managed ones general are based on directly CLK_REQ signals and
1112  * various auto idle settings. The functional spec sets many of these
1113  * as 'tie-high' for their enables.
1114  *
1115  * I-CLOCKS:
1116  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1117  *      CAM, HS-USB.
1118  * F-CLOCK
1119  *      SSI.
1120  *
1121  * GPMC memories and SDRC have timing and clock sensitive registers which
1122  * may very well need notification when the clock changes. Currently for low
1123  * operating points, these are taken care of in sleep.S.
1124  */
1125 static const struct clksel_rate core_l3_core_rates[] = {
1126         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1127         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1128         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1129         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1130         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1131         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1132         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1133         { .div = 0 }
1134 };
1135
1136 static const struct clksel core_l3_clksel[] = {
1137         { .parent = &core_ck, .rates = core_l3_core_rates },
1138         { .parent = NULL }
1139 };
1140
1141 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1142         .name           = "core_l3_ck",
1143         .parent         = &core_ck,
1144         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1145                                 ALWAYS_ENABLED | DELAYED_APP |
1146                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1147         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1148         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1149         .clksel         = core_l3_clksel,
1150         .recalc         = &omap2_clksel_recalc,
1151         .round_rate     = &omap2_clksel_round_rate,
1152         .set_rate       = &omap2_clksel_set_rate
1153 };
1154
1155 /* usb_l4_ick */
1156 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1157         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1158         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1159         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1160         { .div = 0 }
1161 };
1162
1163 static const struct clksel usb_l4_ick_clksel[] = {
1164         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1165         { .parent = NULL },
1166 };
1167
1168 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1169         .name           = "usb_l4_ick",
1170         .parent         = &core_l3_ck,
1171         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1172                                 DELAYED_APP | CONFIG_PARTICIPANT,
1173         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1174         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1175         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1176         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1177         .clksel         = usb_l4_ick_clksel,
1178         .recalc         = &omap2_clksel_recalc,
1179         .round_rate     = &omap2_clksel_round_rate,
1180         .set_rate       = &omap2_clksel_set_rate
1181 };
1182
1183 /*
1184  * SSI is in L3 management domain, its direct parent is core not l3,
1185  * many core power domain entities are grouped into the L3 clock
1186  * domain.
1187  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1188  *
1189  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1190  */
1191 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1192         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1193         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1194         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1195         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1196         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1197         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1198         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1199         { .div = 0 }
1200 };
1201
1202 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1203         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1204         { .parent = NULL }
1205 };
1206
1207 static struct clk ssi_ssr_sst_fck = {
1208         .name           = "ssi_fck",
1209         .parent         = &core_ck,
1210         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1211                                 DELAYED_APP,
1212         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1213         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1214         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1215         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1216         .clksel         = ssi_ssr_sst_fck_clksel,
1217         .recalc         = &omap2_clksel_recalc,
1218         .round_rate     = &omap2_clksel_round_rate,
1219         .set_rate       = &omap2_clksel_set_rate
1220 };
1221
1222 /*
1223  * GFX clock domain
1224  *      Clocks:
1225  * GFX_FCLK, GFX_ICLK
1226  * GFX_CG1(2d), GFX_CG2(3d)
1227  *
1228  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1229  * The 2d and 3d clocks run at a hardware determined
1230  * divided value of fclk.
1231  *
1232  */
1233 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1234
1235 /*
1236  * These clksel_rate/clksel structs are shared between gfx_3d_fck and
1237  * gfx_2d_fck
1238  */
1239 static const struct clksel_rate gfx_fck_core_l3_rates[] = {
1240         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1241         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1242         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1243         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1244         { .div = 0 }
1245 };
1246
1247 static const struct clksel gfx_fck_clksel[] = {
1248         { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
1249         { .parent = NULL },
1250 };
1251
1252 static struct clk gfx_3d_fck = {
1253         .name           = "gfx_3d_fck",
1254         .parent         = &core_l3_ck,
1255         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1256         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1257         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1258         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1259         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1260         .clksel         = gfx_fck_clksel,
1261         .recalc         = &omap2_clksel_recalc,
1262         .round_rate     = &omap2_clksel_round_rate,
1263         .set_rate       = &omap2_clksel_set_rate
1264 };
1265
1266 static struct clk gfx_2d_fck = {
1267         .name           = "gfx_2d_fck",
1268         .parent         = &core_l3_ck,
1269         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1270         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1271         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1272         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1273         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1274         .clksel         = gfx_fck_clksel,
1275         .recalc         = &omap2_clksel_recalc,
1276         .round_rate     = &omap2_clksel_round_rate,
1277         .set_rate       = &omap2_clksel_set_rate
1278 };
1279
1280 static struct clk gfx_ick = {
1281         .name           = "gfx_ick",            /* From l3 */
1282         .parent         = &core_l3_ck,
1283         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1284         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1285         .enable_bit     = OMAP_EN_GFX_SHIFT,
1286         .recalc         = &followparent_recalc,
1287 };
1288
1289 /*
1290  * Modem clock domain (2430)
1291  *      CLOCKS:
1292  *              MDM_OSC_CLK
1293  *              MDM_ICLK
1294  * These clocks are usable in chassis mode only.
1295  */
1296 static const struct clksel_rate mdm_ick_core_rates[] = {
1297         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1298         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1299         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1300         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1301         { .div = 0 }
1302 };
1303
1304 static const struct clksel mdm_ick_clksel[] = {
1305         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1306         { .parent = NULL }
1307 };
1308
1309 static struct clk mdm_ick = {           /* used both as a ick and fck */
1310         .name           = "mdm_ick",
1311         .parent         = &core_ck,
1312         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1313         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1314         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1315         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1316         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1317         .clksel         = mdm_ick_clksel,
1318         .recalc         = &omap2_clksel_recalc,
1319         .round_rate     = &omap2_clksel_round_rate,
1320         .set_rate       = &omap2_clksel_set_rate
1321 };
1322
1323 static struct clk mdm_osc_ck = {
1324         .name           = "mdm_osc_ck",
1325         .parent         = &osc_ck,
1326         .flags          = CLOCK_IN_OMAP243X,
1327         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
1328         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1329         .recalc         = &followparent_recalc,
1330 };
1331
1332 /*
1333  * L4 clock management domain
1334  *
1335  * This domain contains lots of interface clocks from the L4 interface, some
1336  * functional clocks.   Fixed APLL functional source clocks are managed in
1337  * this domain.
1338  */
1339 static const struct clksel_rate l4_core_l3_rates[] = {
1340         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1341         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1342         { .div = 0 }
1343 };
1344
1345 static const struct clksel l4_clksel[] = {
1346         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1347         { .parent = NULL }
1348 };
1349
1350 static struct clk l4_ck = {             /* used both as an ick and fck */
1351         .name           = "l4_ck",
1352         .parent         = &core_l3_ck,
1353         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1354                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1355         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1356         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1357         .clksel         = l4_clksel,
1358         .recalc         = &omap2_clksel_recalc,
1359         .round_rate     = &omap2_clksel_round_rate,
1360         .set_rate       = &omap2_clksel_set_rate
1361 };
1362
1363 static struct clk ssi_l4_ick = {
1364         .name           = "ssi_l4_ick",
1365         .parent         = &l4_ck,
1366         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1367         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1368         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1369         .recalc         = &followparent_recalc,
1370 };
1371
1372 /*
1373  * DSS clock domain
1374  * CLOCKs:
1375  * DSS_L4_ICLK, DSS_L3_ICLK,
1376  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1377  *
1378  * DSS is both initiator and target.
1379  */
1380 /* XXX Add RATE_NOT_VALIDATED */
1381
1382 static const struct clksel_rate dss1_fck_sys_rates[] = {
1383         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1384         { .div = 0 }
1385 };
1386
1387 static const struct clksel_rate dss1_fck_core_rates[] = {
1388         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1389         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1390         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1391         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1392         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1393         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1394         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1395         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1396         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1397         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1398         { .div = 0 }
1399 };
1400
1401 static const struct clksel dss1_fck_clksel[] = {
1402         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1403         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1404         { .parent = NULL },
1405 };
1406
1407 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1408         .name           = "dss_ick",
1409         .parent         = &l4_ck,       /* really both l3 and l4 */
1410         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1411         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1412         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 static struct clk dss1_fck = {
1417         .name           = "dss1_fck",
1418         .parent         = &core_ck,             /* Core or sys */
1419         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1420                                 DELAYED_APP,
1421         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1422         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1423         .init           = &omap2_init_clksel_parent,
1424         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1425         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1426         .clksel         = dss1_fck_clksel,
1427         .recalc         = &omap2_clksel_recalc,
1428         .round_rate     = &omap2_clksel_round_rate,
1429         .set_rate       = &omap2_clksel_set_rate
1430 };
1431
1432 static const struct clksel_rate dss2_fck_sys_rates[] = {
1433         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1434         { .div = 0 }
1435 };
1436
1437 static const struct clksel_rate dss2_fck_48m_rates[] = {
1438         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1439         { .div = 0 }
1440 };
1441
1442 static const struct clksel dss2_fck_clksel[] = {
1443         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1444         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1445         { .parent = NULL }
1446 };
1447
1448 static struct clk dss2_fck = {          /* Alt clk used in power management */
1449         .name           = "dss2_fck",
1450         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1451         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1452                                 DELAYED_APP,
1453         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1455         .init           = &omap2_init_clksel_parent,
1456         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1457         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1458         .clksel         = dss2_fck_clksel,
1459         .recalc         = &followparent_recalc,
1460 };
1461
1462 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1463         .name           = "dss_54m_fck",        /* 54m tv clk */
1464         .parent         = &func_54m_ck,
1465         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1466         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1467         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 /*
1472  * CORE power domain ICLK & FCLK defines.
1473  * Many of the these can have more than one possible parent. Entries
1474  * here will likely have an L4 interface parent, and may have multiple
1475  * functional clock parents.
1476  */
1477 static const struct clksel_rate gpt_32k_rates[] = {
1478         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1479         { .div = 0 }
1480 };
1481
1482 static const struct clksel_rate gpt_sys_rates[] = {
1483         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1484         { .div = 0 }
1485 };
1486
1487 static const struct clksel_rate gpt_alt_rates[] = {
1488         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1489         { .div = 0 }
1490 };
1491
1492 static const struct clksel gpt_clksel[] = {
1493         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1494         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1495         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1496         { .parent = NULL },
1497 };
1498
1499 static struct clk gpt1_ick = {
1500         .name           = "gpt1_ick",
1501         .parent         = &l4_ck,
1502         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1503         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1504         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1505         .recalc         = &followparent_recalc,
1506 };
1507
1508 static struct clk gpt1_fck = {
1509         .name           = "gpt1_fck",
1510         .parent         = &func_32k_ck,
1511         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1512         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1513         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1514         .init           = &omap2_init_clksel_parent,
1515         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1516         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1517         .clksel         = gpt_clksel,
1518         .recalc         = &omap2_clksel_recalc,
1519         .round_rate     = &omap2_clksel_round_rate,
1520         .set_rate       = &omap2_clksel_set_rate
1521 };
1522
1523 static struct clk gpt2_ick = {
1524         .name           = "gpt2_ick",
1525         .parent         = &l4_ck,
1526         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1527         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1528         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1529         .recalc         = &followparent_recalc,
1530 };
1531
1532 static struct clk gpt2_fck = {
1533         .name           = "gpt2_fck",
1534         .parent         = &func_32k_ck,
1535         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1538         .init           = &omap2_init_clksel_parent,
1539         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1540         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1541         .clksel         = gpt_clksel,
1542         .recalc         = &omap2_clksel_recalc,
1543 };
1544
1545 static struct clk gpt3_ick = {
1546         .name           = "gpt3_ick",
1547         .parent         = &l4_ck,
1548         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1550         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk gpt3_fck = {
1555         .name           = "gpt3_fck",
1556         .parent         = &func_32k_ck,
1557         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1558         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1560         .init           = &omap2_init_clksel_parent,
1561         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1562         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1563         .clksel         = gpt_clksel,
1564         .recalc         = &omap2_clksel_recalc,
1565 };
1566
1567 static struct clk gpt4_ick = {
1568         .name           = "gpt4_ick",
1569         .parent         = &l4_ck,
1570         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1572         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk gpt4_fck = {
1577         .name           = "gpt4_fck",
1578         .parent         = &func_32k_ck,
1579         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1582         .init           = &omap2_init_clksel_parent,
1583         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1584         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1585         .clksel         = gpt_clksel,
1586         .recalc         = &omap2_clksel_recalc,
1587 };
1588
1589 static struct clk gpt5_ick = {
1590         .name           = "gpt5_ick",
1591         .parent         = &l4_ck,
1592         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1593         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1594         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1595         .recalc         = &followparent_recalc,
1596 };
1597
1598 static struct clk gpt5_fck = {
1599         .name           = "gpt5_fck",
1600         .parent         = &func_32k_ck,
1601         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1602         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1603         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1604         .init           = &omap2_init_clksel_parent,
1605         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1606         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1607         .clksel         = gpt_clksel,
1608         .recalc         = &omap2_clksel_recalc,
1609 };
1610
1611 static struct clk gpt6_ick = {
1612         .name           = "gpt6_ick",
1613         .parent         = &l4_ck,
1614         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1615         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1616         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1617         .recalc         = &followparent_recalc,
1618 };
1619
1620 static struct clk gpt6_fck = {
1621         .name           = "gpt6_fck",
1622         .parent         = &func_32k_ck,
1623         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1624         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1625         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1626         .init           = &omap2_init_clksel_parent,
1627         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1628         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1629         .clksel         = gpt_clksel,
1630         .recalc         = &omap2_clksel_recalc,
1631 };
1632
1633 static struct clk gpt7_ick = {
1634         .name           = "gpt7_ick",
1635         .parent         = &l4_ck,
1636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1637         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1638         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1639         .recalc         = &followparent_recalc,
1640 };
1641
1642 static struct clk gpt7_fck = {
1643         .name           = "gpt7_fck",
1644         .parent         = &func_32k_ck,
1645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1647         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1648         .init           = &omap2_init_clksel_parent,
1649         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1650         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1651         .clksel         = gpt_clksel,
1652         .recalc         = &omap2_clksel_recalc,
1653 };
1654
1655 static struct clk gpt8_ick = {
1656         .name           = "gpt8_ick",
1657         .parent         = &l4_ck,
1658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1659         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1660         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 static struct clk gpt8_fck = {
1665         .name           = "gpt8_fck",
1666         .parent         = &func_32k_ck,
1667         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1668         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1669         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1670         .init           = &omap2_init_clksel_parent,
1671         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1672         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1673         .clksel         = gpt_clksel,
1674         .recalc         = &omap2_clksel_recalc,
1675 };
1676
1677 static struct clk gpt9_ick = {
1678         .name           = "gpt9_ick",
1679         .parent         = &l4_ck,
1680         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1681         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1682         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1683         .recalc         = &followparent_recalc,
1684 };
1685
1686 static struct clk gpt9_fck = {
1687         .name           = "gpt9_fck",
1688         .parent         = &func_32k_ck,
1689         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1690         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1691         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1692         .init           = &omap2_init_clksel_parent,
1693         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1694         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1695         .clksel         = gpt_clksel,
1696         .recalc         = &omap2_clksel_recalc,
1697 };
1698
1699 static struct clk gpt10_ick = {
1700         .name           = "gpt10_ick",
1701         .parent         = &l4_ck,
1702         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1703         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1704         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1705         .recalc         = &followparent_recalc,
1706 };
1707
1708 static struct clk gpt10_fck = {
1709         .name           = "gpt10_fck",
1710         .parent         = &func_32k_ck,
1711         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1712         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1713         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1714         .init           = &omap2_init_clksel_parent,
1715         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1716         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1717         .clksel         = gpt_clksel,
1718         .recalc         = &omap2_clksel_recalc,
1719 };
1720
1721 static struct clk gpt11_ick = {
1722         .name           = "gpt11_ick",
1723         .parent         = &l4_ck,
1724         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1725         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1726         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1727         .recalc         = &followparent_recalc,
1728 };
1729
1730 static struct clk gpt11_fck = {
1731         .name           = "gpt11_fck",
1732         .parent         = &func_32k_ck,
1733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1735         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1736         .init           = &omap2_init_clksel_parent,
1737         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1738         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1739         .clksel         = gpt_clksel,
1740         .recalc         = &omap2_clksel_recalc,
1741 };
1742
1743 static struct clk gpt12_ick = {
1744         .name           = "gpt12_ick",
1745         .parent         = &l4_ck,
1746         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1747         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1749         .recalc         = &followparent_recalc,
1750 };
1751
1752 static struct clk gpt12_fck = {
1753         .name           = "gpt12_fck",
1754         .parent         = &func_32k_ck,
1755         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1757         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1758         .init           = &omap2_init_clksel_parent,
1759         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1760         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1761         .clksel         = gpt_clksel,
1762         .recalc         = &omap2_clksel_recalc,
1763 };
1764
1765 static struct clk mcbsp1_ick = {
1766         .name           = "mcbsp1_ick",
1767         .parent         = &l4_ck,
1768         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1769         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1770         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk mcbsp1_fck = {
1775         .name           = "mcbsp1_fck",
1776         .parent         = &func_96m_ck,
1777         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1778         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1779         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1780         .recalc         = &followparent_recalc,
1781 };
1782
1783 static struct clk mcbsp2_ick = {
1784         .name           = "mcbsp2_ick",
1785         .parent         = &l4_ck,
1786         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1787         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1789         .recalc         = &followparent_recalc,
1790 };
1791
1792 static struct clk mcbsp2_fck = {
1793         .name           = "mcbsp2_fck",
1794         .parent         = &func_96m_ck,
1795         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1796         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1797         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1798         .recalc         = &followparent_recalc,
1799 };
1800
1801 static struct clk mcbsp3_ick = {
1802         .name           = "mcbsp3_ick",
1803         .parent         = &l4_ck,
1804         .flags          = CLOCK_IN_OMAP243X,
1805         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1806         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1807         .recalc         = &followparent_recalc,
1808 };
1809
1810 static struct clk mcbsp3_fck = {
1811         .name           = "mcbsp3_fck",
1812         .parent         = &func_96m_ck,
1813         .flags          = CLOCK_IN_OMAP243X,
1814         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1815         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 static struct clk mcbsp4_ick = {
1820         .name           = "mcbsp4_ick",
1821         .parent         = &l4_ck,
1822         .flags          = CLOCK_IN_OMAP243X,
1823         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1824         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk mcbsp4_fck = {
1829         .name           = "mcbsp4_fck",
1830         .parent         = &func_96m_ck,
1831         .flags          = CLOCK_IN_OMAP243X,
1832         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1833         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk mcbsp5_ick = {
1838         .name           = "mcbsp5_ick",
1839         .parent         = &l4_ck,
1840         .flags          = CLOCK_IN_OMAP243X,
1841         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1842         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1843         .recalc         = &followparent_recalc,
1844 };
1845
1846 static struct clk mcbsp5_fck = {
1847         .name           = "mcbsp5_fck",
1848         .parent         = &func_96m_ck,
1849         .flags          = CLOCK_IN_OMAP243X,
1850         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1851         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk mcspi1_ick = {
1856         .name           = "mcspi_ick",
1857         .id             = 1,
1858         .parent         = &l4_ck,
1859         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1860         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1861         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1862         .recalc         = &followparent_recalc,
1863 };
1864
1865 static struct clk mcspi1_fck = {
1866         .name           = "mcspi_fck",
1867         .id             = 1,
1868         .parent         = &func_48m_ck,
1869         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1870         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1871         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1872         .recalc         = &followparent_recalc,
1873 };
1874
1875 static struct clk mcspi2_ick = {
1876         .name           = "mcspi_ick",
1877         .id             = 2,
1878         .parent         = &l4_ck,
1879         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1880         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk mcspi2_fck = {
1886         .name           = "mcspi_fck",
1887         .id             = 2,
1888         .parent         = &func_48m_ck,
1889         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1890         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1891         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk mcspi3_ick = {
1896         .name           = "mcspi_ick",
1897         .id             = 3,
1898         .parent         = &l4_ck,
1899         .flags          = CLOCK_IN_OMAP243X,
1900         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1901         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1902         .recalc         = &followparent_recalc,
1903 };
1904
1905 static struct clk mcspi3_fck = {
1906         .name           = "mcspi_fck",
1907         .id             = 3,
1908         .parent         = &func_48m_ck,
1909         .flags          = CLOCK_IN_OMAP243X,
1910         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1911         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1912         .recalc         = &followparent_recalc,
1913 };
1914
1915 static struct clk uart1_ick = {
1916         .name           = "uart1_ick",
1917         .parent         = &l4_ck,
1918         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1919         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1920         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1921         .recalc         = &followparent_recalc,
1922 };
1923
1924 static struct clk uart1_fck = {
1925         .name           = "uart1_fck",
1926         .parent         = &func_48m_ck,
1927         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1928         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1929         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1930         .recalc         = &followparent_recalc,
1931 };
1932
1933 static struct clk uart2_ick = {
1934         .name           = "uart2_ick",
1935         .parent         = &l4_ck,
1936         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1937         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1938         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1939         .recalc         = &followparent_recalc,
1940 };
1941
1942 static struct clk uart2_fck = {
1943         .name           = "uart2_fck",
1944         .parent         = &func_48m_ck,
1945         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1946         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1947         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1948         .recalc         = &followparent_recalc,
1949 };
1950
1951 static struct clk uart3_ick = {
1952         .name           = "uart3_ick",
1953         .parent         = &l4_ck,
1954         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1955         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1956         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk uart3_fck = {
1961         .name           = "uart3_fck",
1962         .parent         = &func_48m_ck,
1963         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1964         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1965         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1966         .recalc         = &followparent_recalc,
1967 };
1968
1969 static struct clk gpios_ick = {
1970         .name           = "gpios_ick",
1971         .parent         = &l4_ck,
1972         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1973         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1974         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1975         .recalc         = &followparent_recalc,
1976 };
1977
1978 static struct clk gpios_fck = {
1979         .name           = "gpios_fck",
1980         .parent         = &func_32k_ck,
1981         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1982         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1983         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1984         .recalc         = &followparent_recalc,
1985 };
1986
1987 static struct clk mpu_wdt_ick = {
1988         .name           = "mpu_wdt_ick",
1989         .parent         = &l4_ck,
1990         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1991         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1992         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1993         .recalc         = &followparent_recalc,
1994 };
1995
1996 static struct clk mpu_wdt_fck = {
1997         .name           = "mpu_wdt_fck",
1998         .parent         = &func_32k_ck,
1999         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2000         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2001         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2002         .recalc         = &followparent_recalc,
2003 };
2004
2005 static struct clk sync_32k_ick = {
2006         .name           = "sync_32k_ick",
2007         .parent         = &l4_ck,
2008         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2009         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2010         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2011         .recalc         = &followparent_recalc,
2012 };
2013 static struct clk wdt1_ick = {
2014         .name           = "wdt1_ick",
2015         .parent         = &l4_ck,
2016         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2017         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2018         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2019         .recalc         = &followparent_recalc,
2020 };
2021 static struct clk omapctrl_ick = {
2022         .name           = "omapctrl_ick",
2023         .parent         = &l4_ck,
2024         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2025         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2026         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2027         .recalc         = &followparent_recalc,
2028 };
2029 static struct clk icr_ick = {
2030         .name           = "icr_ick",
2031         .parent         = &l4_ck,
2032         .flags          = CLOCK_IN_OMAP243X,
2033         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2034         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2035         .recalc         = &followparent_recalc,
2036 };
2037
2038 static struct clk cam_ick = {
2039         .name           = "cam_ick",
2040         .parent         = &l4_ck,
2041         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2042         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2043         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2044         .recalc         = &followparent_recalc,
2045 };
2046
2047 static struct clk cam_fck = {
2048         .name           = "cam_fck",
2049         .parent         = &func_96m_ck,
2050         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2051         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2052         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2053         .recalc         = &followparent_recalc,
2054 };
2055
2056 static struct clk mailboxes_ick = {
2057         .name           = "mailboxes_ick",
2058         .parent         = &l4_ck,
2059         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2060         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2061         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2062         .recalc         = &followparent_recalc,
2063 };
2064
2065 static struct clk wdt4_ick = {
2066         .name           = "wdt4_ick",
2067         .parent         = &l4_ck,
2068         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2069         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2070         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2071         .recalc         = &followparent_recalc,
2072 };
2073
2074 static struct clk wdt4_fck = {
2075         .name           = "wdt4_fck",
2076         .parent         = &func_32k_ck,
2077         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2078         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2079         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2080         .recalc         = &followparent_recalc,
2081 };
2082
2083 static struct clk wdt3_ick = {
2084         .name           = "wdt3_ick",
2085         .parent         = &l4_ck,
2086         .flags          = CLOCK_IN_OMAP242X,
2087         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2088         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2089         .recalc         = &followparent_recalc,
2090 };
2091
2092 static struct clk wdt3_fck = {
2093         .name           = "wdt3_fck",
2094         .parent         = &func_32k_ck,
2095         .flags          = CLOCK_IN_OMAP242X,
2096         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2097         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2098         .recalc         = &followparent_recalc,
2099 };
2100
2101 static struct clk mspro_ick = {
2102         .name           = "mspro_ick",
2103         .parent         = &l4_ck,
2104         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2105         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2106         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2107         .recalc         = &followparent_recalc,
2108 };
2109
2110 static struct clk mspro_fck = {
2111         .name           = "mspro_fck",
2112         .parent         = &func_96m_ck,
2113         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2114         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2115         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2116         .recalc         = &followparent_recalc,
2117 };
2118
2119 static struct clk mmc_ick = {
2120         .name           = "mmc_ick",
2121         .parent         = &l4_ck,
2122         .flags          = CLOCK_IN_OMAP242X,
2123         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2124         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 static struct clk mmc_fck = {
2129         .name           = "mmc_fck",
2130         .parent         = &func_96m_ck,
2131         .flags          = CLOCK_IN_OMAP242X,
2132         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2133         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2134         .recalc         = &followparent_recalc,
2135 };
2136
2137 static struct clk fac_ick = {
2138         .name           = "fac_ick",
2139         .parent         = &l4_ck,
2140         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2141         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2142         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2143         .recalc         = &followparent_recalc,
2144 };
2145
2146 static struct clk fac_fck = {
2147         .name           = "fac_fck",
2148         .parent         = &func_12m_ck,
2149         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2150         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2151         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 static struct clk eac_ick = {
2156         .name           = "eac_ick",
2157         .parent         = &l4_ck,
2158         .flags          = CLOCK_IN_OMAP242X,
2159         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2160         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 static struct clk eac_fck = {
2165         .name           = "eac_fck",
2166         .parent         = &func_96m_ck,
2167         .flags          = CLOCK_IN_OMAP242X,
2168         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2169         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk hdq_ick = {
2174         .name           = "hdq_ick",
2175         .parent         = &l4_ck,
2176         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2177         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2178         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2179         .recalc         = &followparent_recalc,
2180 };
2181
2182 static struct clk hdq_fck = {
2183         .name           = "hdq_fck",
2184         .parent         = &func_12m_ck,
2185         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2186         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2187         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2188         .recalc         = &followparent_recalc,
2189 };
2190
2191 static struct clk i2c2_ick = {
2192         .name           = "i2c_ick",
2193         .id             = 2,
2194         .parent         = &l4_ck,
2195         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2196         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2197         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2198         .recalc         = &followparent_recalc,
2199 };
2200
2201 static struct clk i2c2_fck = {
2202         .name           = "i2c_fck",
2203         .id             = 2,
2204         .parent         = &func_12m_ck,
2205         .flags          = CLOCK_IN_OMAP242X,
2206         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2207         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk i2chs2_fck = {
2212         .name           = "i2chs_fck",
2213         .id             = 2,
2214         .parent         = &func_96m_ck,
2215         .flags          = CLOCK_IN_OMAP243X,
2216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2217         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2218         .recalc         = &followparent_recalc,
2219 };
2220
2221 static struct clk i2c1_ick = {
2222         .name           = "i2c_ick",
2223         .id             = 1,
2224         .parent         = &l4_ck,
2225         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2226         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2227         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 static struct clk i2c1_fck = {
2232         .name           = "i2c_fck",
2233         .id             = 1,
2234         .parent         = &func_12m_ck,
2235         .flags          = CLOCK_IN_OMAP242X,
2236         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2237         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2238         .recalc         = &followparent_recalc,
2239 };
2240
2241 static struct clk i2chs1_fck = {
2242         .name           = "i2chs_fck",
2243         .id             = 1,
2244         .parent         = &func_96m_ck,
2245         .flags          = CLOCK_IN_OMAP243X,
2246         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2247         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 static struct clk gpmc_fck = {
2252         .name           = "gpmc_fck",
2253         .parent         = &core_l3_ck,
2254         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2255         .recalc         = &followparent_recalc,
2256 };
2257
2258 static struct clk sdma_fck = {
2259         .name           = "sdma_fck",
2260         .parent         = &core_l3_ck,
2261         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 static struct clk sdma_ick = {
2266         .name           = "sdma_ick",
2267         .parent         = &l4_ck,
2268         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2269         .recalc         = &followparent_recalc,
2270 };
2271
2272 static struct clk vlynq_ick = {
2273         .name           = "vlynq_ick",
2274         .parent         = &core_l3_ck,
2275         .flags          = CLOCK_IN_OMAP242X,
2276         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2277         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2278         .recalc         = &followparent_recalc,
2279 };
2280
2281 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2282         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2283         { .div = 0 }
2284 };
2285
2286 static const struct clksel_rate vlynq_fck_core_rates[] = {
2287         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2288         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2289         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2290         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2291         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2292         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2293         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2294         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2295         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2296         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2297         { .div = 0 }
2298 };
2299
2300 static const struct clksel vlynq_fck_clksel[] = {
2301         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2302         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2303         { .parent = NULL }
2304 };
2305
2306 static struct clk vlynq_fck = {
2307         .name           = "vlynq_fck",
2308         .parent         = &func_96m_ck,
2309         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2310         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2311         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2312         .init           = &omap2_init_clksel_parent,
2313         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2314         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2315         .clksel         = vlynq_fck_clksel,
2316         .recalc         = &omap2_clksel_recalc,
2317         .round_rate     = &omap2_clksel_round_rate,
2318         .set_rate       = &omap2_clksel_set_rate
2319 };
2320
2321 static struct clk sdrc_ick = {
2322         .name           = "sdrc_ick",
2323         .parent         = &l4_ck,
2324         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2325         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2326         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2327         .recalc         = &followparent_recalc,
2328 };
2329
2330 static struct clk des_ick = {
2331         .name           = "des_ick",
2332         .parent         = &l4_ck,
2333         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2334         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2335         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2336         .recalc         = &followparent_recalc,
2337 };
2338
2339 static struct clk sha_ick = {
2340         .name           = "sha_ick",
2341         .parent         = &l4_ck,
2342         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2343         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2344         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2345         .recalc         = &followparent_recalc,
2346 };
2347
2348 static struct clk rng_ick = {
2349         .name           = "rng_ick",
2350         .parent         = &l4_ck,
2351         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2352         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2353         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2354         .recalc         = &followparent_recalc,
2355 };
2356
2357 static struct clk aes_ick = {
2358         .name           = "aes_ick",
2359         .parent         = &l4_ck,
2360         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2362         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2363         .recalc         = &followparent_recalc,
2364 };
2365
2366 static struct clk pka_ick = {
2367         .name           = "pka_ick",
2368         .parent         = &l4_ck,
2369         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2370         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2371         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2372         .recalc         = &followparent_recalc,
2373 };
2374
2375 static struct clk usb_fck = {
2376         .name           = "usb_fck",
2377         .parent         = &func_48m_ck,
2378         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2379         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2380         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2381         .recalc         = &followparent_recalc,
2382 };
2383
2384 static struct clk usbhs_ick = {
2385         .name           = "usbhs_ick",
2386         .parent         = &core_l3_ck,
2387         .flags          = CLOCK_IN_OMAP243X,
2388         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2389         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2390         .recalc         = &followparent_recalc,
2391 };
2392
2393 static struct clk mmchs1_ick = {
2394         .name           = "mmchs1_ick",
2395         .parent         = &l4_ck,
2396         .flags          = CLOCK_IN_OMAP243X,
2397         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2398         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2399         .recalc         = &followparent_recalc,
2400 };
2401
2402 static struct clk mmchs1_fck = {
2403         .name           = "mmchs1_fck",
2404         .parent         = &func_96m_ck,
2405         .flags          = CLOCK_IN_OMAP243X,
2406         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2407         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2408         .recalc         = &followparent_recalc,
2409 };
2410
2411 static struct clk mmchs2_ick = {
2412         .name           = "mmchs2_ick",
2413         .parent         = &l4_ck,
2414         .flags          = CLOCK_IN_OMAP243X,
2415         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2416         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2417         .recalc         = &followparent_recalc,
2418 };
2419
2420 static struct clk mmchs2_fck = {
2421         .name           = "mmchs2_fck",
2422         .parent         = &func_96m_ck,
2423         .flags          = CLOCK_IN_OMAP243X,
2424         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2425         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2426         .recalc         = &followparent_recalc,
2427 };
2428
2429 static struct clk gpio5_ick = {
2430         .name           = "gpio5_ick",
2431         .parent         = &l4_ck,
2432         .flags          = CLOCK_IN_OMAP243X,
2433         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2434         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2435         .recalc         = &followparent_recalc,
2436 };
2437
2438 static struct clk gpio5_fck = {
2439         .name           = "gpio5_fck",
2440         .parent         = &func_32k_ck,
2441         .flags          = CLOCK_IN_OMAP243X,
2442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2443         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2444         .recalc         = &followparent_recalc,
2445 };
2446
2447 static struct clk mdm_intc_ick = {
2448         .name           = "mdm_intc_ick",
2449         .parent         = &l4_ck,
2450         .flags          = CLOCK_IN_OMAP243X,
2451         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2452         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2453         .recalc         = &followparent_recalc,
2454 };
2455
2456 static struct clk mmchsdb1_fck = {
2457         .name           = "mmchsdb1_fck",
2458         .parent         = &func_32k_ck,
2459         .flags          = CLOCK_IN_OMAP243X,
2460         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2461         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2462         .recalc         = &followparent_recalc,
2463 };
2464
2465 static struct clk mmchsdb2_fck = {
2466         .name           = "mmchsdb2_fck",
2467         .parent         = &func_32k_ck,
2468         .flags          = CLOCK_IN_OMAP243X,
2469         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2470         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2471         .recalc         = &followparent_recalc,
2472 };
2473
2474 /*
2475  * This clock is a composite clock which does entire set changes then
2476  * forces a rebalance. It keys on the MPU speed, but it really could
2477  * be any key speed part of a set in the rate table.
2478  *
2479  * to really change a set, you need memory table sets which get changed
2480  * in sram, pre-notifiers & post notifiers, changing the top set, without
2481  * having low level display recalc's won't work... this is why dpm notifiers
2482  * work, isr's off, walk a list of clocks already _off_ and not messing with
2483  * the bus.
2484  *
2485  * This clock should have no parent. It embodies the entire upper level
2486  * active set. A parent will mess up some of the init also.
2487  */
2488 static struct clk virt_prcm_set = {
2489         .name           = "virt_prcm_set",
2490         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2491                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2492         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2493         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2494         .set_rate       = &omap2_select_table_rate,
2495         .round_rate     = &omap2_round_to_table_rate,
2496 };
2497
2498 static struct clk *onchip_clks[] __initdata = {
2499         /* external root sources */
2500         &func_32k_ck,
2501         &osc_ck,
2502         &sys_ck,
2503         &alt_ck,
2504         /* internal analog sources */
2505         &dpll_ck,
2506         &apll96_ck,
2507         &apll54_ck,
2508         /* internal prcm root sources */
2509         &func_54m_ck,
2510         &core_ck,
2511         &func_96m_ck,
2512         &func_48m_ck,
2513         &func_12m_ck,
2514         &wdt1_osc_ck,
2515         &sys_clkout_src,
2516         &sys_clkout,
2517         &sys_clkout2_src,
2518         &sys_clkout2,
2519         &emul_ck,
2520         /* mpu domain clocks */
2521         &mpu_ck,
2522         /* dsp domain clocks */
2523         &iva2_1_fck,            /* 2430 */
2524         &iva2_1_ick,
2525         &dsp_ick,               /* 2420 */
2526         &dsp_fck,
2527         &iva1_ifck,
2528         &iva1_mpu_int_ifck,
2529         /* GFX domain clocks */
2530         &gfx_3d_fck,
2531         &gfx_2d_fck,
2532         &gfx_ick,
2533         /* Modem domain clocks */
2534         &mdm_ick,
2535         &mdm_osc_ck,
2536         /* DSS domain clocks */
2537         &dss_ick,
2538         &dss1_fck,
2539         &dss2_fck,
2540         &dss_54m_fck,
2541         /* L3 domain clocks */
2542         &core_l3_ck,
2543         &ssi_ssr_sst_fck,
2544         &usb_l4_ick,
2545         /* L4 domain clocks */
2546         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2547         &ssi_l4_ick,
2548         /* virtual meta-group clock */
2549         &virt_prcm_set,
2550         /* general l4 interface ck, multi-parent functional clk */
2551         &gpt1_ick,
2552         &gpt1_fck,
2553         &gpt2_ick,
2554         &gpt2_fck,
2555         &gpt3_ick,
2556         &gpt3_fck,
2557         &gpt4_ick,
2558         &gpt4_fck,
2559         &gpt5_ick,
2560         &gpt5_fck,
2561         &gpt6_ick,
2562         &gpt6_fck,
2563         &gpt7_ick,
2564         &gpt7_fck,
2565         &gpt8_ick,
2566         &gpt8_fck,
2567         &gpt9_ick,
2568         &gpt9_fck,
2569         &gpt10_ick,
2570         &gpt10_fck,
2571         &gpt11_ick,
2572         &gpt11_fck,
2573         &gpt12_ick,
2574         &gpt12_fck,
2575         &mcbsp1_ick,
2576         &mcbsp1_fck,
2577         &mcbsp2_ick,
2578         &mcbsp2_fck,
2579         &mcbsp3_ick,
2580         &mcbsp3_fck,
2581         &mcbsp4_ick,
2582         &mcbsp4_fck,
2583         &mcbsp5_ick,
2584         &mcbsp5_fck,
2585         &mcspi1_ick,
2586         &mcspi1_fck,
2587         &mcspi2_ick,
2588         &mcspi2_fck,
2589         &mcspi3_ick,
2590         &mcspi3_fck,
2591         &uart1_ick,
2592         &uart1_fck,
2593         &uart2_ick,
2594         &uart2_fck,
2595         &uart3_ick,
2596         &uart3_fck,
2597         &gpios_ick,
2598         &gpios_fck,
2599         &mpu_wdt_ick,
2600         &mpu_wdt_fck,
2601         &sync_32k_ick,
2602         &wdt1_ick,
2603         &omapctrl_ick,
2604         &icr_ick,
2605         &cam_fck,
2606         &cam_ick,
2607         &mailboxes_ick,
2608         &wdt4_ick,
2609         &wdt4_fck,
2610         &wdt3_ick,
2611         &wdt3_fck,
2612         &mspro_ick,
2613         &mspro_fck,
2614         &mmc_ick,
2615         &mmc_fck,
2616         &fac_ick,
2617         &fac_fck,
2618         &eac_ick,
2619         &eac_fck,
2620         &hdq_ick,
2621         &hdq_fck,
2622         &i2c1_ick,
2623         &i2c1_fck,
2624         &i2chs1_fck,
2625         &i2c2_ick,
2626         &i2c2_fck,
2627         &i2chs2_fck,
2628         &gpmc_fck,
2629         &sdma_fck,
2630         &sdma_ick,
2631         &vlynq_ick,
2632         &vlynq_fck,
2633         &sdrc_ick,
2634         &des_ick,
2635         &sha_ick,
2636         &rng_ick,
2637         &aes_ick,
2638         &pka_ick,
2639         &usb_fck,
2640         &usbhs_ick,
2641         &mmchs1_ick,
2642         &mmchs1_fck,
2643         &mmchs2_ick,
2644         &mmchs2_fck,
2645         &gpio5_ick,
2646         &gpio5_fck,
2647         &mdm_intc_ick,
2648         &mmchsdb1_fck,
2649         &mmchsdb2_fck,
2650 };
2651
2652 #endif
2653