arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*-------------------------------------------------------------------------
 604  * 24xx clock tree.
 605  *
 606  * NOTE:In many cases here we are assigning a 'default' parent. In many
 607  *      cases the parent is selectable. The get/set parent calls will also
 608  *      switch sources.
 609  *
 610  *      Many some clocks say always_enabled, but they can be auto idled for
 611  *      power savings. They will always be available upon clock request.
 612  *
 613  *      Several sources are given initial rates which may be wrong, this will
 614  *      be fixed up in the init func.
 615  *
 616  *      Things are broadly separated below by clock domains. It is
 617  *      noteworthy that most periferals have dependencies on multiple clock
 618  *      domains. Many get their interface clocks from the L4 domain, but get
 619  *      functional clocks from fixed sources or other core domain derived
 620  *      clocks.
 621  *-------------------------------------------------------------------------*/
 622
 623 /* Base external input clocks */
 624 static struct clk func_32k_ck = {
 625         .name           = "func_32k_ck",
 626         .rate           = 32000,
 627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 628                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 629         .clkdm_name     = "wkup_clkdm",
 630         .recalc         = &propagate_rate,
 631 };
 632
 633 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 634 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 635         .name           = "osc_ck",
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_PROPAGATES,
 638         .clkdm_name     = "wkup_clkdm",
 639         .enable         = &omap2_enable_osc_ck,
 640         .disable        = &omap2_disable_osc_ck,
 641         .recalc         = &omap2_osc_clk_recalc,
 642 };
 643
 644 /* Without modem likely 12MHz, with modem likely 13MHz */
 645 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 646         .name           = "sys_ck",             /* ~ ref_clk also */
 647         .parent         = &osc_ck,
 648         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 649                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 650         .clkdm_name     = "wkup_clkdm",
 651         .recalc         = &omap2_sys_clk_recalc,
 652 };
 653
 654 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 655         .name           = "alt_ck",
 656         .rate           = 54000000,
 657         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 658                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 659         .clkdm_name     = "wkup_clkdm",
 660         .recalc         = &propagate_rate,
 661 };
 662
 663 /*
 664  * Analog domain root source clocks
 665  */
 666
 667 /* dpll_ck, is broken out in to special cases through clksel */
 668 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 669  * deal with this
 670  */
 671
 672 static struct dpll_data dpll_dd = {
 673         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 674         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 675         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 676         .max_multiplier         = 1024,
 677         .max_divider            = 16,
 678         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 679 };
 680
 681 /*
 682  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 683  * not just a DPLL
 684  */
 685 static struct clk dpll_ck = {
 686         .name           = "dpll_ck",
 687         .parent         = &sys_ck,              /* Can be func_32k also */
 688         .dpll_data      = &dpll_dd,
 689         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 690                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 691         .clkdm_name     = "wkup_clkdm",
 692         .recalc         = &omap2_dpllcore_recalc,
 693         .set_rate       = &omap2_reprogram_dpllcore,
 694 };
 695
 696 static struct clk apll96_ck = {
 697         .name           = "apll96_ck",
 698         .parent         = &sys_ck,
 699         .rate           = 96000000,
 700         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 701                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 702         .clkdm_name     = "wkup_clkdm",
 703         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 704         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 705         .enable         = &omap2_clk_fixed_enable,
 706         .disable        = &omap2_clk_fixed_disable,
 707         .recalc         = &propagate_rate,
 708 };
 709
 710 static struct clk apll54_ck = {
 711         .name           = "apll54_ck",
 712         .parent         = &sys_ck,
 713         .rate           = 54000000,
 714         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 715                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 716         .clkdm_name     = "wkup_clkdm",
 717         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 718         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 719         .enable         = &omap2_clk_fixed_enable,
 720         .disable        = &omap2_clk_fixed_disable,
 721         .recalc         = &propagate_rate,
 722 };
 723
 724 /*
 725  * PRCM digital base sources
 726  */
 727
 728 /* func_54m_ck */
 729
 730 static const struct clksel_rate func_54m_apll54_rates[] = {
 731         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 732         { .div = 0 },
 733 };
 734
 735 static const struct clksel_rate func_54m_alt_rates[] = {
 736         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 737         { .div = 0 },
 738 };
 739
 740 static const struct clksel func_54m_clksel[] = {
 741         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 742         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 743         { .parent = NULL },
 744 };
 745
 746 static struct clk func_54m_ck = {
 747         .name           = "func_54m_ck",
 748         .parent         = &apll54_ck,   /* can also be alt_clk */
 749         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 750                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 751         .clkdm_name     = "wkup_clkdm",
 752         .init           = &omap2_init_clksel_parent,
 753         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 754         .clksel_mask    = OMAP24XX_54M_SOURCE,
 755         .clksel         = func_54m_clksel,
 756         .recalc         = &omap2_clksel_recalc,
 757 };
 758
 759 static struct clk core_ck = {
 760         .name           = "core_ck",
 761         .parent         = &dpll_ck,             /* can also be 32k */
 762         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 763                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 764         .clkdm_name     = "wkup_clkdm",
 765         .recalc         = &followparent_recalc,
 766 };
 767
 768 /* func_96m_ck */
 769 static const struct clksel_rate func_96m_apll96_rates[] = {
 770         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 771         { .div = 0 },
 772 };
 773
 774 static const struct clksel_rate func_96m_alt_rates[] = {
 775         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 776         { .div = 0 },
 777 };
 778
 779 static const struct clksel func_96m_clksel[] = {
 780         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 781         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 782         { .parent = NULL }
 783 };
 784
 785 /* The parent of this clock is not selectable on 2420. */
 786 static struct clk func_96m_ck = {
 787         .name           = "func_96m_ck",
 788         .parent         = &apll96_ck,
 789         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 790                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 791         .clkdm_name     = "wkup_clkdm",
 792         .init           = &omap2_init_clksel_parent,
 793         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 794         .clksel_mask    = OMAP2430_96M_SOURCE,
 795         .clksel         = func_96m_clksel,
 796         .recalc         = &omap2_clksel_recalc,
 797         .round_rate     = &omap2_clksel_round_rate,
 798         .set_rate       = &omap2_clksel_set_rate
 799 };
 800
 801 /* func_48m_ck */
 802
 803 static const struct clksel_rate func_48m_apll96_rates[] = {
 804         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 805         { .div = 0 },
 806 };
 807
 808 static const struct clksel_rate func_48m_alt_rates[] = {
 809         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 810         { .div = 0 },
 811 };
 812
 813 static const struct clksel func_48m_clksel[] = {
 814         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 815         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 816         { .parent = NULL }
 817 };
 818
 819 static struct clk func_48m_ck = {
 820         .name           = "func_48m_ck",
 821         .parent         = &apll96_ck,    /* 96M or Alt */
 822         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 823                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 824         .clkdm_name     = "wkup_clkdm",
 825         .init           = &omap2_init_clksel_parent,
 826         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 827         .clksel_mask    = OMAP24XX_48M_SOURCE,
 828         .clksel         = func_48m_clksel,
 829         .recalc         = &omap2_clksel_recalc,
 830         .round_rate     = &omap2_clksel_round_rate,
 831         .set_rate       = &omap2_clksel_set_rate
 832 };
 833
 834 static struct clk func_12m_ck = {
 835         .name           = "func_12m_ck",
 836         .parent         = &func_48m_ck,
 837         .fixed_div      = 4,
 838         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 839                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 840         .clkdm_name     = "wkup_clkdm",
 841         .recalc         = &omap2_fixed_divisor_recalc,
 842 };
 843
 844 /* Secure timer, only available in secure mode */
 845 static struct clk wdt1_osc_ck = {
 846         .name           = "ck_wdt1_osc",
 847         .parent         = &osc_ck,
 848         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 849         .recalc         = &followparent_recalc,
 850 };
 851
 852 /*
 853  * The common_clkout* clksel_rate structs are common to
 854  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 855  * sys_clkout2_* are 2420-only, so the
 856  * clksel_rate flags fields are inaccurate for those clocks. This is
 857  * harmless since access to those clocks are gated by the struct clk
 858  * flags fields, which mark them as 2420-only.
 859  */
 860 static const struct clksel_rate common_clkout_src_core_rates[] = {
 861         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 862         { .div = 0 }
 863 };
 864
 865 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 866         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 867         { .div = 0 }
 868 };
 869
 870 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 871         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 872         { .div = 0 }
 873 };
 874
 875 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 876         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 877         { .div = 0 }
 878 };
 879
 880 static const struct clksel common_clkout_src_clksel[] = {
 881         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 882         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 883         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 884         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 885         { .parent = NULL }
 886 };
 887
 888 static struct clk sys_clkout_src = {
 889         .name           = "sys_clkout_src",
 890         .parent         = &func_54m_ck,
 891         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 892                                 RATE_PROPAGATES,
 893         .clkdm_name     = "wkup_clkdm",
 894         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 895         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 896         .init           = &omap2_init_clksel_parent,
 897         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 898         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 899         .clksel         = common_clkout_src_clksel,
 900         .recalc         = &omap2_clksel_recalc,
 901         .round_rate     = &omap2_clksel_round_rate,
 902         .set_rate       = &omap2_clksel_set_rate
 903 };
 904
 905 static const struct clksel_rate common_clkout_rates[] = {
 906         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 907         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 908         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 909         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 910         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 911         { .div = 0 },
 912 };
 913
 914 static const struct clksel sys_clkout_clksel[] = {
 915         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 916         { .parent = NULL }
 917 };
 918
 919 static struct clk sys_clkout = {
 920         .name           = "sys_clkout",
 921         .parent         = &sys_clkout_src,
 922         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 923                                 PARENT_CONTROLS_CLOCK,
 924         .clkdm_name     = "wkup_clkdm",
 925         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 926         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 927         .clksel         = sys_clkout_clksel,
 928         .recalc         = &omap2_clksel_recalc,
 929         .round_rate     = &omap2_clksel_round_rate,
 930         .set_rate       = &omap2_clksel_set_rate
 931 };
 932
 933 /* In 2430, new in 2420 ES2 */
 934 static struct clk sys_clkout2_src = {
 935         .name           = "sys_clkout2_src",
 936         .parent         = &func_54m_ck,
 937         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 938         .clkdm_name     = "wkup_clkdm",
 939         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 940         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 941         .init           = &omap2_init_clksel_parent,
 942         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 943         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 944         .clksel         = common_clkout_src_clksel,
 945         .recalc         = &omap2_clksel_recalc,
 946         .round_rate     = &omap2_clksel_round_rate,
 947         .set_rate       = &omap2_clksel_set_rate
 948 };
 949
 950 static const struct clksel sys_clkout2_clksel[] = {
 951         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 952         { .parent = NULL }
 953 };
 954
 955 /* In 2430, new in 2420 ES2 */
 956 static struct clk sys_clkout2 = {
 957         .name           = "sys_clkout2",
 958         .parent         = &sys_clkout2_src,
 959         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 960         .clkdm_name     = "wkup_clkdm",
 961         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 962         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 963         .clksel         = sys_clkout2_clksel,
 964         .recalc         = &omap2_clksel_recalc,
 965         .round_rate     = &omap2_clksel_round_rate,
 966         .set_rate       = &omap2_clksel_set_rate
 967 };
 968
 969 static struct clk emul_ck = {
 970         .name           = "emul_ck",
 971         .parent         = &func_54m_ck,
 972         .flags          = CLOCK_IN_OMAP242X,
 973         .clkdm_name     = "wkup_clkdm",
 974         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 975         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 976         .recalc         = &followparent_recalc,
 977
 978 };
 979
 980 /*
 981  * MPU clock domain
 982  *      Clocks:
 983  *              MPU_FCLK, MPU_ICLK
 984  *              INT_M_FCLK, INT_M_I_CLK
 985  *
 986  * - Individual clocks are hardware managed.
 987  * - Base divider comes from: CM_CLKSEL_MPU
 988  *
 989  */
 990 static const struct clksel_rate mpu_core_rates[] = {
 991         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 992         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 993         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 994         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 995         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 996         { .div = 0 },
 997 };
 998
 999 static const struct clksel mpu_clksel[] = {
1000         { .parent = &core_ck, .rates = mpu_core_rates },
1001         { .parent = NULL }
1002 };
1003
1004 static struct clk mpu_ck = {    /* Control cpu */
1005         .name           = "mpu_ck",
1006         .parent         = &core_ck,
1007         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1008                                 ALWAYS_ENABLED | DELAYED_APP |
1009                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1010         .clkdm_name     = "mpu_clkdm",
1011         .init           = &omap2_init_clksel_parent,
1012         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1013         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1014         .clksel         = mpu_clksel,
1015         .recalc         = &omap2_clksel_recalc,
1016         .round_rate     = &omap2_clksel_round_rate,
1017         .set_rate       = &omap2_clksel_set_rate
1018 };
1019
1020 /*
1021  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1022  * Clocks:
1023  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1024  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1025  *
1026  * Won't be too specific here. The core clock comes into this block
1027  * it is divided then tee'ed. One branch goes directly to xyz enable
1028  * controls. The other branch gets further divided by 2 then possibly
1029  * routed into a synchronizer and out of clocks abc.
1030  */
1031 static const struct clksel_rate dsp_fck_core_rates[] = {
1032         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1033         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1034         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1035         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1036         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1037         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1038         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1039         { .div = 0 },
1040 };
1041
1042 static const struct clksel dsp_fck_clksel[] = {
1043         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1044         { .parent = NULL }
1045 };
1046
1047 static struct clk dsp_fck = {
1048         .name           = "dsp_fck",
1049         .parent         = &core_ck,
1050         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1051                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1052         .clkdm_name     = "dsp_clkdm",
1053         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1054         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1055         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1056         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1057         .clksel         = dsp_fck_clksel,
1058         .recalc         = &omap2_clksel_recalc,
1059         .round_rate     = &omap2_clksel_round_rate,
1060         .set_rate       = &omap2_clksel_set_rate
1061 };
1062
1063 /* DSP interface clock */
1064 static const struct clksel_rate dsp_irate_ick_rates[] = {
1065         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1066         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1067         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1068         { .div = 0 },
1069 };
1070
1071 static const struct clksel dsp_irate_ick_clksel[] = {
1072         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1073         { .parent = NULL }
1074 };
1075
1076 /* This clock does not exist as such in the TRM. */
1077 static struct clk dsp_irate_ick = {
1078         .name           = "dsp_irate_ick",
1079         .parent         = &dsp_fck,
1080         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1081                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1082         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1083         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1084         .clksel         = dsp_irate_ick_clksel,
1085         .recalc         = &omap2_clksel_recalc,
1086         .round_rate     = &omap2_clksel_round_rate,
1087         .set_rate             = &omap2_clksel_set_rate
1088 };
1089
1090 /* 2420 only */
1091 static struct clk dsp_ick = {
1092         .name           = "dsp_ick",     /* apparently ipi and isp */
1093         .parent         = &dsp_irate_ick,
1094         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1095         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1096         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1097 };
1098
1099 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1100 static struct clk iva2_1_ick = {
1101         .name           = "iva2_1_ick",
1102         .parent         = &dsp_irate_ick,
1103         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1104         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1105         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1106 };
1107
1108 /*
1109  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1110  * the C54x, but which is contained in the DSP powerdomain.  Does not
1111  * exist on later OMAPs.
1112  */
1113 static struct clk iva1_ifck = {
1114         .name           = "iva1_ifck",
1115         .parent         = &core_ck,
1116         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1117                                 RATE_PROPAGATES | DELAYED_APP,
1118         .clkdm_name     = "iva1_clkdm",
1119         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1120         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1121         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1122         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1123         .clksel         = dsp_fck_clksel,
1124         .recalc         = &omap2_clksel_recalc,
1125         .round_rate     = &omap2_clksel_round_rate,
1126         .set_rate       = &omap2_clksel_set_rate
1127 };
1128
1129 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1130 static struct clk iva1_mpu_int_ifck = {
1131         .name           = "iva1_mpu_int_ifck",
1132         .parent         = &iva1_ifck,
1133         .flags          = CLOCK_IN_OMAP242X,
1134         .clkdm_name     = "iva1_clkdm",
1135         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1136         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1137         .fixed_div      = 2,
1138         .recalc         = &omap2_fixed_divisor_recalc,
1139 };
1140
1141 /*
1142  * L3 clock domain
1143  * L3 clocks are used for both interface and functional clocks to
1144  * multiple entities. Some of these clocks are completely managed
1145  * by hardware, and some others allow software control. Hardware
1146  * managed ones general are based on directly CLK_REQ signals and
1147  * various auto idle settings. The functional spec sets many of these
1148  * as 'tie-high' for their enables.
1149  *
1150  * I-CLOCKS:
1151  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1152  *      CAM, HS-USB.
1153  * F-CLOCK
1154  *      SSI.
1155  *
1156  * GPMC memories and SDRC have timing and clock sensitive registers which
1157  * may very well need notification when the clock changes. Currently for low
1158  * operating points, these are taken care of in sleep.S.
1159  */
1160 static const struct clksel_rate core_l3_core_rates[] = {
1161         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1162         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1163         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1164         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1165         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1166         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1167         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1168         { .div = 0 }
1169 };
1170
1171 static const struct clksel core_l3_clksel[] = {
1172         { .parent = &core_ck, .rates = core_l3_core_rates },
1173         { .parent = NULL }
1174 };
1175
1176 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1177         .name           = "core_l3_ck",
1178         .parent         = &core_ck,
1179         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1180                                 ALWAYS_ENABLED | DELAYED_APP |
1181                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1182         .clkdm_name     = "core_l3_clkdm",
1183         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1184         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1185         .clksel         = core_l3_clksel,
1186         .recalc         = &omap2_clksel_recalc,
1187         .round_rate     = &omap2_clksel_round_rate,
1188         .set_rate       = &omap2_clksel_set_rate
1189 };
1190
1191 /* usb_l4_ick */
1192 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1193         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1194         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1195         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1196         { .div = 0 }
1197 };
1198
1199 static const struct clksel usb_l4_ick_clksel[] = {
1200         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1201         { .parent = NULL },
1202 };
1203
1204 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1205 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1206         .name           = "usb_l4_ick",
1207         .parent         = &core_l3_ck,
1208         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1209                                 DELAYED_APP | CONFIG_PARTICIPANT,
1210         .clkdm_name     = "core_l4_clkdm",
1211         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1212         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1213         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1214         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1215         .clksel         = usb_l4_ick_clksel,
1216         .recalc         = &omap2_clksel_recalc,
1217         .round_rate     = &omap2_clksel_round_rate,
1218         .set_rate       = &omap2_clksel_set_rate
1219 };
1220
1221 /*
1222  * L4 clock management domain
1223  *
1224  * This domain contains lots of interface clocks from the L4 interface, some
1225  * functional clocks.   Fixed APLL functional source clocks are managed in
1226  * this domain.
1227  */
1228 static const struct clksel_rate l4_core_l3_rates[] = {
1229         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1230         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1231         { .div = 0 }
1232 };
1233
1234 static const struct clksel l4_clksel[] = {
1235         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1236         { .parent = NULL }
1237 };
1238
1239 static struct clk l4_ck = {             /* used both as an ick and fck */
1240         .name           = "l4_ck",
1241         .parent         = &core_l3_ck,
1242         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1243                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1244         .clkdm_name     = "core_l4_clkdm",
1245         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1247         .clksel         = l4_clksel,
1248         .recalc         = &omap2_clksel_recalc,
1249         .round_rate     = &omap2_clksel_round_rate,
1250         .set_rate       = &omap2_clksel_set_rate
1251 };
1252
1253 /*
1254  * SSI is in L3 management domain, its direct parent is core not l3,
1255  * many core power domain entities are grouped into the L3 clock
1256  * domain.
1257  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1258  *
1259  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1260  */
1261 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1262         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1263         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1264         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1265         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1266         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1267         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1268         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1269         { .div = 0 }
1270 };
1271
1272 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1273         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1274         { .parent = NULL }
1275 };
1276
1277 static struct clk ssi_ssr_sst_fck = {
1278         .name           = "ssi_fck",
1279         .parent         = &core_ck,
1280         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1281                                 DELAYED_APP,
1282         .clkdm_name     = "core_l3_clkdm",
1283         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1284         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1285         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1286         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1287         .clksel         = ssi_ssr_sst_fck_clksel,
1288         .recalc         = &omap2_clksel_recalc,
1289         .round_rate     = &omap2_clksel_round_rate,
1290         .set_rate       = &omap2_clksel_set_rate
1291 };
1292
1293 /*
1294  * Presumably this is the same as SSI_ICLK.
1295  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1296  */
1297 static struct clk ssi_l4_ick = {
1298         .name           = "ssi_l4_ick",
1299         .parent         = &l4_ck,
1300         .clkdm_name     = "core_l4_clkdm",
1301         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1302         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1303         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1304         .recalc         = &followparent_recalc,
1305 };
1306
1307
1308 /*
1309  * GFX clock domain
1310  *      Clocks:
1311  * GFX_FCLK, GFX_ICLK
1312  * GFX_CG1(2d), GFX_CG2(3d)
1313  *
1314  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1315  * The 2d and 3d clocks run at a hardware determined
1316  * divided value of fclk.
1317  *
1318  */
1319 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1320
1321 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1322 static const struct clksel gfx_fck_clksel[] = {
1323         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1324         { .parent = NULL },
1325 };
1326
1327 static struct clk gfx_3d_fck = {
1328         .name           = "gfx_3d_fck",
1329         .parent         = &core_l3_ck,
1330         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1331         .clkdm_name     = "gfx_clkdm",
1332         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1333         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1334         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1335         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1336         .clksel         = gfx_fck_clksel,
1337         .recalc         = &omap2_clksel_recalc,
1338         .round_rate     = &omap2_clksel_round_rate,
1339         .set_rate       = &omap2_clksel_set_rate
1340 };
1341
1342 static struct clk gfx_2d_fck = {
1343         .name           = "gfx_2d_fck",
1344         .parent         = &core_l3_ck,
1345         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1346         .clkdm_name     = "gfx_clkdm",
1347         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1348         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1349         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1350         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1351         .clksel         = gfx_fck_clksel,
1352         .recalc         = &omap2_clksel_recalc,
1353         .round_rate     = &omap2_clksel_round_rate,
1354         .set_rate       = &omap2_clksel_set_rate
1355 };
1356
1357 static struct clk gfx_ick = {
1358         .name           = "gfx_ick",            /* From l3 */
1359         .parent         = &core_l3_ck,
1360         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1361         .clkdm_name     = "gfx_clkdm",
1362         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1363         .enable_bit     = OMAP_EN_GFX_SHIFT,
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 /*
1368  * Modem clock domain (2430)
1369  *      CLOCKS:
1370  *              MDM_OSC_CLK
1371  *              MDM_ICLK
1372  * These clocks are usable in chassis mode only.
1373  */
1374 static const struct clksel_rate mdm_ick_core_rates[] = {
1375         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1376         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1377         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1378         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1379         { .div = 0 }
1380 };
1381
1382 static const struct clksel mdm_ick_clksel[] = {
1383         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1384         { .parent = NULL }
1385 };
1386
1387 static struct clk mdm_ick = {           /* used both as a ick and fck */
1388         .name           = "mdm_ick",
1389         .parent         = &core_ck,
1390         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1391         .clkdm_name     = "mdm_clkdm",
1392         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1393         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1394         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1395         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1396         .clksel         = mdm_ick_clksel,
1397         .recalc         = &omap2_clksel_recalc,
1398         .round_rate     = &omap2_clksel_round_rate,
1399         .set_rate       = &omap2_clksel_set_rate
1400 };
1401
1402 static struct clk mdm_osc_ck = {
1403         .name           = "mdm_osc_ck",
1404         .parent         = &osc_ck,
1405         .flags          = CLOCK_IN_OMAP243X,
1406         .clkdm_name     = "mdm_clkdm",
1407         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1408         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1409         .recalc         = &followparent_recalc,
1410 };
1411
1412 /*
1413  * DSS clock domain
1414  * CLOCKs:
1415  * DSS_L4_ICLK, DSS_L3_ICLK,
1416  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1417  *
1418  * DSS is both initiator and target.
1419  */
1420 /* XXX Add RATE_NOT_VALIDATED */
1421
1422 static const struct clksel_rate dss1_fck_sys_rates[] = {
1423         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1424         { .div = 0 }
1425 };
1426
1427 static const struct clksel_rate dss1_fck_core_rates[] = {
1428         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1429         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1430         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1431         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1432         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1433         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1434         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1435         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1436         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1437         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1438         { .div = 0 }
1439 };
1440
1441 static const struct clksel dss1_fck_clksel[] = {
1442         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1443         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1444         { .parent = NULL },
1445 };
1446
1447 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1448         .name           = "dss_ick",
1449         .parent         = &l4_ck,       /* really both l3 and l4 */
1450         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1451         .clkdm_name     = "dss_clkdm",
1452         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1453         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1454         .recalc         = &followparent_recalc,
1455 };
1456
1457 static struct clk dss1_fck = {
1458         .name           = "dss1_fck",
1459         .parent         = &core_ck,             /* Core or sys */
1460         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1461                                 DELAYED_APP,
1462         .clkdm_name     = "dss_clkdm",
1463         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1464         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1465         .init           = &omap2_init_clksel_parent,
1466         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1467         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1468         .clksel         = dss1_fck_clksel,
1469         .recalc         = &omap2_clksel_recalc,
1470         .round_rate     = &omap2_clksel_round_rate,
1471         .set_rate       = &omap2_clksel_set_rate
1472 };
1473
1474 static const struct clksel_rate dss2_fck_sys_rates[] = {
1475         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1476         { .div = 0 }
1477 };
1478
1479 static const struct clksel_rate dss2_fck_48m_rates[] = {
1480         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1481         { .div = 0 }
1482 };
1483
1484 static const struct clksel dss2_fck_clksel[] = {
1485         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1486         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1487         { .parent = NULL }
1488 };
1489
1490 static struct clk dss2_fck = {          /* Alt clk used in power management */
1491         .name           = "dss2_fck",
1492         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1493         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1494                                 DELAYED_APP,
1495         .clkdm_name     = "dss_clkdm",
1496         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1498         .init           = &omap2_init_clksel_parent,
1499         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1500         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1501         .clksel         = dss2_fck_clksel,
1502         .recalc         = &followparent_recalc,
1503 };
1504
1505 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1506         .name           = "dss_54m_fck",        /* 54m tv clk */
1507         .parent         = &func_54m_ck,
1508         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1509         .clkdm_name     = "dss_clkdm",
1510         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1511         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1512         .recalc         = &followparent_recalc,
1513 };
1514
1515 /*
1516  * CORE power domain ICLK & FCLK defines.
1517  * Many of the these can have more than one possible parent. Entries
1518  * here will likely have an L4 interface parent, and may have multiple
1519  * functional clock parents.
1520  */
1521 static const struct clksel_rate gpt_alt_rates[] = {
1522         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1523         { .div = 0 }
1524 };
1525
1526 static const struct clksel omap24xx_gpt_clksel[] = {
1527         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1528         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1529         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1530         { .parent = NULL },
1531 };
1532
1533 static struct clk gpt1_ick = {
1534         .name           = "gpt1_ick",
1535         .parent         = &l4_ck,
1536         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1537         .clkdm_name     = "core_l4_clkdm",
1538         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1539         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk gpt1_fck = {
1544         .name           = "gpt1_fck",
1545         .parent         = &func_32k_ck,
1546         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1547         .clkdm_name     = "core_l4_clkdm",
1548         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1549         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1550         .init           = &omap2_init_clksel_parent,
1551         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1552         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1553         .clksel         = omap24xx_gpt_clksel,
1554         .recalc         = &omap2_clksel_recalc,
1555         .round_rate     = &omap2_clksel_round_rate,
1556         .set_rate       = &omap2_clksel_set_rate
1557 };
1558
1559 static struct clk gpt2_ick = {
1560         .name           = "gpt2_ick",
1561         .parent         = &l4_ck,
1562         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1563         .clkdm_name     = "core_l4_clkdm",
1564         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1565         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1566         .recalc         = &followparent_recalc,
1567 };
1568
1569 static struct clk gpt2_fck = {
1570         .name           = "gpt2_fck",
1571         .parent         = &func_32k_ck,
1572         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573         .clkdm_name     = "core_l4_clkdm",
1574         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1575         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1576         .init           = &omap2_init_clksel_parent,
1577         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1578         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1579         .clksel         = omap24xx_gpt_clksel,
1580         .recalc         = &omap2_clksel_recalc,
1581 };
1582
1583 static struct clk gpt3_ick = {
1584         .name           = "gpt3_ick",
1585         .parent         = &l4_ck,
1586         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1587         .clkdm_name     = "core_l4_clkdm",
1588         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1589         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1590         .recalc         = &followparent_recalc,
1591 };
1592
1593 static struct clk gpt3_fck = {
1594         .name           = "gpt3_fck",
1595         .parent         = &func_32k_ck,
1596         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597         .clkdm_name     = "core_l4_clkdm",
1598         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1600         .init           = &omap2_init_clksel_parent,
1601         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1602         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1603         .clksel         = omap24xx_gpt_clksel,
1604         .recalc         = &omap2_clksel_recalc,
1605 };
1606
1607 static struct clk gpt4_ick = {
1608         .name           = "gpt4_ick",
1609         .parent         = &l4_ck,
1610         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1611         .clkdm_name     = "core_l4_clkdm",
1612         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1613         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1614         .recalc         = &followparent_recalc,
1615 };
1616
1617 static struct clk gpt4_fck = {
1618         .name           = "gpt4_fck",
1619         .parent         = &func_32k_ck,
1620         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621         .clkdm_name     = "core_l4_clkdm",
1622         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1623         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1624         .init           = &omap2_init_clksel_parent,
1625         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1626         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1627         .clksel         = omap24xx_gpt_clksel,
1628         .recalc         = &omap2_clksel_recalc,
1629 };
1630
1631 static struct clk gpt5_ick = {
1632         .name           = "gpt5_ick",
1633         .parent         = &l4_ck,
1634         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1635         .clkdm_name     = "core_l4_clkdm",
1636         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1637         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1638         .recalc         = &followparent_recalc,
1639 };
1640
1641 static struct clk gpt5_fck = {
1642         .name           = "gpt5_fck",
1643         .parent         = &func_32k_ck,
1644         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645         .clkdm_name     = "core_l4_clkdm",
1646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1647         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1648         .init           = &omap2_init_clksel_parent,
1649         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1650         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1651         .clksel         = omap24xx_gpt_clksel,
1652         .recalc         = &omap2_clksel_recalc,
1653 };
1654
1655 static struct clk gpt6_ick = {
1656         .name           = "gpt6_ick",
1657         .parent         = &l4_ck,
1658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1659         .clkdm_name     = "core_l4_clkdm",
1660         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1661         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1662         .recalc         = &followparent_recalc,
1663 };
1664
1665 static struct clk gpt6_fck = {
1666         .name           = "gpt6_fck",
1667         .parent         = &func_32k_ck,
1668         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1669         .clkdm_name     = "core_l4_clkdm",
1670         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1671         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1672         .init           = &omap2_init_clksel_parent,
1673         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1674         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1675         .clksel         = omap24xx_gpt_clksel,
1676         .recalc         = &omap2_clksel_recalc,
1677 };
1678
1679 static struct clk gpt7_ick = {
1680         .name           = "gpt7_ick",
1681         .parent         = &l4_ck,
1682         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1683         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1684         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1685         .recalc         = &followparent_recalc,
1686 };
1687
1688 static struct clk gpt7_fck = {
1689         .name           = "gpt7_fck",
1690         .parent         = &func_32k_ck,
1691         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692         .clkdm_name     = "core_l4_clkdm",
1693         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1694         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1695         .init           = &omap2_init_clksel_parent,
1696         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1697         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1698         .clksel         = omap24xx_gpt_clksel,
1699         .recalc         = &omap2_clksel_recalc,
1700 };
1701
1702 static struct clk gpt8_ick = {
1703         .name           = "gpt8_ick",
1704         .parent         = &l4_ck,
1705         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1706         .clkdm_name     = "core_l4_clkdm",
1707         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1708         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1709         .recalc         = &followparent_recalc,
1710 };
1711
1712 static struct clk gpt8_fck = {
1713         .name           = "gpt8_fck",
1714         .parent         = &func_32k_ck,
1715         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716         .clkdm_name     = "core_l4_clkdm",
1717         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1718         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1719         .init           = &omap2_init_clksel_parent,
1720         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1721         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1722         .clksel         = omap24xx_gpt_clksel,
1723         .recalc         = &omap2_clksel_recalc,
1724 };
1725
1726 static struct clk gpt9_ick = {
1727         .name           = "gpt9_ick",
1728         .parent         = &l4_ck,
1729         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1730         .clkdm_name     = "core_l4_clkdm",
1731         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1732         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static struct clk gpt9_fck = {
1737         .name           = "gpt9_fck",
1738         .parent         = &func_32k_ck,
1739         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740         .clkdm_name     = "core_l4_clkdm",
1741         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1742         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1743         .init           = &omap2_init_clksel_parent,
1744         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1745         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1746         .clksel         = omap24xx_gpt_clksel,
1747         .recalc         = &omap2_clksel_recalc,
1748 };
1749
1750 static struct clk gpt10_ick = {
1751         .name           = "gpt10_ick",
1752         .parent         = &l4_ck,
1753         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1754         .clkdm_name     = "core_l4_clkdm",
1755         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1756         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1757         .recalc         = &followparent_recalc,
1758 };
1759
1760 static struct clk gpt10_fck = {
1761         .name           = "gpt10_fck",
1762         .parent         = &func_32k_ck,
1763         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764         .clkdm_name     = "core_l4_clkdm",
1765         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1766         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1767         .init           = &omap2_init_clksel_parent,
1768         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1769         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1770         .clksel         = omap24xx_gpt_clksel,
1771         .recalc         = &omap2_clksel_recalc,
1772 };
1773
1774 static struct clk gpt11_ick = {
1775         .name           = "gpt11_ick",
1776         .parent         = &l4_ck,
1777         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1778         .clkdm_name     = "core_l4_clkdm",
1779         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1780         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 static struct clk gpt11_fck = {
1785         .name           = "gpt11_fck",
1786         .parent         = &func_32k_ck,
1787         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788         .clkdm_name     = "core_l4_clkdm",
1789         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1790         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1791         .init           = &omap2_init_clksel_parent,
1792         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1793         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1794         .clksel         = omap24xx_gpt_clksel,
1795         .recalc         = &omap2_clksel_recalc,
1796 };
1797
1798 static struct clk gpt12_ick = {
1799         .name           = "gpt12_ick",
1800         .parent         = &l4_ck,
1801         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1802         .clkdm_name     = "core_l4_clkdm",
1803         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1804         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1805         .recalc         = &followparent_recalc,
1806 };
1807
1808 static struct clk gpt12_fck = {
1809         .name           = "gpt12_fck",
1810         .parent         = &func_32k_ck,
1811         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1812         .clkdm_name     = "core_l4_clkdm",
1813         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1814         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1815         .init           = &omap2_init_clksel_parent,
1816         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1817         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1818         .clksel         = omap24xx_gpt_clksel,
1819         .recalc         = &omap2_clksel_recalc,
1820 };
1821
1822 static struct clk mcbsp1_ick = {
1823         .name           = "mcbsp1_ick",
1824         .parent         = &l4_ck,
1825         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1826         .clkdm_name     = "core_l4_clkdm",
1827         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1828         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1829         .recalc         = &followparent_recalc,
1830 };
1831
1832 static struct clk mcbsp1_fck = {
1833         .name           = "mcbsp1_fck",
1834         .parent         = &func_96m_ck,
1835         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1836         .clkdm_name     = "core_l4_clkdm",
1837         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1838         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1839         .recalc         = &followparent_recalc,
1840 };
1841
1842 static struct clk mcbsp2_ick = {
1843         .name           = "mcbsp2_ick",
1844         .parent         = &l4_ck,
1845         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846         .clkdm_name     = "core_l4_clkdm",
1847         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1849         .recalc         = &followparent_recalc,
1850 };
1851
1852 static struct clk mcbsp2_fck = {
1853         .name           = "mcbsp2_fck",
1854         .parent         = &func_96m_ck,
1855         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1856         .clkdm_name     = "core_l4_clkdm",
1857         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1858         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1859         .recalc         = &followparent_recalc,
1860 };
1861
1862 static struct clk mcbsp3_ick = {
1863         .name           = "mcbsp3_ick",
1864         .parent         = &l4_ck,
1865         .flags          = CLOCK_IN_OMAP243X,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1868         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk mcbsp3_fck = {
1873         .name           = "mcbsp3_fck",
1874         .parent         = &func_96m_ck,
1875         .flags          = CLOCK_IN_OMAP243X,
1876         .clkdm_name     = "core_l4_clkdm",
1877         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1878         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk mcbsp4_ick = {
1883         .name           = "mcbsp4_ick",
1884         .parent         = &l4_ck,
1885         .flags          = CLOCK_IN_OMAP243X,
1886         .clkdm_name     = "core_l4_clkdm",
1887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1888         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk mcbsp4_fck = {
1893         .name           = "mcbsp4_fck",
1894         .parent         = &func_96m_ck,
1895         .flags          = CLOCK_IN_OMAP243X,
1896         .clkdm_name     = "core_l4_clkdm",
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1898         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk mcbsp5_ick = {
1903         .name           = "mcbsp5_ick",
1904         .parent         = &l4_ck,
1905         .flags          = CLOCK_IN_OMAP243X,
1906         .clkdm_name     = "core_l4_clkdm",
1907         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1908         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1909         .recalc         = &followparent_recalc,
1910 };
1911
1912 static struct clk mcbsp5_fck = {
1913         .name           = "mcbsp5_fck",
1914         .parent         = &func_96m_ck,
1915         .flags          = CLOCK_IN_OMAP243X,
1916         .clkdm_name     = "core_l4_clkdm",
1917         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1918         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk mcspi1_ick = {
1923         .name           = "mcspi_ick",
1924         .id             = 1,
1925         .parent         = &l4_ck,
1926         .clkdm_name     = "core_l4_clkdm",
1927         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1928         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1929         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1930         .recalc         = &followparent_recalc,
1931 };
1932
1933 static struct clk mcspi1_fck = {
1934         .name           = "mcspi_fck",
1935         .id             = 1,
1936         .parent         = &func_48m_ck,
1937         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1938         .clkdm_name     = "core_l4_clkdm",
1939         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1940         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1941         .recalc         = &followparent_recalc,
1942 };
1943
1944 static struct clk mcspi2_ick = {
1945         .name           = "mcspi_ick",
1946         .id             = 2,
1947         .parent         = &l4_ck,
1948         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1949         .clkdm_name     = "core_l4_clkdm",
1950         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1951         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk mcspi2_fck = {
1956         .name           = "mcspi_fck",
1957         .id             = 2,
1958         .parent         = &func_48m_ck,
1959         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1960         .clkdm_name     = "core_l4_clkdm",
1961         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1962         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk mcspi3_ick = {
1967         .name           = "mcspi_ick",
1968         .id             = 3,
1969         .parent         = &l4_ck,
1970         .flags          = CLOCK_IN_OMAP243X,
1971         .clkdm_name     = "core_l4_clkdm",
1972         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1973         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1974         .recalc         = &followparent_recalc,
1975 };
1976
1977 static struct clk mcspi3_fck = {
1978         .name           = "mcspi_fck",
1979         .id             = 3,
1980         .parent         = &func_48m_ck,
1981         .flags          = CLOCK_IN_OMAP243X,
1982         .clkdm_name     = "core_l4_clkdm",
1983         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1984         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk uart1_ick = {
1989         .name           = "uart1_ick",
1990         .parent         = &l4_ck,
1991         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1992         .clkdm_name     = "core_l4_clkdm",
1993         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1994         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1995         .recalc         = &followparent_recalc,
1996 };
1997
1998 static struct clk uart1_fck = {
1999         .name           = "uart1_fck",
2000         .parent         = &func_48m_ck,
2001         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2002         .clkdm_name     = "core_l4_clkdm",
2003         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2004         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 static struct clk uart2_ick = {
2009         .name           = "uart2_ick",
2010         .parent         = &l4_ck,
2011         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2012         .clkdm_name     = "core_l4_clkdm",
2013         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2014         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2015         .recalc         = &followparent_recalc,
2016 };
2017
2018 static struct clk uart2_fck = {
2019         .name           = "uart2_fck",
2020         .parent         = &func_48m_ck,
2021         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2022         .clkdm_name     = "core_l4_clkdm",
2023         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2024         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 static struct clk uart3_ick = {
2029         .name           = "uart3_ick",
2030         .parent         = &l4_ck,
2031         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2032         .clkdm_name     = "core_l4_clkdm",
2033         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2034         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2035         .recalc         = &followparent_recalc,
2036 };
2037
2038 static struct clk uart3_fck = {
2039         .name           = "uart3_fck",
2040         .parent         = &func_48m_ck,
2041         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2042         .clkdm_name     = "core_l4_clkdm",
2043         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2044         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk gpios_ick = {
2049         .name           = "gpios_ick",
2050         .parent         = &l4_ck,
2051         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2052         .clkdm_name     = "core_l4_clkdm",
2053         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2054         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2055         .recalc         = &followparent_recalc,
2056 };
2057
2058 static struct clk gpios_fck = {
2059         .name           = "gpios_fck",
2060         .parent         = &func_32k_ck,
2061         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2062         .clkdm_name     = "wkup_clkdm",
2063         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2064         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2065         .recalc         = &followparent_recalc,
2066 };
2067
2068 static struct clk mpu_wdt_ick = {
2069         .name           = "mpu_wdt_ick",
2070         .parent         = &l4_ck,
2071         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2072         .clkdm_name     = "core_l4_clkdm",
2073         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2074         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2075         .recalc         = &followparent_recalc,
2076 };
2077
2078 static struct clk mpu_wdt_fck = {
2079         .name           = "mpu_wdt_fck",
2080         .parent         = &func_32k_ck,
2081         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2082         .clkdm_name     = "wkup_clkdm",
2083         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2084         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2085         .recalc         = &followparent_recalc,
2086 };
2087
2088 static struct clk sync_32k_ick = {
2089         .name           = "sync_32k_ick",
2090         .parent         = &l4_ck,
2091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2092                                 ENABLE_ON_INIT,
2093         .clkdm_name     = "core_l4_clkdm",
2094         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2095         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2096         .recalc         = &followparent_recalc,
2097 };
2098
2099 static struct clk wdt1_ick = {
2100         .name           = "wdt1_ick",
2101         .parent         = &l4_ck,
2102         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2103         .clkdm_name     = "core_l4_clkdm",
2104         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2105         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2106         .recalc         = &followparent_recalc,
2107 };
2108
2109 static struct clk omapctrl_ick = {
2110         .name           = "omapctrl_ick",
2111         .parent         = &l4_ck,
2112         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2113                                 ENABLE_ON_INIT,
2114         .clkdm_name     = "core_l4_clkdm",
2115         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2116         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk icr_ick = {
2121         .name           = "icr_ick",
2122         .parent         = &l4_ck,
2123         .flags          = CLOCK_IN_OMAP243X,
2124         .clkdm_name     = "core_l4_clkdm",
2125         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2126         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 static struct clk cam_ick = {
2131         .name           = "cam_ick",
2132         .parent         = &l4_ck,
2133         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2134         .clkdm_name     = "core_l4_clkdm",
2135         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2136         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 /*
2141  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2142  * split into two separate clocks, since the parent clocks are different
2143  * and the clockdomains are also different.
2144  */
2145 static struct clk cam_fck = {
2146         .name           = "cam_fck",
2147         .parent         = &func_96m_ck,
2148         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2149         .clkdm_name     = "core_l3_clkdm",
2150         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2151         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 static struct clk mailboxes_ick = {
2156         .name           = "mailboxes_ick",
2157         .parent         = &l4_ck,
2158         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2159         .clkdm_name     = "core_l4_clkdm",
2160         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2161         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 static struct clk wdt4_ick = {
2166         .name           = "wdt4_ick",
2167         .parent         = &l4_ck,
2168         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2169         .clkdm_name     = "core_l4_clkdm",
2170         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2171         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk wdt4_fck = {
2176         .name           = "wdt4_fck",
2177         .parent         = &func_32k_ck,
2178         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2179         .clkdm_name     = "core_l4_clkdm",
2180         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2181         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk wdt3_ick = {
2186         .name           = "wdt3_ick",
2187         .parent         = &l4_ck,
2188         .flags          = CLOCK_IN_OMAP242X,
2189         .clkdm_name     = "core_l4_clkdm",
2190         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2191         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk wdt3_fck = {
2196         .name           = "wdt3_fck",
2197         .parent         = &func_32k_ck,
2198         .flags          = CLOCK_IN_OMAP242X,
2199         .clkdm_name     = "core_l4_clkdm",
2200         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2201         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk mspro_ick = {
2206         .name           = "mspro_ick",
2207         .parent         = &l4_ck,
2208         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2209         .clkdm_name     = "core_l4_clkdm",
2210         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2211         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 static struct clk mspro_fck = {
2216         .name           = "mspro_fck",
2217         .parent         = &func_96m_ck,
2218         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2219         .clkdm_name     = "core_l4_clkdm",
2220         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2221         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk mmc_ick = {
2226         .name           = "mmc_ick",
2227         .parent         = &l4_ck,
2228         .flags          = CLOCK_IN_OMAP242X,
2229         .clkdm_name     = "core_l4_clkdm",
2230         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2231         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2232         .recalc         = &followparent_recalc,
2233 };
2234
2235 static struct clk mmc_fck = {
2236         .name           = "mmc_fck",
2237         .parent         = &func_96m_ck,
2238         .flags          = CLOCK_IN_OMAP242X,
2239         .clkdm_name     = "core_l4_clkdm",
2240         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2241         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk fac_ick = {
2246         .name           = "fac_ick",
2247         .parent         = &l4_ck,
2248         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2249         .clkdm_name     = "core_l4_clkdm",
2250         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2251         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 static struct clk fac_fck = {
2256         .name           = "fac_fck",
2257         .parent         = &func_12m_ck,
2258         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2259         .clkdm_name     = "core_l4_clkdm",
2260         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2261         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 static struct clk eac_ick = {
2266         .name           = "eac_ick",
2267         .parent         = &l4_ck,
2268         .flags          = CLOCK_IN_OMAP242X,
2269         .clkdm_name     = "core_l4_clkdm",
2270         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2271         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2272         .recalc         = &followparent_recalc,
2273 };
2274
2275 static struct clk eac_fck = {
2276         .name           = "eac_fck",
2277         .parent         = &func_96m_ck,
2278         .flags          = CLOCK_IN_OMAP242X,
2279         .clkdm_name     = "core_l4_clkdm",
2280         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2281         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2282         .recalc         = &followparent_recalc,
2283 };
2284
2285 static struct clk hdq_ick = {
2286         .name           = "hdq_ick",
2287         .parent         = &l4_ck,
2288         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2289         .clkdm_name     = "core_l4_clkdm",
2290         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2291         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2292         .recalc         = &followparent_recalc,
2293 };
2294
2295 static struct clk hdq_fck = {
2296         .name           = "hdq_fck",
2297         .parent         = &func_12m_ck,
2298         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2299         .clkdm_name     = "core_l4_clkdm",
2300         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2301         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2302         .recalc         = &followparent_recalc,
2303 };
2304
2305 static struct clk i2c2_ick = {
2306         .name           = "i2c_ick",
2307         .id             = 2,
2308         .parent         = &l4_ck,
2309         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2310         .clkdm_name     = "core_l4_clkdm",
2311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2312         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2313         .recalc         = &followparent_recalc,
2314 };
2315
2316 static struct clk i2c2_fck = {
2317         .name           = "i2c_fck",
2318         .id             = 2,
2319         .parent         = &func_12m_ck,
2320         .flags          = CLOCK_IN_OMAP242X,
2321         .clkdm_name     = "core_l4_clkdm",
2322         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2323         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2324         .recalc         = &followparent_recalc,
2325 };
2326
2327 static struct clk i2chs2_fck = {
2328         .name           = "i2chs_fck",
2329         .id             = 2,
2330         .parent         = &func_96m_ck,
2331         .flags          = CLOCK_IN_OMAP243X,
2332         .clkdm_name     = "core_l4_clkdm",
2333         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2334         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2335         .recalc         = &followparent_recalc,
2336 };
2337
2338 static struct clk i2c1_ick = {
2339         .name           = "i2c_ick",
2340         .id             = 1,
2341         .parent         = &l4_ck,
2342         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2343         .clkdm_name     = "core_l4_clkdm",
2344         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2345         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2346         .recalc         = &followparent_recalc,
2347 };
2348
2349 static struct clk i2c1_fck = {
2350         .name           = "i2c_fck",
2351         .id             = 1,
2352         .parent         = &func_12m_ck,
2353         .flags          = CLOCK_IN_OMAP242X,
2354         .clkdm_name     = "core_l4_clkdm",
2355         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2356         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2357         .recalc         = &followparent_recalc,
2358 };
2359
2360 static struct clk i2chs1_fck = {
2361         .name           = "i2chs_fck",
2362         .id             = 1,
2363         .parent         = &func_96m_ck,
2364         .flags          = CLOCK_IN_OMAP243X,
2365         .clkdm_name     = "core_l4_clkdm",
2366         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2367         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2368         .recalc         = &followparent_recalc,
2369 };
2370
2371 static struct clk gpmc_fck = {
2372         .name           = "gpmc_fck",
2373         .parent         = &core_l3_ck,
2374         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2375                                 ENABLE_ON_INIT,
2376         .clkdm_name     = "core_l3_clkdm",
2377         .recalc         = &followparent_recalc,
2378 };
2379
2380 static struct clk sdma_fck = {
2381         .name           = "sdma_fck",
2382         .parent         = &core_l3_ck,
2383         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2384         .clkdm_name     = "core_l3_clkdm",
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk sdma_ick = {
2389         .name           = "sdma_ick",
2390         .parent         = &l4_ck,
2391         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2392         .clkdm_name     = "core_l3_clkdm",
2393         .recalc         = &followparent_recalc,
2394 };
2395
2396 static struct clk vlynq_ick = {
2397         .name           = "vlynq_ick",
2398         .parent         = &core_l3_ck,
2399         .flags          = CLOCK_IN_OMAP242X,
2400         .clkdm_name     = "core_l3_clkdm",
2401         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2402         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2403         .recalc         = &followparent_recalc,
2404 };
2405
2406 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2407         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2408         { .div = 0 }
2409 };
2410
2411 static const struct clksel_rate vlynq_fck_core_rates[] = {
2412         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2413         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2414         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2415         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2416         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2417         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2418         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2419         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2420         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2421         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2422         { .div = 0 }
2423 };
2424
2425 static const struct clksel vlynq_fck_clksel[] = {
2426         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2427         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2428         { .parent = NULL }
2429 };
2430
2431 static struct clk vlynq_fck = {
2432         .name           = "vlynq_fck",
2433         .parent         = &func_96m_ck,
2434         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2435         .clkdm_name     = "core_l3_clkdm",
2436         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2437         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2438         .init           = &omap2_init_clksel_parent,
2439         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2440         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2441         .clksel         = vlynq_fck_clksel,
2442         .recalc         = &omap2_clksel_recalc,
2443         .round_rate     = &omap2_clksel_round_rate,
2444         .set_rate       = &omap2_clksel_set_rate
2445 };
2446
2447 static struct clk sdrc_ick = {
2448         .name           = "sdrc_ick",
2449         .parent         = &l4_ck,
2450         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2451         .clkdm_name     = "core_l4_clkdm",
2452         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2453         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2454         .recalc         = &followparent_recalc,
2455 };
2456
2457 static struct clk des_ick = {
2458         .name           = "des_ick",
2459         .parent         = &l4_ck,
2460         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2461         .clkdm_name     = "core_l4_clkdm",
2462         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2463         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2464         .recalc         = &followparent_recalc,
2465 };
2466
2467 static struct clk sha_ick = {
2468         .name           = "sha_ick",
2469         .parent         = &l4_ck,
2470         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2471         .clkdm_name     = "core_l4_clkdm",
2472         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2473         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2474         .recalc         = &followparent_recalc,
2475 };
2476
2477 static struct clk rng_ick = {
2478         .name           = "rng_ick",
2479         .parent         = &l4_ck,
2480         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2481         .clkdm_name     = "core_l4_clkdm",
2482         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2483         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2484         .recalc         = &followparent_recalc,
2485 };
2486
2487 static struct clk aes_ick = {
2488         .name           = "aes_ick",
2489         .parent         = &l4_ck,
2490         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2491         .clkdm_name     = "core_l4_clkdm",
2492         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2493         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2494         .recalc         = &followparent_recalc,
2495 };
2496
2497 static struct clk pka_ick = {
2498         .name           = "pka_ick",
2499         .parent         = &l4_ck,
2500         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2501         .clkdm_name     = "core_l4_clkdm",
2502         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2503         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2504         .recalc         = &followparent_recalc,
2505 };
2506
2507 static struct clk usb_fck = {
2508         .name           = "usb_fck",
2509         .parent         = &func_48m_ck,
2510         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2511         .clkdm_name     = "core_l3_clkdm",
2512         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2513         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2514         .recalc         = &followparent_recalc,
2515 };
2516
2517 static struct clk usbhs_ick = {
2518         .name           = "usbhs_ick",
2519         .parent         = &core_l3_ck,
2520         .flags          = CLOCK_IN_OMAP243X,
2521         .clkdm_name     = "core_l3_clkdm",
2522         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2523         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2524         .recalc         = &followparent_recalc,
2525 };
2526
2527 static struct clk mmchs1_ick = {
2528         .name           = "mmchs_ick",
2529         .id             = 1,
2530         .parent         = &l4_ck,
2531         .flags          = CLOCK_IN_OMAP243X,
2532         .clkdm_name     = "core_l4_clkdm",
2533         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2534         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2535         .recalc         = &followparent_recalc,
2536 };
2537
2538 static struct clk mmchs1_fck = {
2539         .name           = "mmchs_fck",
2540         .id             = 1,
2541         .parent         = &func_96m_ck,
2542         .flags          = CLOCK_IN_OMAP243X,
2543         .clkdm_name     = "core_l3_clkdm",
2544         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2545         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2546         .recalc         = &followparent_recalc,
2547 };
2548
2549 static struct clk mmchs2_ick = {
2550         .name           = "mmchs_ick",
2551         .id             = 2,
2552         .parent         = &l4_ck,
2553         .flags          = CLOCK_IN_OMAP243X,
2554         .clkdm_name     = "core_l4_clkdm",
2555         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2556         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2557         .recalc         = &followparent_recalc,
2558 };
2559
2560 static struct clk mmchs2_fck = {
2561         .name           = "mmchs_fck",
2562         .id             = 2,
2563         .parent         = &func_96m_ck,
2564         .flags          = CLOCK_IN_OMAP243X,
2565         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2566         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2567         .recalc         = &followparent_recalc,
2568 };
2569
2570 static struct clk gpio5_ick = {
2571         .name           = "gpio5_ick",
2572         .parent         = &l4_ck,
2573         .flags          = CLOCK_IN_OMAP243X,
2574         .clkdm_name     = "core_l4_clkdm",
2575         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2576         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2577         .recalc         = &followparent_recalc,
2578 };
2579
2580 static struct clk gpio5_fck = {
2581         .name           = "gpio5_fck",
2582         .parent         = &func_32k_ck,
2583         .flags          = CLOCK_IN_OMAP243X,
2584         .clkdm_name     = "core_l4_clkdm",
2585         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2586         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2587         .recalc         = &followparent_recalc,
2588 };
2589
2590 static struct clk mdm_intc_ick = {
2591         .name           = "mdm_intc_ick",
2592         .parent         = &l4_ck,
2593         .flags          = CLOCK_IN_OMAP243X,
2594         .clkdm_name     = "core_l4_clkdm",
2595         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2596         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2597         .recalc         = &followparent_recalc,
2598 };
2599
2600 static struct clk mmchsdb1_fck = {
2601         .name           = "mmchsdb_fck",
2602         .id             = 1,
2603         .parent         = &func_32k_ck,
2604         .flags          = CLOCK_IN_OMAP243X,
2605         .clkdm_name     = "core_l4_clkdm",
2606         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2607         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2608         .recalc         = &followparent_recalc,
2609 };
2610
2611 static struct clk mmchsdb2_fck = {
2612         .name           = "mmchsdb_fck",
2613         .id             = 2,
2614         .parent         = &func_32k_ck,
2615         .flags          = CLOCK_IN_OMAP243X,
2616         .clkdm_name     = "core_l4_clkdm",
2617         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2618         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2619         .recalc         = &followparent_recalc,
2620 };
2621
2622 /*
2623  * This clock is a composite clock which does entire set changes then
2624  * forces a rebalance. It keys on the MPU speed, but it really could
2625  * be any key speed part of a set in the rate table.
2626  *
2627  * to really change a set, you need memory table sets which get changed
2628  * in sram, pre-notifiers & post notifiers, changing the top set, without
2629  * having low level display recalc's won't work... this is why dpm notifiers
2630  * work, isr's off, walk a list of clocks already _off_ and not messing with
2631  * the bus.
2632  *
2633  * This clock should have no parent. It embodies the entire upper level
2634  * active set. A parent will mess up some of the init also.
2635  */
2636 static struct clk virt_prcm_set = {
2637         .name           = "virt_prcm_set",
2638         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2639                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2640         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2641         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2642         .set_rate       = &omap2_select_table_rate,
2643         .round_rate     = &omap2_round_to_table_rate,
2644 };
2645
2646 static struct clk *onchip_24xx_clks[] __initdata = {
2647         /* external root sources */
2648         &func_32k_ck,
2649         &osc_ck,
2650         &sys_ck,
2651         &alt_ck,
2652         /* internal analog sources */
2653         &dpll_ck,
2654         &apll96_ck,
2655         &apll54_ck,
2656         /* internal prcm root sources */
2657         &func_54m_ck,
2658         &core_ck,
2659         &func_96m_ck,
2660         &func_48m_ck,
2661         &func_12m_ck,
2662         &wdt1_osc_ck,
2663         &sys_clkout_src,
2664         &sys_clkout,
2665         &sys_clkout2_src,
2666         &sys_clkout2,
2667         &emul_ck,
2668         /* mpu domain clocks */
2669         &mpu_ck,
2670         /* dsp domain clocks */
2671         &dsp_fck,
2672         &dsp_irate_ick,
2673         &dsp_ick,               /* 242x */
2674         &iva2_1_ick,            /* 243x */
2675         &iva1_ifck,             /* 242x */
2676         &iva1_mpu_int_ifck,     /* 242x */
2677         /* GFX domain clocks */
2678         &gfx_3d_fck,
2679         &gfx_2d_fck,
2680         &gfx_ick,
2681         /* Modem domain clocks */
2682         &mdm_ick,
2683         &mdm_osc_ck,
2684         /* DSS domain clocks */
2685         &dss_ick,
2686         &dss1_fck,
2687         &dss2_fck,
2688         &dss_54m_fck,
2689         /* L3 domain clocks */
2690         &core_l3_ck,
2691         &ssi_ssr_sst_fck,
2692         &usb_l4_ick,
2693         /* L4 domain clocks */
2694         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2695         &ssi_l4_ick,
2696         /* virtual meta-group clock */
2697         &virt_prcm_set,
2698         /* general l4 interface ck, multi-parent functional clk */
2699         &gpt1_ick,
2700         &gpt1_fck,
2701         &gpt2_ick,
2702         &gpt2_fck,
2703         &gpt3_ick,
2704         &gpt3_fck,
2705         &gpt4_ick,
2706         &gpt4_fck,
2707         &gpt5_ick,
2708         &gpt5_fck,
2709         &gpt6_ick,
2710         &gpt6_fck,
2711         &gpt7_ick,
2712         &gpt7_fck,
2713         &gpt8_ick,
2714         &gpt8_fck,
2715         &gpt9_ick,
2716         &gpt9_fck,
2717         &gpt10_ick,
2718         &gpt10_fck,
2719         &gpt11_ick,
2720         &gpt11_fck,
2721         &gpt12_ick,
2722         &gpt12_fck,
2723         &mcbsp1_ick,
2724         &mcbsp1_fck,
2725         &mcbsp2_ick,
2726         &mcbsp2_fck,
2727         &mcbsp3_ick,
2728         &mcbsp3_fck,
2729         &mcbsp4_ick,
2730         &mcbsp4_fck,
2731         &mcbsp5_ick,
2732         &mcbsp5_fck,
2733         &mcspi1_ick,
2734         &mcspi1_fck,
2735         &mcspi2_ick,
2736         &mcspi2_fck,
2737         &mcspi3_ick,
2738         &mcspi3_fck,
2739         &uart1_ick,
2740         &uart1_fck,
2741         &uart2_ick,
2742         &uart2_fck,
2743         &uart3_ick,
2744         &uart3_fck,
2745         &gpios_ick,
2746         &gpios_fck,
2747         &mpu_wdt_ick,
2748         &mpu_wdt_fck,
2749         &sync_32k_ick,
2750         &wdt1_ick,
2751         &omapctrl_ick,
2752         &icr_ick,
2753         &cam_fck,
2754         &cam_ick,
2755         &mailboxes_ick,
2756         &wdt4_ick,
2757         &wdt4_fck,
2758         &wdt3_ick,
2759         &wdt3_fck,
2760         &mspro_ick,
2761         &mspro_fck,
2762         &mmc_ick,
2763         &mmc_fck,
2764         &fac_ick,
2765         &fac_fck,
2766         &eac_ick,
2767         &eac_fck,
2768         &hdq_ick,
2769         &hdq_fck,
2770         &i2c1_ick,
2771         &i2c1_fck,
2772         &i2chs1_fck,
2773         &i2c2_ick,
2774         &i2c2_fck,
2775         &i2chs2_fck,
2776         &gpmc_fck,
2777         &sdma_fck,
2778         &sdma_ick,
2779         &vlynq_ick,
2780         &vlynq_fck,
2781         &sdrc_ick,
2782         &des_ick,
2783         &sha_ick,
2784         &rng_ick,
2785         &aes_ick,
2786         &pka_ick,
2787         &usb_fck,
2788         &usbhs_ick,
2789         &mmchs1_ick,
2790         &mmchs1_fck,
2791         &mmchs2_ick,
2792         &mmchs2_fck,
2793         &gpio5_ick,
2794         &gpio5_fck,
2795         &mdm_intc_ick,
2796         &mmchsdb1_fck,
2797         &mmchsdb2_fck,
2798 };
2799
2800 #endif
2801