arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*
 604  * Since 2420 and 2430 have different cm_base, we use offsets only here.
 605  * Clock code will rewrite the register address as needed.
 606  */
 607 #define _CM_REG_OFFSET(module, reg)                             \
 608                         ((__force void __iomem *)(module) + (reg))
 609 #define _GR_MOD_OFFSET(reg)                                     \
 610                         ((__force void __iomem *)(OMAP24XX_GR_MOD + (reg)))
 611
 612 /*-------------------------------------------------------------------------
 613  * 24xx clock tree.
 614  *
 615  * NOTE:In many cases here we are assigning a 'default' parent. In many
 616  *      cases the parent is selectable. The get/set parent calls will also
 617  *      switch sources.
 618  *
 619  *      Many some clocks say always_enabled, but they can be auto idled for
 620  *      power savings. They will always be available upon clock request.
 621  *
 622  *      Several sources are given initial rates which may be wrong, this will
 623  *      be fixed up in the init func.
 624  *
 625  *      Things are broadly separated below by clock domains. It is
 626  *      noteworthy that most periferals have dependencies on multiple clock
 627  *      domains. Many get their interface clocks from the L4 domain, but get
 628  *      functional clocks from fixed sources or other core domain derived
 629  *      clocks.
 630  *-------------------------------------------------------------------------*/
 631
 632 /* Base external input clocks */
 633 static struct clk func_32k_ck = {
 634         .name           = "func_32k_ck",
 635         .rate           = 32000,
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 638         .clkdm          = { .name = "prm_clkdm" },
 639         .recalc         = &propagate_rate,
 640 };
 641
 642 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 643 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 644         .name           = "osc_ck",
 645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 646                                 RATE_PROPAGATES,
 647         .clkdm          = { .name = "prm_clkdm" },
 648         .enable         = &omap2_enable_osc_ck,
 649         .disable        = &omap2_disable_osc_ck,
 650         .recalc         = &omap2_osc_clk_recalc,
 651 };
 652
 653 /* Without modem likely 12MHz, with modem likely 13MHz */
 654 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 655         .name           = "sys_ck",             /* ~ ref_clk also */
 656         .parent         = &osc_ck,
 657         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 658                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 659         .clkdm          = { .name = "prm_clkdm" },
 660         .recalc         = &omap2_sys_clk_recalc,
 661 };
 662
 663 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 664         .name           = "alt_ck",
 665         .rate           = 54000000,
 666         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 667                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 668         .clkdm          = { .name = "prm_clkdm" },
 669         .recalc         = &propagate_rate,
 670 };
 671
 672 /*
 673  * Analog domain root source clocks
 674  */
 675
 676 /* dpll_ck, is broken out in to special cases through clksel */
 677 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 678  * deal with this
 679  */
 680
 681 static struct dpll_data dpll_dd = {
 682         .mult_div1_reg          = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 683         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 684         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 685         .idlest_reg             = _CM_REG_OFFSET(PLL_MOD, CM_IDLEST),
 686         .idlest_mask            = OMAP24XX_ST_CORE_CLK_MASK,
 687         .max_multiplier         = 1024,
 688         .max_divider            = 16,
 689         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 690 };
 691
 692 /*
 693  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 694  * not just a DPLL
 695  */
 696 static struct clk dpll_ck = {
 697         .name           = "dpll_ck",
 698         .parent         = &sys_ck,              /* Can be func_32k also */
 699         .prcm_mod       = PLL_MOD,
 700         .dpll_data      = &dpll_dd,
 701         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 702                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 703         .clkdm          = { .name = "prm_clkdm" },
 704         .recalc         = &omap2_dpllcore_recalc,
 705         .set_rate       = &omap2_reprogram_dpllcore,
 706 };
 707
 708 static struct clk apll96_ck = {
 709         .name           = "apll96_ck",
 710         .parent         = &sys_ck,
 711         .prcm_mod       = PLL_MOD,
 712         .rate           = 96000000,
 713         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 714                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 715         .clkdm          = { .name = "prm_clkdm" },
 716         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 717         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 718         .enable         = &omap2_clk_fixed_enable,
 719         .disable        = &omap2_clk_fixed_disable,
 720         .recalc         = &propagate_rate,
 721 };
 722
 723 static struct clk apll54_ck = {
 724         .name           = "apll54_ck",
 725         .parent         = &sys_ck,
 726         .prcm_mod       = PLL_MOD,
 727         .rate           = 54000000,
 728         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 729                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 730         .clkdm          = { .name = "prm_clkdm" },
 731         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 732         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 733         .enable         = &omap2_clk_fixed_enable,
 734         .disable        = &omap2_clk_fixed_disable,
 735         .recalc         = &propagate_rate,
 736 };
 737
 738 /*
 739  * PRCM digital base sources
 740  */
 741
 742 /* func_54m_ck */
 743
 744 static const struct clksel_rate func_54m_apll54_rates[] = {
 745         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 746         { .div = 0 },
 747 };
 748
 749 static const struct clksel_rate func_54m_alt_rates[] = {
 750         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 751         { .div = 0 },
 752 };
 753
 754 static const struct clksel func_54m_clksel[] = {
 755         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 756         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 757         { .parent = NULL },
 758 };
 759
 760 static struct clk func_54m_ck = {
 761         .name           = "func_54m_ck",
 762         .parent         = &apll54_ck,   /* can also be alt_clk */
 763         .prcm_mod       = PLL_MOD,
 764         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 765                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 766         .clkdm          = { .name = "cm_clkdm" },
 767         .init           = &omap2_init_clksel_parent,
 768         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 769         .clksel_mask    = OMAP24XX_54M_SOURCE,
 770         .clksel         = func_54m_clksel,
 771         .recalc         = &omap2_clksel_recalc,
 772 };
 773
 774 static struct clk core_ck = {
 775         .name           = "core_ck",
 776         .parent         = &dpll_ck,             /* can also be 32k */
 777         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 778                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 779         .clkdm          = { .name = "cm_clkdm" },
 780         .recalc         = &followparent_recalc,
 781 };
 782
 783 /* func_96m_ck */
 784 static const struct clksel_rate func_96m_apll96_rates[] = {
 785         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 786         { .div = 0 },
 787 };
 788
 789 static const struct clksel_rate func_96m_alt_rates[] = {
 790         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 791         { .div = 0 },
 792 };
 793
 794 static const struct clksel func_96m_clksel[] = {
 795         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 796         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 797         { .parent = NULL }
 798 };
 799
 800 /* The parent of this clock is not selectable on 2420. */
 801 static struct clk func_96m_ck = {
 802         .name           = "func_96m_ck",
 803         .parent         = &apll96_ck,
 804         .prcm_mod       = PLL_MOD,
 805         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 806                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 807         .clkdm          = { .name = "cm_clkdm" },
 808         .init           = &omap2_init_clksel_parent,
 809         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 810         .clksel_mask    = OMAP2430_96M_SOURCE,
 811         .clksel         = func_96m_clksel,
 812         .recalc         = &omap2_clksel_recalc,
 813         .round_rate     = &omap2_clksel_round_rate,
 814         .set_rate       = &omap2_clksel_set_rate
 815 };
 816
 817 /* func_48m_ck */
 818
 819 static const struct clksel_rate func_48m_apll96_rates[] = {
 820         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 821         { .div = 0 },
 822 };
 823
 824 static const struct clksel_rate func_48m_alt_rates[] = {
 825         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 826         { .div = 0 },
 827 };
 828
 829 static const struct clksel func_48m_clksel[] = {
 830         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 831         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 832         { .parent = NULL }
 833 };
 834
 835 static struct clk func_48m_ck = {
 836         .name           = "func_48m_ck",
 837         .parent         = &apll96_ck,    /* 96M or Alt */
 838         .prcm_mod       = PLL_MOD,
 839         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 840                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 841         .clkdm          = { .name = "cm_clkdm" },
 842         .init           = &omap2_init_clksel_parent,
 843         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 844         .clksel_mask    = OMAP24XX_48M_SOURCE,
 845         .clksel         = func_48m_clksel,
 846         .recalc         = &omap2_clksel_recalc,
 847         .round_rate     = &omap2_clksel_round_rate,
 848         .set_rate       = &omap2_clksel_set_rate
 849 };
 850
 851 static struct clk func_12m_ck = {
 852         .name           = "func_12m_ck",
 853         .parent         = &func_48m_ck,
 854         .fixed_div      = 4,
 855         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 856                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 857         .clkdm          = { .name = "cm_clkdm" },
 858         .recalc         = &omap2_fixed_divisor_recalc,
 859 };
 860
 861 /* Secure timer, only available in secure mode */
 862 static struct clk wdt1_osc_ck = {
 863         .name           = "wdt1_osc_ck",
 864         .parent         = &osc_ck,
 865         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 866         .clkdm          = { .name = "prm_clkdm" },
 867         .recalc         = &followparent_recalc,
 868 };
 869
 870 /*
 871  * The common_clkout* clksel_rate structs are common to
 872  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 873  * sys_clkout2_* are 2420-only, so the
 874  * clksel_rate flags fields are inaccurate for those clocks. This is
 875  * harmless since access to those clocks are gated by the struct clk
 876  * flags fields, which mark them as 2420-only.
 877  */
 878 static const struct clksel_rate common_clkout_src_core_rates[] = {
 879         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 880         { .div = 0 }
 881 };
 882
 883 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 884         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 885         { .div = 0 }
 886 };
 887
 888 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 889         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 890         { .div = 0 }
 891 };
 892
 893 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 894         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 895         { .div = 0 }
 896 };
 897
 898 static const struct clksel common_clkout_src_clksel[] = {
 899         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 900         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 901         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 902         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 903         { .parent = NULL }
 904 };
 905
 906 static struct clk sys_clkout_src = {
 907         .name           = "sys_clkout_src",
 908         .parent         = &func_54m_ck,
 909         .prcm_mod       = OMAP24XX_GR_MOD,
 910         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 911                                 RATE_PROPAGATES | OFFSET_GR_MOD,
 912         .clkdm          = { .name = "prm_clkdm" },
 913         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 914         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 915         .init           = &omap2_init_clksel_parent,
 916         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 917         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 918         .clksel         = common_clkout_src_clksel,
 919         .recalc         = &omap2_clksel_recalc,
 920         .round_rate     = &omap2_clksel_round_rate,
 921         .set_rate       = &omap2_clksel_set_rate
 922 };
 923
 924 static const struct clksel_rate common_clkout_rates[] = {
 925         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 926         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 927         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 928         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 929         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 930         { .div = 0 },
 931 };
 932
 933 static const struct clksel sys_clkout_clksel[] = {
 934         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 935         { .parent = NULL }
 936 };
 937
 938 static struct clk sys_clkout = {
 939         .name           = "sys_clkout",
 940         .parent         = &sys_clkout_src,
 941         .prcm_mod       = OMAP24XX_GR_MOD,
 942         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 943                                 PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
 944         .clkdm          = { .name = "prm_clkdm" },
 945         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 946         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 947         .clksel         = sys_clkout_clksel,
 948         .recalc         = &omap2_clksel_recalc,
 949         .round_rate     = &omap2_clksel_round_rate,
 950         .set_rate       = &omap2_clksel_set_rate
 951 };
 952
 953 /* In 2430, new in 2420 ES2 */
 954 static struct clk sys_clkout2_src = {
 955         .name           = "sys_clkout2_src",
 956         .parent         = &func_54m_ck,
 957         .prcm_mod       = OMAP24XX_GR_MOD,
 958         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
 959         .clkdm          = { .name = "cm_clkdm" },
 960         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 961         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 962         .init           = &omap2_init_clksel_parent,
 963         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 964         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 965         .clksel         = common_clkout_src_clksel,
 966         .recalc         = &omap2_clksel_recalc,
 967         .round_rate     = &omap2_clksel_round_rate,
 968         .set_rate       = &omap2_clksel_set_rate
 969 };
 970
 971 static const struct clksel sys_clkout2_clksel[] = {
 972         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 973         { .parent = NULL }
 974 };
 975
 976 /* In 2430, new in 2420 ES2 */
 977 static struct clk sys_clkout2 = {
 978         .name           = "sys_clkout2",
 979         .parent         = &sys_clkout2_src,
 980         .prcm_mod       = OMAP24XX_GR_MOD,
 981         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
 982                                 OFFSET_GR_MOD,
 983         .clkdm          = { .name = "cm_clkdm" },
 984         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 985         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 986         .clksel         = sys_clkout2_clksel,
 987         .recalc         = &omap2_clksel_recalc,
 988         .round_rate     = &omap2_clksel_round_rate,
 989         .set_rate       = &omap2_clksel_set_rate
 990 };
 991
 992 static struct clk emul_ck = {
 993         .name           = "emul_ck",
 994         .parent         = &func_54m_ck,
 995         .prcm_mod       = OMAP24XX_GR_MOD,
 996         .flags          = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
 997         .clkdm          = { .name = "cm_clkdm" },
 998         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
 999         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
1000         .recalc         = &followparent_recalc,
1001
1002 };
1003
1004 /*
1005  * MPU clock domain
1006  *      Clocks:
1007  *              MPU_FCLK, MPU_ICLK
1008  *              INT_M_FCLK, INT_M_I_CLK
1009  *
1010  * - Individual clocks are hardware managed.
1011  * - Base divider comes from: CM_CLKSEL_MPU
1012  *
1013  */
1014 static const struct clksel_rate mpu_core_rates[] = {
1015         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1016         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1017         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1018         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1019         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1020         { .div = 0 },
1021 };
1022
1023 static const struct clksel mpu_clksel[] = {
1024         { .parent = &core_ck, .rates = mpu_core_rates },
1025         { .parent = NULL }
1026 };
1027
1028 static struct clk mpu_ck = {    /* Control cpu */
1029         .name           = "mpu_ck",
1030         .parent         = &core_ck,
1031         .prcm_mod       = MPU_MOD,
1032         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1033                                 ALWAYS_ENABLED | DELAYED_APP |
1034                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1035         .clkdm          = { .name = "mpu_clkdm" },
1036         .init           = &omap2_init_clksel_parent,
1037         .clksel_reg     = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL),
1038         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1039         .clksel         = mpu_clksel,
1040         .recalc         = &omap2_clksel_recalc,
1041         .round_rate     = &omap2_clksel_round_rate,
1042         .set_rate       = &omap2_clksel_set_rate
1043 };
1044
1045 /*
1046  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1047  * Clocks:
1048  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1049  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1050  *
1051  * Won't be too specific here. The core clock comes into this block
1052  * it is divided then tee'ed. One branch goes directly to xyz enable
1053  * controls. The other branch gets further divided by 2 then possibly
1054  * routed into a synchronizer and out of clocks abc.
1055  */
1056 static const struct clksel_rate dsp_fck_core_rates[] = {
1057         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1058         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1059         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1060         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1061         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1062         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1063         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1064         { .div = 0 },
1065 };
1066
1067 static const struct clksel dsp_fck_clksel[] = {
1068         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1069         { .parent = NULL }
1070 };
1071
1072 static struct clk dsp_fck = {
1073         .name           = "dsp_fck",
1074         .parent         = &core_ck,
1075         .prcm_mod       = OMAP24XX_DSP_MOD,
1076         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1077                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1078         .clkdm          = { .name = "dsp_clkdm" },
1079         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1080         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1081         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1082         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1083         .clksel         = dsp_fck_clksel,
1084         .recalc         = &omap2_clksel_recalc,
1085         .round_rate     = &omap2_clksel_round_rate,
1086         .set_rate       = &omap2_clksel_set_rate
1087 };
1088
1089 /* DSP interface clock */
1090 static const struct clksel_rate dsp_irate_ick_rates[] = {
1091         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1092         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1093         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1094         { .div = 0 },
1095 };
1096
1097 static const struct clksel dsp_irate_ick_clksel[] = {
1098         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1099         { .parent = NULL }
1100 };
1101
1102 /* This clock does not exist as such in the TRM. */
1103 static struct clk dsp_irate_ick = {
1104         .name           = "dsp_irate_ick",
1105         .parent         = &dsp_fck,
1106         .prcm_mod       = OMAP24XX_DSP_MOD,
1107         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1108                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1109         .clkdm          = { .name = "dsp_clkdm" },
1110         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1111         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1112         .clksel         = dsp_irate_ick_clksel,
1113         .recalc         = &omap2_clksel_recalc,
1114         .round_rate     = &omap2_clksel_round_rate,
1115         .set_rate       = &omap2_clksel_set_rate
1116 };
1117
1118 /* 2420 only */
1119 static struct clk dsp_ick = {
1120         .name           = "dsp_ick",     /* apparently ipi and isp */
1121         .parent         = &dsp_irate_ick,
1122         .prcm_mod       = OMAP24XX_DSP_MOD,
1123         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1124         .clkdm          = { .name = "dsp_clkdm" },
1125         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
1126         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1127 };
1128
1129 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1130 static struct clk iva2_1_ick = {
1131         .name           = "iva2_1_ick",
1132         .parent         = &dsp_irate_ick,
1133         .prcm_mod       = OMAP24XX_DSP_MOD,
1134         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1135         .clkdm          = { .name = "dsp_clkdm" },
1136         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1137         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1138 };
1139
1140 /*
1141  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1142  * the C54x, but which is contained in the DSP powerdomain.  Does not
1143  * exist on later OMAPs.
1144  */
1145 static struct clk iva1_ifck = {
1146         .name           = "iva1_ifck",
1147         .parent         = &core_ck,
1148         .prcm_mod       = OMAP24XX_DSP_MOD,
1149         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1150                                 RATE_PROPAGATES | DELAYED_APP,
1151         .clkdm          = { .name = "iva1_clkdm" },
1152         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1153         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1154         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1155         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1156         .clksel         = dsp_fck_clksel,
1157         .recalc         = &omap2_clksel_recalc,
1158         .round_rate     = &omap2_clksel_round_rate,
1159         .set_rate       = &omap2_clksel_set_rate
1160 };
1161
1162 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1163 static struct clk iva1_mpu_int_ifck = {
1164         .name           = "iva1_mpu_int_ifck",
1165         .parent         = &iva1_ifck,
1166         .prcm_mod       = OMAP24XX_DSP_MOD,
1167         .flags          = CLOCK_IN_OMAP242X,
1168         .clkdm          = { .name = "iva1_clkdm" },
1169         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1170         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1171         .fixed_div      = 2,
1172         .recalc         = &omap2_fixed_divisor_recalc,
1173 };
1174
1175 /*
1176  * L3 clock domain
1177  * L3 clocks are used for both interface and functional clocks to
1178  * multiple entities. Some of these clocks are completely managed
1179  * by hardware, and some others allow software control. Hardware
1180  * managed ones general are based on directly CLK_REQ signals and
1181  * various auto idle settings. The functional spec sets many of these
1182  * as 'tie-high' for their enables.
1183  *
1184  * I-CLOCKS:
1185  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1186  *      CAM, HS-USB.
1187  * F-CLOCK
1188  *      SSI.
1189  *
1190  * GPMC memories and SDRC have timing and clock sensitive registers which
1191  * may very well need notification when the clock changes. Currently for low
1192  * operating points, these are taken care of in sleep.S.
1193  */
1194 static const struct clksel_rate core_l3_core_rates[] = {
1195         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1196         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1197         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1198         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1199         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1200         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1201         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1202         { .div = 0 }
1203 };
1204
1205 static const struct clksel core_l3_clksel[] = {
1206         { .parent = &core_ck, .rates = core_l3_core_rates },
1207         { .parent = NULL }
1208 };
1209
1210 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1211         .name           = "core_l3_ck",
1212         .parent         = &core_ck,
1213         .prcm_mod       = CORE_MOD,
1214         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1215                                 ALWAYS_ENABLED | DELAYED_APP |
1216                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1217         .clkdm          = { .name = "core_l3_clkdm" },
1218         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1219         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1220         .clksel         = core_l3_clksel,
1221         .recalc         = &omap2_clksel_recalc,
1222         .round_rate     = &omap2_clksel_round_rate,
1223         .set_rate       = &omap2_clksel_set_rate
1224 };
1225
1226 /* usb_l4_ick */
1227 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1228         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1229         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1230         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1231         { .div = 0 }
1232 };
1233
1234 static const struct clksel usb_l4_ick_clksel[] = {
1235         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1236         { .parent = NULL },
1237 };
1238
1239 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1240 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1241         .name           = "usb_l4_ick",
1242         .parent         = &core_l3_ck,
1243         .prcm_mod       = CORE_MOD,
1244         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1245                                 DELAYED_APP | CONFIG_PARTICIPANT,
1246         .clkdm          = { .name = "core_l4_clkdm" },
1247         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1248         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1249         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1250         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1251         .clksel         = usb_l4_ick_clksel,
1252         .recalc         = &omap2_clksel_recalc,
1253         .round_rate     = &omap2_clksel_round_rate,
1254         .set_rate       = &omap2_clksel_set_rate
1255 };
1256
1257 /*
1258  * L4 clock management domain
1259  *
1260  * This domain contains lots of interface clocks from the L4 interface, some
1261  * functional clocks.   Fixed APLL functional source clocks are managed in
1262  * this domain.
1263  */
1264 static const struct clksel_rate l4_core_l3_rates[] = {
1265         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1266         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1267         { .div = 0 }
1268 };
1269
1270 static const struct clksel l4_clksel[] = {
1271         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1272         { .parent = NULL }
1273 };
1274
1275 static struct clk l4_ck = {             /* used both as an ick and fck */
1276         .name           = "l4_ck",
1277         .parent         = &core_l3_ck,
1278         .prcm_mod       = CORE_MOD,
1279         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1280                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1281         .clkdm          = { .name = "core_l4_clkdm" },
1282         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1283         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1284         .clksel         = l4_clksel,
1285         .recalc         = &omap2_clksel_recalc,
1286         .round_rate     = &omap2_clksel_round_rate,
1287         .set_rate       = &omap2_clksel_set_rate
1288 };
1289
1290 /*
1291  * SSI is in L3 management domain, its direct parent is core not l3,
1292  * many core power domain entities are grouped into the L3 clock
1293  * domain.
1294  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1295  *
1296  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1297  */
1298 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1299         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1300         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1301         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1302         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1303         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1304         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1305         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1306         { .div = 0 }
1307 };
1308
1309 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1310         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1311         { .parent = NULL }
1312 };
1313
1314 static struct clk ssi_ssr_sst_fck = {
1315         .name           = "ssi_fck",
1316         .parent         = &core_ck,
1317         .prcm_mod       = CORE_MOD,
1318         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1319                                 DELAYED_APP,
1320         .clkdm          = { .name = "core_l3_clkdm" },
1321         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1322         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1323         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1324         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1325         .clksel         = ssi_ssr_sst_fck_clksel,
1326         .recalc         = &omap2_clksel_recalc,
1327         .round_rate     = &omap2_clksel_round_rate,
1328         .set_rate       = &omap2_clksel_set_rate
1329 };
1330
1331 /*
1332  * Presumably this is the same as SSI_ICLK.
1333  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1334  */
1335 static struct clk ssi_l4_ick = {
1336         .name           = "ssi_l4_ick",
1337         .parent         = &l4_ck,
1338         .prcm_mod       = CORE_MOD,
1339         .clkdm          = { .name = "core_l4_clkdm" },
1340         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1341         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1342         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346
1347 /*
1348  * GFX clock domain
1349  *      Clocks:
1350  * GFX_FCLK, GFX_ICLK
1351  * GFX_CG1(2d), GFX_CG2(3d)
1352  *
1353  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1354  * The 2d and 3d clocks run at a hardware determined
1355  * divided value of fclk.
1356  *
1357  */
1358 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1359
1360 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1361 static const struct clksel gfx_fck_clksel[] = {
1362         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1363         { .parent = NULL },
1364 };
1365
1366 static struct clk gfx_3d_fck = {
1367         .name           = "gfx_3d_fck",
1368         .parent         = &core_l3_ck,
1369         .prcm_mod       = GFX_MOD,
1370         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1371         .clkdm          = { .name = "gfx_clkdm" },
1372         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1373         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1374         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1375         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1376         .clksel         = gfx_fck_clksel,
1377         .recalc         = &omap2_clksel_recalc,
1378         .round_rate     = &omap2_clksel_round_rate,
1379         .set_rate       = &omap2_clksel_set_rate
1380 };
1381
1382 static struct clk gfx_2d_fck = {
1383         .name           = "gfx_2d_fck",
1384         .parent         = &core_l3_ck,
1385         .prcm_mod       = GFX_MOD,
1386         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1387         .clkdm          = { .name = "gfx_clkdm" },
1388         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1389         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1390         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1391         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1392         .clksel         = gfx_fck_clksel,
1393         .recalc         = &omap2_clksel_recalc,
1394         .round_rate     = &omap2_clksel_round_rate,
1395         .set_rate       = &omap2_clksel_set_rate
1396 };
1397
1398 static struct clk gfx_ick = {
1399         .name           = "gfx_ick",            /* From l3 */
1400         .parent         = &core_l3_ck,
1401         .prcm_mod       = GFX_MOD,
1402         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1403         .clkdm          = { .name = "gfx_clkdm" },
1404         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
1405         .enable_bit     = OMAP_EN_GFX_SHIFT,
1406         .recalc         = &followparent_recalc,
1407 };
1408
1409 /*
1410  * Modem clock domain (2430)
1411  *      CLOCKS:
1412  *              MDM_OSC_CLK
1413  *              MDM_ICLK
1414  * These clocks are usable in chassis mode only.
1415  */
1416 static const struct clksel_rate mdm_ick_core_rates[] = {
1417         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1418         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1419         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1420         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1421         { .div = 0 }
1422 };
1423
1424 static const struct clksel mdm_ick_clksel[] = {
1425         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1426         { .parent = NULL }
1427 };
1428
1429 static struct clk mdm_ick = {           /* used both as a ick and fck */
1430         .name           = "mdm_ick",
1431         .parent         = &core_ck,
1432         .prcm_mod       = OMAP2430_MDM_MOD,
1433         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1434         .clkdm          = { .name = "mdm_clkdm" },
1435         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
1436         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1437         .clksel_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL),
1438         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1439         .clksel         = mdm_ick_clksel,
1440         .recalc         = &omap2_clksel_recalc,
1441         .round_rate     = &omap2_clksel_round_rate,
1442         .set_rate       = &omap2_clksel_set_rate
1443 };
1444
1445 static struct clk mdm_osc_ck = {
1446         .name           = "mdm_osc_ck",
1447         .parent         = &osc_ck,
1448         .prcm_mod       = OMAP2430_MDM_MOD,
1449         .flags          = CLOCK_IN_OMAP243X,
1450         .clkdm          = { .name = "mdm_clkdm" },
1451         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
1452         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 /*
1457  * DSS clock domain
1458  * CLOCKs:
1459  * DSS_L4_ICLK, DSS_L3_ICLK,
1460  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1461  *
1462  * DSS is both initiator and target.
1463  */
1464 /* XXX Add RATE_NOT_VALIDATED */
1465
1466 static const struct clksel_rate dss1_fck_sys_rates[] = {
1467         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1468         { .div = 0 }
1469 };
1470
1471 static const struct clksel_rate dss1_fck_core_rates[] = {
1472         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1473         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1474         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1475         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1476         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1477         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1478         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1479         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1480         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1481         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1482         { .div = 0 }
1483 };
1484
1485 static const struct clksel dss1_fck_clksel[] = {
1486         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1487         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1488         { .parent = NULL },
1489 };
1490
1491 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1492         .name           = "dss_ick",
1493         .parent         = &l4_ck,       /* really both l3 and l4 */
1494         .prcm_mod       = CORE_MOD,
1495         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1496         .clkdm          = { .name = "dss_clkdm" },
1497         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1498         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1499         .recalc         = &followparent_recalc,
1500 };
1501
1502 static struct clk dss1_fck = {
1503         .name           = "dss1_fck",
1504         .parent         = &core_ck,             /* Core or sys */
1505         .prcm_mod       = CORE_MOD,
1506         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1507                                 DELAYED_APP,
1508         .clkdm          = { .name = "dss_clkdm" },
1509         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1510         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1511         .init           = &omap2_init_clksel_parent,
1512         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1513         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1514         .clksel         = dss1_fck_clksel,
1515         .recalc         = &omap2_clksel_recalc,
1516         .round_rate     = &omap2_clksel_round_rate,
1517         .set_rate       = &omap2_clksel_set_rate
1518 };
1519
1520 static const struct clksel_rate dss2_fck_sys_rates[] = {
1521         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1522         { .div = 0 }
1523 };
1524
1525 static const struct clksel_rate dss2_fck_48m_rates[] = {
1526         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1527         { .div = 0 }
1528 };
1529
1530 static const struct clksel dss2_fck_clksel[] = {
1531         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1532         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1533         { .parent = NULL }
1534 };
1535
1536 static struct clk dss2_fck = {          /* Alt clk used in power management */
1537         .name           = "dss2_fck",
1538         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1539         .prcm_mod       = CORE_MOD,
1540         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1541                                 DELAYED_APP,
1542         .clkdm          = { .name = "dss_clkdm" },
1543         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1544         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1545         .init           = &omap2_init_clksel_parent,
1546         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1547         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1548         .clksel         = dss2_fck_clksel,
1549         .recalc         = &followparent_recalc,
1550 };
1551
1552 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1553         .name           = "dss_54m_fck",        /* 54m tv clk */
1554         .parent         = &func_54m_ck,
1555         .prcm_mod       = CORE_MOD,
1556         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1557         .clkdm          = { .name = "dss_clkdm" },
1558         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 /*
1564  * CORE power domain ICLK & FCLK defines.
1565  * Many of the these can have more than one possible parent. Entries
1566  * here will likely have an L4 interface parent, and may have multiple
1567  * functional clock parents.
1568  */
1569 static const struct clksel_rate gpt_alt_rates[] = {
1570         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1571         { .div = 0 }
1572 };
1573
1574 static const struct clksel omap24xx_gpt_clksel[] = {
1575         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1576         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1577         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1578         { .parent = NULL },
1579 };
1580
1581 static struct clk gpt1_ick = {
1582         .name           = "gpt1_ick",
1583         .parent         = &l4_ck,
1584         .prcm_mod       = WKUP_MOD,
1585         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1586         .clkdm          = { .name = "core_l4_clkdm" },
1587         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
1588         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1589         .recalc         = &followparent_recalc,
1590 };
1591
1592 static struct clk gpt1_fck = {
1593         .name           = "gpt1_fck",
1594         .parent         = &func_32k_ck,
1595         .prcm_mod       = WKUP_MOD,
1596         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597         .clkdm          = { .name = "core_l4_clkdm" },
1598         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
1599         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1600         .init           = &omap2_init_clksel_parent,
1601         .clksel_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_CLKSEL1),
1602         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1603         .clksel         = omap24xx_gpt_clksel,
1604         .recalc         = &omap2_clksel_recalc,
1605         .round_rate     = &omap2_clksel_round_rate,
1606         .set_rate       = &omap2_clksel_set_rate
1607 };
1608
1609 static struct clk gpt2_ick = {
1610         .name           = "gpt2_ick",
1611         .parent         = &l4_ck,
1612         .prcm_mod       = CORE_MOD,
1613         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1614         .clkdm          = { .name = "core_l4_clkdm" },
1615         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1616         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1617         .recalc         = &followparent_recalc,
1618 };
1619
1620 static struct clk gpt2_fck = {
1621         .name           = "gpt2_fck",
1622         .parent         = &func_32k_ck,
1623         .prcm_mod       = CORE_MOD,
1624         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1625         .clkdm          = { .name = "core_l4_clkdm" },
1626         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1627         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1628         .init           = &omap2_init_clksel_parent,
1629         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1630         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1631         .clksel         = omap24xx_gpt_clksel,
1632         .recalc         = &omap2_clksel_recalc,
1633 };
1634
1635 static struct clk gpt3_ick = {
1636         .name           = "gpt3_ick",
1637         .parent         = &l4_ck,
1638         .prcm_mod       = CORE_MOD,
1639         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1640         .clkdm          = { .name = "core_l4_clkdm" },
1641         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1642         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1643         .recalc         = &followparent_recalc,
1644 };
1645
1646 static struct clk gpt3_fck = {
1647         .name           = "gpt3_fck",
1648         .parent         = &func_32k_ck,
1649         .prcm_mod       = CORE_MOD,
1650         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1651         .clkdm          = { .name = "core_l4_clkdm" },
1652         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1653         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1654         .init           = &omap2_init_clksel_parent,
1655         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1656         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1657         .clksel         = omap24xx_gpt_clksel,
1658         .recalc         = &omap2_clksel_recalc,
1659 };
1660
1661 static struct clk gpt4_ick = {
1662         .name           = "gpt4_ick",
1663         .parent         = &l4_ck,
1664         .prcm_mod       = CORE_MOD,
1665         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1666         .clkdm          = { .name = "core_l4_clkdm" },
1667         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1668         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1669         .recalc         = &followparent_recalc,
1670 };
1671
1672 static struct clk gpt4_fck = {
1673         .name           = "gpt4_fck",
1674         .parent         = &func_32k_ck,
1675         .prcm_mod       = CORE_MOD,
1676         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1677         .clkdm          = { .name = "core_l4_clkdm" },
1678         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1679         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1680         .init           = &omap2_init_clksel_parent,
1681         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1682         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1683         .clksel         = omap24xx_gpt_clksel,
1684         .recalc         = &omap2_clksel_recalc,
1685 };
1686
1687 static struct clk gpt5_ick = {
1688         .name           = "gpt5_ick",
1689         .parent         = &l4_ck,
1690         .prcm_mod       = CORE_MOD,
1691         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692         .clkdm          = { .name = "core_l4_clkdm" },
1693         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1694         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1695         .recalc         = &followparent_recalc,
1696 };
1697
1698 static struct clk gpt5_fck = {
1699         .name           = "gpt5_fck",
1700         .parent         = &func_32k_ck,
1701         .prcm_mod       = CORE_MOD,
1702         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1703         .clkdm          = { .name = "core_l4_clkdm" },
1704         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1705         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1706         .init           = &omap2_init_clksel_parent,
1707         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1708         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1709         .clksel         = omap24xx_gpt_clksel,
1710         .recalc         = &omap2_clksel_recalc,
1711 };
1712
1713 static struct clk gpt6_ick = {
1714         .name           = "gpt6_ick",
1715         .parent         = &l4_ck,
1716         .prcm_mod       = CORE_MOD,
1717         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1718         .clkdm          = { .name = "core_l4_clkdm" },
1719         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1720         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1721         .recalc         = &followparent_recalc,
1722 };
1723
1724 static struct clk gpt6_fck = {
1725         .name           = "gpt6_fck",
1726         .parent         = &func_32k_ck,
1727         .prcm_mod       = CORE_MOD,
1728         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1729         .clkdm          = { .name = "core_l4_clkdm" },
1730         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1731         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1732         .init           = &omap2_init_clksel_parent,
1733         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1734         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1735         .clksel         = omap24xx_gpt_clksel,
1736         .recalc         = &omap2_clksel_recalc,
1737 };
1738
1739 static struct clk gpt7_ick = {
1740         .name           = "gpt7_ick",
1741         .parent         = &l4_ck,
1742         .prcm_mod       = CORE_MOD,
1743         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1744         .clkdm          = { .name = "core_l4_clkdm" },
1745         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1746         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1747         .recalc         = &followparent_recalc,
1748 };
1749
1750 static struct clk gpt7_fck = {
1751         .name           = "gpt7_fck",
1752         .parent         = &func_32k_ck,
1753         .prcm_mod       = CORE_MOD,
1754         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1755         .clkdm          = { .name = "core_l4_clkdm" },
1756         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1757         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1758         .init           = &omap2_init_clksel_parent,
1759         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1760         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1761         .clksel         = omap24xx_gpt_clksel,
1762         .recalc         = &omap2_clksel_recalc,
1763 };
1764
1765 static struct clk gpt8_ick = {
1766         .name           = "gpt8_ick",
1767         .parent         = &l4_ck,
1768         .prcm_mod       = CORE_MOD,
1769         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1770         .clkdm          = { .name = "core_l4_clkdm" },
1771         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1772         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1773         .recalc         = &followparent_recalc,
1774 };
1775
1776 static struct clk gpt8_fck = {
1777         .name           = "gpt8_fck",
1778         .parent         = &func_32k_ck,
1779         .prcm_mod       = CORE_MOD,
1780         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1781         .clkdm          = { .name = "core_l4_clkdm" },
1782         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1783         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1784         .init           = &omap2_init_clksel_parent,
1785         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1786         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1787         .clksel         = omap24xx_gpt_clksel,
1788         .recalc         = &omap2_clksel_recalc,
1789 };
1790
1791 static struct clk gpt9_ick = {
1792         .name           = "gpt9_ick",
1793         .parent         = &l4_ck,
1794         .prcm_mod       = CORE_MOD,
1795         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1796         .clkdm          = { .name = "core_l4_clkdm" },
1797         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1798         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1799         .recalc         = &followparent_recalc,
1800 };
1801
1802 static struct clk gpt9_fck = {
1803         .name           = "gpt9_fck",
1804         .parent         = &func_32k_ck,
1805         .prcm_mod       = CORE_MOD,
1806         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1807         .clkdm          = { .name = "core_l4_clkdm" },
1808         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1809         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1810         .init           = &omap2_init_clksel_parent,
1811         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1812         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1813         .clksel         = omap24xx_gpt_clksel,
1814         .recalc         = &omap2_clksel_recalc,
1815 };
1816
1817 static struct clk gpt10_ick = {
1818         .name           = "gpt10_ick",
1819         .parent         = &l4_ck,
1820         .prcm_mod       = CORE_MOD,
1821         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1822         .clkdm          = { .name = "core_l4_clkdm" },
1823         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1824         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk gpt10_fck = {
1829         .name           = "gpt10_fck",
1830         .parent         = &func_32k_ck,
1831         .prcm_mod       = CORE_MOD,
1832         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1833         .clkdm          = { .name = "core_l4_clkdm" },
1834         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1835         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1836         .init           = &omap2_init_clksel_parent,
1837         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1838         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1839         .clksel         = omap24xx_gpt_clksel,
1840         .recalc         = &omap2_clksel_recalc,
1841 };
1842
1843 static struct clk gpt11_ick = {
1844         .name           = "gpt11_ick",
1845         .parent         = &l4_ck,
1846         .prcm_mod       = CORE_MOD,
1847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1848         .clkdm          = { .name = "core_l4_clkdm" },
1849         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1850         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1851         .recalc         = &followparent_recalc,
1852 };
1853
1854 static struct clk gpt11_fck = {
1855         .name           = "gpt11_fck",
1856         .parent         = &func_32k_ck,
1857         .prcm_mod       = CORE_MOD,
1858         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1859         .clkdm          = { .name = "core_l4_clkdm" },
1860         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1861         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1862         .init           = &omap2_init_clksel_parent,
1863         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1864         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1865         .clksel         = omap24xx_gpt_clksel,
1866         .recalc         = &omap2_clksel_recalc,
1867 };
1868
1869 static struct clk gpt12_ick = {
1870         .name           = "gpt12_ick",
1871         .parent         = &l4_ck,
1872         .prcm_mod       = CORE_MOD,
1873         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1874         .clkdm          = { .name = "core_l4_clkdm" },
1875         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1876         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1877         .recalc         = &followparent_recalc,
1878 };
1879
1880 static struct clk gpt12_fck = {
1881         .name           = "gpt12_fck",
1882         .parent         = &func_32k_ck,
1883         .prcm_mod       = CORE_MOD,
1884         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1885         .clkdm          = { .name = "core_l4_clkdm" },
1886         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1887         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1888         .init           = &omap2_init_clksel_parent,
1889         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1890         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1891         .clksel         = omap24xx_gpt_clksel,
1892         .recalc         = &omap2_clksel_recalc,
1893 };
1894
1895 static struct clk mcbsp1_ick = {
1896         .name           = "mcbsp_ick",
1897         .id             = 1,
1898         .parent         = &l4_ck,
1899         .prcm_mod       = CORE_MOD,
1900         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1901         .clkdm          = { .name = "core_l4_clkdm" },
1902         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1903         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mcbsp1_fck = {
1908         .name           = "mcbsp_fck",
1909         .id             = 1,
1910         .parent         = &func_96m_ck,
1911         .prcm_mod       = CORE_MOD,
1912         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1913         .clkdm          = { .name = "core_l4_clkdm" },
1914         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1915         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1916         .recalc         = &followparent_recalc,
1917 };
1918
1919 static struct clk mcbsp2_ick = {
1920         .name           = "mcbsp_ick",
1921         .id             = 2,
1922         .parent         = &l4_ck,
1923         .prcm_mod       = CORE_MOD,
1924         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1925         .clkdm          = { .name = "core_l4_clkdm" },
1926         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1928         .recalc         = &followparent_recalc,
1929 };
1930
1931 static struct clk mcbsp2_fck = {
1932         .name           = "mcbsp_fck",
1933         .id             = 2,
1934         .parent         = &func_96m_ck,
1935         .prcm_mod       = CORE_MOD,
1936         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1937         .clkdm          = { .name = "core_l4_clkdm" },
1938         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1939         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk mcbsp3_ick = {
1944         .name           = "mcbsp_ick",
1945         .id             = 3,
1946         .parent         = &l4_ck,
1947         .prcm_mod       = CORE_MOD,
1948         .flags          = CLOCK_IN_OMAP243X,
1949         .clkdm          = { .name = "core_l4_clkdm" },
1950         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1951         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk mcbsp3_fck = {
1956         .name           = "mcbsp_fck",
1957         .id             = 3,
1958         .parent         = &func_96m_ck,
1959         .prcm_mod       = CORE_MOD,
1960         .flags          = CLOCK_IN_OMAP243X,
1961         .clkdm          = { .name = "core_l4_clkdm" },
1962         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1963         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1964         .recalc         = &followparent_recalc,
1965 };
1966
1967 static struct clk mcbsp4_ick = {
1968         .name           = "mcbsp_ick",
1969         .id             = 4,
1970         .parent         = &l4_ck,
1971         .prcm_mod       = CORE_MOD,
1972         .flags          = CLOCK_IN_OMAP243X,
1973         .clkdm          = { .name = "core_l4_clkdm" },
1974         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1975         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk mcbsp4_fck = {
1980         .name           = "mcbsp_fck",
1981         .id             = 4,
1982         .parent         = &func_96m_ck,
1983         .prcm_mod       = CORE_MOD,
1984         .flags          = CLOCK_IN_OMAP243X,
1985         .clkdm          = { .name = "core_l4_clkdm" },
1986         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1987         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1988         .recalc         = &followparent_recalc,
1989 };
1990
1991 static struct clk mcbsp5_ick = {
1992         .name           = "mcbsp_ick",
1993         .id             = 5,
1994         .parent         = &l4_ck,
1995         .prcm_mod       = CORE_MOD,
1996         .flags          = CLOCK_IN_OMAP243X,
1997         .clkdm          = { .name = "core_l4_clkdm" },
1998         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1999         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2000         .recalc         = &followparent_recalc,
2001 };
2002
2003 static struct clk mcbsp5_fck = {
2004         .name           = "mcbsp_fck",
2005         .id             = 5,
2006         .parent         = &func_96m_ck,
2007         .prcm_mod       = CORE_MOD,
2008         .flags          = CLOCK_IN_OMAP243X,
2009         .clkdm          = { .name = "core_l4_clkdm" },
2010         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2011         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2012         .recalc         = &followparent_recalc,
2013 };
2014
2015 static struct clk mcspi1_ick = {
2016         .name           = "mcspi_ick",
2017         .id             = 1,
2018         .parent         = &l4_ck,
2019         .prcm_mod       = CORE_MOD,
2020         .clkdm          = { .name = "core_l4_clkdm" },
2021         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2022         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2023         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2024         .recalc         = &followparent_recalc,
2025 };
2026
2027 static struct clk mcspi1_fck = {
2028         .name           = "mcspi_fck",
2029         .id             = 1,
2030         .parent         = &func_48m_ck,
2031         .prcm_mod       = CORE_MOD,
2032         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2033         .clkdm          = { .name = "core_l4_clkdm" },
2034         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2035         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk mcspi2_ick = {
2040         .name           = "mcspi_ick",
2041         .id             = 2,
2042         .parent         = &l4_ck,
2043         .prcm_mod       = CORE_MOD,
2044         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2045         .clkdm          = { .name = "core_l4_clkdm" },
2046         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2047         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2048         .recalc         = &followparent_recalc,
2049 };
2050
2051 static struct clk mcspi2_fck = {
2052         .name           = "mcspi_fck",
2053         .id             = 2,
2054         .parent         = &func_48m_ck,
2055         .prcm_mod       = CORE_MOD,
2056         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2057         .clkdm          = { .name = "core_l4_clkdm" },
2058         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2059         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2060         .recalc         = &followparent_recalc,
2061 };
2062
2063 static struct clk mcspi3_ick = {
2064         .name           = "mcspi_ick",
2065         .id             = 3,
2066         .parent         = &l4_ck,
2067         .prcm_mod       = CORE_MOD,
2068         .flags          = CLOCK_IN_OMAP243X,
2069         .clkdm          = { .name = "core_l4_clkdm" },
2070         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2071         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 static struct clk mcspi3_fck = {
2076         .name           = "mcspi_fck",
2077         .id             = 3,
2078         .parent         = &func_48m_ck,
2079         .prcm_mod       = CORE_MOD,
2080         .flags          = CLOCK_IN_OMAP243X,
2081         .clkdm          = { .name = "core_l4_clkdm" },
2082         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2083         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2084         .recalc         = &followparent_recalc,
2085 };
2086
2087 static struct clk uart1_ick = {
2088         .name           = "uart1_ick",
2089         .parent         = &l4_ck,
2090         .prcm_mod       = CORE_MOD,
2091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2092         .clkdm          = { .name = "core_l4_clkdm" },
2093         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2094         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2095         .recalc         = &followparent_recalc,
2096 };
2097
2098 static struct clk uart1_fck = {
2099         .name           = "uart1_fck",
2100         .parent         = &func_48m_ck,
2101         .prcm_mod       = CORE_MOD,
2102         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2103         .clkdm          = { .name = "core_l4_clkdm" },
2104         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2105         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2106         .recalc         = &followparent_recalc,
2107 };
2108
2109 static struct clk uart2_ick = {
2110         .name           = "uart2_ick",
2111         .parent         = &l4_ck,
2112         .prcm_mod       = CORE_MOD,
2113         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2114         .clkdm          = { .name = "core_l4_clkdm" },
2115         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2116         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk uart2_fck = {
2121         .name           = "uart2_fck",
2122         .parent         = &func_48m_ck,
2123         .prcm_mod       = CORE_MOD,
2124         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2125         .clkdm          = { .name = "core_l4_clkdm" },
2126         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2127         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk uart3_ick = {
2132         .name           = "uart3_ick",
2133         .parent         = &l4_ck,
2134         .prcm_mod       = CORE_MOD,
2135         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2136         .clkdm          = { .name = "core_l4_clkdm" },
2137         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2138         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2139         .recalc         = &followparent_recalc,
2140 };
2141
2142 static struct clk uart3_fck = {
2143         .name           = "uart3_fck",
2144         .parent         = &func_48m_ck,
2145         .prcm_mod       = CORE_MOD,
2146         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2147         .clkdm          = { .name = "core_l4_clkdm" },
2148         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2149         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2150         .recalc         = &followparent_recalc,
2151 };
2152
2153 static struct clk gpios_ick = {
2154         .name           = "gpios_ick",
2155         .parent         = &l4_ck,
2156         .prcm_mod       = WKUP_MOD,
2157         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2158         .clkdm          = { .name = "core_l4_clkdm" },
2159         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2160         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 static struct clk gpios_fck = {
2165         .name           = "gpios_fck",
2166         .parent         = &func_32k_ck,
2167         .prcm_mod       = WKUP_MOD,
2168         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2169         .clkdm          = { .name = "prm_clkdm" },
2170         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2171         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2176 static struct clk mpu_wdt_ick = {
2177         .name           = "mpu_wdt_ick",
2178         .parent         = &l4_ck,
2179         .prcm_mod       = WKUP_MOD,
2180         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2181         .clkdm          = { .name = "prm_clkdm" },
2182         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2183         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2184         .recalc         = &followparent_recalc,
2185 };
2186
2187 /* aka WDT2 */
2188 static struct clk mpu_wdt_fck = {
2189         .name           = "mpu_wdt_fck",
2190         .parent         = &func_32k_ck,
2191         .prcm_mod       = WKUP_MOD,
2192         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2193         .clkdm          = { .name = "prm_clkdm" },
2194         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2195         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2196         .recalc         = &followparent_recalc,
2197 };
2198
2199 static struct clk sync_32k_ick = {
2200         .name           = "sync_32k_ick",
2201         .parent         = &l4_ck,
2202         .prcm_mod       = WKUP_MOD,
2203         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2204                                 ENABLE_ON_INIT,
2205         .clkdm          = { .name = "core_l4_clkdm" },
2206         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2207         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 /* REVISIT: parent is really wu_l4_iclk */
2212 static struct clk wdt1_ick = {
2213         .name           = "wdt1_ick",
2214         .parent         = &l4_ck,
2215         .prcm_mod       = WKUP_MOD,
2216         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2217         .clkdm          = { .name = "prm_clkdm" },
2218         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2219         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk omapctrl_ick = {
2224         .name           = "omapctrl_ick",
2225         .parent         = &l4_ck,
2226         .prcm_mod       = WKUP_MOD,
2227         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2228                                 ENABLE_ON_INIT,
2229         .clkdm          = { .name = "core_l4_clkdm" },
2230         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2231         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2232         .recalc         = &followparent_recalc,
2233 };
2234
2235 static struct clk icr_ick = {
2236         .name           = "icr_ick",
2237         .parent         = &l4_ck,
2238         .prcm_mod       = WKUP_MOD,
2239         .flags          = CLOCK_IN_OMAP243X,
2240         .clkdm          = { .name = "core_l4_clkdm" },
2241         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2242         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2243         .recalc         = &followparent_recalc,
2244 };
2245
2246 static struct clk cam_ick = {
2247         .name           = "cam_ick",
2248         .parent         = &l4_ck,
2249         .prcm_mod       = CORE_MOD,
2250         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2251         .clkdm          = { .name = "core_l4_clkdm" },
2252         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2253         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2254         .recalc         = &followparent_recalc,
2255 };
2256
2257 /*
2258  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2259  * split into two separate clocks, since the parent clocks are different
2260  * and the clockdomains are also different.
2261  */
2262 static struct clk cam_fck = {
2263         .name           = "cam_fck",
2264         .parent         = &func_96m_ck,
2265         .prcm_mod       = CORE_MOD,
2266         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2267         .clkdm          = { .name = "core_l3_clkdm" },
2268         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2269         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk mailboxes_ick = {
2274         .name           = "mailboxes_ick",
2275         .parent         = &l4_ck,
2276         .prcm_mod       = CORE_MOD,
2277         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2278         .clkdm          = { .name = "core_l4_clkdm" },
2279         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2280         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2281         .recalc         = &followparent_recalc,
2282 };
2283
2284 static struct clk wdt4_ick = {
2285         .name           = "wdt4_ick",
2286         .parent         = &l4_ck,
2287         .prcm_mod       = CORE_MOD,
2288         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2289         .clkdm          = { .name = "core_l4_clkdm" },
2290         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2291         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2292         .recalc         = &followparent_recalc,
2293 };
2294
2295 static struct clk wdt4_fck = {
2296         .name           = "wdt4_fck",
2297         .parent         = &func_32k_ck,
2298         .prcm_mod       = CORE_MOD,
2299         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2300         .clkdm          = { .name = "core_l4_clkdm" },
2301         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2302         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2303         .recalc         = &followparent_recalc,
2304 };
2305
2306 static struct clk wdt3_ick = {
2307         .name           = "wdt3_ick",
2308         .parent         = &l4_ck,
2309         .prcm_mod       = CORE_MOD,
2310         .flags          = CLOCK_IN_OMAP242X,
2311         .clkdm          = { .name = "core_l4_clkdm" },
2312         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2313         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2314         .recalc         = &followparent_recalc,
2315 };
2316
2317 static struct clk wdt3_fck = {
2318         .name           = "wdt3_fck",
2319         .parent         = &func_32k_ck,
2320         .prcm_mod       = CORE_MOD,
2321         .flags          = CLOCK_IN_OMAP242X,
2322         .clkdm          = { .name = "core_l4_clkdm" },
2323         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2324         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2325         .recalc         = &followparent_recalc,
2326 };
2327
2328 static struct clk mspro_ick = {
2329         .name           = "mspro_ick",
2330         .parent         = &l4_ck,
2331         .prcm_mod       = CORE_MOD,
2332         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2333         .clkdm          = { .name = "core_l4_clkdm" },
2334         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2335         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2336         .recalc         = &followparent_recalc,
2337 };
2338
2339 static struct clk mspro_fck = {
2340         .name           = "mspro_fck",
2341         .parent         = &func_96m_ck,
2342         .prcm_mod       = CORE_MOD,
2343         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2344         .clkdm          = { .name = "core_l4_clkdm" },
2345         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2346         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2347         .recalc         = &followparent_recalc,
2348 };
2349
2350 static struct clk mmc_ick = {
2351         .name           = "mmc_ick",
2352         .parent         = &l4_ck,
2353         .prcm_mod       = CORE_MOD,
2354         .flags          = CLOCK_IN_OMAP242X,
2355         .clkdm          = { .name = "core_l4_clkdm" },
2356         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2357         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2358         .recalc         = &followparent_recalc,
2359 };
2360
2361 static struct clk mmc_fck = {
2362         .name           = "mmc_fck",
2363         .parent         = &func_96m_ck,
2364         .prcm_mod       = CORE_MOD,
2365         .flags          = CLOCK_IN_OMAP242X,
2366         .clkdm          = { .name = "core_l4_clkdm" },
2367         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2368         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2369         .recalc         = &followparent_recalc,
2370 };
2371
2372 static struct clk fac_ick = {
2373         .name           = "fac_ick",
2374         .parent         = &l4_ck,
2375         .prcm_mod       = CORE_MOD,
2376         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2377         .clkdm          = { .name = "core_l4_clkdm" },
2378         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2379         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2380         .recalc         = &followparent_recalc,
2381 };
2382
2383 static struct clk fac_fck = {
2384         .name           = "fac_fck",
2385         .parent         = &func_12m_ck,
2386         .prcm_mod       = CORE_MOD,
2387         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2388         .clkdm          = { .name = "core_l4_clkdm" },
2389         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2390         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2391         .recalc         = &followparent_recalc,
2392 };
2393
2394 static struct clk eac_ick = {
2395         .name           = "eac_ick",
2396         .parent         = &l4_ck,
2397         .prcm_mod       = CORE_MOD,
2398         .flags          = CLOCK_IN_OMAP242X,
2399         .clkdm          = { .name = "core_l4_clkdm" },
2400         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2401         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2402         .recalc         = &followparent_recalc,
2403 };
2404
2405 static struct clk eac_fck = {
2406         .name           = "eac_fck",
2407         .parent         = &func_96m_ck,
2408         .prcm_mod       = CORE_MOD,
2409         .flags          = CLOCK_IN_OMAP242X,
2410         .clkdm          = { .name = "core_l4_clkdm" },
2411         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2412         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2413         .recalc         = &followparent_recalc,
2414 };
2415
2416 static struct clk hdq_ick = {
2417         .name           = "hdq_ick",
2418         .parent         = &l4_ck,
2419         .prcm_mod       = CORE_MOD,
2420         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2421         .clkdm          = { .name = "core_l4_clkdm" },
2422         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2423         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk hdq_fck = {
2428         .name           = "hdq_fck",
2429         .parent         = &func_12m_ck,
2430         .prcm_mod       = CORE_MOD,
2431         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2432         .clkdm          = { .name = "core_l4_clkdm" },
2433         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2434         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2435         .recalc         = &followparent_recalc,
2436 };
2437
2438 static struct clk i2c2_ick = {
2439         .name           = "i2c_ick",
2440         .id             = 2,
2441         .parent         = &l4_ck,
2442         .prcm_mod       = CORE_MOD,
2443         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2444         .clkdm          = { .name = "core_l4_clkdm" },
2445         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2446         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2447         .recalc         = &followparent_recalc,
2448 };
2449
2450 static struct clk i2c2_fck = {
2451         .name           = "i2c_fck",
2452         .id             = 2,
2453         .parent         = &func_12m_ck,
2454         .prcm_mod       = CORE_MOD,
2455         .flags          = CLOCK_IN_OMAP242X,
2456         .clkdm          = { .name = "core_l4_clkdm" },
2457         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2458         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2459         .recalc         = &followparent_recalc,
2460 };
2461
2462 static struct clk i2chs2_fck = {
2463         .name           = "i2chs_fck",
2464         .id             = 2,
2465         .parent         = &func_96m_ck,
2466         .prcm_mod       = CORE_MOD,
2467         .flags          = CLOCK_IN_OMAP243X,
2468         .clkdm          = { .name = "core_l4_clkdm" },
2469         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2470         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2471         .recalc         = &followparent_recalc,
2472 };
2473
2474 static struct clk i2c1_ick = {
2475         .name           = "i2c_ick",
2476         .id             = 1,
2477         .parent         = &l4_ck,
2478         .prcm_mod       = CORE_MOD,
2479         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2480         .clkdm          = { .name = "core_l4_clkdm" },
2481         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2482         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2483         .recalc         = &followparent_recalc,
2484 };
2485
2486 static struct clk i2c1_fck = {
2487         .name           = "i2c_fck",
2488         .id             = 1,
2489         .parent         = &func_12m_ck,
2490         .prcm_mod       = CORE_MOD,
2491         .flags          = CLOCK_IN_OMAP242X,
2492         .clkdm          = { .name = "core_l4_clkdm" },
2493         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2494         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2495         .recalc         = &followparent_recalc,
2496 };
2497
2498 static struct clk i2chs1_fck = {
2499         .name           = "i2chs_fck",
2500         .id             = 1,
2501         .parent         = &func_96m_ck,
2502         .prcm_mod       = CORE_MOD,
2503         .flags          = CLOCK_IN_OMAP243X,
2504         .clkdm          = { .name = "core_l4_clkdm" },
2505         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2506         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2507         .recalc         = &followparent_recalc,
2508 };
2509
2510 static struct clk gpmc_fck = {
2511         .name           = "gpmc_fck",
2512         .parent         = &core_l3_ck,
2513         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2514                                 ENABLE_ON_INIT,
2515         .clkdm          = { .name = "core_l3_clkdm" },
2516         .recalc         = &followparent_recalc,
2517 };
2518
2519 static struct clk sdma_fck = {
2520         .name           = "sdma_fck",
2521         .parent         = &core_l3_ck,
2522         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2523         .clkdm          = { .name = "core_l3_clkdm" },
2524         .recalc         = &followparent_recalc,
2525 };
2526
2527 static struct clk sdma_ick = {
2528         .name           = "sdma_ick",
2529         .parent         = &l4_ck,
2530         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2531         .clkdm          = { .name = "core_l3_clkdm" },
2532         .recalc         = &followparent_recalc,
2533 };
2534
2535 static struct clk vlynq_ick = {
2536         .name           = "vlynq_ick",
2537         .parent         = &core_l3_ck,
2538         .prcm_mod       = CORE_MOD,
2539         .flags          = CLOCK_IN_OMAP242X,
2540         .clkdm          = { .name = "core_l3_clkdm" },
2541         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2542         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2543         .recalc         = &followparent_recalc,
2544 };
2545
2546 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2547         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2548         { .div = 0 }
2549 };
2550
2551 static const struct clksel_rate vlynq_fck_core_rates[] = {
2552         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2553         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2554         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2555         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2556         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2557         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2558         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2559         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2560         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2561         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2562         { .div = 0 }
2563 };
2564
2565 static const struct clksel vlynq_fck_clksel[] = {
2566         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2567         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2568         { .parent = NULL }
2569 };
2570
2571 static struct clk vlynq_fck = {
2572         .name           = "vlynq_fck",
2573         .parent         = &func_96m_ck,
2574         .prcm_mod       = CORE_MOD,
2575         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2576         .clkdm          = { .name = "core_l3_clkdm" },
2577         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2578         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2579         .init           = &omap2_init_clksel_parent,
2580         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
2581         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2582         .clksel         = vlynq_fck_clksel,
2583         .recalc         = &omap2_clksel_recalc,
2584         .round_rate     = &omap2_clksel_round_rate,
2585         .set_rate       = &omap2_clksel_set_rate
2586 };
2587
2588 static struct clk sdrc_ick = {
2589         .name           = "sdrc_ick",
2590         .parent         = &l4_ck,
2591         .prcm_mod       = CORE_MOD,
2592         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2593         .clkdm          = { .name = "core_l4_clkdm" },
2594         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
2595         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2596         .recalc         = &followparent_recalc,
2597 };
2598
2599 static struct clk des_ick = {
2600         .name           = "des_ick",
2601         .parent         = &l4_ck,
2602         .prcm_mod       = CORE_MOD,
2603         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2604         .clkdm          = { .name = "core_l4_clkdm" },
2605         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2606         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2607         .recalc         = &followparent_recalc,
2608 };
2609
2610 static struct clk sha_ick = {
2611         .name           = "sha_ick",
2612         .parent         = &l4_ck,
2613         .prcm_mod       = CORE_MOD,
2614         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2615         .clkdm          = { .name = "core_l4_clkdm" },
2616         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2617         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2618         .recalc         = &followparent_recalc,
2619 };
2620
2621 static struct clk rng_ick = {
2622         .name           = "rng_ick",
2623         .parent         = &l4_ck,
2624         .prcm_mod       = CORE_MOD,
2625         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2626         .clkdm          = { .name = "core_l4_clkdm" },
2627         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2628         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2629         .recalc         = &followparent_recalc,
2630 };
2631
2632 static struct clk aes_ick = {
2633         .name           = "aes_ick",
2634         .parent         = &l4_ck,
2635         .prcm_mod       = CORE_MOD,
2636         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2637         .clkdm          = { .name = "core_l4_clkdm" },
2638         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2639         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2640         .recalc         = &followparent_recalc,
2641 };
2642
2643 static struct clk pka_ick = {
2644         .name           = "pka_ick",
2645         .parent         = &l4_ck,
2646         .prcm_mod       = CORE_MOD,
2647         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2648         .clkdm          = { .name = "core_l4_clkdm" },
2649         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2650         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2651         .recalc         = &followparent_recalc,
2652 };
2653
2654 static struct clk usb_fck = {
2655         .name           = "usb_fck",
2656         .parent         = &func_48m_ck,
2657         .prcm_mod       = CORE_MOD,
2658         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2659         .clkdm          = { .name = "core_l3_clkdm" },
2660         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2661         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2662         .recalc         = &followparent_recalc,
2663 };
2664
2665 static struct clk usbhs_ick = {
2666         .name           = "usbhs_ick",
2667         .parent         = &core_l3_ck,
2668         .prcm_mod       = CORE_MOD,
2669         .flags          = CLOCK_IN_OMAP243X,
2670         .clkdm          = { .name = "core_l3_clkdm" },
2671         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2672         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2673         .recalc         = &followparent_recalc,
2674 };
2675
2676 static struct clk mmchs1_ick = {
2677         .name           = "mmchs_ick",
2678         .id             = 1,
2679         .parent         = &l4_ck,
2680         .prcm_mod       = CORE_MOD,
2681         .flags          = CLOCK_IN_OMAP243X,
2682         .clkdm          = { .name = "core_l4_clkdm" },
2683         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2684         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2685         .recalc         = &followparent_recalc,
2686 };
2687
2688 static struct clk mmchs1_fck = {
2689         .name           = "mmchs_fck",
2690         .id             = 1,
2691         .parent         = &func_96m_ck,
2692         .prcm_mod       = CORE_MOD,
2693         .flags          = CLOCK_IN_OMAP243X,
2694         .clkdm          = { .name = "core_l3_clkdm" },
2695         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2696         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2697         .recalc         = &followparent_recalc,
2698 };
2699
2700 static struct clk mmchs2_ick = {
2701         .name           = "mmchs_ick",
2702         .id             = 2,
2703         .parent         = &l4_ck,
2704         .prcm_mod       = CORE_MOD,
2705         .flags          = CLOCK_IN_OMAP243X,
2706         .clkdm          = { .name = "core_l4_clkdm" },
2707         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2708         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2709         .recalc         = &followparent_recalc,
2710 };
2711
2712 static struct clk mmchs2_fck = {
2713         .name           = "mmchs_fck",
2714         .id             = 2,
2715         .parent         = &func_96m_ck,
2716         .prcm_mod       = CORE_MOD,
2717         .flags          = CLOCK_IN_OMAP243X,
2718         .clkdm          = { .name = "core_l4_clkdm" },
2719         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2720         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2721         .recalc         = &followparent_recalc,
2722 };
2723
2724 static struct clk gpio5_ick = {
2725         .name           = "gpio5_ick",
2726         .parent         = &l4_ck,
2727         .prcm_mod       = CORE_MOD,
2728         .flags          = CLOCK_IN_OMAP243X,
2729         .clkdm          = { .name = "core_l4_clkdm" },
2730         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2731         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2732         .recalc         = &followparent_recalc,
2733 };
2734
2735 static struct clk gpio5_fck = {
2736         .name           = "gpio5_fck",
2737         .parent         = &func_32k_ck,
2738         .prcm_mod       = CORE_MOD,
2739         .flags          = CLOCK_IN_OMAP243X,
2740         .clkdm          = { .name = "core_l4_clkdm" },
2741         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2742         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2743         .recalc         = &followparent_recalc,
2744 };
2745
2746 static struct clk mdm_intc_ick = {
2747         .name           = "mdm_intc_ick",
2748         .parent         = &l4_ck,
2749         .prcm_mod       = CORE_MOD,
2750         .flags          = CLOCK_IN_OMAP243X,
2751         .clkdm          = { .name = "core_l4_clkdm" },
2752         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2753         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2754         .recalc         = &followparent_recalc,
2755 };
2756
2757 static struct clk mmchsdb1_fck = {
2758         .name           = "mmchsdb_fck",
2759         .id             = 1,
2760         .parent         = &func_32k_ck,
2761         .prcm_mod       = CORE_MOD,
2762         .flags          = CLOCK_IN_OMAP243X,
2763         .clkdm          = { .name = "core_l4_clkdm" },
2764         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2765         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2766         .recalc         = &followparent_recalc,
2767 };
2768
2769 static struct clk mmchsdb2_fck = {
2770         .name           = "mmchsdb_fck",
2771         .id             = 2,
2772         .parent         = &func_32k_ck,
2773         .prcm_mod       = CORE_MOD,
2774         .flags          = CLOCK_IN_OMAP243X,
2775         .clkdm          = { .name = "core_l4_clkdm" },
2776         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2777         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2778         .recalc         = &followparent_recalc,
2779 };
2780
2781 /*
2782  * This clock is a composite clock which does entire set changes then
2783  * forces a rebalance. It keys on the MPU speed, but it really could
2784  * be any key speed part of a set in the rate table.
2785  *
2786  * to really change a set, you need memory table sets which get changed
2787  * in sram, pre-notifiers & post notifiers, changing the top set, without
2788  * having low level display recalc's won't work... this is why dpm notifiers
2789  * work, isr's off, walk a list of clocks already _off_ and not messing with
2790  * the bus.
2791  *
2792  * This clock should have no parent. It embodies the entire upper level
2793  * active set. A parent will mess up some of the init also.
2794  */
2795 static struct clk virt_prcm_set = {
2796         .name           = "virt_prcm_set",
2797         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2798                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2799         .clkdm          = { .name = "virt_opp_clkdm" },
2800         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2801         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2802         .set_rate       = &omap2_select_table_rate,
2803         .round_rate     = &omap2_round_to_table_rate,
2804 };
2805
2806 static struct clk *onchip_24xx_clks[] __initdata = {
2807         /* external root sources */
2808         &func_32k_ck,
2809         &osc_ck,
2810         &sys_ck,
2811         &alt_ck,
2812         /* internal analog sources */
2813         &dpll_ck,
2814         &apll96_ck,
2815         &apll54_ck,
2816         /* internal prcm root sources */
2817         &func_54m_ck,
2818         &core_ck,
2819         &func_96m_ck,
2820         &func_48m_ck,
2821         &func_12m_ck,
2822         &wdt1_osc_ck,
2823         &sys_clkout_src,
2824         &sys_clkout,
2825         &sys_clkout2_src,
2826         &sys_clkout2,
2827         &emul_ck,
2828         /* mpu domain clocks */
2829         &mpu_ck,
2830         /* dsp domain clocks */
2831         &dsp_fck,
2832         &dsp_irate_ick,
2833         &dsp_ick,               /* 242x */
2834         &iva2_1_ick,            /* 243x */
2835         &iva1_ifck,             /* 242x */
2836         &iva1_mpu_int_ifck,     /* 242x */
2837         /* GFX domain clocks */
2838         &gfx_3d_fck,
2839         &gfx_2d_fck,
2840         &gfx_ick,
2841         /* Modem domain clocks */
2842         &mdm_ick,
2843         &mdm_osc_ck,
2844         /* DSS domain clocks */
2845         &dss_ick,
2846         &dss1_fck,
2847         &dss2_fck,
2848         &dss_54m_fck,
2849         /* L3 domain clocks */
2850         &core_l3_ck,
2851         &ssi_ssr_sst_fck,
2852         &usb_l4_ick,
2853         /* L4 domain clocks */
2854         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2855         &ssi_l4_ick,
2856         /* virtual meta-group clock */
2857         &virt_prcm_set,
2858         /* general l4 interface ck, multi-parent functional clk */
2859         &gpt1_ick,
2860         &gpt1_fck,
2861         &gpt2_ick,
2862         &gpt2_fck,
2863         &gpt3_ick,
2864         &gpt3_fck,
2865         &gpt4_ick,
2866         &gpt4_fck,
2867         &gpt5_ick,
2868         &gpt5_fck,
2869         &gpt6_ick,
2870         &gpt6_fck,
2871         &gpt7_ick,
2872         &gpt7_fck,
2873         &gpt8_ick,
2874         &gpt8_fck,
2875         &gpt9_ick,
2876         &gpt9_fck,
2877         &gpt10_ick,
2878         &gpt10_fck,
2879         &gpt11_ick,
2880         &gpt11_fck,
2881         &gpt12_ick,
2882         &gpt12_fck,
2883         &mcbsp1_ick,
2884         &mcbsp1_fck,
2885         &mcbsp2_ick,
2886         &mcbsp2_fck,
2887         &mcbsp3_ick,
2888         &mcbsp3_fck,
2889         &mcbsp4_ick,
2890         &mcbsp4_fck,
2891         &mcbsp5_ick,
2892         &mcbsp5_fck,
2893         &mcspi1_ick,
2894         &mcspi1_fck,
2895         &mcspi2_ick,
2896         &mcspi2_fck,
2897         &mcspi3_ick,
2898         &mcspi3_fck,
2899         &uart1_ick,
2900         &uart1_fck,
2901         &uart2_ick,
2902         &uart2_fck,
2903         &uart3_ick,
2904         &uart3_fck,
2905         &gpios_ick,
2906         &gpios_fck,
2907         &mpu_wdt_ick,
2908         &mpu_wdt_fck,
2909         &sync_32k_ick,
2910         &wdt1_ick,
2911         &omapctrl_ick,
2912         &icr_ick,
2913         &cam_fck,
2914         &cam_ick,
2915         &mailboxes_ick,
2916         &wdt4_ick,
2917         &wdt4_fck,
2918         &wdt3_ick,
2919         &wdt3_fck,
2920         &mspro_ick,
2921         &mspro_fck,
2922         &mmc_ick,
2923         &mmc_fck,
2924         &fac_ick,
2925         &fac_fck,
2926         &eac_ick,
2927         &eac_fck,
2928         &hdq_ick,
2929         &hdq_fck,
2930         &i2c1_ick,
2931         &i2c1_fck,
2932         &i2chs1_fck,
2933         &i2c2_ick,
2934         &i2c2_fck,
2935         &i2chs2_fck,
2936         &gpmc_fck,
2937         &sdma_fck,
2938         &sdma_ick,
2939         &vlynq_ick,
2940         &vlynq_fck,
2941         &sdrc_ick,
2942         &des_ick,
2943         &sha_ick,
2944         &rng_ick,
2945         &aes_ick,
2946         &pka_ick,
2947         &usb_fck,
2948         &usbhs_ick,
2949         &mmchs1_ick,
2950         &mmchs1_fck,
2951         &mmchs2_ick,
2952         &mmchs2_fck,
2953         &gpio5_ick,
2954         &gpio5_fck,
2955         &mdm_intc_ick,
2956         &mmchsdb1_fck,
2957         &mmchsdb2_fck,
2958 };
2959
2960 #endif
2961