arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  23
  24 #include "clock.h"
  25
  26 #include "prm.h"
  27 #include "cm.h"
  28 #include "prm_regbits_24xx.h"
  29 #include "cm_regbits_24xx.h"
  30 #include "sdrc.h"
  31
  32 static void omap2_table_mpu_recalc(struct clk *clk);
  33 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  34 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  35 static void omap2_sys_clk_recalc(struct clk *clk);
  36 static void omap2_osc_clk_recalc(struct clk *clk);
  37 static void omap2_sys_clk_recalc(struct clk *clk);
  38 static void omap2_dpll_recalc(struct clk *clk);
  39 static int omap2_clk_fixed_enable(struct clk *clk);
  40 static void omap2_clk_fixed_disable(struct clk *clk);
  41 static int omap2_enable_osc_ck(struct clk *clk);
  42 static void omap2_disable_osc_ck(struct clk *clk);
  43 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
  44
  45 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  46  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  47  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  48  */
  49 struct prcm_config {
  50         unsigned long xtal_speed;       /* crystal rate */
  51         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  52         unsigned long mpu_speed;        /* speed of MPU */
  53         unsigned long cm_clksel_mpu;    /* mpu divider */
  54         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  55         unsigned long cm_clksel_gfx;    /* gfx dividers */
  56         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  57         unsigned long cm_clksel1_pll;   /* m,n */
  58         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  59         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  60         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  61         unsigned char flags;
  62 };
  63
  64 /*
  65  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  66  * These configurations are characterized by voltage and speed for clocks.
  67  * The device is only validated for certain combinations. One way to express
  68  * these combinations is via the 'ratio's' which the clocks operate with
  69  * respect to each other. These ratio sets are for a given voltage/DPLL
  70  * setting. All configurations can be described by a DPLL setting and a ratio
  71  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  72  *
  73  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  74  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  75  * 2430 (iva2.1, NOdsp, mdm)
  76  */
  77
  78 /* Core fields for cm_clksel, not ratio governed */
  79 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  80 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  81 #define RX_CLKSEL_SSI                   (0x5 << 20)
  82
  83 /*-------------------------------------------------------------------------
  84  * Voltage/DPLL ratios
  85  *-------------------------------------------------------------------------*/
  86
  87 /* 2430 Ratio's, 2430-Ratio Config 1 */
  88 #define R1_CLKSEL_L3                    (4 << 0)
  89 #define R1_CLKSEL_L4                    (2 << 5)
  90 #define R1_CLKSEL_USB                   (4 << 25)
  91 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  92                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  93                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  94 #define R1_CLKSEL_MPU                   (2 << 0)
  95 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  96 #define R1_CLKSEL_DSP                   (2 << 0)
  97 #define R1_CLKSEL_DSP_IF                (2 << 5)
  98 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  99 #define R1_CLKSEL_GFX                   (2 << 0)
 100 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 101 #define R1_CLKSEL_MDM                   (4 << 0)
 102 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 103
 104 /* 2430-Ratio Config 2 */
 105 #define R2_CLKSEL_L3                    (6 << 0)
 106 #define R2_CLKSEL_L4                    (2 << 5)
 107 #define R2_CLKSEL_USB                   (2 << 25)
 108 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 109                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 110                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 111 #define R2_CLKSEL_MPU                   (2 << 0)
 112 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 113 #define R2_CLKSEL_DSP                   (2 << 0)
 114 #define R2_CLKSEL_DSP_IF                (3 << 5)
 115 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 116 #define R2_CLKSEL_GFX                   (2 << 0)
 117 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 118 #define R2_CLKSEL_MDM                   (6 << 0)
 119 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 120
 121 /* 2430-Ratio Bootm (BYPASS) */
 122 #define RB_CLKSEL_L3                    (1 << 0)
 123 #define RB_CLKSEL_L4                    (1 << 5)
 124 #define RB_CLKSEL_USB                   (1 << 25)
 125 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 126                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 127                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 128 #define RB_CLKSEL_MPU                   (1 << 0)
 129 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 130 #define RB_CLKSEL_DSP                   (1 << 0)
 131 #define RB_CLKSEL_DSP_IF                (1 << 5)
 132 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 133 #define RB_CLKSEL_GFX                   (1 << 0)
 134 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 135 #define RB_CLKSEL_MDM                   (1 << 0)
 136 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 137
 138 /* 2420 Ratio Equivalents */
 139 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 140 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 141
 142 /* 2420-PRCM III 532MHz core */
 143 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 144 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 145 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 146 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 147                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 148                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 149                                         RIII_CLKSEL_L3
 150 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 151 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 152 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 153 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 154 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 155 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 156 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 157 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 158                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 159                                         RIII_CLKSEL_DSP
 160 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 161 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 162
 163 /* 2420-PRCM II 600MHz core */
 164 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 165 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 166 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 167 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 168                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 169                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 170                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 171 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 172 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 173 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 174 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 175 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 176 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 177 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 178 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 179                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 180                                         RII_CLKSEL_DSP
 181 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 182 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 183
 184 /* 2420-PRCM I 660MHz core */
 185 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 186 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 187 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 188 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 189                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 190                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 191                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 192 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 193 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 194 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 195 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 196 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 197 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 198 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 199 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 200                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 201                                         RI_CLKSEL_DSP
 202 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 203 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 204
 205 /* 2420-PRCM VII (boot) */
 206 #define RVII_CLKSEL_L3                  (1 << 0)
 207 #define RVII_CLKSEL_L4                  (1 << 5)
 208 #define RVII_CLKSEL_DSS1                (1 << 8)
 209 #define RVII_CLKSEL_DSS2                (0 << 13)
 210 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 211 #define RVII_CLKSEL_SSI                 (1 << 20)
 212 #define RVII_CLKSEL_USB                 (1 << 25)
 213
 214 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 215                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 216                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 217
 218 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 219 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 220
 221 #define RVII_CLKSEL_DSP                 (1 << 0)
 222 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 223 #define RVII_SYNC_DSP                   (0 << 7)
 224 #define RVII_CLKSEL_IVA                 (1 << 8)
 225 #define RVII_SYNC_IVA                   (0 << 13)
 226 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 227                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 228
 229 #define RVII_CLKSEL_GFX                 (1 << 0)
 230 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 231
 232 /*-------------------------------------------------------------------------
 233  * 2430 Target modes: Along with each configuration the CPU has several
 234  * modes which goes along with them. Modes mainly are the addition of
 235  * describe DPLL combinations to go along with a ratio.
 236  *-------------------------------------------------------------------------*/
 237
 238 /* Hardware governed */
 239 #define MX_48M_SRC                      (0 << 3)
 240 #define MX_54M_SRC                      (0 << 5)
 241 #define MX_APLLS_CLIKIN_12              (3 << 23)
 242 #define MX_APLLS_CLIKIN_13              (2 << 23)
 243 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 244
 245 /*
 246  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 247  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 248  */
 249 #define M5A_DPLL_MULT_12                (133 << 12)
 250 #define M5A_DPLL_DIV_12                 (5 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 253                                         MX_APLLS_CLIKIN_12
 254 #define M5A_DPLL_MULT_13                (61 << 12)
 255 #define M5A_DPLL_DIV_13                 (2 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 258                                         MX_APLLS_CLIKIN_13
 259 #define M5A_DPLL_MULT_19                (55 << 12)
 260 #define M5A_DPLL_DIV_19                 (3 << 8)
 261 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 262                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 263                                         MX_APLLS_CLIKIN_19_2
 264 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 265 #define M5B_DPLL_MULT_12                (50 << 12)
 266 #define M5B_DPLL_DIV_12                 (2 << 8)
 267 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 268                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 269                                         MX_APLLS_CLIKIN_12
 270 #define M5B_DPLL_MULT_13                (200 << 12)
 271 #define M5B_DPLL_DIV_13                 (12 << 8)
 272
 273 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 275                                         MX_APLLS_CLIKIN_13
 276 #define M5B_DPLL_MULT_19                (125 << 12)
 277 #define M5B_DPLL_DIV_19                 (31 << 8)
 278 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 279                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 280                                         MX_APLLS_CLIKIN_19_2
 281 /*
 282  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 283  */
 284 #define M4_DPLL_MULT_12                 (133 << 12)
 285 #define M4_DPLL_DIV_12                  (3 << 8)
 286 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 287                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 288                                         MX_APLLS_CLIKIN_12
 289
 290 #define M4_DPLL_MULT_13                 (399 << 12)
 291 #define M4_DPLL_DIV_13                  (12 << 8)
 292 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 293                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 294                                         MX_APLLS_CLIKIN_13
 295
 296 #define M4_DPLL_MULT_19                 (145 << 12)
 297 #define M4_DPLL_DIV_19                  (6 << 8)
 298 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 299                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 300                                         MX_APLLS_CLIKIN_19_2
 301
 302 /*
 303  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 304  */
 305 #define M3_DPLL_MULT_12                 (55 << 12)
 306 #define M3_DPLL_DIV_12                  (1 << 8)
 307 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 309                                         MX_APLLS_CLIKIN_12
 310 #define M3_DPLL_MULT_13                 (76 << 12)
 311 #define M3_DPLL_DIV_13                  (2 << 8)
 312 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 314                                         MX_APLLS_CLIKIN_13
 315 #define M3_DPLL_MULT_19                 (17 << 12)
 316 #define M3_DPLL_DIV_19                  (0 << 8)
 317 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 318                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 319                                         MX_APLLS_CLIKIN_19_2
 320
 321 /*
 322  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 323  */
 324 #define M2_DPLL_MULT_12                 (55 << 12)
 325 #define M2_DPLL_DIV_12                  (1 << 8)
 326 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 327                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 328                                         MX_APLLS_CLIKIN_12
 329
 330 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 331  * relock time issue */
 332 /* Core frequency changed from 330/165 to 329/164 MHz*/
 333 #define M2_DPLL_MULT_13                 (76 << 12)
 334 #define M2_DPLL_DIV_13                  (2 << 8)
 335 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 336                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 337                                         MX_APLLS_CLIKIN_13
 338
 339 #define M2_DPLL_MULT_19                 (17 << 12)
 340 #define M2_DPLL_DIV_19                  (0 << 8)
 341 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 342                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 343                                         MX_APLLS_CLIKIN_19_2
 344
 345 /* boot (boot) */
 346 #define MB_DPLL_MULT                    (1 << 12)
 347 #define MB_DPLL_DIV                     (0 << 8)
 348 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 349                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 350
 351 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 352                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 353
 354 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 355                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 356
 357 /*
 358  * 2430 - chassis (sedna)
 359  * 165 (ratio1) same as above #2
 360  * 150 (ratio1)
 361  * 133 (ratio2) same as above #4
 362  * 110 (ratio2) same as above #3
 363  * 104 (ratio2)
 364  * boot (boot)
 365  */
 366
 367 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 368 #define MI_DPLL_MULT_12                 (55 << 12)
 369 #define MI_DPLL_DIV_12                  (1 << 8)
 370 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 371                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 372                                         MX_APLLS_CLIKIN_12
 373
 374 /*
 375  * 2420 Equivalent - mode registers
 376  * PRCM II , target DPLL = 2*300MHz = 600MHz
 377  */
 378 #define MII_DPLL_MULT_12                (50 << 12)
 379 #define MII_DPLL_DIV_12                 (1 << 8)
 380 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 382                                         MX_APLLS_CLIKIN_12
 383 #define MII_DPLL_MULT_13                (300 << 12)
 384 #define MII_DPLL_DIV_13                 (12 << 8)
 385 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 386                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 387                                         MX_APLLS_CLIKIN_13
 388
 389 /* PRCM III target DPLL = 2*266 = 532MHz*/
 390 #define MIII_DPLL_MULT_12               (133 << 12)
 391 #define MIII_DPLL_DIV_12                (5 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 394                                         MX_APLLS_CLIKIN_12
 395 #define MIII_DPLL_MULT_13               (266 << 12)
 396 #define MIII_DPLL_DIV_13                (12 << 8)
 397 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 398                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 399                                         MX_APLLS_CLIKIN_13
 400
 401 /* PRCM VII (boot bypass) */
 402 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 403 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 404
 405 /* High and low operation value */
 406 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 407 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 408
 409 /* MPU speed defines */
 410 #define S12M    12000000
 411 #define S13M    13000000
 412 #define S19M    19200000
 413 #define S26M    26000000
 414 #define S100M   100000000
 415 #define S133M   133000000
 416 #define S150M   150000000
 417 #define S164M   164000000
 418 #define S165M   165000000
 419 #define S199M   199000000
 420 #define S200M   200000000
 421 #define S266M   266000000
 422 #define S300M   300000000
 423 #define S329M   329000000
 424 #define S330M   330000000
 425 #define S399M   399000000
 426 #define S400M   400000000
 427 #define S532M   532000000
 428 #define S600M   600000000
 429 #define S658M   658000000
 430 #define S660M   660000000
 431 #define S798M   798000000
 432
 433 /*-------------------------------------------------------------------------
 434  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 435  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 436  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 437  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 438  *
 439  * Filling in table based on H4 boards and 2430-SDPs variants available.
 440  * There are quite a few more rates combinations which could be defined.
 441  *
 442  * When multiple values are defined the start up will try and choose the
 443  * fastest one. If a 'fast' value is defined, then automatically, the /2
 444  * one should be included as it can be used.    Generally having more that
 445  * one fast set does not make sense, as static timings need to be changed
 446  * to change the set.    The exception is the bypass setting which is
 447  * availble for low power bypass.
 448  *
 449  * Note: This table needs to be sorted, fastest to slowest.
 450  *-------------------------------------------------------------------------*/
 451 static struct prcm_config rate_table[] = {
 452         /* PRCM I - FAST */
 453         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 454                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 455                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 456                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 457                 RATE_IN_242X},
 458
 459         /* PRCM II - FAST */
 460         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 461                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 462                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 463                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 464                 RATE_IN_242X},
 465
 466         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 467                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 468                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 469                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 470                 RATE_IN_242X},
 471
 472         /* PRCM III - FAST */
 473         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 474                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 475                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 476                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 477                 RATE_IN_242X},
 478
 479         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 480                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 481                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 482                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 483                 RATE_IN_242X},
 484
 485         /* PRCM II - SLOW */
 486         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 487                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 488                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 489                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 490                 RATE_IN_242X},
 491
 492         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 493                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 494                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 495                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 496                 RATE_IN_242X},
 497
 498         /* PRCM III - SLOW */
 499         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 500                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 501                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 502                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 503                 RATE_IN_242X},
 504
 505         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 506                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 507                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 508                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 509                 RATE_IN_242X},
 510
 511         /* PRCM-VII (boot-bypass) */
 512         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 513                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 514                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 515                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 516                 RATE_IN_242X},
 517
 518         /* PRCM-VII (boot-bypass) */
 519         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 520                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 521                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 522                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 523                 RATE_IN_242X},
 524
 525         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 526         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 527                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 528                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 529                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 530                 SDRC_RFR_CTRL_133MHz,
 531                 RATE_IN_243X},
 532
 533         /* PRCM #2 - ratio1 (ES2) - FAST */
 534         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 535                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 536                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 537                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 538                 SDRC_RFR_CTRL_165MHz,
 539                 RATE_IN_243X},
 540
 541         /* PRCM #5a - ratio1 - FAST */
 542         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 543                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 544                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 545                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 546                 SDRC_RFR_CTRL_133MHz,
 547                 RATE_IN_243X},
 548
 549         /* PRCM #5b - ratio1 - FAST */
 550         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 551                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 552                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 553                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 554                 SDRC_RFR_CTRL_100MHz,
 555                 RATE_IN_243X},
 556
 557         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 558         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 559                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 560                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 561                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 562                 SDRC_RFR_CTRL_133MHz,
 563                 RATE_IN_243X},
 564
 565         /* PRCM #2 - ratio1 (ES2) - SLOW */
 566         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 567                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 568                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 569                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 570                 SDRC_RFR_CTRL_165MHz,
 571                 RATE_IN_243X},
 572
 573         /* PRCM #5a - ratio1 - SLOW */
 574         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 575                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 576                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 577                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 578                 SDRC_RFR_CTRL_133MHz,
 579                 RATE_IN_243X},
 580
 581         /* PRCM #5b - ratio1 - SLOW*/
 582         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 583                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 584                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 585                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 586                 SDRC_RFR_CTRL_100MHz,
 587                 RATE_IN_243X},
 588
 589         /* PRCM-boot/bypass */
 590         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 591                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 592                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 593                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 594                 SDRC_RFR_CTRL_BYPASS,
 595                 RATE_IN_243X},
 596
 597         /* PRCM-boot/bypass */
 598         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 599                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 600                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 601                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 602                 SDRC_RFR_CTRL_BYPASS,
 603                 RATE_IN_243X},
 604
 605         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 606 };
 607
 608 /*-------------------------------------------------------------------------
 609  * 24xx clock tree.
 610  *
 611  * NOTE:In many cases here we are assigning a 'default' parent. In many
 612  *      cases the parent is selectable. The get/set parent calls will also
 613  *      switch sources.
 614  *
 615  *      Many some clocks say always_enabled, but they can be auto idled for
 616  *      power savings. They will always be available upon clock request.
 617  *
 618  *      Several sources are given initial rates which may be wrong, this will
 619  *      be fixed up in the init func.
 620  *
 621  *      Things are broadly separated below by clock domains. It is
 622  *      noteworthy that most periferals have dependencies on multiple clock
 623  *      domains. Many get their interface clocks from the L4 domain, but get
 624  *      functional clocks from fixed sources or other core domain derived
 625  *      clocks.
 626  *-------------------------------------------------------------------------*/
 627
 628 /* Base external input clocks */
 629 static struct clk func_32k_ck = {
 630         .name           = "func_32k_ck",
 631         .rate           = 32000,
 632         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 633                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 634         .recalc         = &propagate_rate,
 635 };
 636
 637 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 638 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 639         .name           = "osc_ck",
 640         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 641                                 RATE_PROPAGATES,
 642         .enable         = &omap2_enable_osc_ck,
 643         .disable        = &omap2_disable_osc_ck,
 644         .recalc         = &omap2_osc_clk_recalc,
 645 };
 646
 647 /* With out modem likely 12MHz, with modem likely 13MHz */
 648 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 649         .name           = "sys_ck",             /* ~ ref_clk also */
 650         .parent         = &osc_ck,
 651         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 652                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 653         .recalc         = &omap2_sys_clk_recalc,
 654 };
 655
 656 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 657         .name           = "alt_ck",
 658         .rate           = 54000000,
 659         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 660                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 661         .recalc         = &propagate_rate,
 662 };
 663
 664 /*
 665  * Analog domain root source clocks
 666  */
 667
 668 /* dpll_ck, is broken out in to special cases through clksel */
 669 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 670  * deal with this
 671  */
 672
 673 static const struct dpll_data dpll_dd = {
 674         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 675         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 676         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 677 };
 678
 679 static struct clk dpll_ck = {
 680         .name           = "dpll_ck",
 681         .parent         = &sys_ck,              /* Can be func_32k also */
 682         .dpll_data      = &dpll_dd,
 683         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 684                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 685         .recalc         = &omap2_dpll_recalc,
 686         .set_rate       = &omap2_reprogram_dpll,
 687 };
 688
 689 static struct clk apll96_ck = {
 690         .name           = "apll96_ck",
 691         .parent         = &sys_ck,
 692         .rate           = 96000000,
 693         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 694                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 695         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 696         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 697         .enable         = &omap2_clk_fixed_enable,
 698         .disable        = &omap2_clk_fixed_disable,
 699         .recalc         = &propagate_rate,
 700 };
 701
 702 static struct clk apll54_ck = {
 703         .name           = "apll54_ck",
 704         .parent         = &sys_ck,
 705         .rate           = 54000000,
 706         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 707                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 708         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 709         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 710         .enable         = &omap2_clk_fixed_enable,
 711         .disable        = &omap2_clk_fixed_disable,
 712         .recalc         = &propagate_rate,
 713 };
 714
 715 /*
 716  * PRCM digital base sources
 717  */
 718
 719 /* func_54m_ck */
 720
 721 static const struct clksel_rate func_54m_apll54_rates[] = {
 722         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 723         { .div = 0 },
 724 };
 725
 726 static const struct clksel_rate func_54m_alt_rates[] = {
 727         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 728         { .div = 0 },
 729 };
 730
 731 static const struct clksel func_54m_clksel[] = {
 732         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 733         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 734         { .parent = NULL },
 735 };
 736
 737 static struct clk func_54m_ck = {
 738         .name           = "func_54m_ck",
 739         .parent         = &apll54_ck,   /* can also be alt_clk */
 740         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 741                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 742         .init           = &omap2_init_clksel_parent,
 743         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 744         .clksel_mask    = OMAP24XX_54M_SOURCE,
 745         .clksel         = func_54m_clksel,
 746         .recalc         = &omap2_clksel_recalc,
 747 };
 748
 749 static struct clk core_ck = {
 750         .name           = "core_ck",
 751         .parent         = &dpll_ck,             /* can also be 32k */
 752         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 753                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 754         .recalc         = &followparent_recalc,
 755 };
 756
 757 /* func_96m_ck */
 758 static const struct clksel_rate func_96m_apll96_rates[] = {
 759         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 760         { .div = 0 },
 761 };
 762
 763 static const struct clksel_rate func_96m_alt_rates[] = {
 764         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 765         { .div = 0 },
 766 };
 767
 768 static const struct clksel func_96m_clksel[] = {
 769         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 770         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 771         { .parent = NULL }
 772 };
 773
 774 /* The parent of this clock is not selectable on 2420. */
 775 static struct clk func_96m_ck = {
 776         .name           = "func_96m_ck",
 777         .parent         = &apll96_ck,
 778         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 779                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 780         .init           = &omap2_init_clksel_parent,
 781         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 782         .clksel_mask    = OMAP2430_96M_SOURCE,
 783         .clksel         = func_96m_clksel,
 784         .recalc         = &omap2_clksel_recalc,
 785         .round_rate     = &omap2_clksel_round_rate,
 786         .set_rate       = &omap2_clksel_set_rate
 787 };
 788
 789 /* func_48m_ck */
 790
 791 static const struct clksel_rate func_48m_apll96_rates[] = {
 792         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 793         { .div = 0 },
 794 };
 795
 796 static const struct clksel_rate func_48m_alt_rates[] = {
 797         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 798         { .div = 0 },
 799 };
 800
 801 static const struct clksel func_48m_clksel[] = {
 802         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 803         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 804         { .parent = NULL }
 805 };
 806
 807 static struct clk func_48m_ck = {
 808         .name           = "func_48m_ck",
 809         .parent         = &apll96_ck,    /* 96M or Alt */
 810         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 811                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 812         .init           = &omap2_init_clksel_parent,
 813         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 814         .clksel_mask    = OMAP24XX_48M_SOURCE,
 815         .clksel         = func_48m_clksel,
 816         .recalc         = &omap2_clksel_recalc,
 817         .round_rate     = &omap2_clksel_round_rate,
 818         .set_rate       = &omap2_clksel_set_rate
 819 };
 820
 821 static struct clk func_12m_ck = {
 822         .name           = "func_12m_ck",
 823         .parent         = &func_48m_ck,
 824         .fixed_div      = 4,
 825         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 826                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 827         .recalc         = &omap2_fixed_divisor_recalc,
 828 };
 829
 830 /* Secure timer, only available in secure mode */
 831 static struct clk wdt1_osc_ck = {
 832         .name           = "ck_wdt1_osc",
 833         .parent         = &osc_ck,
 834         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 835         .recalc         = &followparent_recalc,
 836 };
 837
 838 /*
 839  * The common_clkout* clksel_rate structs are common to
 840  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 841  * sys_clkout2_* are 2420-only, so the
 842  * clksel_rate flags fields are inaccurate for those clocks. This is
 843  * harmless since access to those clocks are gated by the struct clk
 844  * flags fields, which mark them as 2420-only.
 845  */
 846 static const struct clksel_rate common_clkout_src_core_rates[] = {
 847         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 848         { .div = 0 }
 849 };
 850
 851 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 852         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 853         { .div = 0 }
 854 };
 855
 856 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 857         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 858         { .div = 0 }
 859 };
 860
 861 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 862         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 863         { .div = 0 }
 864 };
 865
 866 static const struct clksel common_clkout_src_clksel[] = {
 867         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 868         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 869         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 870         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 871         { .parent = NULL }
 872 };
 873
 874 static struct clk sys_clkout_src = {
 875         .name           = "sys_clkout_src",
 876         .parent         = &func_54m_ck,
 877         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 878                                 RATE_PROPAGATES,
 879         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 880         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 881         .init           = &omap2_init_clksel_parent,
 882         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 883         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 884         .clksel         = common_clkout_src_clksel,
 885         .recalc         = &omap2_clksel_recalc,
 886         .round_rate     = &omap2_clksel_round_rate,
 887         .set_rate       = &omap2_clksel_set_rate
 888 };
 889
 890 static const struct clksel_rate common_clkout_rates[] = {
 891         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 892         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 893         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 894         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 895         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 896         { .div = 0 },
 897 };
 898
 899 static const struct clksel sys_clkout_clksel[] = {
 900         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 901         { .parent = NULL }
 902 };
 903
 904 static struct clk sys_clkout = {
 905         .name           = "sys_clkout",
 906         .parent         = &sys_clkout_src,
 907         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 908                                 PARENT_CONTROLS_CLOCK,
 909         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 910         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 911         .clksel         = sys_clkout_clksel,
 912         .recalc         = &omap2_clksel_recalc,
 913         .round_rate     = &omap2_clksel_round_rate,
 914         .set_rate       = &omap2_clksel_set_rate
 915 };
 916
 917 /* In 2430, new in 2420 ES2 */
 918 static struct clk sys_clkout2_src = {
 919         .name           = "sys_clkout2_src",
 920         .parent         = &func_54m_ck,
 921         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 922         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 923         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 924         .init           = &omap2_init_clksel_parent,
 925         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 926         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 927         .clksel         = common_clkout_src_clksel,
 928         .recalc         = &omap2_clksel_recalc,
 929         .round_rate     = &omap2_clksel_round_rate,
 930         .set_rate       = &omap2_clksel_set_rate
 931 };
 932
 933 static const struct clksel sys_clkout2_clksel[] = {
 934         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 935         { .parent = NULL }
 936 };
 937
 938 /* In 2430, new in 2420 ES2 */
 939 static struct clk sys_clkout2 = {
 940         .name           = "sys_clkout2",
 941         .parent         = &sys_clkout2_src,
 942         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 943         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 944         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 945         .clksel         = sys_clkout2_clksel,
 946         .recalc         = &omap2_clksel_recalc,
 947         .round_rate     = &omap2_clksel_round_rate,
 948         .set_rate       = &omap2_clksel_set_rate
 949 };
 950
 951 static struct clk emul_ck = {
 952         .name           = "emul_ck",
 953         .parent         = &func_54m_ck,
 954         .flags          = CLOCK_IN_OMAP242X,
 955         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 956         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 957         .recalc         = &followparent_recalc,
 958
 959 };
 960
 961 /*
 962  * MPU clock domain
 963  *      Clocks:
 964  *              MPU_FCLK, MPU_ICLK
 965  *              INT_M_FCLK, INT_M_I_CLK
 966  *
 967  * - Individual clocks are hardware managed.
 968  * - Base divider comes from: CM_CLKSEL_MPU
 969  *
 970  */
 971 static const struct clksel_rate mpu_core_rates[] = {
 972         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 973         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 974         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 975         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 976         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 977         { .div = 0 },
 978 };
 979
 980 static const struct clksel mpu_clksel[] = {
 981         { .parent = &core_ck, .rates = mpu_core_rates },
 982         { .parent = NULL }
 983 };
 984
 985 static struct clk mpu_ck = {    /* Control cpu */
 986         .name           = "mpu_ck",
 987         .parent         = &core_ck,
 988         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 989                                 ALWAYS_ENABLED | DELAYED_APP |
 990                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 991         .init           = &omap2_init_clksel_parent,
 992         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 993         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 994         .clksel         = mpu_clksel,
 995         .recalc         = &omap2_clksel_recalc,
 996         .round_rate     = &omap2_clksel_round_rate,
 997         .set_rate       = &omap2_clksel_set_rate
 998 };
 999
1000 /*
1001  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1002  * Clocks:
1003  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1004  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1005  *
1006  * Won't be too specific here. The core clock comes into this block
1007  * it is divided then tee'ed. One branch goes directly to xyz enable
1008  * controls. The other branch gets further divided by 2 then possibly
1009  * routed into a synchronizer and out of clocks abc.
1010  */
1011 static const struct clksel_rate dsp_fck_core_rates[] = {
1012         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1013         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1014         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1015         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1016         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1017         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1018         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1019         { .div = 0 },
1020 };
1021
1022 static const struct clksel dsp_fck_clksel[] = {
1023         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1024         { .parent = NULL }
1025 };
1026
1027 static struct clk dsp_fck = {
1028         .name           = "dsp_fck",
1029         .parent         = &core_ck,
1030         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1031                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1032         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1033         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1034         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1035         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1036         .clksel         = dsp_fck_clksel,
1037         .recalc         = &omap2_clksel_recalc,
1038         .round_rate     = &omap2_clksel_round_rate,
1039         .set_rate       = &omap2_clksel_set_rate
1040 };
1041
1042 /* DSP interface clock */
1043 static const struct clksel_rate dsp_irate_ick_rates[] = {
1044         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1045         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1046         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1047         { .div = 0 },
1048 };
1049
1050 static const struct clksel dsp_irate_ick_clksel[] = {
1051         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1052         { .parent = NULL }
1053 };
1054
1055 /*
1056  * This clock does not exist as such in the TRM, but is added to
1057  * separate source selection from  XXX
1058  */
1059 static struct clk dsp_irate_ick = {
1060         .name           = "dsp_irate_ick",
1061         .parent         = &dsp_fck,
1062         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1063                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1064         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1065         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1066         .clksel         = dsp_irate_ick_clksel,
1067         .recalc         = &omap2_clksel_recalc,
1068         .round_rate     = &omap2_clksel_round_rate,
1069         .set_rate             = &omap2_clksel_set_rate
1070 };
1071
1072 /* 2420 only */
1073 static struct clk dsp_ick = {
1074         .name           = "dsp_ick",     /* apparently ipi and isp */
1075         .parent         = &dsp_irate_ick,
1076         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1077         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1078         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1079 };
1080
1081 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1082 static struct clk iva2_1_ick = {
1083         .name           = "iva2_1_ick",
1084         .parent         = &dsp_irate_ick,
1085         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1086         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1087         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1088 };
1089
1090 static struct clk iva1_ifck = {
1091         .name           = "iva1_ifck",
1092         .parent         = &core_ck,
1093         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1094                                 RATE_PROPAGATES | DELAYED_APP,
1095         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1096         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1097         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1098         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1099         .clksel         = dsp_fck_clksel,
1100         .recalc         = &omap2_clksel_recalc,
1101         .round_rate     = &omap2_clksel_round_rate,
1102         .set_rate       = &omap2_clksel_set_rate
1103 };
1104
1105 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1106 static struct clk iva1_mpu_int_ifck = {
1107         .name           = "iva1_mpu_int_ifck",
1108         .parent         = &iva1_ifck,
1109         .flags          = CLOCK_IN_OMAP242X,
1110         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1111         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1112         .fixed_div      = 2,
1113         .recalc         = &omap2_fixed_divisor_recalc,
1114 };
1115
1116 /*
1117  * L3 clock domain
1118  * L3 clocks are used for both interface and functional clocks to
1119  * multiple entities. Some of these clocks are completely managed
1120  * by hardware, and some others allow software control. Hardware
1121  * managed ones general are based on directly CLK_REQ signals and
1122  * various auto idle settings. The functional spec sets many of these
1123  * as 'tie-high' for their enables.
1124  *
1125  * I-CLOCKS:
1126  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1127  *      CAM, HS-USB.
1128  * F-CLOCK
1129  *      SSI.
1130  *
1131  * GPMC memories and SDRC have timing and clock sensitive registers which
1132  * may very well need notification when the clock changes. Currently for low
1133  * operating points, these are taken care of in sleep.S.
1134  */
1135 static const struct clksel_rate core_l3_core_rates[] = {
1136         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1137         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1138         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1139         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1140         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1141         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1142         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1143         { .div = 0 }
1144 };
1145
1146 static const struct clksel core_l3_clksel[] = {
1147         { .parent = &core_ck, .rates = core_l3_core_rates },
1148         { .parent = NULL }
1149 };
1150
1151 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1152         .name           = "core_l3_ck",
1153         .parent         = &core_ck,
1154         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1155                                 ALWAYS_ENABLED | DELAYED_APP |
1156                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1157         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1158         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1159         .clksel         = core_l3_clksel,
1160         .recalc         = &omap2_clksel_recalc,
1161         .round_rate     = &omap2_clksel_round_rate,
1162         .set_rate       = &omap2_clksel_set_rate
1163 };
1164
1165 /* usb_l4_ick */
1166 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1167         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1168         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1169         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1170         { .div = 0 }
1171 };
1172
1173 static const struct clksel usb_l4_ick_clksel[] = {
1174         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1175         { .parent = NULL },
1176 };
1177
1178 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1179         .name           = "usb_l4_ick",
1180         .parent         = &core_l3_ck,
1181         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1182                                 DELAYED_APP | CONFIG_PARTICIPANT,
1183         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1184         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1185         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1186         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1187         .clksel         = usb_l4_ick_clksel,
1188         .recalc         = &omap2_clksel_recalc,
1189         .round_rate     = &omap2_clksel_round_rate,
1190         .set_rate       = &omap2_clksel_set_rate
1191 };
1192
1193 /*
1194  * SSI is in L3 management domain, its direct parent is core not l3,
1195  * many core power domain entities are grouped into the L3 clock
1196  * domain.
1197  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1198  *
1199  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1200  */
1201 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1202         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1203         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1204         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1205         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1206         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1207         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1208         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1209         { .div = 0 }
1210 };
1211
1212 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1213         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1214         { .parent = NULL }
1215 };
1216
1217 static struct clk ssi_ssr_sst_fck = {
1218         .name           = "ssi_fck",
1219         .parent         = &core_ck,
1220         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1221                                 DELAYED_APP,
1222         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1223         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1224         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1225         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1226         .clksel         = ssi_ssr_sst_fck_clksel,
1227         .recalc         = &omap2_clksel_recalc,
1228         .round_rate     = &omap2_clksel_round_rate,
1229         .set_rate       = &omap2_clksel_set_rate
1230 };
1231
1232 /*
1233  * GFX clock domain
1234  *      Clocks:
1235  * GFX_FCLK, GFX_ICLK
1236  * GFX_CG1(2d), GFX_CG2(3d)
1237  *
1238  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1239  * The 2d and 3d clocks run at a hardware determined
1240  * divided value of fclk.
1241  *
1242  */
1243 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1244
1245 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1246 static const struct clksel gfx_fck_clksel[] = {
1247         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1248         { .parent = NULL },
1249 };
1250
1251 static struct clk gfx_3d_fck = {
1252         .name           = "gfx_3d_fck",
1253         .parent         = &core_l3_ck,
1254         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1255         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1256         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1257         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1258         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1259         .clksel         = gfx_fck_clksel,
1260         .recalc         = &omap2_clksel_recalc,
1261         .round_rate     = &omap2_clksel_round_rate,
1262         .set_rate       = &omap2_clksel_set_rate
1263 };
1264
1265 static struct clk gfx_2d_fck = {
1266         .name           = "gfx_2d_fck",
1267         .parent         = &core_l3_ck,
1268         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1269         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1270         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1271         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1272         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1273         .clksel         = gfx_fck_clksel,
1274         .recalc         = &omap2_clksel_recalc,
1275         .round_rate     = &omap2_clksel_round_rate,
1276         .set_rate       = &omap2_clksel_set_rate
1277 };
1278
1279 static struct clk gfx_ick = {
1280         .name           = "gfx_ick",            /* From l3 */
1281         .parent         = &core_l3_ck,
1282         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1283         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1284         .enable_bit     = OMAP_EN_GFX_SHIFT,
1285         .recalc         = &followparent_recalc,
1286 };
1287
1288 /*
1289  * Modem clock domain (2430)
1290  *      CLOCKS:
1291  *              MDM_OSC_CLK
1292  *              MDM_ICLK
1293  * These clocks are usable in chassis mode only.
1294  */
1295 static const struct clksel_rate mdm_ick_core_rates[] = {
1296         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1297         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1298         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1299         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1300         { .div = 0 }
1301 };
1302
1303 static const struct clksel mdm_ick_clksel[] = {
1304         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1305         { .parent = NULL }
1306 };
1307
1308 static struct clk mdm_ick = {           /* used both as a ick and fck */
1309         .name           = "mdm_ick",
1310         .parent         = &core_ck,
1311         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1312         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1313         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1314         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1315         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1316         .clksel         = mdm_ick_clksel,
1317         .recalc         = &omap2_clksel_recalc,
1318         .round_rate     = &omap2_clksel_round_rate,
1319         .set_rate       = &omap2_clksel_set_rate
1320 };
1321
1322 static struct clk mdm_osc_ck = {
1323         .name           = "mdm_osc_ck",
1324         .parent         = &osc_ck,
1325         .flags          = CLOCK_IN_OMAP243X,
1326         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1327         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1328         .recalc         = &followparent_recalc,
1329 };
1330
1331 /*
1332  * L4 clock management domain
1333  *
1334  * This domain contains lots of interface clocks from the L4 interface, some
1335  * functional clocks.   Fixed APLL functional source clocks are managed in
1336  * this domain.
1337  */
1338 static const struct clksel_rate l4_core_l3_rates[] = {
1339         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1340         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1341         { .div = 0 }
1342 };
1343
1344 static const struct clksel l4_clksel[] = {
1345         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1346         { .parent = NULL }
1347 };
1348
1349 static struct clk l4_ck = {             /* used both as an ick and fck */
1350         .name           = "l4_ck",
1351         .parent         = &core_l3_ck,
1352         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1353                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1354         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1355         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1356         .clksel         = l4_clksel,
1357         .recalc         = &omap2_clksel_recalc,
1358         .round_rate     = &omap2_clksel_round_rate,
1359         .set_rate       = &omap2_clksel_set_rate
1360 };
1361
1362 static struct clk ssi_l4_ick = {
1363         .name           = "ssi_l4_ick",
1364         .parent         = &l4_ck,
1365         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1366         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1367         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1368         .recalc         = &followparent_recalc,
1369 };
1370
1371 /*
1372  * DSS clock domain
1373  * CLOCKs:
1374  * DSS_L4_ICLK, DSS_L3_ICLK,
1375  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1376  *
1377  * DSS is both initiator and target.
1378  */
1379 /* XXX Add RATE_NOT_VALIDATED */
1380
1381 static const struct clksel_rate dss1_fck_sys_rates[] = {
1382         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1383         { .div = 0 }
1384 };
1385
1386 static const struct clksel_rate dss1_fck_core_rates[] = {
1387         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1388         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1389         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1390         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1391         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1392         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1393         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1394         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1395         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1396         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1397         { .div = 0 }
1398 };
1399
1400 static const struct clksel dss1_fck_clksel[] = {
1401         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1402         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1403         { .parent = NULL },
1404 };
1405
1406 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1407         .name           = "dss_ick",
1408         .parent         = &l4_ck,       /* really both l3 and l4 */
1409         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1410         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1411         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1412         .recalc         = &followparent_recalc,
1413 };
1414
1415 static struct clk dss1_fck = {
1416         .name           = "dss1_fck",
1417         .parent         = &core_ck,             /* Core or sys */
1418         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1419                                 DELAYED_APP,
1420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1421         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1422         .init           = &omap2_init_clksel_parent,
1423         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1424         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1425         .clksel         = dss1_fck_clksel,
1426         .recalc         = &omap2_clksel_recalc,
1427         .round_rate     = &omap2_clksel_round_rate,
1428         .set_rate       = &omap2_clksel_set_rate
1429 };
1430
1431 static const struct clksel_rate dss2_fck_sys_rates[] = {
1432         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1433         { .div = 0 }
1434 };
1435
1436 static const struct clksel_rate dss2_fck_48m_rates[] = {
1437         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1438         { .div = 0 }
1439 };
1440
1441 static const struct clksel dss2_fck_clksel[] = {
1442         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1443         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1444         { .parent = NULL }
1445 };
1446
1447 static struct clk dss2_fck = {          /* Alt clk used in power management */
1448         .name           = "dss2_fck",
1449         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1450         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1451                                 DELAYED_APP,
1452         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1454         .init           = &omap2_init_clksel_parent,
1455         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1456         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1457         .clksel         = dss2_fck_clksel,
1458         .recalc         = &followparent_recalc,
1459 };
1460
1461 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1462         .name           = "dss_54m_fck",        /* 54m tv clk */
1463         .parent         = &func_54m_ck,
1464         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1465         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1466         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1467         .recalc         = &followparent_recalc,
1468 };
1469
1470 /*
1471  * CORE power domain ICLK & FCLK defines.
1472  * Many of the these can have more than one possible parent. Entries
1473  * here will likely have an L4 interface parent, and may have multiple
1474  * functional clock parents.
1475  */
1476 static const struct clksel_rate gpt_alt_rates[] = {
1477         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1478         { .div = 0 }
1479 };
1480
1481 static const struct clksel omap24xx_gpt_clksel[] = {
1482         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1483         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1484         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1485         { .parent = NULL },
1486 };
1487
1488 static struct clk gpt1_ick = {
1489         .name           = "gpt1_ick",
1490         .parent         = &l4_ck,
1491         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1492         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1493         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1494         .recalc         = &followparent_recalc,
1495 };
1496
1497 static struct clk gpt1_fck = {
1498         .name           = "gpt1_fck",
1499         .parent         = &func_32k_ck,
1500         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1501         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1502         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1503         .init           = &omap2_init_clksel_parent,
1504         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1505         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1506         .clksel         = omap24xx_gpt_clksel,
1507         .recalc         = &omap2_clksel_recalc,
1508         .round_rate     = &omap2_clksel_round_rate,
1509         .set_rate       = &omap2_clksel_set_rate
1510 };
1511
1512 static struct clk gpt2_ick = {
1513         .name           = "gpt2_ick",
1514         .parent         = &l4_ck,
1515         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1516         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1517         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1518         .recalc         = &followparent_recalc,
1519 };
1520
1521 static struct clk gpt2_fck = {
1522         .name           = "gpt2_fck",
1523         .parent         = &func_32k_ck,
1524         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1525         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1526         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1527         .init           = &omap2_init_clksel_parent,
1528         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1529         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1530         .clksel         = omap24xx_gpt_clksel,
1531         .recalc         = &omap2_clksel_recalc,
1532 };
1533
1534 static struct clk gpt3_ick = {
1535         .name           = "gpt3_ick",
1536         .parent         = &l4_ck,
1537         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1538         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1539         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk gpt3_fck = {
1544         .name           = "gpt3_fck",
1545         .parent         = &func_32k_ck,
1546         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1547         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1548         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1549         .init           = &omap2_init_clksel_parent,
1550         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1551         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1552         .clksel         = omap24xx_gpt_clksel,
1553         .recalc         = &omap2_clksel_recalc,
1554 };
1555
1556 static struct clk gpt4_ick = {
1557         .name           = "gpt4_ick",
1558         .parent         = &l4_ck,
1559         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1560         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1561         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1562         .recalc         = &followparent_recalc,
1563 };
1564
1565 static struct clk gpt4_fck = {
1566         .name           = "gpt4_fck",
1567         .parent         = &func_32k_ck,
1568         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1569         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1571         .init           = &omap2_init_clksel_parent,
1572         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1573         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1574         .clksel         = omap24xx_gpt_clksel,
1575         .recalc         = &omap2_clksel_recalc,
1576 };
1577
1578 static struct clk gpt5_ick = {
1579         .name           = "gpt5_ick",
1580         .parent         = &l4_ck,
1581         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1582         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1583         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1584         .recalc         = &followparent_recalc,
1585 };
1586
1587 static struct clk gpt5_fck = {
1588         .name           = "gpt5_fck",
1589         .parent         = &func_32k_ck,
1590         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1591         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1593         .init           = &omap2_init_clksel_parent,
1594         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1595         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1596         .clksel         = omap24xx_gpt_clksel,
1597         .recalc         = &omap2_clksel_recalc,
1598 };
1599
1600 static struct clk gpt6_ick = {
1601         .name           = "gpt6_ick",
1602         .parent         = &l4_ck,
1603         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1604         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1605         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1606         .recalc         = &followparent_recalc,
1607 };
1608
1609 static struct clk gpt6_fck = {
1610         .name           = "gpt6_fck",
1611         .parent         = &func_32k_ck,
1612         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1613         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1614         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1615         .init           = &omap2_init_clksel_parent,
1616         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1617         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1618         .clksel         = omap24xx_gpt_clksel,
1619         .recalc         = &omap2_clksel_recalc,
1620 };
1621
1622 static struct clk gpt7_ick = {
1623         .name           = "gpt7_ick",
1624         .parent         = &l4_ck,
1625         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1626         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1627         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1628         .recalc         = &followparent_recalc,
1629 };
1630
1631 static struct clk gpt7_fck = {
1632         .name           = "gpt7_fck",
1633         .parent         = &func_32k_ck,
1634         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1635         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1636         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1637         .init           = &omap2_init_clksel_parent,
1638         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1639         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1640         .clksel         = omap24xx_gpt_clksel,
1641         .recalc         = &omap2_clksel_recalc,
1642 };
1643
1644 static struct clk gpt8_ick = {
1645         .name           = "gpt8_ick",
1646         .parent         = &l4_ck,
1647         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1648         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1649         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1650         .recalc         = &followparent_recalc,
1651 };
1652
1653 static struct clk gpt8_fck = {
1654         .name           = "gpt8_fck",
1655         .parent         = &func_32k_ck,
1656         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1657         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1658         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1659         .init           = &omap2_init_clksel_parent,
1660         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1661         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1662         .clksel         = omap24xx_gpt_clksel,
1663         .recalc         = &omap2_clksel_recalc,
1664 };
1665
1666 static struct clk gpt9_ick = {
1667         .name           = "gpt9_ick",
1668         .parent         = &l4_ck,
1669         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1670         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1671         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1672         .recalc         = &followparent_recalc,
1673 };
1674
1675 static struct clk gpt9_fck = {
1676         .name           = "gpt9_fck",
1677         .parent         = &func_32k_ck,
1678         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1679         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1680         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1681         .init           = &omap2_init_clksel_parent,
1682         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1683         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1684         .clksel         = omap24xx_gpt_clksel,
1685         .recalc         = &omap2_clksel_recalc,
1686 };
1687
1688 static struct clk gpt10_ick = {
1689         .name           = "gpt10_ick",
1690         .parent         = &l4_ck,
1691         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1693         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1694         .recalc         = &followparent_recalc,
1695 };
1696
1697 static struct clk gpt10_fck = {
1698         .name           = "gpt10_fck",
1699         .parent         = &func_32k_ck,
1700         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1701         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1702         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1703         .init           = &omap2_init_clksel_parent,
1704         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1705         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1706         .clksel         = omap24xx_gpt_clksel,
1707         .recalc         = &omap2_clksel_recalc,
1708 };
1709
1710 static struct clk gpt11_ick = {
1711         .name           = "gpt11_ick",
1712         .parent         = &l4_ck,
1713         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1714         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1715         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1716         .recalc         = &followparent_recalc,
1717 };
1718
1719 static struct clk gpt11_fck = {
1720         .name           = "gpt11_fck",
1721         .parent         = &func_32k_ck,
1722         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1723         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1724         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1725         .init           = &omap2_init_clksel_parent,
1726         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1727         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1728         .clksel         = omap24xx_gpt_clksel,
1729         .recalc         = &omap2_clksel_recalc,
1730 };
1731
1732 static struct clk gpt12_ick = {
1733         .name           = "gpt12_ick",
1734         .parent         = &l4_ck,
1735         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1736         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1737         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1738         .recalc         = &followparent_recalc,
1739 };
1740
1741 static struct clk gpt12_fck = {
1742         .name           = "gpt12_fck",
1743         .parent         = &func_32k_ck,
1744         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1745         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1746         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1747         .init           = &omap2_init_clksel_parent,
1748         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1749         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1750         .clksel         = omap24xx_gpt_clksel,
1751         .recalc         = &omap2_clksel_recalc,
1752 };
1753
1754 static struct clk mcbsp1_ick = {
1755         .name           = "mcbsp1_ick",
1756         .parent         = &l4_ck,
1757         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1758         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1759         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1760         .recalc         = &followparent_recalc,
1761 };
1762
1763 static struct clk mcbsp1_fck = {
1764         .name           = "mcbsp1_fck",
1765         .parent         = &func_96m_ck,
1766         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1768         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1769         .recalc         = &followparent_recalc,
1770 };
1771
1772 static struct clk mcbsp2_ick = {
1773         .name           = "mcbsp2_ick",
1774         .parent         = &l4_ck,
1775         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1776         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1778         .recalc         = &followparent_recalc,
1779 };
1780
1781 static struct clk mcbsp2_fck = {
1782         .name           = "mcbsp2_fck",
1783         .parent         = &func_96m_ck,
1784         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1785         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1786         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1787         .recalc         = &followparent_recalc,
1788 };
1789
1790 static struct clk mcbsp3_ick = {
1791         .name           = "mcbsp3_ick",
1792         .parent         = &l4_ck,
1793         .flags          = CLOCK_IN_OMAP243X,
1794         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1795         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1796         .recalc         = &followparent_recalc,
1797 };
1798
1799 static struct clk mcbsp3_fck = {
1800         .name           = "mcbsp3_fck",
1801         .parent         = &func_96m_ck,
1802         .flags          = CLOCK_IN_OMAP243X,
1803         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1804         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1805         .recalc         = &followparent_recalc,
1806 };
1807
1808 static struct clk mcbsp4_ick = {
1809         .name           = "mcbsp4_ick",
1810         .parent         = &l4_ck,
1811         .flags          = CLOCK_IN_OMAP243X,
1812         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1813         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk mcbsp4_fck = {
1818         .name           = "mcbsp4_fck",
1819         .parent         = &func_96m_ck,
1820         .flags          = CLOCK_IN_OMAP243X,
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1822         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcbsp5_ick = {
1827         .name           = "mcbsp5_ick",
1828         .parent         = &l4_ck,
1829         .flags          = CLOCK_IN_OMAP243X,
1830         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1831         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1832         .recalc         = &followparent_recalc,
1833 };
1834
1835 static struct clk mcbsp5_fck = {
1836         .name           = "mcbsp5_fck",
1837         .parent         = &func_96m_ck,
1838         .flags          = CLOCK_IN_OMAP243X,
1839         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1840         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 static struct clk mcspi1_ick = {
1845         .name           = "mcspi_ick",
1846         .id             = 1,
1847         .parent         = &l4_ck,
1848         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1849         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1850         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1851         .recalc         = &followparent_recalc,
1852 };
1853
1854 static struct clk mcspi1_fck = {
1855         .name           = "mcspi_fck",
1856         .id             = 1,
1857         .parent         = &func_48m_ck,
1858         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1859         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1860         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1861         .recalc         = &followparent_recalc,
1862 };
1863
1864 static struct clk mcspi2_ick = {
1865         .name           = "mcspi_ick",
1866         .id             = 2,
1867         .parent         = &l4_ck,
1868         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1869         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1870         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1871         .recalc         = &followparent_recalc,
1872 };
1873
1874 static struct clk mcspi2_fck = {
1875         .name           = "mcspi_fck",
1876         .id             = 2,
1877         .parent         = &func_48m_ck,
1878         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1879         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1880         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1881         .recalc         = &followparent_recalc,
1882 };
1883
1884 static struct clk mcspi3_ick = {
1885         .name           = "mcspi_ick",
1886         .id             = 3,
1887         .parent         = &l4_ck,
1888         .flags          = CLOCK_IN_OMAP243X,
1889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1890         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk mcspi3_fck = {
1895         .name           = "mcspi_fck",
1896         .id             = 3,
1897         .parent         = &func_48m_ck,
1898         .flags          = CLOCK_IN_OMAP243X,
1899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1900         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1901         .recalc         = &followparent_recalc,
1902 };
1903
1904 static struct clk uart1_ick = {
1905         .name           = "uart1_ick",
1906         .parent         = &l4_ck,
1907         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1908         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1909         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1910         .recalc         = &followparent_recalc,
1911 };
1912
1913 static struct clk uart1_fck = {
1914         .name           = "uart1_fck",
1915         .parent         = &func_48m_ck,
1916         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1917         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1918         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk uart2_ick = {
1923         .name           = "uart2_ick",
1924         .parent         = &l4_ck,
1925         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1928         .recalc         = &followparent_recalc,
1929 };
1930
1931 static struct clk uart2_fck = {
1932         .name           = "uart2_fck",
1933         .parent         = &func_48m_ck,
1934         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1936         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 static struct clk uart3_ick = {
1941         .name           = "uart3_ick",
1942         .parent         = &l4_ck,
1943         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1944         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1945         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk uart3_fck = {
1950         .name           = "uart3_fck",
1951         .parent         = &func_48m_ck,
1952         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1953         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1954         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1955         .recalc         = &followparent_recalc,
1956 };
1957
1958 static struct clk gpios_ick = {
1959         .name           = "gpios_ick",
1960         .parent         = &l4_ck,
1961         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1962         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1963         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1964         .recalc         = &followparent_recalc,
1965 };
1966
1967 static struct clk gpios_fck = {
1968         .name           = "gpios_fck",
1969         .parent         = &func_32k_ck,
1970         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1971         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1972         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk mpu_wdt_ick = {
1977         .name           = "mpu_wdt_ick",
1978         .parent         = &l4_ck,
1979         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1980         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1981         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1982         .recalc         = &followparent_recalc,
1983 };
1984
1985 static struct clk mpu_wdt_fck = {
1986         .name           = "mpu_wdt_fck",
1987         .parent         = &func_32k_ck,
1988         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1989         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1990         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1991         .recalc         = &followparent_recalc,
1992 };
1993
1994 static struct clk sync_32k_ick = {
1995         .name           = "sync_32k_ick",
1996         .parent         = &l4_ck,
1997         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1998         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1999         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2000         .recalc         = &followparent_recalc,
2001 };
2002 static struct clk wdt1_ick = {
2003         .name           = "wdt1_ick",
2004         .parent         = &l4_ck,
2005         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2006         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2007         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2008         .recalc         = &followparent_recalc,
2009 };
2010 static struct clk omapctrl_ick = {
2011         .name           = "omapctrl_ick",
2012         .parent         = &l4_ck,
2013         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2014         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2015         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2016         .recalc         = &followparent_recalc,
2017 };
2018 static struct clk icr_ick = {
2019         .name           = "icr_ick",
2020         .parent         = &l4_ck,
2021         .flags          = CLOCK_IN_OMAP243X,
2022         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2023         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2024         .recalc         = &followparent_recalc,
2025 };
2026
2027 static struct clk cam_ick = {
2028         .name           = "cam_ick",
2029         .parent         = &l4_ck,
2030         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2031         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2032         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2033         .recalc         = &followparent_recalc,
2034 };
2035
2036 static struct clk cam_fck = {
2037         .name           = "cam_fck",
2038         .parent         = &func_96m_ck,
2039         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2040         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2041         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2042         .recalc         = &followparent_recalc,
2043 };
2044
2045 static struct clk mailboxes_ick = {
2046         .name           = "mailboxes_ick",
2047         .parent         = &l4_ck,
2048         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2049         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2050         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2051         .recalc         = &followparent_recalc,
2052 };
2053
2054 static struct clk wdt4_ick = {
2055         .name           = "wdt4_ick",
2056         .parent         = &l4_ck,
2057         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2059         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2060         .recalc         = &followparent_recalc,
2061 };
2062
2063 static struct clk wdt4_fck = {
2064         .name           = "wdt4_fck",
2065         .parent         = &func_32k_ck,
2066         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2067         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2068         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2069         .recalc         = &followparent_recalc,
2070 };
2071
2072 static struct clk wdt3_ick = {
2073         .name           = "wdt3_ick",
2074         .parent         = &l4_ck,
2075         .flags          = CLOCK_IN_OMAP242X,
2076         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2077         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2078         .recalc         = &followparent_recalc,
2079 };
2080
2081 static struct clk wdt3_fck = {
2082         .name           = "wdt3_fck",
2083         .parent         = &func_32k_ck,
2084         .flags          = CLOCK_IN_OMAP242X,
2085         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2086         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2087         .recalc         = &followparent_recalc,
2088 };
2089
2090 static struct clk mspro_ick = {
2091         .name           = "mspro_ick",
2092         .parent         = &l4_ck,
2093         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2094         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2095         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2096         .recalc         = &followparent_recalc,
2097 };
2098
2099 static struct clk mspro_fck = {
2100         .name           = "mspro_fck",
2101         .parent         = &func_96m_ck,
2102         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2103         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2104         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2105         .recalc         = &followparent_recalc,
2106 };
2107
2108 static struct clk mmc_ick = {
2109         .name           = "mmc_ick",
2110         .parent         = &l4_ck,
2111         .flags          = CLOCK_IN_OMAP242X,
2112         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2113         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk mmc_fck = {
2118         .name           = "mmc_fck",
2119         .parent         = &func_96m_ck,
2120         .flags          = CLOCK_IN_OMAP242X,
2121         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2122         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2123         .recalc         = &followparent_recalc,
2124 };
2125
2126 static struct clk fac_ick = {
2127         .name           = "fac_ick",
2128         .parent         = &l4_ck,
2129         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2130         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2131         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk fac_fck = {
2136         .name           = "fac_fck",
2137         .parent         = &func_12m_ck,
2138         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2139         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2140         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 static struct clk eac_ick = {
2145         .name           = "eac_ick",
2146         .parent         = &l4_ck,
2147         .flags          = CLOCK_IN_OMAP242X,
2148         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2149         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2150         .recalc         = &followparent_recalc,
2151 };
2152
2153 static struct clk eac_fck = {
2154         .name           = "eac_fck",
2155         .parent         = &func_96m_ck,
2156         .flags          = CLOCK_IN_OMAP242X,
2157         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2158         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2159         .recalc         = &followparent_recalc,
2160 };
2161
2162 static struct clk hdq_ick = {
2163         .name           = "hdq_ick",
2164         .parent         = &l4_ck,
2165         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2166         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2167         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2168         .recalc         = &followparent_recalc,
2169 };
2170
2171 static struct clk hdq_fck = {
2172         .name           = "hdq_fck",
2173         .parent         = &func_12m_ck,
2174         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2175         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2176         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2177         .recalc         = &followparent_recalc,
2178 };
2179
2180 static struct clk i2c2_ick = {
2181         .name           = "i2c_ick",
2182         .id             = 2,
2183         .parent         = &l4_ck,
2184         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2185         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2186         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2187         .recalc         = &followparent_recalc,
2188 };
2189
2190 static struct clk i2c2_fck = {
2191         .name           = "i2c_fck",
2192         .id             = 2,
2193         .parent         = &func_12m_ck,
2194         .flags          = CLOCK_IN_OMAP242X,
2195         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2196         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2197         .recalc         = &followparent_recalc,
2198 };
2199
2200 static struct clk i2chs2_fck = {
2201         .name           = "i2chs_fck",
2202         .id             = 2,
2203         .parent         = &func_96m_ck,
2204         .flags          = CLOCK_IN_OMAP243X,
2205         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2206         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2207         .recalc         = &followparent_recalc,
2208 };
2209
2210 static struct clk i2c1_ick = {
2211         .name           = "i2c_ick",
2212         .id             = 1,
2213         .parent         = &l4_ck,
2214         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2215         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2216         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 static struct clk i2c1_fck = {
2221         .name           = "i2c_fck",
2222         .id             = 1,
2223         .parent         = &func_12m_ck,
2224         .flags          = CLOCK_IN_OMAP242X,
2225         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2226         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2227         .recalc         = &followparent_recalc,
2228 };
2229
2230 static struct clk i2chs1_fck = {
2231         .name           = "i2chs_fck",
2232         .id             = 1,
2233         .parent         = &func_96m_ck,
2234         .flags          = CLOCK_IN_OMAP243X,
2235         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2236         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2237         .recalc         = &followparent_recalc,
2238 };
2239
2240 static struct clk gpmc_fck = {
2241         .name           = "gpmc_fck",
2242         .parent         = &core_l3_ck,
2243         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2244         .recalc         = &followparent_recalc,
2245 };
2246
2247 static struct clk sdma_fck = {
2248         .name           = "sdma_fck",
2249         .parent         = &core_l3_ck,
2250         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2251         .recalc         = &followparent_recalc,
2252 };
2253
2254 static struct clk sdma_ick = {
2255         .name           = "sdma_ick",
2256         .parent         = &l4_ck,
2257         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2258         .recalc         = &followparent_recalc,
2259 };
2260
2261 static struct clk vlynq_ick = {
2262         .name           = "vlynq_ick",
2263         .parent         = &core_l3_ck,
2264         .flags          = CLOCK_IN_OMAP242X,
2265         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2266         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2267         .recalc         = &followparent_recalc,
2268 };
2269
2270 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2271         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2272         { .div = 0 }
2273 };
2274
2275 static const struct clksel_rate vlynq_fck_core_rates[] = {
2276         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2277         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2278         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2279         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2280         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2281         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2282         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2283         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2284         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2285         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2286         { .div = 0 }
2287 };
2288
2289 static const struct clksel vlynq_fck_clksel[] = {
2290         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2291         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2292         { .parent = NULL }
2293 };
2294
2295 static struct clk vlynq_fck = {
2296         .name           = "vlynq_fck",
2297         .parent         = &func_96m_ck,
2298         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2299         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2300         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2301         .init           = &omap2_init_clksel_parent,
2302         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2303         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2304         .clksel         = vlynq_fck_clksel,
2305         .recalc         = &omap2_clksel_recalc,
2306         .round_rate     = &omap2_clksel_round_rate,
2307         .set_rate       = &omap2_clksel_set_rate
2308 };
2309
2310 static struct clk sdrc_ick = {
2311         .name           = "sdrc_ick",
2312         .parent         = &l4_ck,
2313         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2314         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2315         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2316         .recalc         = &followparent_recalc,
2317 };
2318
2319 static struct clk des_ick = {
2320         .name           = "des_ick",
2321         .parent         = &l4_ck,
2322         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2323         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2324         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2325         .recalc         = &followparent_recalc,
2326 };
2327
2328 static struct clk sha_ick = {
2329         .name           = "sha_ick",
2330         .parent         = &l4_ck,
2331         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2333         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2334         .recalc         = &followparent_recalc,
2335 };
2336
2337 static struct clk rng_ick = {
2338         .name           = "rng_ick",
2339         .parent         = &l4_ck,
2340         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2342         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2343         .recalc         = &followparent_recalc,
2344 };
2345
2346 static struct clk aes_ick = {
2347         .name           = "aes_ick",
2348         .parent         = &l4_ck,
2349         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2350         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2351         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk pka_ick = {
2356         .name           = "pka_ick",
2357         .parent         = &l4_ck,
2358         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2359         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2360         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 static struct clk usb_fck = {
2365         .name           = "usb_fck",
2366         .parent         = &func_48m_ck,
2367         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2369         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk usbhs_ick = {
2374         .name           = "usbhs_ick",
2375         .parent         = &core_l3_ck,
2376         .flags          = CLOCK_IN_OMAP243X,
2377         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2378         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2379         .recalc         = &followparent_recalc,
2380 };
2381
2382 static struct clk mmchs1_ick = {
2383         .name           = "mmchs1_ick",
2384         .parent         = &l4_ck,
2385         .flags          = CLOCK_IN_OMAP243X,
2386         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2387         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2388         .recalc         = &followparent_recalc,
2389 };
2390
2391 static struct clk mmchs1_fck = {
2392         .name           = "mmchs1_fck",
2393         .parent         = &func_96m_ck,
2394         .flags          = CLOCK_IN_OMAP243X,
2395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2396         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2397         .recalc         = &followparent_recalc,
2398 };
2399
2400 static struct clk mmchs2_ick = {
2401         .name           = "mmchs2_ick",
2402         .parent         = &l4_ck,
2403         .flags          = CLOCK_IN_OMAP243X,
2404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2405         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 static struct clk mmchs2_fck = {
2410         .name           = "mmchs2_fck",
2411         .parent         = &func_96m_ck,
2412         .flags          = CLOCK_IN_OMAP243X,
2413         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2414         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk gpio5_ick = {
2419         .name           = "gpio5_ick",
2420         .parent         = &l4_ck,
2421         .flags          = CLOCK_IN_OMAP243X,
2422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2423         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk gpio5_fck = {
2428         .name           = "gpio5_fck",
2429         .parent         = &func_32k_ck,
2430         .flags          = CLOCK_IN_OMAP243X,
2431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2432         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk mdm_intc_ick = {
2437         .name           = "mdm_intc_ick",
2438         .parent         = &l4_ck,
2439         .flags          = CLOCK_IN_OMAP243X,
2440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2441         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2442         .recalc         = &followparent_recalc,
2443 };
2444
2445 static struct clk mmchsdb1_fck = {
2446         .name           = "mmchsdb1_fck",
2447         .parent         = &func_32k_ck,
2448         .flags          = CLOCK_IN_OMAP243X,
2449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2450         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2451         .recalc         = &followparent_recalc,
2452 };
2453
2454 static struct clk mmchsdb2_fck = {
2455         .name           = "mmchsdb2_fck",
2456         .parent         = &func_32k_ck,
2457         .flags          = CLOCK_IN_OMAP243X,
2458         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2459         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2460         .recalc         = &followparent_recalc,
2461 };
2462
2463 /*
2464  * This clock is a composite clock which does entire set changes then
2465  * forces a rebalance. It keys on the MPU speed, but it really could
2466  * be any key speed part of a set in the rate table.
2467  *
2468  * to really change a set, you need memory table sets which get changed
2469  * in sram, pre-notifiers & post notifiers, changing the top set, without
2470  * having low level display recalc's won't work... this is why dpm notifiers
2471  * work, isr's off, walk a list of clocks already _off_ and not messing with
2472  * the bus.
2473  *
2474  * This clock should have no parent. It embodies the entire upper level
2475  * active set. A parent will mess up some of the init also.
2476  */
2477 static struct clk virt_prcm_set = {
2478         .name           = "virt_prcm_set",
2479         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2480                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2481         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2482         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2483         .set_rate       = &omap2_select_table_rate,
2484         .round_rate     = &omap2_round_to_table_rate,
2485 };
2486
2487 static struct clk *onchip_24xx_clks[] __initdata = {
2488         /* external root sources */
2489         &func_32k_ck,
2490         &osc_ck,
2491         &sys_ck,
2492         &alt_ck,
2493         /* internal analog sources */
2494         &dpll_ck,
2495         &apll96_ck,
2496         &apll54_ck,
2497         /* internal prcm root sources */
2498         &func_54m_ck,
2499         &core_ck,
2500         &func_96m_ck,
2501         &func_48m_ck,
2502         &func_12m_ck,
2503         &wdt1_osc_ck,
2504         &sys_clkout_src,
2505         &sys_clkout,
2506         &sys_clkout2_src,
2507         &sys_clkout2,
2508         &emul_ck,
2509         /* mpu domain clocks */
2510         &mpu_ck,
2511         /* dsp domain clocks */
2512         &dsp_fck,
2513         &dsp_irate_ick,
2514         &dsp_ick,               /* 242x */
2515         &iva2_1_ick,            /* 243x */
2516         &iva1_ifck,             /* 242x */
2517         &iva1_mpu_int_ifck,     /* 242x */
2518         /* GFX domain clocks */
2519         &gfx_3d_fck,
2520         &gfx_2d_fck,
2521         &gfx_ick,
2522         /* Modem domain clocks */
2523         &mdm_ick,
2524         &mdm_osc_ck,
2525         /* DSS domain clocks */
2526         &dss_ick,
2527         &dss1_fck,
2528         &dss2_fck,
2529         &dss_54m_fck,
2530         /* L3 domain clocks */
2531         &core_l3_ck,
2532         &ssi_ssr_sst_fck,
2533         &usb_l4_ick,
2534         /* L4 domain clocks */
2535         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2536         &ssi_l4_ick,
2537         /* virtual meta-group clock */
2538         &virt_prcm_set,
2539         /* general l4 interface ck, multi-parent functional clk */
2540         &gpt1_ick,
2541         &gpt1_fck,
2542         &gpt2_ick,
2543         &gpt2_fck,
2544         &gpt3_ick,
2545         &gpt3_fck,
2546         &gpt4_ick,
2547         &gpt4_fck,
2548         &gpt5_ick,
2549         &gpt5_fck,
2550         &gpt6_ick,
2551         &gpt6_fck,
2552         &gpt7_ick,
2553         &gpt7_fck,
2554         &gpt8_ick,
2555         &gpt8_fck,
2556         &gpt9_ick,
2557         &gpt9_fck,
2558         &gpt10_ick,
2559         &gpt10_fck,
2560         &gpt11_ick,
2561         &gpt11_fck,
2562         &gpt12_ick,
2563         &gpt12_fck,
2564         &mcbsp1_ick,
2565         &mcbsp1_fck,
2566         &mcbsp2_ick,
2567         &mcbsp2_fck,
2568         &mcbsp3_ick,
2569         &mcbsp3_fck,
2570         &mcbsp4_ick,
2571         &mcbsp4_fck,
2572         &mcbsp5_ick,
2573         &mcbsp5_fck,
2574         &mcspi1_ick,
2575         &mcspi1_fck,
2576         &mcspi2_ick,
2577         &mcspi2_fck,
2578         &mcspi3_ick,
2579         &mcspi3_fck,
2580         &uart1_ick,
2581         &uart1_fck,
2582         &uart2_ick,
2583         &uart2_fck,
2584         &uart3_ick,
2585         &uart3_fck,
2586         &gpios_ick,
2587         &gpios_fck,
2588         &mpu_wdt_ick,
2589         &mpu_wdt_fck,
2590         &sync_32k_ick,
2591         &wdt1_ick,
2592         &omapctrl_ick,
2593         &icr_ick,
2594         &cam_fck,
2595         &cam_ick,
2596         &mailboxes_ick,
2597         &wdt4_ick,
2598         &wdt4_fck,
2599         &wdt3_ick,
2600         &wdt3_fck,
2601         &mspro_ick,
2602         &mspro_fck,
2603         &mmc_ick,
2604         &mmc_fck,
2605         &fac_ick,
2606         &fac_fck,
2607         &eac_ick,
2608         &eac_fck,
2609         &hdq_ick,
2610         &hdq_fck,
2611         &i2c1_ick,
2612         &i2c1_fck,
2613         &i2chs1_fck,
2614         &i2c2_ick,
2615         &i2c2_fck,
2616         &i2chs2_fck,
2617         &gpmc_fck,
2618         &sdma_fck,
2619         &sdma_ick,
2620         &vlynq_ick,
2621         &vlynq_fck,
2622         &sdrc_ick,
2623         &des_ick,
2624         &sha_ick,
2625         &rng_ick,
2626         &aes_ick,
2627         &pka_ick,
2628         &usb_fck,
2629         &usbhs_ick,
2630         &mmchs1_ick,
2631         &mmchs1_fck,
2632         &mmchs2_ick,
2633         &mmchs2_fck,
2634         &gpio5_ick,
2635         &gpio5_fck,
2636         &mdm_intc_ick,
2637         &mmchsdb1_fck,
2638         &mmchsdb2_fck,
2639 };
2640
2641 #endif
2642