2 * linux/arch/arm/mach-omap2/clock24xx.h
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
23 #include "prm-regbits-24xx.h"
24 #include "cm-regbits-24xx.h"
27 static void omap2_table_mpu_recalc(struct clk *clk, unsigned long parent_rate,
29 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
30 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
31 static void omap2_sys_clk_recalc(struct clk *clk, unsigned long parent_rate,
33 static void omap2_osc_clk_recalc(struct clk *clk, unsigned long parent_rate,
35 static void omap2_dpllcore_recalc(struct clk *clk, unsigned long parent_rate,
37 static int omap2_clk_fixed_enable(struct clk *clk);
38 static void omap2_clk_fixed_disable(struct clk *clk);
39 static int omap2_enable_osc_ck(struct clk *clk);
40 static void omap2_disable_osc_ck(struct clk *clk);
41 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
43 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
44 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
45 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
48 unsigned long xtal_speed; /* crystal rate */
49 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
50 unsigned long mpu_speed; /* speed of MPU */
51 unsigned long cm_clksel_mpu; /* mpu divider */
52 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
53 unsigned long cm_clksel_gfx; /* gfx dividers */
54 unsigned long cm_clksel1_core; /* major subsystem dividers */
55 unsigned long cm_clksel1_pll; /* m,n */
56 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
57 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
58 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
63 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
64 * These configurations are characterized by voltage and speed for clocks.
65 * The device is only validated for certain combinations. One way to express
66 * these combinations is via the 'ratio's' which the clocks operate with
67 * respect to each other. These ratio sets are for a given voltage/DPLL
68 * setting. All configurations can be described by a DPLL setting and a ratio
69 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
71 * 2430 differs from 2420 in that there are no more phase synchronizers used.
72 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
73 * 2430 (iva2.1, NOdsp, mdm)
76 /* Core fields for cm_clksel, not ratio governed */
77 #define RX_CLKSEL_DSS1 (0x10 << 8)
78 #define RX_CLKSEL_DSS2 (0x0 << 13)
79 #define RX_CLKSEL_SSI (0x5 << 20)
81 /*-------------------------------------------------------------------------
83 *-------------------------------------------------------------------------*/
85 /* 2430 Ratio's, 2430-Ratio Config 1 */
86 #define R1_CLKSEL_L3 (4 << 0)
87 #define R1_CLKSEL_L4 (2 << 5)
88 #define R1_CLKSEL_USB (4 << 25)
89 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
90 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
91 R1_CLKSEL_L4 | R1_CLKSEL_L3
92 #define R1_CLKSEL_MPU (2 << 0)
93 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
94 #define R1_CLKSEL_DSP (2 << 0)
95 #define R1_CLKSEL_DSP_IF (2 << 5)
96 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
97 #define R1_CLKSEL_GFX (2 << 0)
98 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
99 #define R1_CLKSEL_MDM (4 << 0)
100 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
102 /* 2430-Ratio Config 2 */
103 #define R2_CLKSEL_L3 (6 << 0)
104 #define R2_CLKSEL_L4 (2 << 5)
105 #define R2_CLKSEL_USB (2 << 25)
106 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
107 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
108 R2_CLKSEL_L4 | R2_CLKSEL_L3
109 #define R2_CLKSEL_MPU (2 << 0)
110 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
111 #define R2_CLKSEL_DSP (2 << 0)
112 #define R2_CLKSEL_DSP_IF (3 << 5)
113 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
114 #define R2_CLKSEL_GFX (2 << 0)
115 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
116 #define R2_CLKSEL_MDM (6 << 0)
117 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
119 /* 2430-Ratio Bootm (BYPASS) */
120 #define RB_CLKSEL_L3 (1 << 0)
121 #define RB_CLKSEL_L4 (1 << 5)
122 #define RB_CLKSEL_USB (1 << 25)
123 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
124 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
125 RB_CLKSEL_L4 | RB_CLKSEL_L3
126 #define RB_CLKSEL_MPU (1 << 0)
127 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
128 #define RB_CLKSEL_DSP (1 << 0)
129 #define RB_CLKSEL_DSP_IF (1 << 5)
130 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
131 #define RB_CLKSEL_GFX (1 << 0)
132 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
133 #define RB_CLKSEL_MDM (1 << 0)
134 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
136 /* 2420 Ratio Equivalents */
137 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
138 #define RXX_CLKSEL_SSI (0x8 << 20)
140 /* 2420-PRCM III 532MHz core */
141 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
142 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
143 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
144 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
145 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
146 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
148 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
149 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
150 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
151 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
152 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
153 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
154 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
155 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
156 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
158 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
159 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
161 /* 2420-PRCM II 600MHz core */
162 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
163 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
164 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
165 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
166 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
167 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
168 RII_CLKSEL_L4 | RII_CLKSEL_L3
169 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
170 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
171 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
172 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
173 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
174 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
175 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
176 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
177 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
179 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
180 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
182 /* 2420-PRCM I 660MHz core */
183 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
184 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
185 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
186 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
187 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
188 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
189 RI_CLKSEL_L4 | RI_CLKSEL_L3
190 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
191 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
192 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
193 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
194 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
195 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
196 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
197 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
198 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
200 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
201 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
203 /* 2420-PRCM VII (boot) */
204 #define RVII_CLKSEL_L3 (1 << 0)
205 #define RVII_CLKSEL_L4 (1 << 5)
206 #define RVII_CLKSEL_DSS1 (1 << 8)
207 #define RVII_CLKSEL_DSS2 (0 << 13)
208 #define RVII_CLKSEL_VLYNQ (1 << 15)
209 #define RVII_CLKSEL_SSI (1 << 20)
210 #define RVII_CLKSEL_USB (1 << 25)
212 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
213 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
214 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
216 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
217 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
219 #define RVII_CLKSEL_DSP (1 << 0)
220 #define RVII_CLKSEL_DSP_IF (1 << 5)
221 #define RVII_SYNC_DSP (0 << 7)
222 #define RVII_CLKSEL_IVA (1 << 8)
223 #define RVII_SYNC_IVA (0 << 13)
224 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
225 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
227 #define RVII_CLKSEL_GFX (1 << 0)
228 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
230 /*-------------------------------------------------------------------------
231 * 2430 Target modes: Along with each configuration the CPU has several
232 * modes which goes along with them. Modes mainly are the addition of
233 * describe DPLL combinations to go along with a ratio.
234 *-------------------------------------------------------------------------*/
236 /* Hardware governed */
237 #define MX_48M_SRC (0 << 3)
238 #define MX_54M_SRC (0 << 5)
239 #define MX_APLLS_CLIKIN_12 (3 << 23)
240 #define MX_APLLS_CLIKIN_13 (2 << 23)
241 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
244 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
245 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 #define M5A_DPLL_MULT_12 (133 << 12)
248 #define M5A_DPLL_DIV_12 (5 << 8)
249 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
250 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
252 #define M5A_DPLL_MULT_13 (61 << 12)
253 #define M5A_DPLL_DIV_13 (2 << 8)
254 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
255 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
257 #define M5A_DPLL_MULT_19 (55 << 12)
258 #define M5A_DPLL_DIV_19 (3 << 8)
259 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
260 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
262 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
263 #define M5B_DPLL_MULT_12 (50 << 12)
264 #define M5B_DPLL_DIV_12 (2 << 8)
265 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
266 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
268 #define M5B_DPLL_MULT_13 (200 << 12)
269 #define M5B_DPLL_DIV_13 (12 << 8)
271 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
272 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
274 #define M5B_DPLL_MULT_19 (125 << 12)
275 #define M5B_DPLL_DIV_19 (31 << 8)
276 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
277 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
280 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
282 #define M4_DPLL_MULT_12 (133 << 12)
283 #define M4_DPLL_DIV_12 (3 << 8)
284 #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
285 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
288 #define M4_DPLL_MULT_13 (399 << 12)
289 #define M4_DPLL_DIV_13 (12 << 8)
290 #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
291 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
294 #define M4_DPLL_MULT_19 (145 << 12)
295 #define M4_DPLL_DIV_19 (6 << 8)
296 #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
297 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
301 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
303 #define M3_DPLL_MULT_12 (55 << 12)
304 #define M3_DPLL_DIV_12 (1 << 8)
305 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
306 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
308 #define M3_DPLL_MULT_13 (76 << 12)
309 #define M3_DPLL_DIV_13 (2 << 8)
310 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
311 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
313 #define M3_DPLL_MULT_19 (17 << 12)
314 #define M3_DPLL_DIV_19 (0 << 8)
315 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
316 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
320 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
322 #define M2_DPLL_MULT_12 (55 << 12)
323 #define M2_DPLL_DIV_12 (1 << 8)
324 #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
325 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
328 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
329 * relock time issue */
330 /* Core frequency changed from 330/165 to 329/164 MHz*/
331 #define M2_DPLL_MULT_13 (76 << 12)
332 #define M2_DPLL_DIV_13 (2 << 8)
333 #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
334 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
337 #define M2_DPLL_MULT_19 (17 << 12)
338 #define M2_DPLL_DIV_19 (0 << 8)
339 #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
340 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
344 #define MB_DPLL_MULT (1 << 12)
345 #define MB_DPLL_DIV (0 << 8)
346 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
347 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
349 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
350 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
352 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
353 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
356 * 2430 - chassis (sedna)
357 * 165 (ratio1) same as above #2
359 * 133 (ratio2) same as above #4
360 * 110 (ratio2) same as above #3
365 /* PRCM I target DPLL = 2*330MHz = 660MHz */
366 #define MI_DPLL_MULT_12 (55 << 12)
367 #define MI_DPLL_DIV_12 (1 << 8)
368 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
369 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
373 * 2420 Equivalent - mode registers
374 * PRCM II , target DPLL = 2*300MHz = 600MHz
376 #define MII_DPLL_MULT_12 (50 << 12)
377 #define MII_DPLL_DIV_12 (1 << 8)
378 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
379 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
381 #define MII_DPLL_MULT_13 (300 << 12)
382 #define MII_DPLL_DIV_13 (12 << 8)
383 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
384 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
387 /* PRCM III target DPLL = 2*266 = 532MHz*/
388 #define MIII_DPLL_MULT_12 (133 << 12)
389 #define MIII_DPLL_DIV_12 (5 << 8)
390 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
391 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
393 #define MIII_DPLL_MULT_13 (266 << 12)
394 #define MIII_DPLL_DIV_13 (12 << 8)
395 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
396 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
399 /* PRCM VII (boot bypass) */
400 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
401 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
403 /* High and low operation value */
404 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
405 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
407 /* MPU speed defines */
408 #define S12M 12000000
409 #define S13M 13000000
410 #define S19M 19200000
411 #define S26M 26000000
412 #define S100M 100000000
413 #define S133M 133000000
414 #define S150M 150000000
415 #define S164M 164000000
416 #define S165M 165000000
417 #define S199M 199000000
418 #define S200M 200000000
419 #define S266M 266000000
420 #define S300M 300000000
421 #define S329M 329000000
422 #define S330M 330000000
423 #define S399M 399000000
424 #define S400M 400000000
425 #define S532M 532000000
426 #define S600M 600000000
427 #define S658M 658000000
428 #define S660M 660000000
429 #define S798M 798000000
431 /*-------------------------------------------------------------------------
432 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
433 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
434 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
435 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
437 * Filling in table based on H4 boards and 2430-SDPs variants available.
438 * There are quite a few more rates combinations which could be defined.
440 * When multiple values are defined the start up will try and choose the
441 * fastest one. If a 'fast' value is defined, then automatically, the /2
442 * one should be included as it can be used. Generally having more that
443 * one fast set does not make sense, as static timings need to be changed
444 * to change the set. The exception is the bypass setting which is
445 * availble for low power bypass.
447 * Note: This table needs to be sorted, fastest to slowest.
448 *-------------------------------------------------------------------------*/
449 static struct prcm_config rate_table[] = {
451 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
452 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
453 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
454 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
458 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
459 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
460 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
461 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
464 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
465 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
466 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
470 /* PRCM III - FAST */
471 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
472 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
473 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
474 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
477 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
478 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
479 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
480 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
484 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
485 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
486 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
487 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
490 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
491 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
492 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
493 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
496 /* PRCM III - SLOW */
497 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
498 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
499 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
500 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
503 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
504 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
505 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
506 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
509 /* PRCM-VII (boot-bypass) */
510 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
511 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
512 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
513 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
516 /* PRCM-VII (boot-bypass) */
517 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
518 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
519 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
520 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
523 /* PRCM #4 - ratio2 (ES2.1) - FAST */
524 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
525 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
526 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
527 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
528 SDRC_RFR_CTRL_133MHz,
531 /* PRCM #2 - ratio1 (ES2) - FAST */
532 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
533 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
534 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
535 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
536 SDRC_RFR_CTRL_165MHz,
539 /* PRCM #5a - ratio1 - FAST */
540 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
541 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
542 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
543 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
544 SDRC_RFR_CTRL_133MHz,
547 /* PRCM #5b - ratio1 - FAST */
548 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
549 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
550 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
551 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
552 SDRC_RFR_CTRL_100MHz,
555 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
556 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
557 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
558 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
559 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
560 SDRC_RFR_CTRL_133MHz,
563 /* PRCM #2 - ratio1 (ES2) - SLOW */
564 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
565 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
566 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
567 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
568 SDRC_RFR_CTRL_165MHz,
571 /* PRCM #5a - ratio1 - SLOW */
572 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
573 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
574 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
575 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
576 SDRC_RFR_CTRL_133MHz,
579 /* PRCM #5b - ratio1 - SLOW*/
580 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
581 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
582 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
583 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
584 SDRC_RFR_CTRL_100MHz,
587 /* PRCM-boot/bypass */
588 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
589 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
590 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
591 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
592 SDRC_RFR_CTRL_BYPASS,
595 /* PRCM-boot/bypass */
596 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
597 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
598 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
599 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
600 SDRC_RFR_CTRL_BYPASS,
603 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
606 /*-------------------------------------------------------------------------
609 * NOTE:In many cases here we are assigning a 'default' parent. In many
610 * cases the parent is selectable. The get/set parent calls will also
613 * Many some clocks say always_enabled, but they can be auto idled for
614 * power savings. They will always be available upon clock request.
616 * Several sources are given initial rates which may be wrong, this will
617 * be fixed up in the init func.
619 * Things are broadly separated below by clock domains. It is
620 * noteworthy that most periferals have dependencies on multiple clock
621 * domains. Many get their interface clocks from the L4 domain, but get
622 * functional clocks from fixed sources or other core domain derived
624 *-------------------------------------------------------------------------*/
626 /* Base external input clocks */
627 static struct clk func_32k_ck = {
628 .name = "func_32k_ck",
630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
632 .clkdm = { .name = "prm_clkdm" },
635 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
636 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
638 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
639 .clkdm = { .name = "prm_clkdm" },
640 .enable = &omap2_enable_osc_ck,
641 .disable = &omap2_disable_osc_ck,
642 .recalc = &omap2_osc_clk_recalc,
645 /* Without modem likely 12MHz, with modem likely 13MHz */
646 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
647 .name = "sys_ck", /* ~ ref_clk also */
649 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
651 .clkdm = { .name = "prm_clkdm" },
652 .recalc = &omap2_sys_clk_recalc,
655 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
658 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
660 .clkdm = { .name = "prm_clkdm" },
664 * Analog domain root source clocks
667 /* dpll_ck, is broken out in to special cases through clksel */
668 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
672 static struct dpll_data dpll_dd = {
673 .mult_div1_reg = CM_CLKSEL1,
674 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
675 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
676 .control_reg = CM_CLKEN,
677 .enable_mask = OMAP24XX_EN_DPLL_MASK,
678 .max_multiplier = 1024,
681 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
685 * XXX Cannot add round_rate here yet, as this is still a composite clock,
688 static struct clk dpll_ck = {
690 .parent = &sys_ck, /* Can be func_32k also */
692 .dpll_data = &dpll_dd,
693 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
695 .clkdm = { .name = "prm_clkdm" },
696 .recalc = &omap2_dpllcore_recalc,
697 .set_rate = &omap2_reprogram_dpllcore,
700 static struct clk apll96_ck = {
705 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
707 .clkdm = { .name = "prm_clkdm" },
708 .enable_reg = CM_CLKEN,
709 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
710 .enable = &omap2_clk_fixed_enable,
711 .disable = &omap2_clk_fixed_disable,
714 static struct clk apll54_ck = {
719 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
721 .clkdm = { .name = "prm_clkdm" },
722 .enable_reg = CM_CLKEN,
723 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
724 .enable = &omap2_clk_fixed_enable,
725 .disable = &omap2_clk_fixed_disable,
729 * PRCM digital base sources
734 static const struct clksel_rate func_54m_apll54_rates[] = {
735 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
739 static const struct clksel_rate func_54m_alt_rates[] = {
740 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
744 static const struct clksel func_54m_clksel[] = {
745 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
746 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
750 static struct clk func_54m_ck = {
751 .name = "func_54m_ck",
752 .parent = &apll54_ck, /* can also be alt_clk */
754 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
755 PARENT_CONTROLS_CLOCK,
756 .clkdm = { .name = "cm_clkdm" },
757 .init = &omap2_init_clksel_parent,
758 .clksel_reg = CM_CLKSEL1,
759 .clksel_mask = OMAP24XX_54M_SOURCE,
760 .clksel = func_54m_clksel,
761 .recalc = &omap2_clksel_recalc,
764 static struct clk core_ck = {
766 .parent = &dpll_ck, /* can also be 32k */
767 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
769 .clkdm = { .name = "cm_clkdm" },
770 .recalc = &followparent_recalc,
774 static const struct clksel_rate func_96m_apll96_rates[] = {
775 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
779 static const struct clksel_rate func_96m_alt_rates[] = {
780 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
784 static const struct clksel func_96m_clksel[] = {
785 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
786 { .parent = &alt_ck, .rates = func_96m_alt_rates },
790 /* The parent of this clock is not selectable on 2420. */
791 static struct clk func_96m_ck = {
792 .name = "func_96m_ck",
793 .parent = &apll96_ck,
795 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
796 PARENT_CONTROLS_CLOCK,
797 .clkdm = { .name = "cm_clkdm" },
798 .init = &omap2_init_clksel_parent,
799 .clksel_reg = CM_CLKSEL1,
800 .clksel_mask = OMAP2430_96M_SOURCE,
801 .clksel = func_96m_clksel,
802 .recalc = &omap2_clksel_recalc,
803 .round_rate = &omap2_clksel_round_rate,
804 .set_rate = &omap2_clksel_set_rate
809 static const struct clksel_rate func_48m_apll96_rates[] = {
810 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
814 static const struct clksel_rate func_48m_alt_rates[] = {
815 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
819 static const struct clksel func_48m_clksel[] = {
820 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
821 { .parent = &alt_ck, .rates = func_48m_alt_rates },
825 static struct clk func_48m_ck = {
826 .name = "func_48m_ck",
827 .parent = &apll96_ck, /* 96M or Alt */
829 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
830 PARENT_CONTROLS_CLOCK,
831 .clkdm = { .name = "cm_clkdm" },
832 .init = &omap2_init_clksel_parent,
833 .clksel_reg = CM_CLKSEL1,
834 .clksel_mask = OMAP24XX_48M_SOURCE,
835 .clksel = func_48m_clksel,
836 .recalc = &omap2_clksel_recalc,
837 .round_rate = &omap2_clksel_round_rate,
838 .set_rate = &omap2_clksel_set_rate
841 static struct clk func_12m_ck = {
842 .name = "func_12m_ck",
843 .parent = &func_48m_ck,
845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
846 PARENT_CONTROLS_CLOCK,
847 .clkdm = { .name = "cm_clkdm" },
848 .recalc = &omap2_fixed_divisor_recalc,
851 /* Secure timer, only available in secure mode */
852 static struct clk wdt1_osc_ck = {
853 .name = "wdt1_osc_ck",
855 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
856 .clkdm = { .name = "prm_clkdm" },
857 .recalc = &followparent_recalc,
861 * The common_clkout* clksel_rate structs are common to
862 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
863 * sys_clkout2_* are 2420-only, so the
864 * clksel_rate flags fields are inaccurate for those clocks. This is
865 * harmless since access to those clocks are gated by the struct clk
866 * flags fields, which mark them as 2420-only.
868 static const struct clksel_rate common_clkout_src_core_rates[] = {
869 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
873 static const struct clksel_rate common_clkout_src_sys_rates[] = {
874 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
878 static const struct clksel_rate common_clkout_src_96m_rates[] = {
879 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
883 static const struct clksel_rate common_clkout_src_54m_rates[] = {
884 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
888 static const struct clksel common_clkout_src_clksel[] = {
889 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
890 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
891 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
892 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
896 static struct clk sys_clkout_src = {
897 .name = "sys_clkout_src",
898 .parent = &func_54m_ck,
899 .prcm_mod = OMAP24XX_GR_MOD,
900 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
901 .clkdm = { .name = "prm_clkdm" },
902 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
903 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
904 .init = &omap2_init_clksel_parent,
905 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
906 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
907 .clksel = common_clkout_src_clksel,
908 .recalc = &omap2_clksel_recalc,
909 .round_rate = &omap2_clksel_round_rate,
910 .set_rate = &omap2_clksel_set_rate
913 static const struct clksel_rate common_clkout_rates[] = {
914 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
915 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
916 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
917 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
918 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
922 static const struct clksel sys_clkout_clksel[] = {
923 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
927 static struct clk sys_clkout = {
928 .name = "sys_clkout",
929 .parent = &sys_clkout_src,
930 .prcm_mod = OMAP24XX_GR_MOD,
931 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
932 PARENT_CONTROLS_CLOCK,
933 .clkdm = { .name = "prm_clkdm" },
934 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
935 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
936 .clksel = sys_clkout_clksel,
937 .recalc = &omap2_clksel_recalc,
938 .round_rate = &omap2_clksel_round_rate,
939 .set_rate = &omap2_clksel_set_rate
942 /* In 2430, new in 2420 ES2 */
943 static struct clk sys_clkout2_src = {
944 .name = "sys_clkout2_src",
945 .parent = &func_54m_ck,
946 .prcm_mod = OMAP24XX_GR_MOD,
947 .flags = CLOCK_IN_OMAP242X,
948 .clkdm = { .name = "cm_clkdm" },
949 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
950 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
951 .init = &omap2_init_clksel_parent,
952 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
953 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
954 .clksel = common_clkout_src_clksel,
955 .recalc = &omap2_clksel_recalc,
956 .round_rate = &omap2_clksel_round_rate,
957 .set_rate = &omap2_clksel_set_rate
960 static const struct clksel sys_clkout2_clksel[] = {
961 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
965 /* In 2430, new in 2420 ES2 */
966 static struct clk sys_clkout2 = {
967 .name = "sys_clkout2",
968 .parent = &sys_clkout2_src,
969 .prcm_mod = OMAP24XX_GR_MOD,
970 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
971 .clkdm = { .name = "cm_clkdm" },
972 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
973 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
974 .clksel = sys_clkout2_clksel,
975 .recalc = &omap2_clksel_recalc,
976 .round_rate = &omap2_clksel_round_rate,
977 .set_rate = &omap2_clksel_set_rate
980 static struct clk emul_ck = {
982 .parent = &func_54m_ck,
983 .prcm_mod = OMAP24XX_GR_MOD,
984 .flags = CLOCK_IN_OMAP242X,
985 .clkdm = { .name = "cm_clkdm" },
986 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET,
987 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
988 .recalc = &followparent_recalc,
996 * INT_M_FCLK, INT_M_I_CLK
998 * - Individual clocks are hardware managed.
999 * - Base divider comes from: CM_CLKSEL_MPU
1002 static const struct clksel_rate mpu_core_rates[] = {
1003 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1004 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1005 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1006 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1007 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1011 static const struct clksel mpu_clksel[] = {
1012 { .parent = &core_ck, .rates = mpu_core_rates },
1016 static struct clk mpu_ck = { /* Control cpu */
1019 .prcm_mod = MPU_MOD,
1020 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1021 ALWAYS_ENABLED | DELAYED_APP |
1023 .clkdm = { .name = "mpu_clkdm" },
1024 .init = &omap2_init_clksel_parent,
1025 .clksel_reg = CM_CLKSEL,
1026 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
1027 .clksel = mpu_clksel,
1028 .recalc = &omap2_clksel_recalc,
1029 .round_rate = &omap2_clksel_round_rate,
1030 .set_rate = &omap2_clksel_set_rate
1034 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1036 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1037 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1039 * Won't be too specific here. The core clock comes into this block
1040 * it is divided then tee'ed. One branch goes directly to xyz enable
1041 * controls. The other branch gets further divided by 2 then possibly
1042 * routed into a synchronizer and out of clocks abc.
1044 static const struct clksel_rate dsp_fck_core_rates[] = {
1045 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1046 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1047 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1048 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1049 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1050 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1051 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1055 static const struct clksel dsp_fck_clksel[] = {
1056 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1060 static struct clk dsp_fck = {
1063 .prcm_mod = OMAP24XX_DSP_MOD,
1064 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1066 .clkdm = { .name = "dsp_clkdm" },
1067 .enable_reg = CM_FCLKEN,
1068 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1069 .clksel_reg = CM_CLKSEL,
1070 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1071 .clksel = dsp_fck_clksel,
1072 .recalc = &omap2_clksel_recalc,
1073 .round_rate = &omap2_clksel_round_rate,
1074 .set_rate = &omap2_clksel_set_rate
1077 /* DSP interface clock */
1078 static const struct clksel_rate dsp_irate_ick_rates[] = {
1079 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1080 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1081 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1085 static const struct clksel dsp_irate_ick_clksel[] = {
1086 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1090 /* This clock does not exist as such in the TRM. */
1091 static struct clk dsp_irate_ick = {
1092 .name = "dsp_irate_ick",
1094 .prcm_mod = OMAP24XX_DSP_MOD,
1095 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1096 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1097 .clkdm = { .name = "dsp_clkdm" },
1098 .clksel_reg = CM_CLKSEL,
1099 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1100 .clksel = dsp_irate_ick_clksel,
1101 .recalc = &omap2_clksel_recalc,
1102 .round_rate = &omap2_clksel_round_rate,
1103 .set_rate = &omap2_clksel_set_rate
1107 static struct clk dsp_ick = {
1108 .name = "dsp_ick", /* apparently ipi and isp */
1109 .parent = &dsp_irate_ick,
1110 .prcm_mod = OMAP24XX_DSP_MOD,
1111 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1112 .clkdm = { .name = "dsp_clkdm" },
1113 .enable_reg = CM_ICLKEN,
1114 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1117 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1118 static struct clk iva2_1_ick = {
1119 .name = "iva2_1_ick",
1120 .parent = &dsp_irate_ick,
1121 .prcm_mod = OMAP24XX_DSP_MOD,
1122 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1123 .clkdm = { .name = "dsp_clkdm" },
1124 .enable_reg = CM_FCLKEN,
1125 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1129 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1130 * the C54x, but which is contained in the DSP powerdomain. Does not
1131 * exist on later OMAPs.
1133 static struct clk iva1_ifck = {
1134 .name = "iva1_ifck",
1136 .prcm_mod = OMAP24XX_DSP_MOD,
1137 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | DELAYED_APP,
1138 .clkdm = { .name = "iva1_clkdm" },
1139 .enable_reg = CM_FCLKEN,
1140 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1141 .clksel_reg = CM_CLKSEL,
1142 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1143 .clksel = dsp_fck_clksel,
1144 .recalc = &omap2_clksel_recalc,
1145 .round_rate = &omap2_clksel_round_rate,
1146 .set_rate = &omap2_clksel_set_rate
1149 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1150 static struct clk iva1_mpu_int_ifck = {
1151 .name = "iva1_mpu_int_ifck",
1152 .parent = &iva1_ifck,
1153 .prcm_mod = OMAP24XX_DSP_MOD,
1154 .flags = CLOCK_IN_OMAP242X,
1155 .clkdm = { .name = "iva1_clkdm" },
1156 .enable_reg = CM_FCLKEN,
1157 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1159 .recalc = &omap2_fixed_divisor_recalc,
1164 * L3 clocks are used for both interface and functional clocks to
1165 * multiple entities. Some of these clocks are completely managed
1166 * by hardware, and some others allow software control. Hardware
1167 * managed ones general are based on directly CLK_REQ signals and
1168 * various auto idle settings. The functional spec sets many of these
1169 * as 'tie-high' for their enables.
1172 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1177 * GPMC memories and SDRC have timing and clock sensitive registers which
1178 * may very well need notification when the clock changes. Currently for low
1179 * operating points, these are taken care of in sleep.S.
1181 static const struct clksel_rate core_l3_core_rates[] = {
1182 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1183 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1184 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1185 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1186 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1187 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1188 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1192 static const struct clksel core_l3_clksel[] = {
1193 { .parent = &core_ck, .rates = core_l3_core_rates },
1197 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1198 .name = "core_l3_ck",
1200 .prcm_mod = CORE_MOD,
1201 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1202 ALWAYS_ENABLED | DELAYED_APP |
1204 .clkdm = { .name = "core_l3_clkdm" },
1205 .clksel_reg = CM_CLKSEL1,
1206 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1207 .clksel = core_l3_clksel,
1208 .recalc = &omap2_clksel_recalc,
1209 .round_rate = &omap2_clksel_round_rate,
1210 .set_rate = &omap2_clksel_set_rate
1214 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1215 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1216 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1217 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1221 static const struct clksel usb_l4_ick_clksel[] = {
1222 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1226 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1227 static struct clk usb_l4_ick = { /* FS-USB interface clock */
1228 .name = "usb_l4_ick",
1229 .parent = &core_l3_ck,
1230 .prcm_mod = CORE_MOD,
1231 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1232 DELAYED_APP | CONFIG_PARTICIPANT | WAIT_READY,
1233 .clkdm = { .name = "core_l4_clkdm" },
1234 .enable_reg = CM_ICLKEN2,
1235 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1236 .idlest_bit = OMAP24XX_ST_USB_SHIFT,
1237 .clksel_reg = CM_CLKSEL1,
1238 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1239 .clksel = usb_l4_ick_clksel,
1240 .recalc = &omap2_clksel_recalc,
1241 .round_rate = &omap2_clksel_round_rate,
1242 .set_rate = &omap2_clksel_set_rate
1246 * L4 clock management domain
1248 * This domain contains lots of interface clocks from the L4 interface, some
1249 * functional clocks. Fixed APLL functional source clocks are managed in
1252 static const struct clksel_rate l4_core_l3_rates[] = {
1253 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1254 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1258 static const struct clksel l4_clksel[] = {
1259 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1263 static struct clk l4_ck = { /* used both as an ick and fck */
1265 .parent = &core_l3_ck,
1266 .prcm_mod = CORE_MOD,
1267 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1268 ALWAYS_ENABLED | DELAYED_APP,
1269 .clkdm = { .name = "core_l4_clkdm" },
1270 .clksel_reg = CM_CLKSEL1,
1271 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1272 .clksel = l4_clksel,
1273 .recalc = &omap2_clksel_recalc,
1274 .round_rate = &omap2_clksel_round_rate,
1275 .set_rate = &omap2_clksel_set_rate
1279 * SSI is in L3 management domain, its direct parent is core not l3,
1280 * many core power domain entities are grouped into the L3 clock
1282 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1284 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1286 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1287 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1288 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1289 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1290 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1291 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1292 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1293 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1297 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1298 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1302 static struct clk ssi_ssr_sst_fck = {
1305 .prcm_mod = CORE_MOD,
1306 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY |
1308 .clkdm = { .name = "core_l3_clkdm" },
1309 .enable_reg = OMAP24XX_CM_FCLKEN2,
1310 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1311 .idlest_bit = OMAP24XX_ST_SSI_SHIFT,
1312 .clksel_reg = CM_CLKSEL1,
1313 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1314 .clksel = ssi_ssr_sst_fck_clksel,
1315 .recalc = &omap2_clksel_recalc,
1316 .round_rate = &omap2_clksel_round_rate,
1317 .set_rate = &omap2_clksel_set_rate
1321 * Presumably this is the same as SSI_ICLK.
1322 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1324 static struct clk ssi_l4_ick = {
1325 .name = "ssi_l4_ick",
1327 .prcm_mod = CORE_MOD,
1328 .clkdm = { .name = "core_l4_clkdm" },
1329 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1330 .enable_reg = CM_ICLKEN2,
1331 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1332 .idlest_bit = OMAP24XX_ST_SSI_SHIFT,
1333 .recalc = &followparent_recalc,
1340 * GFX_FCLK, GFX_ICLK
1341 * GFX_CG1(2d), GFX_CG2(3d)
1343 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1344 * The 2d and 3d clocks run at a hardware determined
1345 * divided value of fclk.
1348 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1350 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1351 static const struct clksel gfx_fck_clksel[] = {
1352 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1356 static struct clk gfx_3d_fck = {
1357 .name = "gfx_3d_fck",
1358 .parent = &core_l3_ck,
1359 .prcm_mod = GFX_MOD,
1360 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1361 .clkdm = { .name = "gfx_clkdm" },
1362 .enable_reg = CM_FCLKEN,
1363 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1364 .clksel_reg = CM_CLKSEL,
1365 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1366 .clksel = gfx_fck_clksel,
1367 .recalc = &omap2_clksel_recalc,
1368 .round_rate = &omap2_clksel_round_rate,
1369 .set_rate = &omap2_clksel_set_rate
1372 static struct clk gfx_2d_fck = {
1373 .name = "gfx_2d_fck",
1374 .parent = &core_l3_ck,
1375 .prcm_mod = GFX_MOD,
1376 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1377 .clkdm = { .name = "gfx_clkdm" },
1378 .enable_reg = CM_FCLKEN,
1379 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1380 .clksel_reg = CM_CLKSEL,
1381 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1382 .clksel = gfx_fck_clksel,
1383 .recalc = &omap2_clksel_recalc,
1384 .round_rate = &omap2_clksel_round_rate,
1385 .set_rate = &omap2_clksel_set_rate
1388 static struct clk gfx_ick = {
1389 .name = "gfx_ick", /* From l3 */
1390 .parent = &core_l3_ck,
1391 .prcm_mod = GFX_MOD,
1392 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1393 .clkdm = { .name = "gfx_clkdm" },
1394 .enable_reg = CM_ICLKEN,
1395 .enable_bit = OMAP_EN_GFX_SHIFT,
1396 .recalc = &followparent_recalc,
1400 * Modem clock domain (2430)
1404 * These clocks are usable in chassis mode only.
1406 static const struct clksel_rate mdm_ick_core_rates[] = {
1407 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1408 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1409 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1410 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1414 static const struct clksel mdm_ick_clksel[] = {
1415 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1419 static struct clk mdm_ick = { /* used both as a ick and fck */
1422 .prcm_mod = OMAP2430_MDM_MOD,
1423 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1424 .clkdm = { .name = "mdm_clkdm" },
1425 .enable_reg = CM_ICLKEN,
1426 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1427 .clksel_reg = CM_CLKSEL,
1428 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1429 .clksel = mdm_ick_clksel,
1430 .recalc = &omap2_clksel_recalc,
1431 .round_rate = &omap2_clksel_round_rate,
1432 .set_rate = &omap2_clksel_set_rate
1435 static struct clk mdm_osc_ck = {
1436 .name = "mdm_osc_ck",
1438 .prcm_mod = OMAP2430_MDM_MOD,
1439 .flags = CLOCK_IN_OMAP243X,
1440 .clkdm = { .name = "mdm_clkdm" },
1441 .enable_reg = CM_FCLKEN,
1442 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1443 .recalc = &followparent_recalc,
1449 * DSS_L4_ICLK, DSS_L3_ICLK,
1450 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1452 * DSS is both initiator and target.
1454 /* XXX Add RATE_NOT_VALIDATED */
1456 static const struct clksel_rate dss1_fck_sys_rates[] = {
1457 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1461 static const struct clksel_rate dss1_fck_core_rates[] = {
1462 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1463 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1464 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1465 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1466 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1467 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1468 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1469 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1470 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1471 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1475 static const struct clksel dss1_fck_clksel[] = {
1476 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1477 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1481 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1483 .parent = &l4_ck, /* really both l3 and l4 */
1484 .prcm_mod = CORE_MOD,
1485 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1486 .clkdm = { .name = "dss_clkdm" },
1487 .enable_reg = CM_ICLKEN1,
1488 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1489 .recalc = &followparent_recalc,
1492 static struct clk dss1_fck = {
1494 .parent = &core_ck, /* Core or sys */
1495 .prcm_mod = CORE_MOD,
1496 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1498 .clkdm = { .name = "dss_clkdm" },
1499 .enable_reg = CM_FCLKEN1,
1500 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1501 .init = &omap2_init_clksel_parent,
1502 .clksel_reg = CM_CLKSEL1,
1503 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1504 .clksel = dss1_fck_clksel,
1505 .recalc = &omap2_clksel_recalc,
1506 .round_rate = &omap2_clksel_round_rate,
1507 .set_rate = &omap2_clksel_set_rate
1510 static const struct clksel_rate dss2_fck_sys_rates[] = {
1511 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1515 static const struct clksel_rate dss2_fck_48m_rates[] = {
1516 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1520 static const struct clksel dss2_fck_clksel[] = {
1521 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1522 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1526 static struct clk dss2_fck = { /* Alt clk used in power management */
1528 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1529 .prcm_mod = CORE_MOD,
1530 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1532 .clkdm = { .name = "dss_clkdm" },
1533 .enable_reg = CM_FCLKEN1,
1534 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1535 .init = &omap2_init_clksel_parent,
1536 .clksel_reg = CM_CLKSEL1,
1537 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1538 .clksel = dss2_fck_clksel,
1539 .recalc = &followparent_recalc,
1542 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1543 .name = "dss_54m_fck", /* 54m tv clk */
1544 .parent = &func_54m_ck,
1545 .prcm_mod = CORE_MOD,
1546 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1547 .clkdm = { .name = "dss_clkdm" },
1548 .enable_reg = CM_FCLKEN1,
1549 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1550 .recalc = &followparent_recalc,
1554 * CORE power domain ICLK & FCLK defines.
1555 * Many of the these can have more than one possible parent. Entries
1556 * here will likely have an L4 interface parent, and may have multiple
1557 * functional clock parents.
1559 static const struct clksel_rate gpt_alt_rates[] = {
1560 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1564 static const struct clksel omap24xx_gpt_clksel[] = {
1565 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1566 { .parent = &sys_ck, .rates = gpt_sys_rates },
1567 { .parent = &alt_ck, .rates = gpt_alt_rates },
1571 static struct clk gpt1_ick = {
1574 .prcm_mod = WKUP_MOD,
1575 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1576 .clkdm = { .name = "core_l4_clkdm" },
1577 .enable_reg = CM_ICLKEN,
1578 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1579 .idlest_bit = OMAP24XX_ST_GPT1_SHIFT,
1580 .recalc = &followparent_recalc,
1583 static struct clk gpt1_fck = {
1585 .parent = &func_32k_ck,
1586 .prcm_mod = WKUP_MOD,
1587 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1588 .clkdm = { .name = "core_l4_clkdm" },
1589 .enable_reg = CM_FCLKEN,
1590 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1591 .init = &omap2_init_clksel_parent,
1592 .clksel_reg = CM_CLKSEL1,
1593 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1594 .clksel = omap24xx_gpt_clksel,
1595 .recalc = &omap2_clksel_recalc,
1596 .round_rate = &omap2_clksel_round_rate,
1597 .set_rate = &omap2_clksel_set_rate
1600 static struct clk gpt2_ick = {
1603 .prcm_mod = CORE_MOD,
1604 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1605 .clkdm = { .name = "core_l4_clkdm" },
1606 .enable_reg = CM_ICLKEN1,
1607 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1608 .idlest_bit = OMAP24XX_ST_GPT2_SHIFT,
1609 .recalc = &followparent_recalc,
1612 static struct clk gpt2_fck = {
1614 .parent = &func_32k_ck,
1615 .prcm_mod = CORE_MOD,
1616 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1617 .clkdm = { .name = "core_l4_clkdm" },
1618 .enable_reg = CM_FCLKEN1,
1619 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1620 .init = &omap2_init_clksel_parent,
1621 .clksel_reg = CM_CLKSEL2,
1622 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1623 .clksel = omap24xx_gpt_clksel,
1624 .recalc = &omap2_clksel_recalc,
1627 static struct clk gpt3_ick = {
1630 .prcm_mod = CORE_MOD,
1631 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1632 .clkdm = { .name = "core_l4_clkdm" },
1633 .enable_reg = CM_ICLKEN1,
1634 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1635 .idlest_bit = OMAP24XX_ST_GPT3_SHIFT,
1636 .recalc = &followparent_recalc,
1639 static struct clk gpt3_fck = {
1641 .parent = &func_32k_ck,
1642 .prcm_mod = CORE_MOD,
1643 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1644 .clkdm = { .name = "core_l4_clkdm" },
1645 .enable_reg = CM_FCLKEN1,
1646 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1647 .init = &omap2_init_clksel_parent,
1648 .clksel_reg = CM_CLKSEL2,
1649 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1650 .clksel = omap24xx_gpt_clksel,
1651 .recalc = &omap2_clksel_recalc,
1654 static struct clk gpt4_ick = {
1657 .prcm_mod = CORE_MOD,
1658 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1659 .clkdm = { .name = "core_l4_clkdm" },
1660 .enable_reg = CM_ICLKEN1,
1661 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1662 .idlest_bit = OMAP24XX_ST_GPT4_SHIFT,
1663 .recalc = &followparent_recalc,
1666 static struct clk gpt4_fck = {
1668 .parent = &func_32k_ck,
1669 .prcm_mod = CORE_MOD,
1670 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1671 .clkdm = { .name = "core_l4_clkdm" },
1672 .enable_reg = CM_FCLKEN1,
1673 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1674 .init = &omap2_init_clksel_parent,
1675 .clksel_reg = CM_CLKSEL2,
1676 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1677 .clksel = omap24xx_gpt_clksel,
1678 .recalc = &omap2_clksel_recalc,
1681 static struct clk gpt5_ick = {
1684 .prcm_mod = CORE_MOD,
1685 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1686 .clkdm = { .name = "core_l4_clkdm" },
1687 .enable_reg = CM_ICLKEN1,
1688 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1689 .idlest_bit = OMAP24XX_ST_GPT5_SHIFT,
1690 .recalc = &followparent_recalc,
1693 static struct clk gpt5_fck = {
1695 .parent = &func_32k_ck,
1696 .prcm_mod = CORE_MOD,
1697 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1698 .clkdm = { .name = "core_l4_clkdm" },
1699 .enable_reg = CM_FCLKEN1,
1700 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1701 .init = &omap2_init_clksel_parent,
1702 .clksel_reg = CM_CLKSEL2,
1703 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1704 .clksel = omap24xx_gpt_clksel,
1705 .recalc = &omap2_clksel_recalc,
1708 static struct clk gpt6_ick = {
1711 .prcm_mod = CORE_MOD,
1712 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1713 .clkdm = { .name = "core_l4_clkdm" },
1714 .enable_reg = CM_ICLKEN1,
1715 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1716 .idlest_bit = OMAP24XX_ST_GPT6_SHIFT,
1717 .recalc = &followparent_recalc,
1720 static struct clk gpt6_fck = {
1722 .parent = &func_32k_ck,
1723 .prcm_mod = CORE_MOD,
1724 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1725 .clkdm = { .name = "core_l4_clkdm" },
1726 .enable_reg = CM_FCLKEN1,
1727 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1728 .init = &omap2_init_clksel_parent,
1729 .clksel_reg = CM_CLKSEL2,
1730 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1731 .clksel = omap24xx_gpt_clksel,
1732 .recalc = &omap2_clksel_recalc,
1735 static struct clk gpt7_ick = {
1738 .prcm_mod = CORE_MOD,
1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1740 .clkdm = { .name = "core_l4_clkdm" },
1741 .enable_reg = CM_ICLKEN1,
1742 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1743 .idlest_bit = OMAP24XX_ST_GPT7_SHIFT,
1744 .recalc = &followparent_recalc,
1747 static struct clk gpt7_fck = {
1749 .parent = &func_32k_ck,
1750 .prcm_mod = CORE_MOD,
1751 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1752 .clkdm = { .name = "core_l4_clkdm" },
1753 .enable_reg = CM_FCLKEN1,
1754 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1755 .init = &omap2_init_clksel_parent,
1756 .clksel_reg = CM_CLKSEL2,
1757 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1758 .clksel = omap24xx_gpt_clksel,
1759 .recalc = &omap2_clksel_recalc,
1762 static struct clk gpt8_ick = {
1765 .prcm_mod = CORE_MOD,
1766 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1767 .clkdm = { .name = "core_l4_clkdm" },
1768 .enable_reg = CM_ICLKEN1,
1769 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1770 .idlest_bit = OMAP24XX_ST_GPT8_SHIFT,
1771 .recalc = &followparent_recalc,
1774 static struct clk gpt8_fck = {
1776 .parent = &func_32k_ck,
1777 .prcm_mod = CORE_MOD,
1778 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1779 .clkdm = { .name = "core_l4_clkdm" },
1780 .enable_reg = CM_FCLKEN1,
1781 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1782 .init = &omap2_init_clksel_parent,
1783 .clksel_reg = CM_CLKSEL2,
1784 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1785 .clksel = omap24xx_gpt_clksel,
1786 .recalc = &omap2_clksel_recalc,
1789 static struct clk gpt9_ick = {
1792 .prcm_mod = CORE_MOD,
1793 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1794 .clkdm = { .name = "core_l4_clkdm" },
1795 .enable_reg = CM_ICLKEN1,
1796 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1797 .idlest_bit = OMAP24XX_ST_GPT9_SHIFT,
1798 .recalc = &followparent_recalc,
1801 static struct clk gpt9_fck = {
1803 .parent = &func_32k_ck,
1804 .prcm_mod = CORE_MOD,
1805 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1806 .clkdm = { .name = "core_l4_clkdm" },
1807 .enable_reg = CM_FCLKEN1,
1808 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1809 .init = &omap2_init_clksel_parent,
1810 .clksel_reg = CM_CLKSEL2,
1811 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1812 .clksel = omap24xx_gpt_clksel,
1813 .recalc = &omap2_clksel_recalc,
1816 static struct clk gpt10_ick = {
1817 .name = "gpt10_ick",
1819 .prcm_mod = CORE_MOD,
1820 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1821 .clkdm = { .name = "core_l4_clkdm" },
1822 .enable_reg = CM_ICLKEN1,
1823 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1824 .idlest_bit = OMAP24XX_ST_GPT10_SHIFT,
1825 .recalc = &followparent_recalc,
1828 static struct clk gpt10_fck = {
1829 .name = "gpt10_fck",
1830 .parent = &func_32k_ck,
1831 .prcm_mod = CORE_MOD,
1832 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1833 .clkdm = { .name = "core_l4_clkdm" },
1834 .enable_reg = CM_FCLKEN1,
1835 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1836 .init = &omap2_init_clksel_parent,
1837 .clksel_reg = CM_CLKSEL2,
1838 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1839 .clksel = omap24xx_gpt_clksel,
1840 .recalc = &omap2_clksel_recalc,
1843 static struct clk gpt11_ick = {
1844 .name = "gpt11_ick",
1846 .prcm_mod = CORE_MOD,
1847 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1848 .clkdm = { .name = "core_l4_clkdm" },
1849 .enable_reg = CM_ICLKEN1,
1850 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1851 .idlest_bit = OMAP24XX_ST_GPT11_SHIFT,
1852 .recalc = &followparent_recalc,
1855 static struct clk gpt11_fck = {
1856 .name = "gpt11_fck",
1857 .parent = &func_32k_ck,
1858 .prcm_mod = CORE_MOD,
1859 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1860 .clkdm = { .name = "core_l4_clkdm" },
1861 .enable_reg = CM_FCLKEN1,
1862 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1863 .init = &omap2_init_clksel_parent,
1864 .clksel_reg = CM_CLKSEL2,
1865 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1866 .clksel = omap24xx_gpt_clksel,
1867 .recalc = &omap2_clksel_recalc,
1870 static struct clk gpt12_ick = {
1871 .name = "gpt12_ick",
1873 .prcm_mod = CORE_MOD,
1874 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1875 .clkdm = { .name = "core_l4_clkdm" },
1876 .enable_reg = CM_ICLKEN1,
1877 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1878 .idlest_bit = OMAP24XX_ST_GPT12_SHIFT,
1879 .recalc = &followparent_recalc,
1882 static struct clk gpt12_fck = {
1883 .name = "gpt12_fck",
1884 .parent = &func_32k_ck,
1885 .prcm_mod = CORE_MOD,
1886 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1887 .clkdm = { .name = "core_l4_clkdm" },
1888 .enable_reg = CM_FCLKEN1,
1889 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1890 .init = &omap2_init_clksel_parent,
1891 .clksel_reg = CM_CLKSEL2,
1892 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1893 .clksel = omap24xx_gpt_clksel,
1894 .recalc = &omap2_clksel_recalc,
1897 static struct clk mcbsp1_ick = {
1898 .name = "mcbsp_ick",
1901 .prcm_mod = CORE_MOD,
1902 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1903 .clkdm = { .name = "core_l4_clkdm" },
1904 .enable_reg = CM_ICLKEN1,
1905 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1906 .idlest_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1907 .recalc = &followparent_recalc,
1910 static struct clk mcbsp1_fck = {
1911 .name = "mcbsp_fck",
1913 .parent = &func_96m_ck,
1914 .prcm_mod = CORE_MOD,
1915 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1916 .clkdm = { .name = "core_l4_clkdm" },
1917 .enable_reg = CM_FCLKEN1,
1918 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1919 .recalc = &followparent_recalc,
1922 static struct clk mcbsp2_ick = {
1923 .name = "mcbsp_ick",
1926 .prcm_mod = CORE_MOD,
1927 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1928 .clkdm = { .name = "core_l4_clkdm" },
1929 .enable_reg = CM_ICLKEN1,
1930 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1931 .idlest_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1932 .recalc = &followparent_recalc,
1935 static struct clk mcbsp2_fck = {
1936 .name = "mcbsp_fck",
1938 .parent = &func_96m_ck,
1939 .prcm_mod = CORE_MOD,
1940 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1941 .clkdm = { .name = "core_l4_clkdm" },
1942 .enable_reg = CM_FCLKEN1,
1943 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1944 .recalc = &followparent_recalc,
1947 static struct clk mcbsp3_ick = {
1948 .name = "mcbsp_ick",
1951 .prcm_mod = CORE_MOD,
1952 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
1953 .clkdm = { .name = "core_l4_clkdm" },
1954 .enable_reg = CM_ICLKEN2,
1955 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1956 .idlest_bit = OMAP2430_ST_MCBSP3_SHIFT,
1957 .recalc = &followparent_recalc,
1960 static struct clk mcbsp3_fck = {
1961 .name = "mcbsp_fck",
1963 .parent = &func_96m_ck,
1964 .prcm_mod = CORE_MOD,
1965 .flags = CLOCK_IN_OMAP243X,
1966 .clkdm = { .name = "core_l4_clkdm" },
1967 .enable_reg = OMAP24XX_CM_FCLKEN2,
1968 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1969 .recalc = &followparent_recalc,
1972 static struct clk mcbsp4_ick = {
1973 .name = "mcbsp_ick",
1976 .prcm_mod = CORE_MOD,
1977 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
1978 .clkdm = { .name = "core_l4_clkdm" },
1979 .enable_reg = CM_ICLKEN2,
1980 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1981 .idlest_bit = OMAP2430_ST_MCBSP4_SHIFT,
1982 .recalc = &followparent_recalc,
1985 static struct clk mcbsp4_fck = {
1986 .name = "mcbsp_fck",
1988 .parent = &func_96m_ck,
1989 .prcm_mod = CORE_MOD,
1990 .flags = CLOCK_IN_OMAP243X,
1991 .clkdm = { .name = "core_l4_clkdm" },
1992 .enable_reg = OMAP24XX_CM_FCLKEN2,
1993 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1994 .recalc = &followparent_recalc,
1997 static struct clk mcbsp5_ick = {
1998 .name = "mcbsp_ick",
2001 .prcm_mod = CORE_MOD,
2002 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
2003 .clkdm = { .name = "core_l4_clkdm" },
2004 .enable_reg = CM_ICLKEN2,
2005 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
2006 .idlest_bit = OMAP2430_ST_MCBSP5_SHIFT,
2007 .recalc = &followparent_recalc,
2010 static struct clk mcbsp5_fck = {
2011 .name = "mcbsp_fck",
2013 .parent = &func_96m_ck,
2014 .prcm_mod = CORE_MOD,
2015 .flags = CLOCK_IN_OMAP243X,
2016 .clkdm = { .name = "core_l4_clkdm" },
2017 .enable_reg = OMAP24XX_CM_FCLKEN2,
2018 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
2019 .recalc = &followparent_recalc,
2022 static struct clk mcspi1_ick = {
2023 .name = "mcspi_ick",
2026 .prcm_mod = CORE_MOD,
2027 .clkdm = { .name = "core_l4_clkdm" },
2028 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2029 .enable_reg = CM_ICLKEN1,
2030 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2031 .idlest_bit = OMAP24XX_ST_MCSPI1_SHIFT,
2032 .recalc = &followparent_recalc,
2035 static struct clk mcspi1_fck = {
2036 .name = "mcspi_fck",
2038 .parent = &func_48m_ck,
2039 .prcm_mod = CORE_MOD,
2040 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2041 .clkdm = { .name = "core_l4_clkdm" },
2042 .enable_reg = CM_FCLKEN1,
2043 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2044 .recalc = &followparent_recalc,
2047 static struct clk mcspi2_ick = {
2048 .name = "mcspi_ick",
2051 .prcm_mod = CORE_MOD,
2052 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2053 .clkdm = { .name = "core_l4_clkdm" },
2054 .enable_reg = CM_ICLKEN1,
2055 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2056 .idlest_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2057 .recalc = &followparent_recalc,
2060 static struct clk mcspi2_fck = {
2061 .name = "mcspi_fck",
2063 .parent = &func_48m_ck,
2064 .prcm_mod = CORE_MOD,
2065 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2066 .clkdm = { .name = "core_l4_clkdm" },
2067 .enable_reg = CM_FCLKEN1,
2068 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2069 .recalc = &followparent_recalc,
2072 static struct clk mcspi3_ick = {
2073 .name = "mcspi_ick",
2076 .prcm_mod = CORE_MOD,
2077 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
2078 .clkdm = { .name = "core_l4_clkdm" },
2079 .enable_reg = CM_ICLKEN2,
2080 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
2081 .idlest_bit = OMAP2430_ST_MCSPI3_SHIFT,
2082 .recalc = &followparent_recalc,
2085 static struct clk mcspi3_fck = {
2086 .name = "mcspi_fck",
2088 .parent = &func_48m_ck,
2089 .prcm_mod = CORE_MOD,
2090 .flags = CLOCK_IN_OMAP243X,
2091 .clkdm = { .name = "core_l4_clkdm" },
2092 .enable_reg = OMAP24XX_CM_FCLKEN2,
2093 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
2094 .recalc = &followparent_recalc,
2097 static struct clk uart1_ick = {
2098 .name = "uart1_ick",
2100 .prcm_mod = CORE_MOD,
2101 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2102 .clkdm = { .name = "core_l4_clkdm" },
2103 .enable_reg = CM_ICLKEN1,
2104 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2105 .idlest_bit = OMAP24XX_ST_UART1_SHIFT,
2106 .recalc = &followparent_recalc,
2109 static struct clk uart1_fck = {
2110 .name = "uart1_fck",
2111 .parent = &func_48m_ck,
2112 .prcm_mod = CORE_MOD,
2113 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2114 .clkdm = { .name = "core_l4_clkdm" },
2115 .enable_reg = CM_FCLKEN1,
2116 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2117 .recalc = &followparent_recalc,
2120 static struct clk uart2_ick = {
2121 .name = "uart2_ick",
2123 .prcm_mod = CORE_MOD,
2124 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2125 .clkdm = { .name = "core_l4_clkdm" },
2126 .enable_reg = CM_ICLKEN1,
2127 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2128 .idlest_bit = OMAP24XX_ST_UART2_SHIFT,
2129 .recalc = &followparent_recalc,
2132 static struct clk uart2_fck = {
2133 .name = "uart2_fck",
2134 .parent = &func_48m_ck,
2135 .prcm_mod = CORE_MOD,
2136 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2137 .clkdm = { .name = "core_l4_clkdm" },
2138 .enable_reg = CM_FCLKEN1,
2139 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2140 .recalc = &followparent_recalc,
2143 static struct clk uart3_ick = {
2144 .name = "uart3_ick",
2146 .prcm_mod = CORE_MOD,
2147 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2148 .clkdm = { .name = "core_l4_clkdm" },
2149 .enable_reg = CM_ICLKEN2,
2150 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2151 .idlest_bit = OMAP24XX_ST_UART3_SHIFT,
2152 .recalc = &followparent_recalc,
2155 static struct clk uart3_fck = {
2156 .name = "uart3_fck",
2157 .parent = &func_48m_ck,
2158 .prcm_mod = CORE_MOD,
2159 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2160 .clkdm = { .name = "core_l4_clkdm" },
2161 .enable_reg = OMAP24XX_CM_FCLKEN2,
2162 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2163 .recalc = &followparent_recalc,
2166 static struct clk gpios_ick = {
2167 .name = "gpios_ick",
2169 .prcm_mod = WKUP_MOD,
2170 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2171 .clkdm = { .name = "core_l4_clkdm" },
2172 .enable_reg = CM_ICLKEN,
2173 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2174 .idlest_bit = OMAP24XX_ST_GPIOS_SHIFT,
2175 .recalc = &followparent_recalc,
2178 static struct clk gpios_fck = {
2179 .name = "gpios_fck",
2180 .parent = &func_32k_ck,
2181 .prcm_mod = WKUP_MOD,
2182 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2183 .clkdm = { .name = "prm_clkdm" },
2184 .enable_reg = CM_FCLKEN,
2185 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2186 .idlest_bit = OMAP24XX_ST_GPIOS_SHIFT,
2187 .recalc = &followparent_recalc,
2190 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2191 static struct clk mpu_wdt_ick = {
2192 .name = "mpu_wdt_ick",
2194 .prcm_mod = WKUP_MOD,
2195 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2196 .clkdm = { .name = "prm_clkdm" },
2197 .enable_reg = CM_ICLKEN,
2198 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2199 .idlest_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
2200 .recalc = &followparent_recalc,
2204 static struct clk mpu_wdt_fck = {
2205 .name = "mpu_wdt_fck",
2206 .parent = &func_32k_ck,
2207 .prcm_mod = WKUP_MOD,
2208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2209 .clkdm = { .name = "prm_clkdm" },
2210 .enable_reg = CM_FCLKEN,
2211 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2212 .idlest_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
2213 .recalc = &followparent_recalc,
2216 static struct clk sync_32k_ick = {
2217 .name = "sync_32k_ick",
2219 .prcm_mod = WKUP_MOD,
2220 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2221 ENABLE_ON_INIT | WAIT_READY,
2222 .clkdm = { .name = "core_l4_clkdm" },
2223 .enable_reg = CM_ICLKEN,
2224 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2225 .idlest_bit = OMAP24XX_ST_32KSYNC_SHIFT,
2226 .recalc = &followparent_recalc,
2229 /* REVISIT: parent is really wu_l4_iclk */
2230 static struct clk wdt1_ick = {
2233 .prcm_mod = WKUP_MOD,
2234 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2235 .clkdm = { .name = "prm_clkdm" },
2236 .enable_reg = CM_ICLKEN,
2237 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2238 .idlest_bit = OMAP24XX_ST_WDT1_SHIFT,
2239 .recalc = &followparent_recalc,
2242 static struct clk omapctrl_ick = {
2243 .name = "omapctrl_ick",
2245 .prcm_mod = WKUP_MOD,
2246 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2248 .clkdm = { .name = "core_l4_clkdm" },
2249 .enable_reg = CM_ICLKEN,
2250 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2251 .idlest_bit = OMAP24XX_ST_OMAPCTRL_SHIFT,
2252 .recalc = &followparent_recalc,
2255 static struct clk icr_ick = {
2258 .prcm_mod = WKUP_MOD,
2259 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
2260 .clkdm = { .name = "core_l4_clkdm" },
2261 .enable_reg = CM_ICLKEN,
2262 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2263 .idlest_bit = OMAP2430_ST_ICR_SHIFT,
2264 .recalc = &followparent_recalc,
2267 static struct clk cam_ick = {
2270 .prcm_mod = CORE_MOD,
2271 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2272 .clkdm = { .name = "core_l4_clkdm" },
2273 .enable_reg = CM_ICLKEN1,
2274 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2275 .recalc = &followparent_recalc,
2279 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2280 * split into two separate clocks, since the parent clocks are different
2281 * and the clockdomains are also different.
2283 static struct clk cam_fck = {
2285 .parent = &func_96m_ck,
2286 .prcm_mod = CORE_MOD,
2287 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2288 .clkdm = { .name = "core_l3_clkdm" },
2289 .enable_reg = CM_FCLKEN1,
2290 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2291 .recalc = &followparent_recalc,
2294 static struct clk mailboxes_ick = {
2295 .name = "mailboxes_ick",
2297 .prcm_mod = CORE_MOD,
2298 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2299 .clkdm = { .name = "core_l4_clkdm" },
2300 .enable_reg = CM_ICLKEN1,
2301 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2302 .idlest_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
2303 .recalc = &followparent_recalc,
2306 static struct clk wdt4_ick = {
2309 .prcm_mod = CORE_MOD,
2310 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2311 .clkdm = { .name = "core_l4_clkdm" },
2312 .enable_reg = CM_ICLKEN1,
2313 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2314 .idlest_bit = OMAP24XX_ST_WDT4_SHIFT,
2315 .recalc = &followparent_recalc,
2318 static struct clk wdt4_fck = {
2320 .parent = &func_32k_ck,
2321 .prcm_mod = CORE_MOD,
2322 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2323 .clkdm = { .name = "core_l4_clkdm" },
2324 .enable_reg = CM_FCLKEN1,
2325 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2326 .recalc = &followparent_recalc,
2329 static struct clk wdt3_ick = {
2332 .prcm_mod = CORE_MOD,
2333 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2334 .clkdm = { .name = "core_l4_clkdm" },
2335 .enable_reg = CM_ICLKEN1,
2336 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2337 .idlest_bit = OMAP2420_ST_WDT3_SHIFT,
2338 .recalc = &followparent_recalc,
2341 static struct clk wdt3_fck = {
2343 .parent = &func_32k_ck,
2344 .prcm_mod = CORE_MOD,
2345 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2346 .clkdm = { .name = "core_l4_clkdm" },
2347 .enable_reg = CM_FCLKEN1,
2348 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2349 .enable_bit = OMAP2420_ST_WDT3_SHIFT,
2350 .recalc = &followparent_recalc,
2353 static struct clk mspro_ick = {
2354 .name = "mspro_ick",
2356 .prcm_mod = CORE_MOD,
2357 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2358 .clkdm = { .name = "core_l4_clkdm" },
2359 .enable_reg = CM_ICLKEN1,
2360 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2361 .idlest_bit = OMAP24XX_ST_MSPRO_SHIFT,
2362 .recalc = &followparent_recalc,
2365 static struct clk mspro_fck = {
2366 .name = "mspro_fck",
2367 .parent = &func_96m_ck,
2368 .prcm_mod = CORE_MOD,
2369 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2370 .clkdm = { .name = "core_l4_clkdm" },
2371 .enable_reg = CM_FCLKEN1,
2372 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2373 .idlest_bit = OMAP24XX_ST_MSPRO_SHIFT,
2374 .recalc = &followparent_recalc,
2377 static struct clk mmc_ick = {
2380 .prcm_mod = CORE_MOD,
2381 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2382 .clkdm = { .name = "core_l4_clkdm" },
2383 .enable_reg = CM_ICLKEN1,
2384 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2385 .idlest_bit = OMAP2420_ST_MMC_SHIFT,
2386 .recalc = &followparent_recalc,
2389 static struct clk mmc_fck = {
2391 .parent = &func_96m_ck,
2392 .prcm_mod = CORE_MOD,
2393 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2394 .clkdm = { .name = "core_l4_clkdm" },
2395 .enable_reg = CM_FCLKEN1,
2396 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2397 .idlest_bit = OMAP2420_ST_MMC_SHIFT,
2398 .recalc = &followparent_recalc,
2401 static struct clk fac_ick = {
2404 .prcm_mod = CORE_MOD,
2405 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2406 .clkdm = { .name = "core_l4_clkdm" },
2407 .enable_reg = CM_ICLKEN1,
2408 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2409 .idlest_bit = OMAP24XX_ST_FAC_SHIFT,
2410 .recalc = &followparent_recalc,
2413 static struct clk fac_fck = {
2415 .parent = &func_12m_ck,
2416 .prcm_mod = CORE_MOD,
2417 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2418 .clkdm = { .name = "core_l4_clkdm" },
2419 .enable_reg = CM_FCLKEN1,
2420 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2421 .idlest_bit = OMAP24XX_ST_FAC_SHIFT,
2422 .recalc = &followparent_recalc,
2425 static struct clk eac_ick = {
2428 .prcm_mod = CORE_MOD,
2429 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2430 .clkdm = { .name = "core_l4_clkdm" },
2431 .enable_reg = CM_ICLKEN1,
2432 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2433 .idlest_bit = OMAP2420_ST_EAC_SHIFT,
2434 .recalc = &followparent_recalc,
2437 static struct clk eac_fck = {
2439 .parent = &func_96m_ck,
2440 .prcm_mod = CORE_MOD,
2441 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2442 .clkdm = { .name = "core_l4_clkdm" },
2443 .enable_reg = CM_FCLKEN1,
2444 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2445 .idlest_bit = OMAP2420_ST_EAC_SHIFT,
2446 .recalc = &followparent_recalc,
2449 static struct clk hdq_ick = {
2452 .prcm_mod = CORE_MOD,
2453 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2454 .clkdm = { .name = "core_l4_clkdm" },
2455 .enable_reg = CM_ICLKEN1,
2456 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2457 .idlest_bit = OMAP24XX_ST_HDQ_SHIFT,
2458 .recalc = &followparent_recalc,
2461 static struct clk hdq_fck = {
2463 .parent = &func_12m_ck,
2464 .prcm_mod = CORE_MOD,
2465 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2466 .clkdm = { .name = "core_l4_clkdm" },
2467 .enable_reg = CM_FCLKEN1,
2468 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2469 .idlest_bit = OMAP24XX_ST_HDQ_SHIFT,
2470 .recalc = &followparent_recalc,
2473 static struct clk i2c2_ick = {
2477 .prcm_mod = CORE_MOD,
2478 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2479 .clkdm = { .name = "core_l4_clkdm" },
2480 .enable_reg = CM_ICLKEN1,
2481 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2482 .idlest_bit = OMAP2420_ST_I2C2_SHIFT,
2483 .recalc = &followparent_recalc,
2486 static struct clk i2c2_fck = {
2489 .parent = &func_12m_ck,
2490 .prcm_mod = CORE_MOD,
2491 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2492 .clkdm = { .name = "core_l4_clkdm" },
2493 .enable_reg = CM_FCLKEN1,
2494 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2495 .idlest_bit = OMAP2420_ST_I2C2_SHIFT,
2496 .recalc = &followparent_recalc,
2499 static struct clk i2chs2_fck = {
2502 .parent = &func_96m_ck,
2503 .prcm_mod = CORE_MOD,
2504 .flags = CLOCK_IN_OMAP243X,
2505 .clkdm = { .name = "core_l4_clkdm" },
2506 .enable_reg = OMAP24XX_CM_FCLKEN2,
2507 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2508 .recalc = &followparent_recalc,
2511 static struct clk i2c1_ick = {
2515 .prcm_mod = CORE_MOD,
2516 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2517 .clkdm = { .name = "core_l4_clkdm" },
2518 .enable_reg = CM_ICLKEN1,
2519 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2520 .idlest_bit = OMAP2420_ST_I2C1_SHIFT,
2521 .recalc = &followparent_recalc,
2524 static struct clk i2c1_fck = {
2527 .parent = &func_12m_ck,
2528 .prcm_mod = CORE_MOD,
2529 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2530 .clkdm = { .name = "core_l4_clkdm" },
2531 .enable_reg = CM_FCLKEN1,
2532 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2533 .idlest_bit = OMAP2420_ST_I2C1_SHIFT,
2534 .recalc = &followparent_recalc,
2537 static struct clk i2chs1_fck = {
2540 .parent = &func_96m_ck,
2541 .prcm_mod = CORE_MOD,
2542 .flags = CLOCK_IN_OMAP243X,
2543 .clkdm = { .name = "core_l4_clkdm" },
2544 .enable_reg = OMAP24XX_CM_FCLKEN2,
2545 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2546 .recalc = &followparent_recalc,
2549 static struct clk gpmc_fck = {
2551 .parent = &core_l3_ck,
2552 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2554 .clkdm = { .name = "core_l3_clkdm" },
2555 .recalc = &followparent_recalc,
2558 static struct clk sdma_fck = {
2560 .parent = &core_l3_ck,
2561 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2562 .clkdm = { .name = "core_l3_clkdm" },
2563 .recalc = &followparent_recalc,
2566 static struct clk sdma_ick = {
2569 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2570 .clkdm = { .name = "core_l3_clkdm" },
2571 .recalc = &followparent_recalc,
2574 static struct clk vlynq_ick = {
2575 .name = "vlynq_ick",
2576 .parent = &core_l3_ck,
2577 .prcm_mod = CORE_MOD,
2578 .flags = CLOCK_IN_OMAP242X | WAIT_READY,
2579 .clkdm = { .name = "core_l3_clkdm" },
2580 .enable_reg = CM_ICLKEN1,
2581 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2582 .idlest_bit = OMAP2420_ST_VLYNQ_SHIFT,
2583 .recalc = &followparent_recalc,
2586 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2587 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2591 static const struct clksel_rate vlynq_fck_core_rates[] = {
2592 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2593 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2594 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2595 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2596 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2597 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2598 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2599 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2600 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2601 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2605 static const struct clksel vlynq_fck_clksel[] = {
2606 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2607 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2611 static struct clk vlynq_fck = {
2612 .name = "vlynq_fck",
2613 .parent = &func_96m_ck,
2614 .prcm_mod = CORE_MOD,
2615 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | WAIT_READY,
2616 .clkdm = { .name = "core_l3_clkdm" },
2617 .enable_reg = CM_FCLKEN1,
2618 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2619 .idlest_bit = OMAP2420_ST_VLYNQ_SHIFT,
2620 .init = &omap2_init_clksel_parent,
2621 .clksel_reg = CM_CLKSEL1,
2622 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2623 .clksel = vlynq_fck_clksel,
2624 .recalc = &omap2_clksel_recalc,
2625 .round_rate = &omap2_clksel_round_rate,
2626 .set_rate = &omap2_clksel_set_rate
2629 static struct clk sdrc_ick = {
2632 .prcm_mod = CORE_MOD,
2633 .flags = CLOCK_IN_OMAP243X | WAIT_READY | ENABLE_ON_INIT,
2634 .clkdm = { .name = "core_l4_clkdm" },
2635 .enable_reg = CM_ICLKEN3,
2636 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2637 .idlest_bit = OMAP2430_ST_SDRC_SHIFT,
2638 .recalc = &followparent_recalc,
2641 static struct clk des_ick = {
2644 .prcm_mod = CORE_MOD,
2645 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2646 .clkdm = { .name = "core_l4_clkdm" },
2647 .enable_reg = OMAP24XX_CM_ICLKEN4,
2648 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2649 .idlest_bit = OMAP24XX_ST_DES_SHIFT,
2650 .recalc = &followparent_recalc,
2653 static struct clk sha_ick = {
2656 .prcm_mod = CORE_MOD,
2657 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2658 .clkdm = { .name = "core_l4_clkdm" },
2659 .enable_reg = OMAP24XX_CM_ICLKEN4,
2660 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2661 .idlest_bit = OMAP24XX_ST_SHA_SHIFT,
2662 .recalc = &followparent_recalc,
2665 static struct clk rng_ick = {
2668 .prcm_mod = CORE_MOD,
2669 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2670 .clkdm = { .name = "core_l4_clkdm" },
2671 .enable_reg = OMAP24XX_CM_ICLKEN4,
2672 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2673 .idlest_bit = OMAP24XX_ST_RNG_SHIFT,
2674 .recalc = &followparent_recalc,
2677 static struct clk aes_ick = {
2680 .prcm_mod = CORE_MOD,
2681 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2682 .clkdm = { .name = "core_l4_clkdm" },
2683 .enable_reg = OMAP24XX_CM_ICLKEN4,
2684 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2685 .idlest_bit = OMAP24XX_ST_AES_SHIFT,
2686 .recalc = &followparent_recalc,
2689 static struct clk pka_ick = {
2692 .prcm_mod = CORE_MOD,
2693 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2694 .clkdm = { .name = "core_l4_clkdm" },
2695 .enable_reg = OMAP24XX_CM_ICLKEN4,
2696 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2697 .idlest_bit = OMAP24XX_ST_PKA_SHIFT,
2698 .recalc = &followparent_recalc,
2701 static struct clk usb_fck = {
2703 .parent = &func_48m_ck,
2704 .prcm_mod = CORE_MOD,
2705 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2706 .clkdm = { .name = "core_l3_clkdm" },
2707 .enable_reg = OMAP24XX_CM_FCLKEN2,
2708 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2709 .idlest_bit = OMAP24XX_ST_USB_SHIFT,
2710 .recalc = &followparent_recalc,
2713 static struct clk usbhs_ick = {
2714 .name = "usbhs_ick",
2715 .parent = &core_l3_ck,
2716 .prcm_mod = CORE_MOD,
2717 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
2718 .clkdm = { .name = "core_l3_clkdm" },
2719 .enable_reg = CM_ICLKEN2,
2720 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2721 .idlest_bit = OMAP2430_ST_USBHS_SHIFT,
2722 .recalc = &followparent_recalc,
2725 static struct clk mmchs1_ick = {
2726 .name = "mmchs_ick",
2728 .prcm_mod = CORE_MOD,
2729 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
2730 .clkdm = { .name = "core_l4_clkdm" },
2731 .enable_reg = CM_ICLKEN2,
2732 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2733 .idlest_bit = OMAP2430_ST_MMCHS1_SHIFT,
2734 .recalc = &followparent_recalc,
2737 static struct clk mmchs1_fck = {
2738 .name = "mmchs_fck",
2739 .parent = &func_96m_ck,
2740 .prcm_mod = CORE_MOD,
2741 .flags = CLOCK_IN_OMAP243X,
2742 .clkdm = { .name = "core_l3_clkdm" },
2743 .enable_reg = OMAP24XX_CM_FCLKEN2,
2744 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2745 .recalc = &followparent_recalc,
2748 static struct clk mmchs2_ick = {
2749 .name = "mmchs_ick",
2752 .prcm_mod = CORE_MOD,
2753 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
2754 .clkdm = { .name = "core_l4_clkdm" },
2755 .enable_reg = CM_ICLKEN2,
2756 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2757 .idlest_bit = OMAP2430_ST_MMCHS2_SHIFT,
2758 .recalc = &followparent_recalc,
2761 static struct clk mmchs2_fck = {
2762 .name = "mmchs_fck",
2764 .parent = &func_96m_ck,
2765 .prcm_mod = CORE_MOD,
2766 .flags = CLOCK_IN_OMAP243X,
2767 .clkdm = { .name = "core_l4_clkdm" },
2768 .enable_reg = OMAP24XX_CM_FCLKEN2,
2769 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2770 .recalc = &followparent_recalc,
2773 static struct clk gpio5_ick = {
2774 .name = "gpio5_ick",
2776 .prcm_mod = CORE_MOD,
2777 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
2778 .clkdm = { .name = "core_l4_clkdm" },
2779 .enable_reg = CM_ICLKEN2,
2780 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2781 .idlest_bit = OMAP2430_ST_GPIO5_SHIFT,
2782 .recalc = &followparent_recalc,
2785 static struct clk gpio5_fck = {
2786 .name = "gpio5_fck",
2787 .parent = &func_32k_ck,
2788 .prcm_mod = CORE_MOD,
2789 .flags = CLOCK_IN_OMAP243X,
2790 .clkdm = { .name = "core_l4_clkdm" },
2791 .enable_reg = OMAP24XX_CM_FCLKEN2,
2792 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2793 .recalc = &followparent_recalc,
2796 static struct clk mdm_intc_ick = {
2797 .name = "mdm_intc_ick",
2799 .prcm_mod = CORE_MOD,
2800 .flags = CLOCK_IN_OMAP243X | WAIT_READY,
2801 .clkdm = { .name = "core_l4_clkdm" },
2802 .enable_reg = CM_ICLKEN2,
2803 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2804 .idlest_bit = OMAP2430_ST_MDM_INTC_SHIFT,
2805 .recalc = &followparent_recalc,
2808 static struct clk mmchsdb1_fck = {
2809 .name = "mmchsdb_fck",
2810 .parent = &func_32k_ck,
2811 .prcm_mod = CORE_MOD,
2812 .flags = CLOCK_IN_OMAP243X,
2813 .clkdm = { .name = "core_l4_clkdm" },
2814 .enable_reg = OMAP24XX_CM_FCLKEN2,
2815 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2816 .recalc = &followparent_recalc,
2819 static struct clk mmchsdb2_fck = {
2820 .name = "mmchsdb_fck",
2822 .parent = &func_32k_ck,
2823 .prcm_mod = CORE_MOD,
2824 .flags = CLOCK_IN_OMAP243X,
2825 .clkdm = { .name = "core_l4_clkdm" },
2826 .enable_reg = OMAP24XX_CM_FCLKEN2,
2827 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2828 .recalc = &followparent_recalc,
2832 * This clock is a composite clock which does entire set changes then
2833 * forces a rebalance. It keys on the MPU speed, but it really could
2834 * be any key speed part of a set in the rate table.
2836 * to really change a set, you need memory table sets which get changed
2837 * in sram, pre-notifiers & post notifiers, changing the top set, without
2838 * having low level display recalc's won't work... this is why dpm notifiers
2839 * work, isr's off, walk a list of clocks already _off_ and not messing with
2842 * This clock should have no parent. It embodies the entire upper level
2843 * active set. A parent will mess up some of the init also.
2845 static struct clk virt_prcm_set = {
2846 .name = "virt_prcm_set",
2847 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2848 ALWAYS_ENABLED | DELAYED_APP,
2849 .clkdm = { .name = "virt_opp_clkdm" },
2850 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2851 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2852 .set_rate = &omap2_select_table_rate,
2853 .round_rate = &omap2_round_to_table_rate,
2856 static struct clk *onchip_24xx_clks[] __initdata = {
2857 /* external root sources */
2862 /* internal analog sources */
2866 /* internal prcm root sources */
2878 /* mpu domain clocks */
2880 /* dsp domain clocks */
2883 &dsp_ick, /* 242x */
2884 &iva2_1_ick, /* 243x */
2885 &iva1_ifck, /* 242x */
2886 &iva1_mpu_int_ifck, /* 242x */
2887 /* GFX domain clocks */
2891 /* Modem domain clocks */
2894 /* DSS domain clocks */
2899 /* L3 domain clocks */
2903 /* L4 domain clocks */
2904 &l4_ck, /* used as both core_l4 and wu_l4 */
2906 /* virtual meta-group clock */
2908 /* general l4 interface ck, multi-parent functional clk */