arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*
 604  * Since 2420 and 2430 have different cm_base, we use offsets only here.
 605  * Clock code will rewrite the register address as needed.
 606  */
 607 #define _CM_REG_OFFSET(module, reg)                             \
 608                         ((__force void __iomem *)(module) + (reg))
 609 #define _GR_MOD_OFFSET(reg)                                     \
 610                         ((__force void __iomem *)(OMAP24XX_GR_MOD + (reg)))
 611
 612 /*-------------------------------------------------------------------------
 613  * 24xx clock tree.
 614  *
 615  * NOTE:In many cases here we are assigning a 'default' parent. In many
 616  *      cases the parent is selectable. The get/set parent calls will also
 617  *      switch sources.
 618  *
 619  *      Many some clocks say always_enabled, but they can be auto idled for
 620  *      power savings. They will always be available upon clock request.
 621  *
 622  *      Several sources are given initial rates which may be wrong, this will
 623  *      be fixed up in the init func.
 624  *
 625  *      Things are broadly separated below by clock domains. It is
 626  *      noteworthy that most periferals have dependencies on multiple clock
 627  *      domains. Many get their interface clocks from the L4 domain, but get
 628  *      functional clocks from fixed sources or other core domain derived
 629  *      clocks.
 630  *-------------------------------------------------------------------------*/
 631
 632 /* Base external input clocks */
 633 static struct clk func_32k_ck = {
 634         .name           = "func_32k_ck",
 635         .rate           = 32000,
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 638         .clkdm          = { .name = "wkup_clkdm" },
 639         .recalc         = &propagate_rate,
 640 };
 641
 642 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 643 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 644         .name           = "osc_ck",
 645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 646                                 RATE_PROPAGATES,
 647         .clkdm          = { .name = "wkup_clkdm" },
 648         .enable         = &omap2_enable_osc_ck,
 649         .disable        = &omap2_disable_osc_ck,
 650         .recalc         = &omap2_osc_clk_recalc,
 651 };
 652
 653 /* Without modem likely 12MHz, with modem likely 13MHz */
 654 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 655         .name           = "sys_ck",             /* ~ ref_clk also */
 656         .parent         = &osc_ck,
 657         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 658                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 659         .clkdm          = { .name = "wkup_clkdm" },
 660         .recalc         = &omap2_sys_clk_recalc,
 661 };
 662
 663 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 664         .name           = "alt_ck",
 665         .rate           = 54000000,
 666         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 667                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 668         .clkdm          = { .name = "wkup_clkdm" },
 669         .recalc         = &propagate_rate,
 670 };
 671
 672 /*
 673  * Analog domain root source clocks
 674  */
 675
 676 /* dpll_ck, is broken out in to special cases through clksel */
 677 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 678  * deal with this
 679  */
 680
 681 static struct dpll_data dpll_dd = {
 682         .mult_div1_reg          = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 683         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 684         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 685         .max_multiplier         = 1024,
 686         .max_divider            = 16,
 687         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 688 };
 689
 690 /*
 691  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 692  * not just a DPLL
 693  */
 694 static struct clk dpll_ck = {
 695         .name           = "dpll_ck",
 696         .parent         = &sys_ck,              /* Can be func_32k also */
 697         .dpll_data      = &dpll_dd,
 698         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 699                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 700         .clkdm          = { .name = "wkup_clkdm" },
 701         .recalc         = &omap2_dpllcore_recalc,
 702         .set_rate       = &omap2_reprogram_dpllcore,
 703 };
 704
 705 static struct clk apll96_ck = {
 706         .name           = "apll96_ck",
 707         .parent         = &sys_ck,
 708         .rate           = 96000000,
 709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 710                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 711         .clkdm          = { .name = "wkup_clkdm" },
 712         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 713         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 714         .enable         = &omap2_clk_fixed_enable,
 715         .disable        = &omap2_clk_fixed_disable,
 716         .recalc         = &propagate_rate,
 717 };
 718
 719 static struct clk apll54_ck = {
 720         .name           = "apll54_ck",
 721         .parent         = &sys_ck,
 722         .rate           = 54000000,
 723         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 724                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 725         .clkdm          = { .name = "wkup_clkdm" },
 726         .enable_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
 727         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 728         .enable         = &omap2_clk_fixed_enable,
 729         .disable        = &omap2_clk_fixed_disable,
 730         .recalc         = &propagate_rate,
 731 };
 732
 733 /*
 734  * PRCM digital base sources
 735  */
 736
 737 /* func_54m_ck */
 738
 739 static const struct clksel_rate func_54m_apll54_rates[] = {
 740         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 741         { .div = 0 },
 742 };
 743
 744 static const struct clksel_rate func_54m_alt_rates[] = {
 745         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 746         { .div = 0 },
 747 };
 748
 749 static const struct clksel func_54m_clksel[] = {
 750         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 751         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 752         { .parent = NULL },
 753 };
 754
 755 static struct clk func_54m_ck = {
 756         .name           = "func_54m_ck",
 757         .parent         = &apll54_ck,   /* can also be alt_clk */
 758         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 759                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 760         .clkdm          = { .name = "wkup_clkdm" },
 761         .init           = &omap2_init_clksel_parent,
 762         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 763         .clksel_mask    = OMAP24XX_54M_SOURCE,
 764         .clksel         = func_54m_clksel,
 765         .recalc         = &omap2_clksel_recalc,
 766 };
 767
 768 static struct clk core_ck = {
 769         .name           = "core_ck",
 770         .parent         = &dpll_ck,             /* can also be 32k */
 771         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 772                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 773         .clkdm          = { .name = "wkup_clkdm" },
 774         .recalc         = &followparent_recalc,
 775 };
 776
 777 /* func_96m_ck */
 778 static const struct clksel_rate func_96m_apll96_rates[] = {
 779         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 780         { .div = 0 },
 781 };
 782
 783 static const struct clksel_rate func_96m_alt_rates[] = {
 784         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 785         { .div = 0 },
 786 };
 787
 788 static const struct clksel func_96m_clksel[] = {
 789         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 790         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 791         { .parent = NULL }
 792 };
 793
 794 /* The parent of this clock is not selectable on 2420. */
 795 static struct clk func_96m_ck = {
 796         .name           = "func_96m_ck",
 797         .parent         = &apll96_ck,
 798         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 799                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 800         .clkdm          = { .name = "wkup_clkdm" },
 801         .init           = &omap2_init_clksel_parent,
 802         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 803         .clksel_mask    = OMAP2430_96M_SOURCE,
 804         .clksel         = func_96m_clksel,
 805         .recalc         = &omap2_clksel_recalc,
 806         .round_rate     = &omap2_clksel_round_rate,
 807         .set_rate       = &omap2_clksel_set_rate
 808 };
 809
 810 /* func_48m_ck */
 811
 812 static const struct clksel_rate func_48m_apll96_rates[] = {
 813         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 814         { .div = 0 },
 815 };
 816
 817 static const struct clksel_rate func_48m_alt_rates[] = {
 818         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 819         { .div = 0 },
 820 };
 821
 822 static const struct clksel func_48m_clksel[] = {
 823         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 824         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 825         { .parent = NULL }
 826 };
 827
 828 static struct clk func_48m_ck = {
 829         .name           = "func_48m_ck",
 830         .parent         = &apll96_ck,    /* 96M or Alt */
 831         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 832                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 833         .clkdm          = { .name = "wkup_clkdm" },
 834         .init           = &omap2_init_clksel_parent,
 835         .clksel_reg     = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
 836         .clksel_mask    = OMAP24XX_48M_SOURCE,
 837         .clksel         = func_48m_clksel,
 838         .recalc         = &omap2_clksel_recalc,
 839         .round_rate     = &omap2_clksel_round_rate,
 840         .set_rate       = &omap2_clksel_set_rate
 841 };
 842
 843 static struct clk func_12m_ck = {
 844         .name           = "func_12m_ck",
 845         .parent         = &func_48m_ck,
 846         .fixed_div      = 4,
 847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 848                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 849         .clkdm          = { .name = "wkup_clkdm" },
 850         .recalc         = &omap2_fixed_divisor_recalc,
 851 };
 852
 853 /* Secure timer, only available in secure mode */
 854 static struct clk wdt1_osc_ck = {
 855         .name           = "ck_wdt1_osc",
 856         .parent         = &osc_ck,
 857         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 858         .recalc         = &followparent_recalc,
 859 };
 860
 861 /*
 862  * The common_clkout* clksel_rate structs are common to
 863  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 864  * sys_clkout2_* are 2420-only, so the
 865  * clksel_rate flags fields are inaccurate for those clocks. This is
 866  * harmless since access to those clocks are gated by the struct clk
 867  * flags fields, which mark them as 2420-only.
 868  */
 869 static const struct clksel_rate common_clkout_src_core_rates[] = {
 870         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 871         { .div = 0 }
 872 };
 873
 874 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 875         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 876         { .div = 0 }
 877 };
 878
 879 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 880         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 881         { .div = 0 }
 882 };
 883
 884 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 885         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 886         { .div = 0 }
 887 };
 888
 889 static const struct clksel common_clkout_src_clksel[] = {
 890         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 891         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 892         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 893         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 894         { .parent = NULL }
 895 };
 896
 897 static struct clk sys_clkout_src = {
 898         .name           = "sys_clkout_src",
 899         .parent         = &func_54m_ck,
 900         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 901                                 RATE_PROPAGATES | OFFSET_GR_MOD,
 902         .clkdm          = { .name = "wkup_clkdm" },
 903         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 904         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 905         .init           = &omap2_init_clksel_parent,
 906         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 907         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 908         .clksel         = common_clkout_src_clksel,
 909         .recalc         = &omap2_clksel_recalc,
 910         .round_rate     = &omap2_clksel_round_rate,
 911         .set_rate       = &omap2_clksel_set_rate
 912 };
 913
 914 static const struct clksel_rate common_clkout_rates[] = {
 915         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 916         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 917         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 918         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 919         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 920         { .div = 0 },
 921 };
 922
 923 static const struct clksel sys_clkout_clksel[] = {
 924         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 925         { .parent = NULL }
 926 };
 927
 928 static struct clk sys_clkout = {
 929         .name           = "sys_clkout",
 930         .parent         = &sys_clkout_src,
 931         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 932                                 PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
 933         .clkdm          = { .name = "wkup_clkdm" },
 934         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 935         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 936         .clksel         = sys_clkout_clksel,
 937         .recalc         = &omap2_clksel_recalc,
 938         .round_rate     = &omap2_clksel_round_rate,
 939         .set_rate       = &omap2_clksel_set_rate
 940 };
 941
 942 /* In 2430, new in 2420 ES2 */
 943 static struct clk sys_clkout2_src = {
 944         .name           = "sys_clkout2_src",
 945         .parent         = &func_54m_ck,
 946         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
 947         .clkdm          = { .name = "wkup_clkdm" },
 948         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 949         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 950         .init           = &omap2_init_clksel_parent,
 951         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 952         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 953         .clksel         = common_clkout_src_clksel,
 954         .recalc         = &omap2_clksel_recalc,
 955         .round_rate     = &omap2_clksel_round_rate,
 956         .set_rate       = &omap2_clksel_set_rate
 957 };
 958
 959 static const struct clksel sys_clkout2_clksel[] = {
 960         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 961         { .parent = NULL }
 962 };
 963
 964 /* In 2430, new in 2420 ES2 */
 965 static struct clk sys_clkout2 = {
 966         .name           = "sys_clkout2",
 967         .parent         = &sys_clkout2_src,
 968         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
 969                                 OFFSET_GR_MOD,
 970         .clkdm          = { .name = "wkup_clkdm" },
 971         .clksel_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
 972         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 973         .clksel         = sys_clkout2_clksel,
 974         .recalc         = &omap2_clksel_recalc,
 975         .round_rate     = &omap2_clksel_round_rate,
 976         .set_rate       = &omap2_clksel_set_rate
 977 };
 978
 979 static struct clk emul_ck = {
 980         .name           = "emul_ck",
 981         .parent         = &func_54m_ck,
 982         .flags          = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
 983         .clkdm          = { .name = "wkup_clkdm" },
 984         .enable_reg     = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
 985         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 986         .recalc         = &followparent_recalc,
 987
 988 };
 989
 990 /*
 991  * MPU clock domain
 992  *      Clocks:
 993  *              MPU_FCLK, MPU_ICLK
 994  *              INT_M_FCLK, INT_M_I_CLK
 995  *
 996  * - Individual clocks are hardware managed.
 997  * - Base divider comes from: CM_CLKSEL_MPU
 998  *
 999  */
1000 static const struct clksel_rate mpu_core_rates[] = {
1001         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1002         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1003         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1004         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1005         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1006         { .div = 0 },
1007 };
1008
1009 static const struct clksel mpu_clksel[] = {
1010         { .parent = &core_ck, .rates = mpu_core_rates },
1011         { .parent = NULL }
1012 };
1013
1014 static struct clk mpu_ck = {    /* Control cpu */
1015         .name           = "mpu_ck",
1016         .parent         = &core_ck,
1017         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1018                                 ALWAYS_ENABLED | DELAYED_APP |
1019                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1020         .clkdm          = { .name = "mpu_clkdm" },
1021         .init           = &omap2_init_clksel_parent,
1022         .clksel_reg     = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL),
1023         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1024         .clksel         = mpu_clksel,
1025         .recalc         = &omap2_clksel_recalc,
1026         .round_rate     = &omap2_clksel_round_rate,
1027         .set_rate       = &omap2_clksel_set_rate
1028 };
1029
1030 /*
1031  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1032  * Clocks:
1033  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1034  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1035  *
1036  * Won't be too specific here. The core clock comes into this block
1037  * it is divided then tee'ed. One branch goes directly to xyz enable
1038  * controls. The other branch gets further divided by 2 then possibly
1039  * routed into a synchronizer and out of clocks abc.
1040  */
1041 static const struct clksel_rate dsp_fck_core_rates[] = {
1042         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1043         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1044         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1045         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1046         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1047         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1048         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1049         { .div = 0 },
1050 };
1051
1052 static const struct clksel dsp_fck_clksel[] = {
1053         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1054         { .parent = NULL }
1055 };
1056
1057 static struct clk dsp_fck = {
1058         .name           = "dsp_fck",
1059         .parent         = &core_ck,
1060         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1061                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1062         .clkdm          = { .name = "dsp_clkdm" },
1063         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1064         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1065         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1066         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1067         .clksel         = dsp_fck_clksel,
1068         .recalc         = &omap2_clksel_recalc,
1069         .round_rate     = &omap2_clksel_round_rate,
1070         .set_rate       = &omap2_clksel_set_rate
1071 };
1072
1073 /* DSP interface clock */
1074 static const struct clksel_rate dsp_irate_ick_rates[] = {
1075         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1076         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1077         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1078         { .div = 0 },
1079 };
1080
1081 static const struct clksel dsp_irate_ick_clksel[] = {
1082         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1083         { .parent = NULL }
1084 };
1085
1086 /* This clock does not exist as such in the TRM. */
1087 static struct clk dsp_irate_ick = {
1088         .name           = "dsp_irate_ick",
1089         .parent         = &dsp_fck,
1090         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1091                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1092         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1093         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1094         .clksel         = dsp_irate_ick_clksel,
1095         .recalc         = &omap2_clksel_recalc,
1096         .round_rate     = &omap2_clksel_round_rate,
1097         .set_rate             = &omap2_clksel_set_rate
1098 };
1099
1100 /* 2420 only */
1101 static struct clk dsp_ick = {
1102         .name           = "dsp_ick",     /* apparently ipi and isp */
1103         .parent         = &dsp_irate_ick,
1104         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1105         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
1106         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1107 };
1108
1109 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1110 static struct clk iva2_1_ick = {
1111         .name           = "iva2_1_ick",
1112         .parent         = &dsp_irate_ick,
1113         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1114         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1115         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1116 };
1117
1118 /*
1119  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1120  * the C54x, but which is contained in the DSP powerdomain.  Does not
1121  * exist on later OMAPs.
1122  */
1123 static struct clk iva1_ifck = {
1124         .name           = "iva1_ifck",
1125         .parent         = &core_ck,
1126         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1127                                 RATE_PROPAGATES | DELAYED_APP,
1128         .clkdm          = { .name = "iva1_clkdm" },
1129         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1130         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1131         .clksel_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
1132         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1133         .clksel         = dsp_fck_clksel,
1134         .recalc         = &omap2_clksel_recalc,
1135         .round_rate     = &omap2_clksel_round_rate,
1136         .set_rate       = &omap2_clksel_set_rate
1137 };
1138
1139 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1140 static struct clk iva1_mpu_int_ifck = {
1141         .name           = "iva1_mpu_int_ifck",
1142         .parent         = &iva1_ifck,
1143         .flags          = CLOCK_IN_OMAP242X,
1144         .clkdm          = { .name = "iva1_clkdm" },
1145         .enable_reg     = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
1146         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1147         .fixed_div      = 2,
1148         .recalc         = &omap2_fixed_divisor_recalc,
1149 };
1150
1151 /*
1152  * L3 clock domain
1153  * L3 clocks are used for both interface and functional clocks to
1154  * multiple entities. Some of these clocks are completely managed
1155  * by hardware, and some others allow software control. Hardware
1156  * managed ones general are based on directly CLK_REQ signals and
1157  * various auto idle settings. The functional spec sets many of these
1158  * as 'tie-high' for their enables.
1159  *
1160  * I-CLOCKS:
1161  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1162  *      CAM, HS-USB.
1163  * F-CLOCK
1164  *      SSI.
1165  *
1166  * GPMC memories and SDRC have timing and clock sensitive registers which
1167  * may very well need notification when the clock changes. Currently for low
1168  * operating points, these are taken care of in sleep.S.
1169  */
1170 static const struct clksel_rate core_l3_core_rates[] = {
1171         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1172         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1173         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1174         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1175         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1176         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1177         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1178         { .div = 0 }
1179 };
1180
1181 static const struct clksel core_l3_clksel[] = {
1182         { .parent = &core_ck, .rates = core_l3_core_rates },
1183         { .parent = NULL }
1184 };
1185
1186 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1187         .name           = "core_l3_ck",
1188         .parent         = &core_ck,
1189         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1190                                 ALWAYS_ENABLED | DELAYED_APP |
1191                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1192         .clkdm          = { .name = "core_l3_clkdm" },
1193         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1194         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1195         .clksel         = core_l3_clksel,
1196         .recalc         = &omap2_clksel_recalc,
1197         .round_rate     = &omap2_clksel_round_rate,
1198         .set_rate       = &omap2_clksel_set_rate
1199 };
1200
1201 /* usb_l4_ick */
1202 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1203         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1204         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1205         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1206         { .div = 0 }
1207 };
1208
1209 static const struct clksel usb_l4_ick_clksel[] = {
1210         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1211         { .parent = NULL },
1212 };
1213
1214 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1215 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1216         .name           = "usb_l4_ick",
1217         .parent         = &core_l3_ck,
1218         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1219                                 DELAYED_APP | CONFIG_PARTICIPANT,
1220         .clkdm          = { .name = "core_l4_clkdm" },
1221         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1222         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1223         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1224         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1225         .clksel         = usb_l4_ick_clksel,
1226         .recalc         = &omap2_clksel_recalc,
1227         .round_rate     = &omap2_clksel_round_rate,
1228         .set_rate       = &omap2_clksel_set_rate
1229 };
1230
1231 /*
1232  * L4 clock management domain
1233  *
1234  * This domain contains lots of interface clocks from the L4 interface, some
1235  * functional clocks.   Fixed APLL functional source clocks are managed in
1236  * this domain.
1237  */
1238 static const struct clksel_rate l4_core_l3_rates[] = {
1239         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1240         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1241         { .div = 0 }
1242 };
1243
1244 static const struct clksel l4_clksel[] = {
1245         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1246         { .parent = NULL }
1247 };
1248
1249 static struct clk l4_ck = {             /* used both as an ick and fck */
1250         .name           = "l4_ck",
1251         .parent         = &core_l3_ck,
1252         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1253                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1254         .clkdm          = { .name = "core_l4_clkdm" },
1255         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1256         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1257         .clksel         = l4_clksel,
1258         .recalc         = &omap2_clksel_recalc,
1259         .round_rate     = &omap2_clksel_round_rate,
1260         .set_rate       = &omap2_clksel_set_rate
1261 };
1262
1263 /*
1264  * SSI is in L3 management domain, its direct parent is core not l3,
1265  * many core power domain entities are grouped into the L3 clock
1266  * domain.
1267  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1268  *
1269  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1270  */
1271 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1272         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1273         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1274         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1275         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1276         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1277         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1278         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1279         { .div = 0 }
1280 };
1281
1282 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1283         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1284         { .parent = NULL }
1285 };
1286
1287 static struct clk ssi_ssr_sst_fck = {
1288         .name           = "ssi_fck",
1289         .parent         = &core_ck,
1290         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1291                                 DELAYED_APP,
1292         .clkdm          = { .name = "core_l3_clkdm" },
1293         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1294         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1295         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1296         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1297         .clksel         = ssi_ssr_sst_fck_clksel,
1298         .recalc         = &omap2_clksel_recalc,
1299         .round_rate     = &omap2_clksel_round_rate,
1300         .set_rate       = &omap2_clksel_set_rate
1301 };
1302
1303 /*
1304  * Presumably this is the same as SSI_ICLK.
1305  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1306  */
1307 static struct clk ssi_l4_ick = {
1308         .name           = "ssi_l4_ick",
1309         .parent         = &l4_ck,
1310         .clkdm          = { .name = "core_l4_clkdm" },
1311         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1312         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1313         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1314         .recalc         = &followparent_recalc,
1315 };
1316
1317
1318 /*
1319  * GFX clock domain
1320  *      Clocks:
1321  * GFX_FCLK, GFX_ICLK
1322  * GFX_CG1(2d), GFX_CG2(3d)
1323  *
1324  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1325  * The 2d and 3d clocks run at a hardware determined
1326  * divided value of fclk.
1327  *
1328  */
1329 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1330
1331 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1332 static const struct clksel gfx_fck_clksel[] = {
1333         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1334         { .parent = NULL },
1335 };
1336
1337 static struct clk gfx_3d_fck = {
1338         .name           = "gfx_3d_fck",
1339         .parent         = &core_l3_ck,
1340         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1341         .clkdm          = { .name = "gfx_clkdm" },
1342         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1343         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1344         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1345         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1346         .clksel         = gfx_fck_clksel,
1347         .recalc         = &omap2_clksel_recalc,
1348         .round_rate     = &omap2_clksel_round_rate,
1349         .set_rate       = &omap2_clksel_set_rate
1350 };
1351
1352 static struct clk gfx_2d_fck = {
1353         .name           = "gfx_2d_fck",
1354         .parent         = &core_l3_ck,
1355         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1356         .clkdm          = { .name = "gfx_clkdm" },
1357         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
1358         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1359         .clksel_reg     = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
1360         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1361         .clksel         = gfx_fck_clksel,
1362         .recalc         = &omap2_clksel_recalc,
1363         .round_rate     = &omap2_clksel_round_rate,
1364         .set_rate       = &omap2_clksel_set_rate
1365 };
1366
1367 static struct clk gfx_ick = {
1368         .name           = "gfx_ick",            /* From l3 */
1369         .parent         = &core_l3_ck,
1370         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1371         .clkdm          = { .name = "gfx_clkdm" },
1372         .enable_reg     = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
1373         .enable_bit     = OMAP_EN_GFX_SHIFT,
1374         .recalc         = &followparent_recalc,
1375 };
1376
1377 /*
1378  * Modem clock domain (2430)
1379  *      CLOCKS:
1380  *              MDM_OSC_CLK
1381  *              MDM_ICLK
1382  * These clocks are usable in chassis mode only.
1383  */
1384 static const struct clksel_rate mdm_ick_core_rates[] = {
1385         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1386         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1387         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1388         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1389         { .div = 0 }
1390 };
1391
1392 static const struct clksel mdm_ick_clksel[] = {
1393         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1394         { .parent = NULL }
1395 };
1396
1397 static struct clk mdm_ick = {           /* used both as a ick and fck */
1398         .name           = "mdm_ick",
1399         .parent         = &core_ck,
1400         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1401         .clkdm          = { .name = "mdm_clkdm" },
1402         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
1403         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1404         .clksel_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL),
1405         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1406         .clksel         = mdm_ick_clksel,
1407         .recalc         = &omap2_clksel_recalc,
1408         .round_rate     = &omap2_clksel_round_rate,
1409         .set_rate       = &omap2_clksel_set_rate
1410 };
1411
1412 static struct clk mdm_osc_ck = {
1413         .name           = "mdm_osc_ck",
1414         .parent         = &osc_ck,
1415         .flags          = CLOCK_IN_OMAP243X,
1416         .clkdm          = { .name = "mdm_clkdm" },
1417         .enable_reg     = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
1418         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1419         .recalc         = &followparent_recalc,
1420 };
1421
1422 /*
1423  * DSS clock domain
1424  * CLOCKs:
1425  * DSS_L4_ICLK, DSS_L3_ICLK,
1426  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1427  *
1428  * DSS is both initiator and target.
1429  */
1430 /* XXX Add RATE_NOT_VALIDATED */
1431
1432 static const struct clksel_rate dss1_fck_sys_rates[] = {
1433         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1434         { .div = 0 }
1435 };
1436
1437 static const struct clksel_rate dss1_fck_core_rates[] = {
1438         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1439         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1440         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1441         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1442         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1443         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1444         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1445         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1446         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1447         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1448         { .div = 0 }
1449 };
1450
1451 static const struct clksel dss1_fck_clksel[] = {
1452         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1453         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1454         { .parent = NULL },
1455 };
1456
1457 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1458         .name           = "dss_ick",
1459         .parent         = &l4_ck,       /* really both l3 and l4 */
1460         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1461         .clkdm          = { .name = "dss_clkdm" },
1462         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1463         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk dss1_fck = {
1468         .name           = "dss1_fck",
1469         .parent         = &core_ck,             /* Core or sys */
1470         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1471                                 DELAYED_APP,
1472         .clkdm          = { .name = "dss_clkdm" },
1473         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1474         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1475         .init           = &omap2_init_clksel_parent,
1476         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1477         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1478         .clksel         = dss1_fck_clksel,
1479         .recalc         = &omap2_clksel_recalc,
1480         .round_rate     = &omap2_clksel_round_rate,
1481         .set_rate       = &omap2_clksel_set_rate
1482 };
1483
1484 static const struct clksel_rate dss2_fck_sys_rates[] = {
1485         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1486         { .div = 0 }
1487 };
1488
1489 static const struct clksel_rate dss2_fck_48m_rates[] = {
1490         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1491         { .div = 0 }
1492 };
1493
1494 static const struct clksel dss2_fck_clksel[] = {
1495         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1496         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1497         { .parent = NULL }
1498 };
1499
1500 static struct clk dss2_fck = {          /* Alt clk used in power management */
1501         .name           = "dss2_fck",
1502         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1503         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1504                                 DELAYED_APP,
1505         .clkdm          = { .name = "dss_clkdm" },
1506         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1507         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1508         .init           = &omap2_init_clksel_parent,
1509         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
1510         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1511         .clksel         = dss2_fck_clksel,
1512         .recalc         = &followparent_recalc,
1513 };
1514
1515 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1516         .name           = "dss_54m_fck",        /* 54m tv clk */
1517         .parent         = &func_54m_ck,
1518         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1519         .clkdm          = { .name = "dss_clkdm" },
1520         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1521         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1522         .recalc         = &followparent_recalc,
1523 };
1524
1525 /*
1526  * CORE power domain ICLK & FCLK defines.
1527  * Many of the these can have more than one possible parent. Entries
1528  * here will likely have an L4 interface parent, and may have multiple
1529  * functional clock parents.
1530  */
1531 static const struct clksel_rate gpt_alt_rates[] = {
1532         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1533         { .div = 0 }
1534 };
1535
1536 static const struct clksel omap24xx_gpt_clksel[] = {
1537         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1538         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1539         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1540         { .parent = NULL },
1541 };
1542
1543 static struct clk gpt1_ick = {
1544         .name           = "gpt1_ick",
1545         .parent         = &l4_ck,
1546         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1547         .clkdm          = { .name = "core_l4_clkdm" },
1548         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
1549         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1550         .recalc         = &followparent_recalc,
1551 };
1552
1553 static struct clk gpt1_fck = {
1554         .name           = "gpt1_fck",
1555         .parent         = &func_32k_ck,
1556         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1557         .clkdm          = { .name = "core_l4_clkdm" },
1558         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
1559         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1560         .init           = &omap2_init_clksel_parent,
1561         .clksel_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_CLKSEL1),
1562         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1563         .clksel         = omap24xx_gpt_clksel,
1564         .recalc         = &omap2_clksel_recalc,
1565         .round_rate     = &omap2_clksel_round_rate,
1566         .set_rate       = &omap2_clksel_set_rate
1567 };
1568
1569 static struct clk gpt2_ick = {
1570         .name           = "gpt2_ick",
1571         .parent         = &l4_ck,
1572         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573         .clkdm          = { .name = "core_l4_clkdm" },
1574         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1575         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1576         .recalc         = &followparent_recalc,
1577 };
1578
1579 static struct clk gpt2_fck = {
1580         .name           = "gpt2_fck",
1581         .parent         = &func_32k_ck,
1582         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1583         .clkdm          = { .name = "core_l4_clkdm" },
1584         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1585         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1586         .init           = &omap2_init_clksel_parent,
1587         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1588         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1589         .clksel         = omap24xx_gpt_clksel,
1590         .recalc         = &omap2_clksel_recalc,
1591 };
1592
1593 static struct clk gpt3_ick = {
1594         .name           = "gpt3_ick",
1595         .parent         = &l4_ck,
1596         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597         .clkdm          = { .name = "core_l4_clkdm" },
1598         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1599         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 static struct clk gpt3_fck = {
1604         .name           = "gpt3_fck",
1605         .parent         = &func_32k_ck,
1606         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607         .clkdm          = { .name = "core_l4_clkdm" },
1608         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1609         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1610         .init           = &omap2_init_clksel_parent,
1611         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1612         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1613         .clksel         = omap24xx_gpt_clksel,
1614         .recalc         = &omap2_clksel_recalc,
1615 };
1616
1617 static struct clk gpt4_ick = {
1618         .name           = "gpt4_ick",
1619         .parent         = &l4_ck,
1620         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621         .clkdm          = { .name = "core_l4_clkdm" },
1622         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1623         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk gpt4_fck = {
1628         .name           = "gpt4_fck",
1629         .parent         = &func_32k_ck,
1630         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631         .clkdm          = { .name = "core_l4_clkdm" },
1632         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1633         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1634         .init           = &omap2_init_clksel_parent,
1635         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1636         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1637         .clksel         = omap24xx_gpt_clksel,
1638         .recalc         = &omap2_clksel_recalc,
1639 };
1640
1641 static struct clk gpt5_ick = {
1642         .name           = "gpt5_ick",
1643         .parent         = &l4_ck,
1644         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645         .clkdm          = { .name = "core_l4_clkdm" },
1646         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1647         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1648         .recalc         = &followparent_recalc,
1649 };
1650
1651 static struct clk gpt5_fck = {
1652         .name           = "gpt5_fck",
1653         .parent         = &func_32k_ck,
1654         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655         .clkdm          = { .name = "core_l4_clkdm" },
1656         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1657         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1658         .init           = &omap2_init_clksel_parent,
1659         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1660         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1661         .clksel         = omap24xx_gpt_clksel,
1662         .recalc         = &omap2_clksel_recalc,
1663 };
1664
1665 static struct clk gpt6_ick = {
1666         .name           = "gpt6_ick",
1667         .parent         = &l4_ck,
1668         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1669         .clkdm          = { .name = "core_l4_clkdm" },
1670         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1671         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1672         .recalc         = &followparent_recalc,
1673 };
1674
1675 static struct clk gpt6_fck = {
1676         .name           = "gpt6_fck",
1677         .parent         = &func_32k_ck,
1678         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1679         .clkdm          = { .name = "core_l4_clkdm" },
1680         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1681         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1682         .init           = &omap2_init_clksel_parent,
1683         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1684         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1685         .clksel         = omap24xx_gpt_clksel,
1686         .recalc         = &omap2_clksel_recalc,
1687 };
1688
1689 static struct clk gpt7_ick = {
1690         .name           = "gpt7_ick",
1691         .parent         = &l4_ck,
1692         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1693         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1694         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1695         .recalc         = &followparent_recalc,
1696 };
1697
1698 static struct clk gpt7_fck = {
1699         .name           = "gpt7_fck",
1700         .parent         = &func_32k_ck,
1701         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702         .clkdm          = { .name = "core_l4_clkdm" },
1703         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1704         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1705         .init           = &omap2_init_clksel_parent,
1706         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1707         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1708         .clksel         = omap24xx_gpt_clksel,
1709         .recalc         = &omap2_clksel_recalc,
1710 };
1711
1712 static struct clk gpt8_ick = {
1713         .name           = "gpt8_ick",
1714         .parent         = &l4_ck,
1715         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716         .clkdm          = { .name = "core_l4_clkdm" },
1717         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1718         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1719         .recalc         = &followparent_recalc,
1720 };
1721
1722 static struct clk gpt8_fck = {
1723         .name           = "gpt8_fck",
1724         .parent         = &func_32k_ck,
1725         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1726         .clkdm          = { .name = "core_l4_clkdm" },
1727         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1728         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1729         .init           = &omap2_init_clksel_parent,
1730         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1731         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1732         .clksel         = omap24xx_gpt_clksel,
1733         .recalc         = &omap2_clksel_recalc,
1734 };
1735
1736 static struct clk gpt9_ick = {
1737         .name           = "gpt9_ick",
1738         .parent         = &l4_ck,
1739         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740         .clkdm          = { .name = "core_l4_clkdm" },
1741         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1742         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1743         .recalc         = &followparent_recalc,
1744 };
1745
1746 static struct clk gpt9_fck = {
1747         .name           = "gpt9_fck",
1748         .parent         = &func_32k_ck,
1749         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1750         .clkdm          = { .name = "core_l4_clkdm" },
1751         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1752         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1753         .init           = &omap2_init_clksel_parent,
1754         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1755         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1756         .clksel         = omap24xx_gpt_clksel,
1757         .recalc         = &omap2_clksel_recalc,
1758 };
1759
1760 static struct clk gpt10_ick = {
1761         .name           = "gpt10_ick",
1762         .parent         = &l4_ck,
1763         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764         .clkdm          = { .name = "core_l4_clkdm" },
1765         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1766         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1767         .recalc         = &followparent_recalc,
1768 };
1769
1770 static struct clk gpt10_fck = {
1771         .name           = "gpt10_fck",
1772         .parent         = &func_32k_ck,
1773         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774         .clkdm          = { .name = "core_l4_clkdm" },
1775         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1776         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1777         .init           = &omap2_init_clksel_parent,
1778         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1779         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1780         .clksel         = omap24xx_gpt_clksel,
1781         .recalc         = &omap2_clksel_recalc,
1782 };
1783
1784 static struct clk gpt11_ick = {
1785         .name           = "gpt11_ick",
1786         .parent         = &l4_ck,
1787         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788         .clkdm          = { .name = "core_l4_clkdm" },
1789         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1790         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1791         .recalc         = &followparent_recalc,
1792 };
1793
1794 static struct clk gpt11_fck = {
1795         .name           = "gpt11_fck",
1796         .parent         = &func_32k_ck,
1797         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1798         .clkdm          = { .name = "core_l4_clkdm" },
1799         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1800         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1801         .init           = &omap2_init_clksel_parent,
1802         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1803         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1804         .clksel         = omap24xx_gpt_clksel,
1805         .recalc         = &omap2_clksel_recalc,
1806 };
1807
1808 static struct clk gpt12_ick = {
1809         .name           = "gpt12_ick",
1810         .parent         = &l4_ck,
1811         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1812         .clkdm          = { .name = "core_l4_clkdm" },
1813         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1814         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1815         .recalc         = &followparent_recalc,
1816 };
1817
1818 static struct clk gpt12_fck = {
1819         .name           = "gpt12_fck",
1820         .parent         = &func_32k_ck,
1821         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1822         .clkdm          = { .name = "core_l4_clkdm" },
1823         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1824         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1825         .init           = &omap2_init_clksel_parent,
1826         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2),
1827         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1828         .clksel         = omap24xx_gpt_clksel,
1829         .recalc         = &omap2_clksel_recalc,
1830 };
1831
1832 static struct clk mcbsp1_ick = {
1833         .name           = "mcbsp_ick",
1834         .id             = 1,
1835         .parent         = &l4_ck,
1836         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1837         .clkdm          = { .name = "core_l4_clkdm" },
1838         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1839         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1840         .recalc         = &followparent_recalc,
1841 };
1842
1843 static struct clk mcbsp1_fck = {
1844         .name           = "mcbsp_fck",
1845         .id             = 1,
1846         .parent         = &func_96m_ck,
1847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1848         .clkdm          = { .name = "core_l4_clkdm" },
1849         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1850         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1851         .recalc         = &followparent_recalc,
1852 };
1853
1854 static struct clk mcbsp2_ick = {
1855         .name           = "mcbsp_ick",
1856         .id             = 2,
1857         .parent         = &l4_ck,
1858         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1859         .clkdm          = { .name = "core_l4_clkdm" },
1860         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1861         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1862         .recalc         = &followparent_recalc,
1863 };
1864
1865 static struct clk mcbsp2_fck = {
1866         .name           = "mcbsp_fck",
1867         .id             = 2,
1868         .parent         = &func_96m_ck,
1869         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1870         .clkdm          = { .name = "core_l4_clkdm" },
1871         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1872         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1873         .recalc         = &followparent_recalc,
1874 };
1875
1876 static struct clk mcbsp3_ick = {
1877         .name           = "mcbsp_ick",
1878         .id             = 3,
1879         .parent         = &l4_ck,
1880         .flags          = CLOCK_IN_OMAP243X,
1881         .clkdm          = { .name = "core_l4_clkdm" },
1882         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1883         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1884         .recalc         = &followparent_recalc,
1885 };
1886
1887 static struct clk mcbsp3_fck = {
1888         .name           = "mcbsp_fck",
1889         .id             = 3,
1890         .parent         = &func_96m_ck,
1891         .flags          = CLOCK_IN_OMAP243X,
1892         .clkdm          = { .name = "core_l4_clkdm" },
1893         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1894         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1895         .recalc         = &followparent_recalc,
1896 };
1897
1898 static struct clk mcbsp4_ick = {
1899         .name           = "mcbsp_ick",
1900         .id             = 4,
1901         .parent         = &l4_ck,
1902         .flags          = CLOCK_IN_OMAP243X,
1903         .clkdm          = { .name = "core_l4_clkdm" },
1904         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1905         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1906         .recalc         = &followparent_recalc,
1907 };
1908
1909 static struct clk mcbsp4_fck = {
1910         .name           = "mcbsp_fck",
1911         .id             = 4,
1912         .parent         = &func_96m_ck,
1913         .flags          = CLOCK_IN_OMAP243X,
1914         .clkdm          = { .name = "core_l4_clkdm" },
1915         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1916         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk mcbsp5_ick = {
1921         .name           = "mcbsp_ick",
1922         .id             = 5,
1923         .parent         = &l4_ck,
1924         .flags          = CLOCK_IN_OMAP243X,
1925         .clkdm          = { .name = "core_l4_clkdm" },
1926         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1927         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1928         .recalc         = &followparent_recalc,
1929 };
1930
1931 static struct clk mcbsp5_fck = {
1932         .name           = "mcbsp_fck",
1933         .id             = 5,
1934         .parent         = &func_96m_ck,
1935         .flags          = CLOCK_IN_OMAP243X,
1936         .clkdm          = { .name = "core_l4_clkdm" },
1937         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1938         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1939         .recalc         = &followparent_recalc,
1940 };
1941
1942 static struct clk mcspi1_ick = {
1943         .name           = "mcspi_ick",
1944         .id             = 1,
1945         .parent         = &l4_ck,
1946         .clkdm          = { .name = "core_l4_clkdm" },
1947         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1948         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1949         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1950         .recalc         = &followparent_recalc,
1951 };
1952
1953 static struct clk mcspi1_fck = {
1954         .name           = "mcspi_fck",
1955         .id             = 1,
1956         .parent         = &func_48m_ck,
1957         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1958         .clkdm          = { .name = "core_l4_clkdm" },
1959         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1960         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1961         .recalc         = &followparent_recalc,
1962 };
1963
1964 static struct clk mcspi2_ick = {
1965         .name           = "mcspi_ick",
1966         .id             = 2,
1967         .parent         = &l4_ck,
1968         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1969         .clkdm          = { .name = "core_l4_clkdm" },
1970         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
1971         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1972         .recalc         = &followparent_recalc,
1973 };
1974
1975 static struct clk mcspi2_fck = {
1976         .name           = "mcspi_fck",
1977         .id             = 2,
1978         .parent         = &func_48m_ck,
1979         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1980         .clkdm          = { .name = "core_l4_clkdm" },
1981         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
1982         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1983         .recalc         = &followparent_recalc,
1984 };
1985
1986 static struct clk mcspi3_ick = {
1987         .name           = "mcspi_ick",
1988         .id             = 3,
1989         .parent         = &l4_ck,
1990         .flags          = CLOCK_IN_OMAP243X,
1991         .clkdm          = { .name = "core_l4_clkdm" },
1992         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
1993         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk mcspi3_fck = {
1998         .name           = "mcspi_fck",
1999         .id             = 3,
2000         .parent         = &func_48m_ck,
2001         .flags          = CLOCK_IN_OMAP243X,
2002         .clkdm          = { .name = "core_l4_clkdm" },
2003         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2004         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 static struct clk uart1_ick = {
2009         .name           = "uart1_ick",
2010         .parent         = &l4_ck,
2011         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2012         .clkdm          = { .name = "core_l4_clkdm" },
2013         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2014         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2015         .recalc         = &followparent_recalc,
2016 };
2017
2018 static struct clk uart1_fck = {
2019         .name           = "uart1_fck",
2020         .parent         = &func_48m_ck,
2021         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2022         .clkdm          = { .name = "core_l4_clkdm" },
2023         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2024         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 static struct clk uart2_ick = {
2029         .name           = "uart2_ick",
2030         .parent         = &l4_ck,
2031         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2032         .clkdm          = { .name = "core_l4_clkdm" },
2033         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2034         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2035         .recalc         = &followparent_recalc,
2036 };
2037
2038 static struct clk uart2_fck = {
2039         .name           = "uart2_fck",
2040         .parent         = &func_48m_ck,
2041         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2042         .clkdm          = { .name = "core_l4_clkdm" },
2043         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2044         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk uart3_ick = {
2049         .name           = "uart3_ick",
2050         .parent         = &l4_ck,
2051         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2052         .clkdm          = { .name = "core_l4_clkdm" },
2053         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2054         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2055         .recalc         = &followparent_recalc,
2056 };
2057
2058 static struct clk uart3_fck = {
2059         .name           = "uart3_fck",
2060         .parent         = &func_48m_ck,
2061         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2062         .clkdm          = { .name = "core_l4_clkdm" },
2063         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2064         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2065         .recalc         = &followparent_recalc,
2066 };
2067
2068 static struct clk gpios_ick = {
2069         .name           = "gpios_ick",
2070         .parent         = &l4_ck,
2071         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2072         .clkdm          = { .name = "core_l4_clkdm" },
2073         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2074         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2075         .recalc         = &followparent_recalc,
2076 };
2077
2078 static struct clk gpios_fck = {
2079         .name           = "gpios_fck",
2080         .parent         = &func_32k_ck,
2081         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2082         .clkdm          = { .name = "wkup_clkdm" },
2083         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2084         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2085         .recalc         = &followparent_recalc,
2086 };
2087
2088 static struct clk mpu_wdt_ick = {
2089         .name           = "mpu_wdt_ick",
2090         .parent         = &l4_ck,
2091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2092         .clkdm          = { .name = "core_l4_clkdm" },
2093         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2094         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2095         .recalc         = &followparent_recalc,
2096 };
2097
2098 static struct clk mpu_wdt_fck = {
2099         .name           = "mpu_wdt_fck",
2100         .parent         = &func_32k_ck,
2101         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2102         .clkdm          = { .name = "wkup_clkdm" },
2103         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
2104         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2105         .recalc         = &followparent_recalc,
2106 };
2107
2108 static struct clk sync_32k_ick = {
2109         .name           = "sync_32k_ick",
2110         .parent         = &l4_ck,
2111         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2112                                 ENABLE_ON_INIT,
2113         .clkdm          = { .name = "core_l4_clkdm" },
2114         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2115         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2116         .recalc         = &followparent_recalc,
2117 };
2118
2119 static struct clk wdt1_ick = {
2120         .name           = "wdt1_ick",
2121         .parent         = &l4_ck,
2122         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2123         .clkdm          = { .name = "core_l4_clkdm" },
2124         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2125         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2126         .recalc         = &followparent_recalc,
2127 };
2128
2129 static struct clk omapctrl_ick = {
2130         .name           = "omapctrl_ick",
2131         .parent         = &l4_ck,
2132         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2133                                 ENABLE_ON_INIT,
2134         .clkdm          = { .name = "core_l4_clkdm" },
2135         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2136         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 static struct clk icr_ick = {
2141         .name           = "icr_ick",
2142         .parent         = &l4_ck,
2143         .flags          = CLOCK_IN_OMAP243X,
2144         .clkdm          = { .name = "core_l4_clkdm" },
2145         .enable_reg     = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
2146         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2147         .recalc         = &followparent_recalc,
2148 };
2149
2150 static struct clk cam_ick = {
2151         .name           = "cam_ick",
2152         .parent         = &l4_ck,
2153         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2154         .clkdm          = { .name = "core_l4_clkdm" },
2155         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2156         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2157         .recalc         = &followparent_recalc,
2158 };
2159
2160 /*
2161  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2162  * split into two separate clocks, since the parent clocks are different
2163  * and the clockdomains are also different.
2164  */
2165 static struct clk cam_fck = {
2166         .name           = "cam_fck",
2167         .parent         = &func_96m_ck,
2168         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2169         .clkdm          = { .name = "core_l3_clkdm" },
2170         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2171         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk mailboxes_ick = {
2176         .name           = "mailboxes_ick",
2177         .parent         = &l4_ck,
2178         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2179         .clkdm          = { .name = "core_l4_clkdm" },
2180         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2181         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk wdt4_ick = {
2186         .name           = "wdt4_ick",
2187         .parent         = &l4_ck,
2188         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2189         .clkdm          = { .name = "core_l4_clkdm" },
2190         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2191         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk wdt4_fck = {
2196         .name           = "wdt4_fck",
2197         .parent         = &func_32k_ck,
2198         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2199         .clkdm          = { .name = "core_l4_clkdm" },
2200         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2201         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk wdt3_ick = {
2206         .name           = "wdt3_ick",
2207         .parent         = &l4_ck,
2208         .flags          = CLOCK_IN_OMAP242X,
2209         .clkdm          = { .name = "core_l4_clkdm" },
2210         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2211         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 static struct clk wdt3_fck = {
2216         .name           = "wdt3_fck",
2217         .parent         = &func_32k_ck,
2218         .flags          = CLOCK_IN_OMAP242X,
2219         .clkdm          = { .name = "core_l4_clkdm" },
2220         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2221         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk mspro_ick = {
2226         .name           = "mspro_ick",
2227         .parent         = &l4_ck,
2228         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2229         .clkdm          = { .name = "core_l4_clkdm" },
2230         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2231         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2232         .recalc         = &followparent_recalc,
2233 };
2234
2235 static struct clk mspro_fck = {
2236         .name           = "mspro_fck",
2237         .parent         = &func_96m_ck,
2238         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2239         .clkdm          = { .name = "core_l4_clkdm" },
2240         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2241         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk mmc_ick = {
2246         .name           = "mmc_ick",
2247         .parent         = &l4_ck,
2248         .flags          = CLOCK_IN_OMAP242X,
2249         .clkdm          = { .name = "core_l4_clkdm" },
2250         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2251         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 static struct clk mmc_fck = {
2256         .name           = "mmc_fck",
2257         .parent         = &func_96m_ck,
2258         .flags          = CLOCK_IN_OMAP242X,
2259         .clkdm          = { .name = "core_l4_clkdm" },
2260         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2261         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 static struct clk fac_ick = {
2266         .name           = "fac_ick",
2267         .parent         = &l4_ck,
2268         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2269         .clkdm          = { .name = "core_l4_clkdm" },
2270         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2271         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2272         .recalc         = &followparent_recalc,
2273 };
2274
2275 static struct clk fac_fck = {
2276         .name           = "fac_fck",
2277         .parent         = &func_12m_ck,
2278         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2279         .clkdm          = { .name = "core_l4_clkdm" },
2280         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2281         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2282         .recalc         = &followparent_recalc,
2283 };
2284
2285 static struct clk eac_ick = {
2286         .name           = "eac_ick",
2287         .parent         = &l4_ck,
2288         .flags          = CLOCK_IN_OMAP242X,
2289         .clkdm          = { .name = "core_l4_clkdm" },
2290         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2291         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2292         .recalc         = &followparent_recalc,
2293 };
2294
2295 static struct clk eac_fck = {
2296         .name           = "eac_fck",
2297         .parent         = &func_96m_ck,
2298         .flags          = CLOCK_IN_OMAP242X,
2299         .clkdm          = { .name = "core_l4_clkdm" },
2300         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2301         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2302         .recalc         = &followparent_recalc,
2303 };
2304
2305 static struct clk hdq_ick = {
2306         .name           = "hdq_ick",
2307         .parent         = &l4_ck,
2308         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2309         .clkdm          = { .name = "core_l4_clkdm" },
2310         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2311         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2312         .recalc         = &followparent_recalc,
2313 };
2314
2315 static struct clk hdq_fck = {
2316         .name           = "hdq_fck",
2317         .parent         = &func_12m_ck,
2318         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2319         .clkdm          = { .name = "core_l4_clkdm" },
2320         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2321         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2322         .recalc         = &followparent_recalc,
2323 };
2324
2325 static struct clk i2c2_ick = {
2326         .name           = "i2c_ick",
2327         .id             = 2,
2328         .parent         = &l4_ck,
2329         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2330         .clkdm          = { .name = "core_l4_clkdm" },
2331         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2332         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2333         .recalc         = &followparent_recalc,
2334 };
2335
2336 static struct clk i2c2_fck = {
2337         .name           = "i2c_fck",
2338         .id             = 2,
2339         .parent         = &func_12m_ck,
2340         .flags          = CLOCK_IN_OMAP242X,
2341         .clkdm          = { .name = "core_l4_clkdm" },
2342         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2343         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2344         .recalc         = &followparent_recalc,
2345 };
2346
2347 static struct clk i2chs2_fck = {
2348         .name           = "i2chs_fck",
2349         .id             = 2,
2350         .parent         = &func_96m_ck,
2351         .flags          = CLOCK_IN_OMAP243X,
2352         .clkdm          = { .name = "core_l4_clkdm" },
2353         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2354         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2355         .recalc         = &followparent_recalc,
2356 };
2357
2358 static struct clk i2c1_ick = {
2359         .name           = "i2c_ick",
2360         .id             = 1,
2361         .parent         = &l4_ck,
2362         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2363         .clkdm          = { .name = "core_l4_clkdm" },
2364         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2365         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2366         .recalc         = &followparent_recalc,
2367 };
2368
2369 static struct clk i2c1_fck = {
2370         .name           = "i2c_fck",
2371         .id             = 1,
2372         .parent         = &func_12m_ck,
2373         .flags          = CLOCK_IN_OMAP242X,
2374         .clkdm          = { .name = "core_l4_clkdm" },
2375         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2376         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2377         .recalc         = &followparent_recalc,
2378 };
2379
2380 static struct clk i2chs1_fck = {
2381         .name           = "i2chs_fck",
2382         .id             = 1,
2383         .parent         = &func_96m_ck,
2384         .flags          = CLOCK_IN_OMAP243X,
2385         .clkdm          = { .name = "core_l4_clkdm" },
2386         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2387         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2388         .recalc         = &followparent_recalc,
2389 };
2390
2391 static struct clk gpmc_fck = {
2392         .name           = "gpmc_fck",
2393         .parent         = &core_l3_ck,
2394         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2395                                 ENABLE_ON_INIT,
2396         .clkdm          = { .name = "core_l3_clkdm" },
2397         .recalc         = &followparent_recalc,
2398 };
2399
2400 static struct clk sdma_fck = {
2401         .name           = "sdma_fck",
2402         .parent         = &core_l3_ck,
2403         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2404         .clkdm          = { .name = "core_l3_clkdm" },
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk sdma_ick = {
2409         .name           = "sdma_ick",
2410         .parent         = &l4_ck,
2411         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2412         .clkdm          = { .name = "core_l3_clkdm" },
2413         .recalc         = &followparent_recalc,
2414 };
2415
2416 static struct clk vlynq_ick = {
2417         .name           = "vlynq_ick",
2418         .parent         = &core_l3_ck,
2419         .flags          = CLOCK_IN_OMAP242X,
2420         .clkdm          = { .name = "core_l3_clkdm" },
2421         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
2422         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2423         .recalc         = &followparent_recalc,
2424 };
2425
2426 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2427         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2428         { .div = 0 }
2429 };
2430
2431 static const struct clksel_rate vlynq_fck_core_rates[] = {
2432         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2433         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2434         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2435         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2436         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2437         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2438         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2439         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2440         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2441         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2442         { .div = 0 }
2443 };
2444
2445 static const struct clksel vlynq_fck_clksel[] = {
2446         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2447         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2448         { .parent = NULL }
2449 };
2450
2451 static struct clk vlynq_fck = {
2452         .name           = "vlynq_fck",
2453         .parent         = &func_96m_ck,
2454         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2455         .clkdm          = { .name = "core_l3_clkdm" },
2456         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
2457         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2458         .init           = &omap2_init_clksel_parent,
2459         .clksel_reg     = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
2460         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2461         .clksel         = vlynq_fck_clksel,
2462         .recalc         = &omap2_clksel_recalc,
2463         .round_rate     = &omap2_clksel_round_rate,
2464         .set_rate       = &omap2_clksel_set_rate
2465 };
2466
2467 static struct clk sdrc_ick = {
2468         .name           = "sdrc_ick",
2469         .parent         = &l4_ck,
2470         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2471         .clkdm          = { .name = "core_l4_clkdm" },
2472         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
2473         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2474         .recalc         = &followparent_recalc,
2475 };
2476
2477 static struct clk des_ick = {
2478         .name           = "des_ick",
2479         .parent         = &l4_ck,
2480         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2481         .clkdm          = { .name = "core_l4_clkdm" },
2482         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2483         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2484         .recalc         = &followparent_recalc,
2485 };
2486
2487 static struct clk sha_ick = {
2488         .name           = "sha_ick",
2489         .parent         = &l4_ck,
2490         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2491         .clkdm          = { .name = "core_l4_clkdm" },
2492         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2493         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2494         .recalc         = &followparent_recalc,
2495 };
2496
2497 static struct clk rng_ick = {
2498         .name           = "rng_ick",
2499         .parent         = &l4_ck,
2500         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2501         .clkdm          = { .name = "core_l4_clkdm" },
2502         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2503         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2504         .recalc         = &followparent_recalc,
2505 };
2506
2507 static struct clk aes_ick = {
2508         .name           = "aes_ick",
2509         .parent         = &l4_ck,
2510         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2511         .clkdm          = { .name = "core_l4_clkdm" },
2512         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2513         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2514         .recalc         = &followparent_recalc,
2515 };
2516
2517 static struct clk pka_ick = {
2518         .name           = "pka_ick",
2519         .parent         = &l4_ck,
2520         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2521         .clkdm          = { .name = "core_l4_clkdm" },
2522         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2523         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2524         .recalc         = &followparent_recalc,
2525 };
2526
2527 static struct clk usb_fck = {
2528         .name           = "usb_fck",
2529         .parent         = &func_48m_ck,
2530         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2531         .clkdm          = { .name = "core_l3_clkdm" },
2532         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2533         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2534         .recalc         = &followparent_recalc,
2535 };
2536
2537 static struct clk usbhs_ick = {
2538         .name           = "usbhs_ick",
2539         .parent         = &core_l3_ck,
2540         .flags          = CLOCK_IN_OMAP243X,
2541         .clkdm          = { .name = "core_l3_clkdm" },
2542         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2543         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2544         .recalc         = &followparent_recalc,
2545 };
2546
2547 static struct clk mmchs1_ick = {
2548         .name           = "mmchs_ick",
2549         .id             = 1,
2550         .parent         = &l4_ck,
2551         .flags          = CLOCK_IN_OMAP243X,
2552         .clkdm          = { .name = "core_l4_clkdm" },
2553         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2554         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2555         .recalc         = &followparent_recalc,
2556 };
2557
2558 static struct clk mmchs1_fck = {
2559         .name           = "mmchs_fck",
2560         .id             = 1,
2561         .parent         = &func_96m_ck,
2562         .flags          = CLOCK_IN_OMAP243X,
2563         .clkdm          = { .name = "core_l3_clkdm" },
2564         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2565         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2566         .recalc         = &followparent_recalc,
2567 };
2568
2569 static struct clk mmchs2_ick = {
2570         .name           = "mmchs_ick",
2571         .id             = 2,
2572         .parent         = &l4_ck,
2573         .flags          = CLOCK_IN_OMAP243X,
2574         .clkdm          = { .name = "core_l4_clkdm" },
2575         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2576         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2577         .recalc         = &followparent_recalc,
2578 };
2579
2580 static struct clk mmchs2_fck = {
2581         .name           = "mmchs_fck",
2582         .id             = 2,
2583         .parent         = &func_96m_ck,
2584         .flags          = CLOCK_IN_OMAP243X,
2585         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2586         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2587         .recalc         = &followparent_recalc,
2588 };
2589
2590 static struct clk gpio5_ick = {
2591         .name           = "gpio5_ick",
2592         .parent         = &l4_ck,
2593         .flags          = CLOCK_IN_OMAP243X,
2594         .clkdm          = { .name = "core_l4_clkdm" },
2595         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2596         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2597         .recalc         = &followparent_recalc,
2598 };
2599
2600 static struct clk gpio5_fck = {
2601         .name           = "gpio5_fck",
2602         .parent         = &func_32k_ck,
2603         .flags          = CLOCK_IN_OMAP243X,
2604         .clkdm          = { .name = "core_l4_clkdm" },
2605         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2606         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2607         .recalc         = &followparent_recalc,
2608 };
2609
2610 static struct clk mdm_intc_ick = {
2611         .name           = "mdm_intc_ick",
2612         .parent         = &l4_ck,
2613         .flags          = CLOCK_IN_OMAP243X,
2614         .clkdm          = { .name = "core_l4_clkdm" },
2615         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
2616         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2617         .recalc         = &followparent_recalc,
2618 };
2619
2620 static struct clk mmchsdb1_fck = {
2621         .name           = "mmchsdb_fck",
2622         .id             = 1,
2623         .parent         = &func_32k_ck,
2624         .flags          = CLOCK_IN_OMAP243X,
2625         .clkdm          = { .name = "core_l4_clkdm" },
2626         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2627         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2628         .recalc         = &followparent_recalc,
2629 };
2630
2631 static struct clk mmchsdb2_fck = {
2632         .name           = "mmchsdb_fck",
2633         .id             = 2,
2634         .parent         = &func_32k_ck,
2635         .flags          = CLOCK_IN_OMAP243X,
2636         .clkdm          = { .name = "core_l4_clkdm" },
2637         .enable_reg     = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2638         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2639         .recalc         = &followparent_recalc,
2640 };
2641
2642 /*
2643  * This clock is a composite clock which does entire set changes then
2644  * forces a rebalance. It keys on the MPU speed, but it really could
2645  * be any key speed part of a set in the rate table.
2646  *
2647  * to really change a set, you need memory table sets which get changed
2648  * in sram, pre-notifiers & post notifiers, changing the top set, without
2649  * having low level display recalc's won't work... this is why dpm notifiers
2650  * work, isr's off, walk a list of clocks already _off_ and not messing with
2651  * the bus.
2652  *
2653  * This clock should have no parent. It embodies the entire upper level
2654  * active set. A parent will mess up some of the init also.
2655  */
2656 static struct clk virt_prcm_set = {
2657         .name           = "virt_prcm_set",
2658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2659                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2660         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2661         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2662         .set_rate       = &omap2_select_table_rate,
2663         .round_rate     = &omap2_round_to_table_rate,
2664 };
2665
2666 static struct clk *onchip_24xx_clks[] __initdata = {
2667         /* external root sources */
2668         &func_32k_ck,
2669         &osc_ck,
2670         &sys_ck,
2671         &alt_ck,
2672         /* internal analog sources */
2673         &dpll_ck,
2674         &apll96_ck,
2675         &apll54_ck,
2676         /* internal prcm root sources */
2677         &func_54m_ck,
2678         &core_ck,
2679         &func_96m_ck,
2680         &func_48m_ck,
2681         &func_12m_ck,
2682         &wdt1_osc_ck,
2683         &sys_clkout_src,
2684         &sys_clkout,
2685         &sys_clkout2_src,
2686         &sys_clkout2,
2687         &emul_ck,
2688         /* mpu domain clocks */
2689         &mpu_ck,
2690         /* dsp domain clocks */
2691         &dsp_fck,
2692         &dsp_irate_ick,
2693         &dsp_ick,               /* 242x */
2694         &iva2_1_ick,            /* 243x */
2695         &iva1_ifck,             /* 242x */
2696         &iva1_mpu_int_ifck,     /* 242x */
2697         /* GFX domain clocks */
2698         &gfx_3d_fck,
2699         &gfx_2d_fck,
2700         &gfx_ick,
2701         /* Modem domain clocks */
2702         &mdm_ick,
2703         &mdm_osc_ck,
2704         /* DSS domain clocks */
2705         &dss_ick,
2706         &dss1_fck,
2707         &dss2_fck,
2708         &dss_54m_fck,
2709         /* L3 domain clocks */
2710         &core_l3_ck,
2711         &ssi_ssr_sst_fck,
2712         &usb_l4_ick,
2713         /* L4 domain clocks */
2714         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2715         &ssi_l4_ick,
2716         /* virtual meta-group clock */
2717         &virt_prcm_set,
2718         /* general l4 interface ck, multi-parent functional clk */
2719         &gpt1_ick,
2720         &gpt1_fck,
2721         &gpt2_ick,
2722         &gpt2_fck,
2723         &gpt3_ick,
2724         &gpt3_fck,
2725         &gpt4_ick,
2726         &gpt4_fck,
2727         &gpt5_ick,
2728         &gpt5_fck,
2729         &gpt6_ick,
2730         &gpt6_fck,
2731         &gpt7_ick,
2732         &gpt7_fck,
2733         &gpt8_ick,
2734         &gpt8_fck,
2735         &gpt9_ick,
2736         &gpt9_fck,
2737         &gpt10_ick,
2738         &gpt10_fck,
2739         &gpt11_ick,
2740         &gpt11_fck,
2741         &gpt12_ick,
2742         &gpt12_fck,
2743         &mcbsp1_ick,
2744         &mcbsp1_fck,
2745         &mcbsp2_ick,
2746         &mcbsp2_fck,
2747         &mcbsp3_ick,
2748         &mcbsp3_fck,
2749         &mcbsp4_ick,
2750         &mcbsp4_fck,
2751         &mcbsp5_ick,
2752         &mcbsp5_fck,
2753         &mcspi1_ick,
2754         &mcspi1_fck,
2755         &mcspi2_ick,
2756         &mcspi2_fck,
2757         &mcspi3_ick,
2758         &mcspi3_fck,
2759         &uart1_ick,
2760         &uart1_fck,
2761         &uart2_ick,
2762         &uart2_fck,
2763         &uart3_ick,
2764         &uart3_fck,
2765         &gpios_ick,
2766         &gpios_fck,
2767         &mpu_wdt_ick,
2768         &mpu_wdt_fck,
2769         &sync_32k_ick,
2770         &wdt1_ick,
2771         &omapctrl_ick,
2772         &icr_ick,
2773         &cam_fck,
2774         &cam_ick,
2775         &mailboxes_ick,
2776         &wdt4_ick,
2777         &wdt4_fck,
2778         &wdt3_ick,
2779         &wdt3_fck,
2780         &mspro_ick,
2781         &mspro_fck,
2782         &mmc_ick,
2783         &mmc_fck,
2784         &fac_ick,
2785         &fac_fck,
2786         &eac_ick,
2787         &eac_fck,
2788         &hdq_ick,
2789         &hdq_fck,
2790         &i2c1_ick,
2791         &i2c1_fck,
2792         &i2chs1_fck,
2793         &i2c2_ick,
2794         &i2c2_fck,
2795         &i2chs2_fck,
2796         &gpmc_fck,
2797         &sdma_fck,
2798         &sdma_ick,
2799         &vlynq_ick,
2800         &vlynq_fck,
2801         &sdrc_ick,
2802         &des_ick,
2803         &sha_ick,
2804         &rng_ick,
2805         &aes_ick,
2806         &pka_ick,
2807         &usb_fck,
2808         &usbhs_ick,
2809         &mmchs1_ick,
2810         &mmchs1_fck,
2811         &mmchs2_ick,
2812         &mmchs2_fck,
2813         &gpio5_ick,
2814         &gpio5_fck,
2815         &mdm_intc_ick,
2816         &mmchsdb1_fck,
2817         &mmchsdb2_fck,
2818 };
2819
2820 #endif
2821