2 * linux/arch/arm/mach-omap2/clock24xx.h
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
23 #include "prm-regbits-24xx.h"
24 #include "cm-regbits-24xx.h"
27 static unsigned long omap2_table_mpu_recalc(struct clk *clk);
28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30 static unsigned long omap2_sys_clk_recalc(struct clk *clk);
31 static unsigned long omap2_osc_clk_recalc(struct clk *clk);
32 static unsigned long omap2_sys_clk_recalc(struct clk *clk);
33 static unsigned long omap2_dpllcore_recalc(struct clk *clk);
34 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
41 unsigned long xtal_speed; /* crystal rate */
42 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
43 unsigned long mpu_speed; /* speed of MPU */
44 unsigned long cm_clksel_mpu; /* mpu divider */
45 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
46 unsigned long cm_clksel_gfx; /* gfx dividers */
47 unsigned long cm_clksel1_core; /* major subsystem dividers */
48 unsigned long cm_clksel1_pll; /* m,n */
49 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
50 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
51 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
56 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
57 * These configurations are characterized by voltage and speed for clocks.
58 * The device is only validated for certain combinations. One way to express
59 * these combinations is via the 'ratio's' which the clocks operate with
60 * respect to each other. These ratio sets are for a given voltage/DPLL
61 * setting. All configurations can be described by a DPLL setting and a ratio
62 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
64 * 2430 differs from 2420 in that there are no more phase synchronizers used.
65 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
66 * 2430 (iva2.1, NOdsp, mdm)
69 /* Core fields for cm_clksel, not ratio governed */
70 #define RX_CLKSEL_DSS1 (0x10 << 8)
71 #define RX_CLKSEL_DSS2 (0x0 << 13)
72 #define RX_CLKSEL_SSI (0x5 << 20)
74 /*-------------------------------------------------------------------------
76 *-------------------------------------------------------------------------*/
78 /* 2430 Ratio's, 2430-Ratio Config 1 */
79 #define R1_CLKSEL_L3 (4 << 0)
80 #define R1_CLKSEL_L4 (2 << 5)
81 #define R1_CLKSEL_USB (4 << 25)
82 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
83 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
84 R1_CLKSEL_L4 | R1_CLKSEL_L3
85 #define R1_CLKSEL_MPU (2 << 0)
86 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
87 #define R1_CLKSEL_DSP (2 << 0)
88 #define R1_CLKSEL_DSP_IF (2 << 5)
89 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
90 #define R1_CLKSEL_GFX (2 << 0)
91 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
92 #define R1_CLKSEL_MDM (4 << 0)
93 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
95 /* 2430-Ratio Config 2 */
96 #define R2_CLKSEL_L3 (6 << 0)
97 #define R2_CLKSEL_L4 (2 << 5)
98 #define R2_CLKSEL_USB (2 << 25)
99 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
100 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
101 R2_CLKSEL_L4 | R2_CLKSEL_L3
102 #define R2_CLKSEL_MPU (2 << 0)
103 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
104 #define R2_CLKSEL_DSP (2 << 0)
105 #define R2_CLKSEL_DSP_IF (3 << 5)
106 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
107 #define R2_CLKSEL_GFX (2 << 0)
108 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
109 #define R2_CLKSEL_MDM (6 << 0)
110 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
112 /* 2430-Ratio Bootm (BYPASS) */
113 #define RB_CLKSEL_L3 (1 << 0)
114 #define RB_CLKSEL_L4 (1 << 5)
115 #define RB_CLKSEL_USB (1 << 25)
116 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
117 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
118 RB_CLKSEL_L4 | RB_CLKSEL_L3
119 #define RB_CLKSEL_MPU (1 << 0)
120 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
121 #define RB_CLKSEL_DSP (1 << 0)
122 #define RB_CLKSEL_DSP_IF (1 << 5)
123 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
124 #define RB_CLKSEL_GFX (1 << 0)
125 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
126 #define RB_CLKSEL_MDM (1 << 0)
127 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
129 /* 2420 Ratio Equivalents */
130 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
131 #define RXX_CLKSEL_SSI (0x8 << 20)
133 /* 2420-PRCM III 532MHz core */
134 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
135 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
136 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
137 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
138 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
139 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
141 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
142 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
143 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
144 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
145 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
146 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
147 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
148 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
149 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
151 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
152 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
154 /* 2420-PRCM II 600MHz core */
155 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
156 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
157 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
158 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
159 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
160 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
161 RII_CLKSEL_L4 | RII_CLKSEL_L3
162 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
163 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
164 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
165 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
166 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
167 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
168 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
169 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
170 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
172 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
173 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
175 /* 2420-PRCM I 660MHz core */
176 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
177 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
178 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
179 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
180 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
181 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
182 RI_CLKSEL_L4 | RI_CLKSEL_L3
183 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
184 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
185 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
186 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
187 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
188 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
189 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
190 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
191 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
193 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
194 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
196 /* 2420-PRCM VII (boot) */
197 #define RVII_CLKSEL_L3 (1 << 0)
198 #define RVII_CLKSEL_L4 (1 << 5)
199 #define RVII_CLKSEL_DSS1 (1 << 8)
200 #define RVII_CLKSEL_DSS2 (0 << 13)
201 #define RVII_CLKSEL_VLYNQ (1 << 15)
202 #define RVII_CLKSEL_SSI (1 << 20)
203 #define RVII_CLKSEL_USB (1 << 25)
205 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
206 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
207 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
209 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
210 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
212 #define RVII_CLKSEL_DSP (1 << 0)
213 #define RVII_CLKSEL_DSP_IF (1 << 5)
214 #define RVII_SYNC_DSP (0 << 7)
215 #define RVII_CLKSEL_IVA (1 << 8)
216 #define RVII_SYNC_IVA (0 << 13)
217 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
218 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
220 #define RVII_CLKSEL_GFX (1 << 0)
221 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
223 /*-------------------------------------------------------------------------
224 * 2430 Target modes: Along with each configuration the CPU has several
225 * modes which goes along with them. Modes mainly are the addition of
226 * describe DPLL combinations to go along with a ratio.
227 *-------------------------------------------------------------------------*/
229 /* Hardware governed */
230 #define MX_48M_SRC (0 << 3)
231 #define MX_54M_SRC (0 << 5)
232 #define MX_APLLS_CLIKIN_12 (3 << 23)
233 #define MX_APLLS_CLIKIN_13 (2 << 23)
234 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
237 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
238 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
240 #define M5A_DPLL_MULT_12 (133 << 12)
241 #define M5A_DPLL_DIV_12 (5 << 8)
242 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
243 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
245 #define M5A_DPLL_MULT_13 (61 << 12)
246 #define M5A_DPLL_DIV_13 (2 << 8)
247 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
248 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
250 #define M5A_DPLL_MULT_19 (55 << 12)
251 #define M5A_DPLL_DIV_19 (3 << 8)
252 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
253 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
255 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
256 #define M5B_DPLL_MULT_12 (50 << 12)
257 #define M5B_DPLL_DIV_12 (2 << 8)
258 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
259 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
261 #define M5B_DPLL_MULT_13 (200 << 12)
262 #define M5B_DPLL_DIV_13 (12 << 8)
264 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
265 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
267 #define M5B_DPLL_MULT_19 (125 << 12)
268 #define M5B_DPLL_DIV_19 (31 << 8)
269 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
270 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
273 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
275 #define M4_DPLL_MULT_12 (133 << 12)
276 #define M4_DPLL_DIV_12 (3 << 8)
277 #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
278 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
281 #define M4_DPLL_MULT_13 (399 << 12)
282 #define M4_DPLL_DIV_13 (12 << 8)
283 #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
284 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
287 #define M4_DPLL_MULT_19 (145 << 12)
288 #define M4_DPLL_DIV_19 (6 << 8)
289 #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
290 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
294 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
296 #define M3_DPLL_MULT_12 (55 << 12)
297 #define M3_DPLL_DIV_12 (1 << 8)
298 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
299 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
301 #define M3_DPLL_MULT_13 (76 << 12)
302 #define M3_DPLL_DIV_13 (2 << 8)
303 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
304 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
306 #define M3_DPLL_MULT_19 (17 << 12)
307 #define M3_DPLL_DIV_19 (0 << 8)
308 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
309 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
313 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
315 #define M2_DPLL_MULT_12 (55 << 12)
316 #define M2_DPLL_DIV_12 (1 << 8)
317 #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
318 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
321 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
322 * relock time issue */
323 /* Core frequency changed from 330/165 to 329/164 MHz*/
324 #define M2_DPLL_MULT_13 (76 << 12)
325 #define M2_DPLL_DIV_13 (2 << 8)
326 #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
327 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
330 #define M2_DPLL_MULT_19 (17 << 12)
331 #define M2_DPLL_DIV_19 (0 << 8)
332 #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
333 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
337 #define MB_DPLL_MULT (1 << 12)
338 #define MB_DPLL_DIV (0 << 8)
339 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
340 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
342 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
343 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
345 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
346 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
349 * 2430 - chassis (sedna)
350 * 165 (ratio1) same as above #2
352 * 133 (ratio2) same as above #4
353 * 110 (ratio2) same as above #3
358 /* PRCM I target DPLL = 2*330MHz = 660MHz */
359 #define MI_DPLL_MULT_12 (55 << 12)
360 #define MI_DPLL_DIV_12 (1 << 8)
361 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
362 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
366 * 2420 Equivalent - mode registers
367 * PRCM II , target DPLL = 2*300MHz = 600MHz
369 #define MII_DPLL_MULT_12 (50 << 12)
370 #define MII_DPLL_DIV_12 (1 << 8)
371 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
372 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
374 #define MII_DPLL_MULT_13 (300 << 12)
375 #define MII_DPLL_DIV_13 (12 << 8)
376 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
377 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
380 /* PRCM III target DPLL = 2*266 = 532MHz*/
381 #define MIII_DPLL_MULT_12 (133 << 12)
382 #define MIII_DPLL_DIV_12 (5 << 8)
383 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
384 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
386 #define MIII_DPLL_MULT_13 (266 << 12)
387 #define MIII_DPLL_DIV_13 (12 << 8)
388 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
389 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
392 /* PRCM VII (boot bypass) */
393 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
394 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
396 /* High and low operation value */
397 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
398 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
400 /* MPU speed defines */
401 #define S12M 12000000
402 #define S13M 13000000
403 #define S19M 19200000
404 #define S26M 26000000
405 #define S100M 100000000
406 #define S133M 133000000
407 #define S150M 150000000
408 #define S164M 164000000
409 #define S165M 165000000
410 #define S199M 199000000
411 #define S200M 200000000
412 #define S266M 266000000
413 #define S300M 300000000
414 #define S329M 329000000
415 #define S330M 330000000
416 #define S399M 399000000
417 #define S400M 400000000
418 #define S532M 532000000
419 #define S600M 600000000
420 #define S658M 658000000
421 #define S660M 660000000
422 #define S798M 798000000
424 /*-------------------------------------------------------------------------
425 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
426 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
427 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
428 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
430 * Filling in table based on H4 boards and 2430-SDPs variants available.
431 * There are quite a few more rates combinations which could be defined.
433 * When multiple values are defined the start up will try and choose the
434 * fastest one. If a 'fast' value is defined, then automatically, the /2
435 * one should be included as it can be used. Generally having more that
436 * one fast set does not make sense, as static timings need to be changed
437 * to change the set. The exception is the bypass setting which is
438 * availble for low power bypass.
440 * Note: This table needs to be sorted, fastest to slowest.
441 *-------------------------------------------------------------------------*/
442 static struct prcm_config rate_table[] = {
444 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
445 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
446 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
447 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
451 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
452 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
453 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
454 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
457 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
458 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
459 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
460 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
463 /* PRCM III - FAST */
464 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
465 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
466 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
470 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
471 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
472 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
473 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
477 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
478 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
479 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
480 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
483 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
484 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
485 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
486 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
489 /* PRCM III - SLOW */
490 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
491 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
492 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
493 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
496 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
497 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
498 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
499 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
502 /* PRCM-VII (boot-bypass) */
503 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
504 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
505 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
506 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
509 /* PRCM-VII (boot-bypass) */
510 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
511 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
512 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
513 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
516 /* PRCM #4 - ratio2 (ES2.1) - FAST */
517 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
518 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
519 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
520 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
521 SDRC_RFR_CTRL_133MHz,
524 /* PRCM #2 - ratio1 (ES2) - FAST */
525 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
526 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
527 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
528 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
529 SDRC_RFR_CTRL_165MHz,
532 /* PRCM #5a - ratio1 - FAST */
533 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
534 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
535 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
536 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
537 SDRC_RFR_CTRL_133MHz,
540 /* PRCM #5b - ratio1 - FAST */
541 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
542 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
543 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
544 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
545 SDRC_RFR_CTRL_100MHz,
548 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
549 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
550 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
551 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
552 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
553 SDRC_RFR_CTRL_133MHz,
556 /* PRCM #2 - ratio1 (ES2) - SLOW */
557 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
558 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
559 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
560 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
561 SDRC_RFR_CTRL_165MHz,
564 /* PRCM #5a - ratio1 - SLOW */
565 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
566 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
567 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
568 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
569 SDRC_RFR_CTRL_133MHz,
572 /* PRCM #5b - ratio1 - SLOW*/
573 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
574 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
575 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
576 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
577 SDRC_RFR_CTRL_100MHz,
580 /* PRCM-boot/bypass */
581 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
582 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
583 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
584 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
585 SDRC_RFR_CTRL_BYPASS,
588 /* PRCM-boot/bypass */
589 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
590 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
591 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
592 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
593 SDRC_RFR_CTRL_BYPASS,
596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
599 /*-------------------------------------------------------------------------
602 * NOTE:In many cases here we are assigning a 'default' parent. In many
603 * cases the parent is selectable. The get/set parent calls will also
606 * Many some clocks say always_enabled, but they can be auto idled for
607 * power savings. They will always be available upon clock request.
609 * Several sources are given initial rates which may be wrong, this will
610 * be fixed up in the init func.
612 * Things are broadly separated below by clock domains. It is
613 * noteworthy that most periferals have dependencies on multiple clock
614 * domains. Many get their interface clocks from the L4 domain, but get
615 * functional clocks from fixed sources or other core domain derived
617 *-------------------------------------------------------------------------*/
619 /* Base external input clocks */
620 static struct clk func_32k_ck = {
621 .name = "func_32k_ck",
625 .clkdm_name = "wkup_clkdm",
628 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
629 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
631 .ops = &clkops_oscck,
632 .clkdm_name = "wkup_clkdm",
633 .recalc = &omap2_osc_clk_recalc,
636 /* Without modem likely 12MHz, with modem likely 13MHz */
637 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
638 .name = "sys_ck", /* ~ ref_clk also */
641 .clkdm_name = "wkup_clkdm",
642 .recalc = &omap2_sys_clk_recalc,
645 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
650 .clkdm_name = "wkup_clkdm",
654 * Analog domain root source clocks
657 /* dpll_ck, is broken out in to special cases through clksel */
658 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
662 static struct dpll_data dpll_dd = {
663 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
664 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
665 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
666 .max_multiplier = 1024,
669 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
673 * XXX Cannot add round_rate here yet, as this is still a composite clock,
676 static struct clk dpll_ck = {
679 .parent = &sys_ck, /* Can be func_32k also */
680 .dpll_data = &dpll_dd,
681 .clkdm_name = "wkup_clkdm",
682 .recalc = &omap2_dpllcore_recalc,
683 .set_rate = &omap2_reprogram_dpllcore,
686 static struct clk apll96_ck = {
688 .ops = &clkops_fixed,
691 .flags = RATE_FIXED | ENABLE_ON_INIT,
692 .clkdm_name = "wkup_clkdm",
693 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
694 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
697 static struct clk apll54_ck = {
699 .ops = &clkops_fixed,
702 .flags = RATE_FIXED | ENABLE_ON_INIT,
703 .clkdm_name = "wkup_clkdm",
704 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
705 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
709 * PRCM digital base sources
714 static const struct clksel_rate func_54m_apll54_rates[] = {
715 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
719 static const struct clksel_rate func_54m_alt_rates[] = {
720 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
724 static const struct clksel func_54m_clksel[] = {
725 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
726 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
730 static struct clk func_54m_ck = {
731 .name = "func_54m_ck",
733 .parent = &apll54_ck, /* can also be alt_clk */
734 .clkdm_name = "wkup_clkdm",
735 .init = &omap2_init_clksel_parent,
736 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
737 .clksel_mask = OMAP24XX_54M_SOURCE,
738 .clksel = func_54m_clksel,
739 .recalc = &omap2_clksel_recalc,
742 static struct clk core_ck = {
745 .parent = &dpll_ck, /* can also be 32k */
746 .clkdm_name = "wkup_clkdm",
747 .recalc = &followparent_recalc,
751 static const struct clksel_rate func_96m_apll96_rates[] = {
752 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
756 static const struct clksel_rate func_96m_alt_rates[] = {
757 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
761 static const struct clksel func_96m_clksel[] = {
762 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
763 { .parent = &alt_ck, .rates = func_96m_alt_rates },
767 /* The parent of this clock is not selectable on 2420. */
768 static struct clk func_96m_ck = {
769 .name = "func_96m_ck",
771 .parent = &apll96_ck,
772 .clkdm_name = "wkup_clkdm",
773 .init = &omap2_init_clksel_parent,
774 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
775 .clksel_mask = OMAP2430_96M_SOURCE,
776 .clksel = func_96m_clksel,
777 .recalc = &omap2_clksel_recalc,
778 .round_rate = &omap2_clksel_round_rate,
779 .set_rate = &omap2_clksel_set_rate
784 static const struct clksel_rate func_48m_apll96_rates[] = {
785 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
789 static const struct clksel_rate func_48m_alt_rates[] = {
790 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
794 static const struct clksel func_48m_clksel[] = {
795 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
796 { .parent = &alt_ck, .rates = func_48m_alt_rates },
800 static struct clk func_48m_ck = {
801 .name = "func_48m_ck",
803 .parent = &apll96_ck, /* 96M or Alt */
804 .clkdm_name = "wkup_clkdm",
805 .init = &omap2_init_clksel_parent,
806 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
807 .clksel_mask = OMAP24XX_48M_SOURCE,
808 .clksel = func_48m_clksel,
809 .recalc = &omap2_clksel_recalc,
810 .round_rate = &omap2_clksel_round_rate,
811 .set_rate = &omap2_clksel_set_rate
814 static struct clk func_12m_ck = {
815 .name = "func_12m_ck",
817 .parent = &func_48m_ck,
819 .clkdm_name = "wkup_clkdm",
820 .recalc = &omap2_fixed_divisor_recalc,
823 /* Secure timer, only available in secure mode */
824 static struct clk wdt1_osc_ck = {
825 .name = "ck_wdt1_osc",
826 .ops = &clkops_null, /* RMK: missing? */
828 .recalc = &followparent_recalc,
832 * The common_clkout* clksel_rate structs are common to
833 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
834 * sys_clkout2_* are 2420-only, so the
835 * clksel_rate flags fields are inaccurate for those clocks. This is
836 * harmless since access to those clocks are gated by the struct clk
837 * flags fields, which mark them as 2420-only.
839 static const struct clksel_rate common_clkout_src_core_rates[] = {
840 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
844 static const struct clksel_rate common_clkout_src_sys_rates[] = {
845 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
849 static const struct clksel_rate common_clkout_src_96m_rates[] = {
850 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
854 static const struct clksel_rate common_clkout_src_54m_rates[] = {
855 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
859 static const struct clksel common_clkout_src_clksel[] = {
860 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
861 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
862 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
863 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
867 static struct clk sys_clkout_src = {
868 .name = "sys_clkout_src",
869 .ops = &clkops_omap2_dflt,
870 .parent = &func_54m_ck,
871 .clkdm_name = "wkup_clkdm",
872 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
873 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
874 .init = &omap2_init_clksel_parent,
875 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
876 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
877 .clksel = common_clkout_src_clksel,
878 .recalc = &omap2_clksel_recalc,
879 .round_rate = &omap2_clksel_round_rate,
880 .set_rate = &omap2_clksel_set_rate
883 static const struct clksel_rate common_clkout_rates[] = {
884 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
885 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
886 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
887 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
888 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
892 static const struct clksel sys_clkout_clksel[] = {
893 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
897 static struct clk sys_clkout = {
898 .name = "sys_clkout",
900 .parent = &sys_clkout_src,
901 .clkdm_name = "wkup_clkdm",
902 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
903 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
904 .clksel = sys_clkout_clksel,
905 .recalc = &omap2_clksel_recalc,
906 .round_rate = &omap2_clksel_round_rate,
907 .set_rate = &omap2_clksel_set_rate
910 /* In 2430, new in 2420 ES2 */
911 static struct clk sys_clkout2_src = {
912 .name = "sys_clkout2_src",
913 .ops = &clkops_omap2_dflt,
914 .parent = &func_54m_ck,
915 .clkdm_name = "wkup_clkdm",
916 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
917 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
918 .init = &omap2_init_clksel_parent,
919 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
920 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
921 .clksel = common_clkout_src_clksel,
922 .recalc = &omap2_clksel_recalc,
923 .round_rate = &omap2_clksel_round_rate,
924 .set_rate = &omap2_clksel_set_rate
927 static const struct clksel sys_clkout2_clksel[] = {
928 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
932 /* In 2430, new in 2420 ES2 */
933 static struct clk sys_clkout2 = {
934 .name = "sys_clkout2",
936 .parent = &sys_clkout2_src,
937 .clkdm_name = "wkup_clkdm",
938 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
939 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
940 .clksel = sys_clkout2_clksel,
941 .recalc = &omap2_clksel_recalc,
942 .round_rate = &omap2_clksel_round_rate,
943 .set_rate = &omap2_clksel_set_rate
946 static struct clk emul_ck = {
948 .ops = &clkops_omap2_dflt,
949 .parent = &func_54m_ck,
950 .clkdm_name = "wkup_clkdm",
951 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
952 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
953 .recalc = &followparent_recalc,
961 * INT_M_FCLK, INT_M_I_CLK
963 * - Individual clocks are hardware managed.
964 * - Base divider comes from: CM_CLKSEL_MPU
967 static const struct clksel_rate mpu_core_rates[] = {
968 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
969 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
970 { .div = 4, .val = 4, .flags = RATE_IN_242X },
971 { .div = 6, .val = 6, .flags = RATE_IN_242X },
972 { .div = 8, .val = 8, .flags = RATE_IN_242X },
976 static const struct clksel mpu_clksel[] = {
977 { .parent = &core_ck, .rates = mpu_core_rates },
981 static struct clk mpu_ck = { /* Control cpu */
985 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
986 .clkdm_name = "mpu_clkdm",
987 .init = &omap2_init_clksel_parent,
988 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
989 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
990 .clksel = mpu_clksel,
991 .recalc = &omap2_clksel_recalc,
992 .round_rate = &omap2_clksel_round_rate,
993 .set_rate = &omap2_clksel_set_rate
997 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
999 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1000 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1002 * Won't be too specific here. The core clock comes into this block
1003 * it is divided then tee'ed. One branch goes directly to xyz enable
1004 * controls. The other branch gets further divided by 2 then possibly
1005 * routed into a synchronizer and out of clocks abc.
1007 static const struct clksel_rate dsp_fck_core_rates[] = {
1008 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1009 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1010 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1011 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1012 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1013 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1014 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1018 static const struct clksel dsp_fck_clksel[] = {
1019 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1023 static struct clk dsp_fck = {
1025 .ops = &clkops_omap2_dflt_wait,
1027 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1028 .clkdm_name = "dsp_clkdm",
1029 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1030 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1031 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1032 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1033 .clksel = dsp_fck_clksel,
1034 .recalc = &omap2_clksel_recalc,
1035 .round_rate = &omap2_clksel_round_rate,
1036 .set_rate = &omap2_clksel_set_rate
1039 /* DSP interface clock */
1040 static const struct clksel_rate dsp_irate_ick_rates[] = {
1041 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1042 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1043 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1047 static const struct clksel dsp_irate_ick_clksel[] = {
1048 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1052 /* This clock does not exist as such in the TRM. */
1053 static struct clk dsp_irate_ick = {
1054 .name = "dsp_irate_ick",
1055 .ops = &clkops_null,
1057 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1058 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1059 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1060 .clksel = dsp_irate_ick_clksel,
1061 .recalc = &omap2_clksel_recalc,
1062 .round_rate = &omap2_clksel_round_rate,
1063 .set_rate = &omap2_clksel_set_rate
1067 static struct clk dsp_ick = {
1068 .name = "dsp_ick", /* apparently ipi and isp */
1069 .ops = &clkops_omap2_dflt_wait,
1070 .parent = &dsp_irate_ick,
1071 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1072 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1073 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1076 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1077 static struct clk iva2_1_ick = {
1078 .name = "iva2_1_ick",
1079 .ops = &clkops_omap2_dflt_wait,
1080 .parent = &dsp_irate_ick,
1081 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1082 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1083 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1087 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1088 * the C54x, but which is contained in the DSP powerdomain. Does not
1089 * exist on later OMAPs.
1091 static struct clk iva1_ifck = {
1092 .name = "iva1_ifck",
1093 .ops = &clkops_omap2_dflt_wait,
1095 .flags = CONFIG_PARTICIPANT | DELAYED_APP,
1096 .clkdm_name = "iva1_clkdm",
1097 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1098 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1099 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1100 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1101 .clksel = dsp_fck_clksel,
1102 .recalc = &omap2_clksel_recalc,
1103 .round_rate = &omap2_clksel_round_rate,
1104 .set_rate = &omap2_clksel_set_rate
1107 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1108 static struct clk iva1_mpu_int_ifck = {
1109 .name = "iva1_mpu_int_ifck",
1110 .ops = &clkops_omap2_dflt_wait,
1111 .parent = &iva1_ifck,
1112 .clkdm_name = "iva1_clkdm",
1113 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1114 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1116 .recalc = &omap2_fixed_divisor_recalc,
1121 * L3 clocks are used for both interface and functional clocks to
1122 * multiple entities. Some of these clocks are completely managed
1123 * by hardware, and some others allow software control. Hardware
1124 * managed ones general are based on directly CLK_REQ signals and
1125 * various auto idle settings. The functional spec sets many of these
1126 * as 'tie-high' for their enables.
1129 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1134 * GPMC memories and SDRC have timing and clock sensitive registers which
1135 * may very well need notification when the clock changes. Currently for low
1136 * operating points, these are taken care of in sleep.S.
1138 static const struct clksel_rate core_l3_core_rates[] = {
1139 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1140 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1141 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1142 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1143 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1144 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1145 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1149 static const struct clksel core_l3_clksel[] = {
1150 { .parent = &core_ck, .rates = core_l3_core_rates },
1154 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1155 .name = "core_l3_ck",
1156 .ops = &clkops_null,
1158 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1159 .clkdm_name = "core_l3_clkdm",
1160 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1161 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1162 .clksel = core_l3_clksel,
1163 .recalc = &omap2_clksel_recalc,
1164 .round_rate = &omap2_clksel_round_rate,
1165 .set_rate = &omap2_clksel_set_rate
1169 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1170 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1171 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1172 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1176 static const struct clksel usb_l4_ick_clksel[] = {
1177 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1181 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1182 static struct clk usb_l4_ick = { /* FS-USB interface clock */
1183 .name = "usb_l4_ick",
1184 .ops = &clkops_omap2_dflt_wait,
1185 .parent = &core_l3_ck,
1186 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1187 .clkdm_name = "core_l4_clkdm",
1188 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1189 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1190 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1191 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1192 .clksel = usb_l4_ick_clksel,
1193 .recalc = &omap2_clksel_recalc,
1194 .round_rate = &omap2_clksel_round_rate,
1195 .set_rate = &omap2_clksel_set_rate
1199 * L4 clock management domain
1201 * This domain contains lots of interface clocks from the L4 interface, some
1202 * functional clocks. Fixed APLL functional source clocks are managed in
1205 static const struct clksel_rate l4_core_l3_rates[] = {
1206 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1207 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1211 static const struct clksel l4_clksel[] = {
1212 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1216 static struct clk l4_ck = { /* used both as an ick and fck */
1218 .ops = &clkops_null,
1219 .parent = &core_l3_ck,
1220 .flags = DELAYED_APP,
1221 .clkdm_name = "core_l4_clkdm",
1222 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1223 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1224 .clksel = l4_clksel,
1225 .recalc = &omap2_clksel_recalc,
1226 .round_rate = &omap2_clksel_round_rate,
1227 .set_rate = &omap2_clksel_set_rate
1231 * SSI is in L3 management domain, its direct parent is core not l3,
1232 * many core power domain entities are grouped into the L3 clock
1234 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1236 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1238 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1239 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1240 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1241 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1242 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1243 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1244 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1245 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1249 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1250 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1254 static struct clk ssi_ssr_sst_fck = {
1256 .ops = &clkops_omap2_dflt_wait,
1258 .flags = DELAYED_APP,
1259 .clkdm_name = "core_l3_clkdm",
1260 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1261 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1262 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1263 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1264 .clksel = ssi_ssr_sst_fck_clksel,
1265 .recalc = &omap2_clksel_recalc,
1266 .round_rate = &omap2_clksel_round_rate,
1267 .set_rate = &omap2_clksel_set_rate
1271 * Presumably this is the same as SSI_ICLK.
1272 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1274 static struct clk ssi_l4_ick = {
1275 .name = "ssi_l4_ick",
1276 .ops = &clkops_omap2_dflt_wait,
1278 .clkdm_name = "core_l4_clkdm",
1279 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1280 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1281 .recalc = &followparent_recalc,
1288 * GFX_FCLK, GFX_ICLK
1289 * GFX_CG1(2d), GFX_CG2(3d)
1291 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1292 * The 2d and 3d clocks run at a hardware determined
1293 * divided value of fclk.
1296 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1298 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1299 static const struct clksel gfx_fck_clksel[] = {
1300 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1304 static struct clk gfx_3d_fck = {
1305 .name = "gfx_3d_fck",
1306 .ops = &clkops_omap2_dflt_wait,
1307 .parent = &core_l3_ck,
1308 .clkdm_name = "gfx_clkdm",
1309 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1310 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1311 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1312 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1313 .clksel = gfx_fck_clksel,
1314 .recalc = &omap2_clksel_recalc,
1315 .round_rate = &omap2_clksel_round_rate,
1316 .set_rate = &omap2_clksel_set_rate
1319 static struct clk gfx_2d_fck = {
1320 .name = "gfx_2d_fck",
1321 .ops = &clkops_omap2_dflt_wait,
1322 .parent = &core_l3_ck,
1323 .clkdm_name = "gfx_clkdm",
1324 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1325 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1326 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1327 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1328 .clksel = gfx_fck_clksel,
1329 .recalc = &omap2_clksel_recalc,
1330 .round_rate = &omap2_clksel_round_rate,
1331 .set_rate = &omap2_clksel_set_rate
1334 static struct clk gfx_ick = {
1335 .name = "gfx_ick", /* From l3 */
1336 .ops = &clkops_omap2_dflt_wait,
1337 .parent = &core_l3_ck,
1338 .clkdm_name = "gfx_clkdm",
1339 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1340 .enable_bit = OMAP_EN_GFX_SHIFT,
1341 .recalc = &followparent_recalc,
1345 * Modem clock domain (2430)
1349 * These clocks are usable in chassis mode only.
1351 static const struct clksel_rate mdm_ick_core_rates[] = {
1352 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1353 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1354 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1355 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1359 static const struct clksel mdm_ick_clksel[] = {
1360 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1364 static struct clk mdm_ick = { /* used both as a ick and fck */
1366 .ops = &clkops_omap2_dflt_wait,
1368 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1369 .clkdm_name = "mdm_clkdm",
1370 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1371 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1372 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1373 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1374 .clksel = mdm_ick_clksel,
1375 .recalc = &omap2_clksel_recalc,
1376 .round_rate = &omap2_clksel_round_rate,
1377 .set_rate = &omap2_clksel_set_rate
1380 static struct clk mdm_osc_ck = {
1381 .name = "mdm_osc_ck",
1382 .ops = &clkops_omap2_dflt_wait,
1384 .clkdm_name = "mdm_clkdm",
1385 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1386 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1387 .recalc = &followparent_recalc,
1393 * DSS_L4_ICLK, DSS_L3_ICLK,
1394 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1396 * DSS is both initiator and target.
1398 /* XXX Add RATE_NOT_VALIDATED */
1400 static const struct clksel_rate dss1_fck_sys_rates[] = {
1401 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1405 static const struct clksel_rate dss1_fck_core_rates[] = {
1406 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1407 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1408 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1409 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1410 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1411 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1412 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1413 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1414 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1415 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1419 static const struct clksel dss1_fck_clksel[] = {
1420 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1421 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1425 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1427 .ops = &clkops_omap2_dflt,
1428 .parent = &l4_ck, /* really both l3 and l4 */
1429 .clkdm_name = "dss_clkdm",
1430 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1431 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1432 .recalc = &followparent_recalc,
1435 static struct clk dss1_fck = {
1437 .ops = &clkops_omap2_dflt,
1438 .parent = &core_ck, /* Core or sys */
1439 .flags = DELAYED_APP,
1440 .clkdm_name = "dss_clkdm",
1441 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1442 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1443 .init = &omap2_init_clksel_parent,
1444 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1445 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1446 .clksel = dss1_fck_clksel,
1447 .recalc = &omap2_clksel_recalc,
1448 .round_rate = &omap2_clksel_round_rate,
1449 .set_rate = &omap2_clksel_set_rate
1452 static const struct clksel_rate dss2_fck_sys_rates[] = {
1453 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1457 static const struct clksel_rate dss2_fck_48m_rates[] = {
1458 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1462 static const struct clksel dss2_fck_clksel[] = {
1463 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1464 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1468 static struct clk dss2_fck = { /* Alt clk used in power management */
1470 .ops = &clkops_omap2_dflt,
1471 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1472 .flags = DELAYED_APP,
1473 .clkdm_name = "dss_clkdm",
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1476 .init = &omap2_init_clksel_parent,
1477 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1478 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1479 .clksel = dss2_fck_clksel,
1480 .recalc = &followparent_recalc,
1483 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1484 .name = "dss_54m_fck", /* 54m tv clk */
1485 .ops = &clkops_omap2_dflt_wait,
1486 .parent = &func_54m_ck,
1487 .clkdm_name = "dss_clkdm",
1488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1489 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1490 .recalc = &followparent_recalc,
1494 * CORE power domain ICLK & FCLK defines.
1495 * Many of the these can have more than one possible parent. Entries
1496 * here will likely have an L4 interface parent, and may have multiple
1497 * functional clock parents.
1499 static const struct clksel_rate gpt_alt_rates[] = {
1500 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1504 static const struct clksel omap24xx_gpt_clksel[] = {
1505 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1506 { .parent = &sys_ck, .rates = gpt_sys_rates },
1507 { .parent = &alt_ck, .rates = gpt_alt_rates },
1511 static struct clk gpt1_ick = {
1513 .ops = &clkops_omap2_dflt_wait,
1515 .clkdm_name = "core_l4_clkdm",
1516 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1517 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1518 .recalc = &followparent_recalc,
1521 static struct clk gpt1_fck = {
1523 .ops = &clkops_omap2_dflt_wait,
1524 .parent = &func_32k_ck,
1525 .clkdm_name = "core_l4_clkdm",
1526 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1527 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1528 .init = &omap2_init_clksel_parent,
1529 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1530 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1531 .clksel = omap24xx_gpt_clksel,
1532 .recalc = &omap2_clksel_recalc,
1533 .round_rate = &omap2_clksel_round_rate,
1534 .set_rate = &omap2_clksel_set_rate
1537 static struct clk gpt2_ick = {
1539 .ops = &clkops_omap2_dflt_wait,
1541 .clkdm_name = "core_l4_clkdm",
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1543 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1544 .recalc = &followparent_recalc,
1547 static struct clk gpt2_fck = {
1549 .ops = &clkops_omap2_dflt_wait,
1550 .parent = &func_32k_ck,
1551 .clkdm_name = "core_l4_clkdm",
1552 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1553 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1554 .init = &omap2_init_clksel_parent,
1555 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1556 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1557 .clksel = omap24xx_gpt_clksel,
1558 .recalc = &omap2_clksel_recalc,
1561 static struct clk gpt3_ick = {
1563 .ops = &clkops_omap2_dflt_wait,
1565 .clkdm_name = "core_l4_clkdm",
1566 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1567 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1568 .recalc = &followparent_recalc,
1571 static struct clk gpt3_fck = {
1573 .ops = &clkops_omap2_dflt_wait,
1574 .parent = &func_32k_ck,
1575 .clkdm_name = "core_l4_clkdm",
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1578 .init = &omap2_init_clksel_parent,
1579 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1580 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1581 .clksel = omap24xx_gpt_clksel,
1582 .recalc = &omap2_clksel_recalc,
1585 static struct clk gpt4_ick = {
1587 .ops = &clkops_omap2_dflt_wait,
1589 .clkdm_name = "core_l4_clkdm",
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1591 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1592 .recalc = &followparent_recalc,
1595 static struct clk gpt4_fck = {
1597 .ops = &clkops_omap2_dflt_wait,
1598 .parent = &func_32k_ck,
1599 .clkdm_name = "core_l4_clkdm",
1600 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1601 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1602 .init = &omap2_init_clksel_parent,
1603 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1604 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1605 .clksel = omap24xx_gpt_clksel,
1606 .recalc = &omap2_clksel_recalc,
1609 static struct clk gpt5_ick = {
1611 .ops = &clkops_omap2_dflt_wait,
1613 .clkdm_name = "core_l4_clkdm",
1614 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1615 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1616 .recalc = &followparent_recalc,
1619 static struct clk gpt5_fck = {
1621 .ops = &clkops_omap2_dflt_wait,
1622 .parent = &func_32k_ck,
1623 .clkdm_name = "core_l4_clkdm",
1624 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1625 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1626 .init = &omap2_init_clksel_parent,
1627 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1628 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1629 .clksel = omap24xx_gpt_clksel,
1630 .recalc = &omap2_clksel_recalc,
1633 static struct clk gpt6_ick = {
1635 .ops = &clkops_omap2_dflt_wait,
1637 .clkdm_name = "core_l4_clkdm",
1638 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1639 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1640 .recalc = &followparent_recalc,
1643 static struct clk gpt6_fck = {
1645 .ops = &clkops_omap2_dflt_wait,
1646 .parent = &func_32k_ck,
1647 .clkdm_name = "core_l4_clkdm",
1648 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1649 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1650 .init = &omap2_init_clksel_parent,
1651 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1652 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1653 .clksel = omap24xx_gpt_clksel,
1654 .recalc = &omap2_clksel_recalc,
1657 static struct clk gpt7_ick = {
1659 .ops = &clkops_omap2_dflt_wait,
1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1662 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1663 .recalc = &followparent_recalc,
1666 static struct clk gpt7_fck = {
1668 .ops = &clkops_omap2_dflt_wait,
1669 .parent = &func_32k_ck,
1670 .clkdm_name = "core_l4_clkdm",
1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1672 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1673 .init = &omap2_init_clksel_parent,
1674 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1675 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1676 .clksel = omap24xx_gpt_clksel,
1677 .recalc = &omap2_clksel_recalc,
1680 static struct clk gpt8_ick = {
1682 .ops = &clkops_omap2_dflt_wait,
1684 .clkdm_name = "core_l4_clkdm",
1685 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1686 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1687 .recalc = &followparent_recalc,
1690 static struct clk gpt8_fck = {
1692 .ops = &clkops_omap2_dflt_wait,
1693 .parent = &func_32k_ck,
1694 .clkdm_name = "core_l4_clkdm",
1695 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1696 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1697 .init = &omap2_init_clksel_parent,
1698 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1699 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1700 .clksel = omap24xx_gpt_clksel,
1701 .recalc = &omap2_clksel_recalc,
1704 static struct clk gpt9_ick = {
1706 .ops = &clkops_omap2_dflt_wait,
1708 .clkdm_name = "core_l4_clkdm",
1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1710 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1711 .recalc = &followparent_recalc,
1714 static struct clk gpt9_fck = {
1716 .ops = &clkops_omap2_dflt_wait,
1717 .parent = &func_32k_ck,
1718 .clkdm_name = "core_l4_clkdm",
1719 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1720 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1721 .init = &omap2_init_clksel_parent,
1722 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1723 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1724 .clksel = omap24xx_gpt_clksel,
1725 .recalc = &omap2_clksel_recalc,
1728 static struct clk gpt10_ick = {
1729 .name = "gpt10_ick",
1730 .ops = &clkops_omap2_dflt_wait,
1732 .clkdm_name = "core_l4_clkdm",
1733 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1734 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1735 .recalc = &followparent_recalc,
1738 static struct clk gpt10_fck = {
1739 .name = "gpt10_fck",
1740 .ops = &clkops_omap2_dflt_wait,
1741 .parent = &func_32k_ck,
1742 .clkdm_name = "core_l4_clkdm",
1743 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1744 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1745 .init = &omap2_init_clksel_parent,
1746 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1747 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1748 .clksel = omap24xx_gpt_clksel,
1749 .recalc = &omap2_clksel_recalc,
1752 static struct clk gpt11_ick = {
1753 .name = "gpt11_ick",
1754 .ops = &clkops_omap2_dflt_wait,
1756 .clkdm_name = "core_l4_clkdm",
1757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1759 .recalc = &followparent_recalc,
1762 static struct clk gpt11_fck = {
1763 .name = "gpt11_fck",
1764 .ops = &clkops_omap2_dflt_wait,
1765 .parent = &func_32k_ck,
1766 .clkdm_name = "core_l4_clkdm",
1767 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1768 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1769 .init = &omap2_init_clksel_parent,
1770 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1771 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1772 .clksel = omap24xx_gpt_clksel,
1773 .recalc = &omap2_clksel_recalc,
1776 static struct clk gpt12_ick = {
1777 .name = "gpt12_ick",
1778 .ops = &clkops_omap2_dflt_wait,
1780 .clkdm_name = "core_l4_clkdm",
1781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1782 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1783 .recalc = &followparent_recalc,
1786 static struct clk gpt12_fck = {
1787 .name = "gpt12_fck",
1788 .ops = &clkops_omap2_dflt_wait,
1789 .parent = &func_32k_ck,
1790 .clkdm_name = "core_l4_clkdm",
1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1792 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1793 .init = &omap2_init_clksel_parent,
1794 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1795 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1796 .clksel = omap24xx_gpt_clksel,
1797 .recalc = &omap2_clksel_recalc,
1800 static struct clk mcbsp1_ick = {
1801 .name = "mcbsp_ick",
1802 .ops = &clkops_omap2_dflt_wait,
1805 .clkdm_name = "core_l4_clkdm",
1806 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1807 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1808 .recalc = &followparent_recalc,
1811 static struct clk mcbsp1_fck = {
1812 .name = "mcbsp_fck",
1813 .ops = &clkops_omap2_dflt_wait,
1815 .parent = &func_96m_ck,
1816 .clkdm_name = "core_l4_clkdm",
1817 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1818 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1819 .recalc = &followparent_recalc,
1822 static struct clk mcbsp2_ick = {
1823 .name = "mcbsp_ick",
1824 .ops = &clkops_omap2_dflt_wait,
1827 .clkdm_name = "core_l4_clkdm",
1828 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1830 .recalc = &followparent_recalc,
1833 static struct clk mcbsp2_fck = {
1834 .name = "mcbsp_fck",
1835 .ops = &clkops_omap2_dflt_wait,
1837 .parent = &func_96m_ck,
1838 .clkdm_name = "core_l4_clkdm",
1839 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1840 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1841 .recalc = &followparent_recalc,
1844 static struct clk mcbsp3_ick = {
1845 .name = "mcbsp_ick",
1846 .ops = &clkops_omap2_dflt_wait,
1849 .clkdm_name = "core_l4_clkdm",
1850 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1851 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1852 .recalc = &followparent_recalc,
1855 static struct clk mcbsp3_fck = {
1856 .name = "mcbsp_fck",
1857 .ops = &clkops_omap2_dflt_wait,
1859 .parent = &func_96m_ck,
1860 .clkdm_name = "core_l4_clkdm",
1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1862 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1863 .recalc = &followparent_recalc,
1866 static struct clk mcbsp4_ick = {
1867 .name = "mcbsp_ick",
1868 .ops = &clkops_omap2_dflt_wait,
1871 .clkdm_name = "core_l4_clkdm",
1872 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1873 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1874 .recalc = &followparent_recalc,
1877 static struct clk mcbsp4_fck = {
1878 .name = "mcbsp_fck",
1879 .ops = &clkops_omap2_dflt_wait,
1881 .parent = &func_96m_ck,
1882 .clkdm_name = "core_l4_clkdm",
1883 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1884 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1885 .recalc = &followparent_recalc,
1888 static struct clk mcbsp5_ick = {
1889 .name = "mcbsp_ick",
1890 .ops = &clkops_omap2_dflt_wait,
1893 .clkdm_name = "core_l4_clkdm",
1894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1895 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1896 .recalc = &followparent_recalc,
1899 static struct clk mcbsp5_fck = {
1900 .name = "mcbsp_fck",
1901 .ops = &clkops_omap2_dflt_wait,
1903 .parent = &func_96m_ck,
1904 .clkdm_name = "core_l4_clkdm",
1905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1906 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1907 .recalc = &followparent_recalc,
1910 static struct clk mcspi1_ick = {
1911 .name = "mcspi_ick",
1912 .ops = &clkops_omap2_dflt_wait,
1915 .clkdm_name = "core_l4_clkdm",
1916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1917 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1918 .recalc = &followparent_recalc,
1921 static struct clk mcspi1_fck = {
1922 .name = "mcspi_fck",
1923 .ops = &clkops_omap2_dflt_wait,
1925 .parent = &func_48m_ck,
1926 .clkdm_name = "core_l4_clkdm",
1927 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1928 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1929 .recalc = &followparent_recalc,
1932 static struct clk mcspi2_ick = {
1933 .name = "mcspi_ick",
1934 .ops = &clkops_omap2_dflt_wait,
1937 .clkdm_name = "core_l4_clkdm",
1938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1940 .recalc = &followparent_recalc,
1943 static struct clk mcspi2_fck = {
1944 .name = "mcspi_fck",
1945 .ops = &clkops_omap2_dflt_wait,
1947 .parent = &func_48m_ck,
1948 .clkdm_name = "core_l4_clkdm",
1949 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1950 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1951 .recalc = &followparent_recalc,
1954 static struct clk mcspi3_ick = {
1955 .name = "mcspi_ick",
1956 .ops = &clkops_omap2_dflt_wait,
1959 .clkdm_name = "core_l4_clkdm",
1960 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1961 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1962 .recalc = &followparent_recalc,
1965 static struct clk mcspi3_fck = {
1966 .name = "mcspi_fck",
1967 .ops = &clkops_omap2_dflt_wait,
1969 .parent = &func_48m_ck,
1970 .clkdm_name = "core_l4_clkdm",
1971 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1972 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1973 .recalc = &followparent_recalc,
1976 static struct clk uart1_ick = {
1977 .name = "uart1_ick",
1978 .ops = &clkops_omap2_dflt_wait,
1980 .clkdm_name = "core_l4_clkdm",
1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1982 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1983 .recalc = &followparent_recalc,
1986 static struct clk uart1_fck = {
1987 .name = "uart1_fck",
1988 .ops = &clkops_omap2_dflt_wait,
1989 .parent = &func_48m_ck,
1990 .clkdm_name = "core_l4_clkdm",
1991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1992 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1993 .recalc = &followparent_recalc,
1996 static struct clk uart2_ick = {
1997 .name = "uart2_ick",
1998 .ops = &clkops_omap2_dflt_wait,
2000 .clkdm_name = "core_l4_clkdm",
2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2002 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2003 .recalc = &followparent_recalc,
2006 static struct clk uart2_fck = {
2007 .name = "uart2_fck",
2008 .ops = &clkops_omap2_dflt_wait,
2009 .parent = &func_48m_ck,
2010 .clkdm_name = "core_l4_clkdm",
2011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2012 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2013 .recalc = &followparent_recalc,
2016 static struct clk uart3_ick = {
2017 .name = "uart3_ick",
2018 .ops = &clkops_omap2_dflt_wait,
2020 .clkdm_name = "core_l4_clkdm",
2021 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2022 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2023 .recalc = &followparent_recalc,
2026 static struct clk uart3_fck = {
2027 .name = "uart3_fck",
2028 .ops = &clkops_omap2_dflt_wait,
2029 .parent = &func_48m_ck,
2030 .clkdm_name = "core_l4_clkdm",
2031 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2032 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2033 .recalc = &followparent_recalc,
2036 static struct clk gpios_ick = {
2037 .name = "gpios_ick",
2038 .ops = &clkops_omap2_dflt_wait,
2040 .clkdm_name = "core_l4_clkdm",
2041 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2042 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2043 .recalc = &followparent_recalc,
2046 static struct clk gpios_fck = {
2047 .name = "gpios_fck",
2048 .ops = &clkops_omap2_dflt_wait,
2049 .parent = &func_32k_ck,
2050 .clkdm_name = "wkup_clkdm",
2051 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2052 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2053 .recalc = &followparent_recalc,
2056 static struct clk mpu_wdt_ick = {
2057 .name = "mpu_wdt_ick",
2058 .ops = &clkops_omap2_dflt_wait,
2060 .clkdm_name = "core_l4_clkdm",
2061 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2062 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2063 .recalc = &followparent_recalc,
2066 static struct clk mpu_wdt_fck = {
2067 .name = "mpu_wdt_fck",
2068 .ops = &clkops_omap2_dflt_wait,
2069 .parent = &func_32k_ck,
2070 .clkdm_name = "wkup_clkdm",
2071 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2072 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2073 .recalc = &followparent_recalc,
2076 static struct clk sync_32k_ick = {
2077 .name = "sync_32k_ick",
2078 .ops = &clkops_omap2_dflt_wait,
2080 .flags = ENABLE_ON_INIT,
2081 .clkdm_name = "core_l4_clkdm",
2082 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2083 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2084 .recalc = &followparent_recalc,
2087 static struct clk wdt1_ick = {
2089 .ops = &clkops_omap2_dflt_wait,
2091 .clkdm_name = "core_l4_clkdm",
2092 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2093 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2094 .recalc = &followparent_recalc,
2097 static struct clk omapctrl_ick = {
2098 .name = "omapctrl_ick",
2099 .ops = &clkops_omap2_dflt_wait,
2101 .flags = ENABLE_ON_INIT,
2102 .clkdm_name = "core_l4_clkdm",
2103 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2104 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2105 .recalc = &followparent_recalc,
2108 static struct clk icr_ick = {
2110 .ops = &clkops_omap2_dflt_wait,
2112 .clkdm_name = "core_l4_clkdm",
2113 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2114 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2115 .recalc = &followparent_recalc,
2118 static struct clk cam_ick = {
2120 .ops = &clkops_omap2_dflt,
2122 .clkdm_name = "core_l4_clkdm",
2123 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2124 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2125 .recalc = &followparent_recalc,
2129 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2130 * split into two separate clocks, since the parent clocks are different
2131 * and the clockdomains are also different.
2133 static struct clk cam_fck = {
2135 .ops = &clkops_omap2_dflt,
2136 .parent = &func_96m_ck,
2137 .clkdm_name = "core_l3_clkdm",
2138 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2139 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2140 .recalc = &followparent_recalc,
2143 static struct clk mailboxes_ick = {
2144 .name = "mailboxes_ick",
2145 .ops = &clkops_omap2_dflt_wait,
2147 .clkdm_name = "core_l4_clkdm",
2148 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2149 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2150 .recalc = &followparent_recalc,
2153 static struct clk wdt4_ick = {
2155 .ops = &clkops_omap2_dflt_wait,
2157 .clkdm_name = "core_l4_clkdm",
2158 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2159 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2160 .recalc = &followparent_recalc,
2163 static struct clk wdt4_fck = {
2165 .ops = &clkops_omap2_dflt_wait,
2166 .parent = &func_32k_ck,
2167 .clkdm_name = "core_l4_clkdm",
2168 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2169 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2170 .recalc = &followparent_recalc,
2173 static struct clk wdt3_ick = {
2175 .ops = &clkops_omap2_dflt_wait,
2177 .clkdm_name = "core_l4_clkdm",
2178 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2179 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2180 .recalc = &followparent_recalc,
2183 static struct clk wdt3_fck = {
2185 .ops = &clkops_omap2_dflt_wait,
2186 .parent = &func_32k_ck,
2187 .clkdm_name = "core_l4_clkdm",
2188 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2189 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2190 .recalc = &followparent_recalc,
2193 static struct clk mspro_ick = {
2194 .name = "mspro_ick",
2195 .ops = &clkops_omap2_dflt_wait,
2197 .clkdm_name = "core_l4_clkdm",
2198 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2199 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2200 .recalc = &followparent_recalc,
2203 static struct clk mspro_fck = {
2204 .name = "mspro_fck",
2205 .ops = &clkops_omap2_dflt_wait,
2206 .parent = &func_96m_ck,
2207 .clkdm_name = "core_l4_clkdm",
2208 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2209 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2210 .recalc = &followparent_recalc,
2213 static struct clk mmc_ick = {
2215 .ops = &clkops_omap2_dflt_wait,
2217 .clkdm_name = "core_l4_clkdm",
2218 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2219 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2220 .recalc = &followparent_recalc,
2223 static struct clk mmc_fck = {
2225 .ops = &clkops_omap2_dflt_wait,
2226 .parent = &func_96m_ck,
2227 .clkdm_name = "core_l4_clkdm",
2228 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2229 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2230 .recalc = &followparent_recalc,
2233 static struct clk fac_ick = {
2235 .ops = &clkops_omap2_dflt_wait,
2237 .clkdm_name = "core_l4_clkdm",
2238 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2239 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2240 .recalc = &followparent_recalc,
2243 static struct clk fac_fck = {
2245 .ops = &clkops_omap2_dflt_wait,
2246 .parent = &func_12m_ck,
2247 .clkdm_name = "core_l4_clkdm",
2248 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2249 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2250 .recalc = &followparent_recalc,
2253 static struct clk eac_ick = {
2255 .ops = &clkops_omap2_dflt_wait,
2257 .clkdm_name = "core_l4_clkdm",
2258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2259 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2260 .recalc = &followparent_recalc,
2263 static struct clk eac_fck = {
2265 .ops = &clkops_omap2_dflt_wait,
2266 .parent = &func_96m_ck,
2267 .clkdm_name = "core_l4_clkdm",
2268 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2269 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2270 .recalc = &followparent_recalc,
2273 static struct clk hdq_ick = {
2275 .ops = &clkops_omap2_dflt_wait,
2277 .clkdm_name = "core_l4_clkdm",
2278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2279 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2280 .recalc = &followparent_recalc,
2283 static struct clk hdq_fck = {
2285 .ops = &clkops_omap2_dflt_wait,
2286 .parent = &func_12m_ck,
2287 .clkdm_name = "core_l4_clkdm",
2288 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2289 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2290 .recalc = &followparent_recalc,
2293 static struct clk i2c2_ick = {
2295 .ops = &clkops_omap2_dflt_wait,
2298 .clkdm_name = "core_l4_clkdm",
2299 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2300 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2301 .recalc = &followparent_recalc,
2304 static struct clk i2c2_fck = {
2306 .ops = &clkops_omap2_dflt_wait,
2308 .parent = &func_12m_ck,
2309 .clkdm_name = "core_l4_clkdm",
2310 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2311 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2312 .recalc = &followparent_recalc,
2315 static struct clk i2chs2_fck = {
2317 .ops = &clkops_omap2_dflt_wait,
2319 .parent = &func_96m_ck,
2320 .clkdm_name = "core_l4_clkdm",
2321 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2322 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2323 .recalc = &followparent_recalc,
2326 static struct clk i2c1_ick = {
2328 .ops = &clkops_omap2_dflt_wait,
2331 .clkdm_name = "core_l4_clkdm",
2332 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2333 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2334 .recalc = &followparent_recalc,
2337 static struct clk i2c1_fck = {
2339 .ops = &clkops_omap2_dflt_wait,
2341 .parent = &func_12m_ck,
2342 .clkdm_name = "core_l4_clkdm",
2343 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2344 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2345 .recalc = &followparent_recalc,
2348 static struct clk i2chs1_fck = {
2350 .ops = &clkops_omap2_dflt_wait,
2352 .parent = &func_96m_ck,
2353 .clkdm_name = "core_l4_clkdm",
2354 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2355 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2356 .recalc = &followparent_recalc,
2359 static struct clk gpmc_fck = {
2361 .ops = &clkops_null, /* RMK: missing? */
2362 .parent = &core_l3_ck,
2363 .flags = ENABLE_ON_INIT,
2364 .clkdm_name = "core_l3_clkdm",
2365 .recalc = &followparent_recalc,
2368 static struct clk sdma_fck = {
2370 .ops = &clkops_null, /* RMK: missing? */
2371 .parent = &core_l3_ck,
2372 .clkdm_name = "core_l3_clkdm",
2373 .recalc = &followparent_recalc,
2376 static struct clk sdma_ick = {
2378 .ops = &clkops_null, /* RMK: missing? */
2380 .clkdm_name = "core_l3_clkdm",
2381 .recalc = &followparent_recalc,
2384 static struct clk vlynq_ick = {
2385 .name = "vlynq_ick",
2386 .ops = &clkops_omap2_dflt_wait,
2387 .parent = &core_l3_ck,
2388 .clkdm_name = "core_l3_clkdm",
2389 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2390 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2391 .recalc = &followparent_recalc,
2394 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2395 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2399 static const struct clksel_rate vlynq_fck_core_rates[] = {
2400 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2401 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2402 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2403 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2404 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2405 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2406 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2407 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2408 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2409 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2413 static const struct clksel vlynq_fck_clksel[] = {
2414 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2415 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2419 static struct clk vlynq_fck = {
2420 .name = "vlynq_fck",
2421 .ops = &clkops_omap2_dflt_wait,
2422 .parent = &func_96m_ck,
2423 .flags = DELAYED_APP,
2424 .clkdm_name = "core_l3_clkdm",
2425 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2426 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2427 .init = &omap2_init_clksel_parent,
2428 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2429 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2430 .clksel = vlynq_fck_clksel,
2431 .recalc = &omap2_clksel_recalc,
2432 .round_rate = &omap2_clksel_round_rate,
2433 .set_rate = &omap2_clksel_set_rate
2436 static struct clk sdrc_ick = {
2438 .ops = &clkops_omap2_dflt_wait,
2440 .flags = ENABLE_ON_INIT,
2441 .clkdm_name = "core_l4_clkdm",
2442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2443 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2444 .recalc = &followparent_recalc,
2447 static struct clk des_ick = {
2449 .ops = &clkops_omap2_dflt_wait,
2451 .clkdm_name = "core_l4_clkdm",
2452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2453 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2454 .recalc = &followparent_recalc,
2457 static struct clk sha_ick = {
2459 .ops = &clkops_omap2_dflt_wait,
2461 .clkdm_name = "core_l4_clkdm",
2462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2463 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2464 .recalc = &followparent_recalc,
2467 static struct clk rng_ick = {
2469 .ops = &clkops_omap2_dflt_wait,
2471 .clkdm_name = "core_l4_clkdm",
2472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2473 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2474 .recalc = &followparent_recalc,
2477 static struct clk aes_ick = {
2479 .ops = &clkops_omap2_dflt_wait,
2481 .clkdm_name = "core_l4_clkdm",
2482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2483 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2484 .recalc = &followparent_recalc,
2487 static struct clk pka_ick = {
2489 .ops = &clkops_omap2_dflt_wait,
2491 .clkdm_name = "core_l4_clkdm",
2492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2493 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2494 .recalc = &followparent_recalc,
2497 static struct clk usb_fck = {
2499 .ops = &clkops_omap2_dflt_wait,
2500 .parent = &func_48m_ck,
2501 .clkdm_name = "core_l3_clkdm",
2502 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2503 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2504 .recalc = &followparent_recalc,
2507 static struct clk usbhs_ick = {
2508 .name = "usbhs_ick",
2509 .ops = &clkops_omap2_dflt_wait,
2510 .parent = &core_l3_ck,
2511 .clkdm_name = "core_l3_clkdm",
2512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2513 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2514 .recalc = &followparent_recalc,
2517 static struct clk mmchs1_ick = {
2518 .name = "mmchs_ick",
2519 .ops = &clkops_omap2_dflt_wait,
2521 .clkdm_name = "core_l4_clkdm",
2522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2523 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2524 .recalc = &followparent_recalc,
2527 static struct clk mmchs1_fck = {
2528 .name = "mmchs_fck",
2529 .ops = &clkops_omap2_dflt_wait,
2530 .parent = &func_96m_ck,
2531 .clkdm_name = "core_l3_clkdm",
2532 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2533 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2534 .recalc = &followparent_recalc,
2537 static struct clk mmchs2_ick = {
2538 .name = "mmchs_ick",
2539 .ops = &clkops_omap2_dflt_wait,
2542 .clkdm_name = "core_l4_clkdm",
2543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2544 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2545 .recalc = &followparent_recalc,
2548 static struct clk mmchs2_fck = {
2549 .name = "mmchs_fck",
2550 .ops = &clkops_omap2_dflt_wait,
2552 .parent = &func_96m_ck,
2553 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2554 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2555 .recalc = &followparent_recalc,
2558 static struct clk gpio5_ick = {
2559 .name = "gpio5_ick",
2560 .ops = &clkops_omap2_dflt_wait,
2562 .clkdm_name = "core_l4_clkdm",
2563 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2564 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2565 .recalc = &followparent_recalc,
2568 static struct clk gpio5_fck = {
2569 .name = "gpio5_fck",
2570 .ops = &clkops_omap2_dflt_wait,
2571 .parent = &func_32k_ck,
2572 .clkdm_name = "core_l4_clkdm",
2573 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2574 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2575 .recalc = &followparent_recalc,
2578 static struct clk mdm_intc_ick = {
2579 .name = "mdm_intc_ick",
2580 .ops = &clkops_omap2_dflt_wait,
2582 .clkdm_name = "core_l4_clkdm",
2583 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2584 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2585 .recalc = &followparent_recalc,
2588 static struct clk mmchsdb1_fck = {
2589 .name = "mmchsdb_fck",
2590 .ops = &clkops_omap2_dflt_wait,
2591 .parent = &func_32k_ck,
2592 .clkdm_name = "core_l4_clkdm",
2593 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2594 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2595 .recalc = &followparent_recalc,
2598 static struct clk mmchsdb2_fck = {
2599 .name = "mmchsdb_fck",
2600 .ops = &clkops_omap2_dflt_wait,
2602 .parent = &func_32k_ck,
2603 .clkdm_name = "core_l4_clkdm",
2604 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2605 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2606 .recalc = &followparent_recalc,
2610 * This clock is a composite clock which does entire set changes then
2611 * forces a rebalance. It keys on the MPU speed, but it really could
2612 * be any key speed part of a set in the rate table.
2614 * to really change a set, you need memory table sets which get changed
2615 * in sram, pre-notifiers & post notifiers, changing the top set, without
2616 * having low level display recalc's won't work... this is why dpm notifiers
2617 * work, isr's off, walk a list of clocks already _off_ and not messing with
2620 * This clock should have no parent. It embodies the entire upper level
2621 * active set. A parent will mess up some of the init also.
2623 static struct clk virt_prcm_set = {
2624 .name = "virt_prcm_set",
2625 .ops = &clkops_null,
2626 .flags = DELAYED_APP,
2627 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2628 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2629 .set_rate = &omap2_select_table_rate,
2630 .round_rate = &omap2_round_to_table_rate,