2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/sram.h>
33 #include <asm/div64.h>
34 #include <asm/bitops.h>
38 #include "clock24xx.h"
40 #include "prm-regbits-24xx.h"
42 #include "cm-regbits-24xx.h"
44 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
45 #define EN_APLL_STOPPED 0
46 #define EN_APLL_LOCKED 3
48 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
49 #define APLLS_CLKIN_19_2MHZ 0
50 #define APLLS_CLKIN_13MHZ 2
51 #define APLLS_CLKIN_12MHZ 3
53 /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
55 static struct prcm_config *curr_prcm_set;
56 static struct clk *vclk;
57 static struct clk *sclk;
59 /*-------------------------------------------------------------------------
60 * Omap24xx specific clock functions
61 *-------------------------------------------------------------------------*/
63 /* This actually returns the rate of core_ck, not dpll_ck. */
64 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
69 dpll_clk = omap2_get_dpll_rate(tclk);
71 amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
72 amult &= OMAP24XX_CORE_CLK_SRC_MASK;
78 static int omap2_enable_osc_ck(struct clk *clk)
81 prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, ~OMAP_AUTOEXTCLKMODE_MASK,
82 OMAP24XX_PRCM_CLKSRC_CTRL);
87 static void omap2_disable_osc_ck(struct clk *clk)
89 prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
90 OMAP24XX_PRCM_CLKSRC_CTRL);
93 /* Enable an APLL if off */
94 static int omap2_clk_fixed_enable(struct clk *clk)
98 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
100 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
102 if ((cval & apll_mask) == apll_mask)
103 return 0; /* apll already enabled */
107 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
109 if (clk == &apll96_ck)
110 cval = OMAP24XX_ST_96M_APLL;
111 else if (clk == &apll54_ck)
112 cval = OMAP24XX_ST_54M_APLL;
114 omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
118 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
125 static void omap2_clk_fixed_disable(struct clk *clk)
129 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
130 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
131 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
135 * Uses the current prcm set to tell if a rate is valid.
136 * You can go slower, but not faster within a given rate set.
138 long omap2_dpllcore_round_rate(unsigned long target_rate)
140 u32 high, low, core_clk_src;
142 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
143 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
145 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
146 high = curr_prcm_set->dpll_speed * 2;
147 low = curr_prcm_set->dpll_speed;
148 } else { /* DPLL clockout x 2 */
149 high = curr_prcm_set->dpll_speed;
150 low = curr_prcm_set->dpll_speed / 2;
153 #ifdef DOWN_VARIABLE_DPLL
154 if (target_rate > high)
159 if (target_rate > low)
167 static void omap2_dpllcore_recalc(struct clk *clk)
169 clk->rate = omap2_get_dpll_rate_24xx(clk);
174 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
176 u32 cur_rate, low, mult, div, valid_rate, done_rate;
178 struct prcm_config tmpset;
179 const struct dpll_data *dd;
183 local_irq_save(flags);
184 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
185 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
186 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
188 if ((rate == (cur_rate / 2)) && (mult == 2)) {
189 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
190 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
191 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
192 } else if (rate != cur_rate) {
193 valid_rate = omap2_dpllcore_round_rate(rate);
194 if (valid_rate != rate)
198 low = curr_prcm_set->dpll_speed;
200 low = curr_prcm_set->dpll_speed / 2;
206 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
207 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
209 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
210 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
211 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
213 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
214 mult = ((rate / 2) / 1000000);
215 done_rate = CORE_CLK_SRC_DPLL_X2;
217 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
218 mult = (rate / 1000000);
219 done_rate = CORE_CLK_SRC_DPLL;
221 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
222 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
225 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
227 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
230 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
232 /* Force dll lock mode */
233 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
236 /* Errata: ret dll entry state */
237 omap2_init_memory_params(omap2_dll_force_needed());
238 omap2_reprogram_sdrc(done_rate, 0);
240 omap2_dpllcore_recalc(&dpll_ck);
244 local_irq_restore(flags);
249 * omap2_table_mpu_recalc - just return the MPU speed
250 * @clk: virt_prcm_set struct clk
252 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
254 static void omap2_table_mpu_recalc(struct clk *clk)
256 clk->rate = curr_prcm_set->mpu_speed;
260 * Look for a rate equal or less than the target rate given a configuration set.
262 * What's not entirely clear is "which" field represents the key field.
263 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
264 * just uses the ARM rates.
266 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
268 struct prcm_config *ptr;
271 if (clk != &virt_prcm_set)
274 highest_rate = -EINVAL;
276 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
277 if (!(ptr->flags & cpu_mask))
279 if (ptr->xtal_speed != sys_ck.rate)
282 highest_rate = ptr->mpu_speed;
284 /* Can check only after xtal frequency check */
285 if (ptr->mpu_speed <= rate)
291 /* Sets basic clocks based on the specified rate */
292 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
294 u32 cur_rate, done_rate, bypass = 0, tmp;
295 struct prcm_config *prcm;
296 unsigned long found_speed = 0;
299 if (clk != &virt_prcm_set)
302 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
303 if (!(prcm->flags & cpu_mask))
306 if (prcm->xtal_speed != sys_ck.rate)
309 if (prcm->mpu_speed <= rate) {
310 found_speed = prcm->mpu_speed;
316 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
321 curr_prcm_set = prcm;
322 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
324 if (prcm->dpll_speed == cur_rate / 2) {
325 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
326 } else if (prcm->dpll_speed == cur_rate * 2) {
327 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
328 } else if (prcm->dpll_speed != cur_rate) {
329 local_irq_save(flags);
331 if (prcm->dpll_speed == prcm->xtal_speed)
334 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
335 CORE_CLK_SRC_DPLL_X2)
336 done_rate = CORE_CLK_SRC_DPLL_X2;
338 done_rate = CORE_CLK_SRC_DPLL;
341 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
343 /* dsp + iva1 div(2420), iva2.1(2430) */
344 cm_write_mod_reg(prcm->cm_clksel_dsp,
345 OMAP24XX_DSP_MOD, CM_CLKSEL);
347 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
349 /* Major subsystem dividers */
350 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
351 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
352 if (cpu_is_omap2430())
353 cm_write_mod_reg(prcm->cm_clksel_mdm,
354 OMAP2430_MDM_MOD, CM_CLKSEL);
356 /* x2 to enter init_mem */
357 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
359 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
362 omap2_init_memory_params(omap2_dll_force_needed());
363 omap2_reprogram_sdrc(done_rate, 0);
365 local_irq_restore(flags);
367 omap2_dpllcore_recalc(&dpll_ck);
372 #ifdef CONFIG_CPU_FREQ
374 * Walk PRCM rate table and fillout cpufreq freq_table
376 static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
378 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
380 struct prcm_config *prcm;
383 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
384 if (!(prcm->flags & cpu_mask))
386 if (prcm->xtal_speed != sys_ck.rate)
389 /* don't put bypass rates in table */
390 if (prcm->dpll_speed == prcm->xtal_speed)
393 freq_table[i].index = i;
394 freq_table[i].frequency = prcm->mpu_speed / 1000;
399 printk(KERN_WARNING "%s: failed to initialize frequency table\n",
404 freq_table[i].index = i;
405 freq_table[i].frequency = CPUFREQ_TABLE_END;
407 *table = &freq_table[0];
411 static struct clk_functions omap2_clk_functions = {
412 .clk_enable = omap2_clk_enable,
413 .clk_disable = omap2_clk_disable,
414 .clk_round_rate = omap2_clk_round_rate,
415 .clk_set_rate = omap2_clk_set_rate,
416 .clk_set_parent = omap2_clk_set_parent,
417 .clk_disable_unused = omap2_clk_disable_unused,
418 #ifdef CONFIG_CPU_FREQ
419 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
423 static u32 omap2_get_apll_clkin(void)
427 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
428 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
429 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
431 if (aplls == APLLS_CLKIN_19_2MHZ)
433 else if (aplls == APLLS_CLKIN_13MHZ)
435 else if (aplls == APLLS_CLKIN_12MHZ)
441 static u32 omap2_get_sysclkdiv(void)
445 div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
446 div &= OMAP_SYSCLKDIV_MASK;
447 div >>= OMAP_SYSCLKDIV_SHIFT;
452 static void omap2_osc_clk_recalc(struct clk *clk)
454 clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
458 static void omap2_sys_clk_recalc(struct clk *clk)
460 clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
465 * Set clocks for bypass mode for reboot to work.
467 void omap2_clk_prepare_for_reboot(void)
471 if (vclk == NULL || sclk == NULL)
474 rate = clk_get_rate(sclk);
475 clk_set_rate(vclk, rate);
479 * Switch the MPU rate if specified on cmdline.
480 * We cannot do this early until cmdline is parsed.
482 static int __init omap2_clk_arch_init(void)
487 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
488 printk(KERN_ERR "Could not find matching MPU rate\n");
490 recalculate_root_clocks();
492 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
493 "%ld.%01ld/%ld/%ld MHz\n",
494 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
495 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
499 arch_initcall(omap2_clk_arch_init);
501 int __init omap2_clk_init(void)
503 struct prcm_config *prcm;
507 if (cpu_is_omap242x())
508 cpu_mask = RATE_IN_242X;
509 else if (cpu_is_omap2430())
510 cpu_mask = RATE_IN_243X;
512 clk_init(&omap2_clk_functions);
514 omap2_osc_clk_recalc(&osc_ck);
515 omap2_sys_clk_recalc(&sys_ck);
517 for (clkp = onchip_24xx_clks;
518 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
521 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
526 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
532 /* Check the MPU rate set by bootloader */
533 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
534 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
535 if (!(prcm->flags & cpu_mask))
537 if (prcm->xtal_speed != sys_ck.rate)
539 if (prcm->dpll_speed <= clkrate)
542 curr_prcm_set = prcm;
544 recalculate_root_clocks();
546 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
547 "%ld.%01ld/%ld/%ld MHz\n",
548 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
549 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
552 * Only enable those clocks we will need, let the drivers
553 * enable other clocks as necessary
555 clk_enable_init_clocks();
557 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
558 vclk = clk_get(NULL, "virt_prcm_set");
559 sclk = clk_get(NULL, "sys_ck");