arch/arm/mach-omap2/clock24xx.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Cleaned up and modified to use omap shared clock framework by
   9  *  Tony Lindgren <tony@atomide.com>
  10  *
  11  *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
  12  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #undef DEBUG
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/list.h>
  24 #include <linux/errno.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27
  28 #include <linux/io.h>
  29
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/sram.h>
  32 #include <asm/div64.h>
  33
  34 #include "memory.h"
  35 #include "clock.h"
  36 #include "clock24xx.h"
  37 #include "prm.h"
  38 #include "prm_regbits_24xx.h"
  39 #include "cm.h"
  40 #include "cm_regbits_24xx.h"
  41
  42 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
  43 #define EN_APLL_STOPPED                 0
  44 #define EN_APLL_LOCKED                  3
  45
  46 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
  47 #define APLLS_CLKIN_19_2MHZ             0
  48 #define APLLS_CLKIN_13MHZ               2
  49 #define APLLS_CLKIN_12MHZ               3
  50
  51 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
  52
  53 static struct prcm_config *curr_prcm_set;
  54 static struct clk *vclk;
  55 static struct clk *sclk;
  56
  57 /*-------------------------------------------------------------------------
  58  * Omap24xx specific clock functions
  59  *-------------------------------------------------------------------------*/
  60
  61 /* This actually returns the rate of core_ck, not dpll_ck. */
  62 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
  63 {
  64         long long dpll_clk;
  65         u8 amult;
  66
  67         dpll_clk = omap2_get_dpll_rate(tclk);
  68
  69         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  70         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  71         dpll_clk *= amult;
  72
  73         return dpll_clk;
  74 }
  75
  76 static int omap2_enable_osc_ck(struct clk *clk)
  77 {
  78         u32 pcc;
  79
  80         pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
  81
  82         prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
  83                       OMAP24XX_PRCM_CLKSRC_CTRL);
  84
  85         return 0;
  86 }
  87
  88 static void omap2_disable_osc_ck(struct clk *clk)
  89 {
  90         u32 pcc;
  91
  92         pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
  93
  94         prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
  95                       OMAP24XX_PRCM_CLKSRC_CTRL);
  96 }
  97
  98 /* Enable an APLL if off */
  99 static int omap2_clk_fixed_enable(struct clk *clk)
 100 {
 101         u32 cval, apll_mask;
 102
 103         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 104
 105         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 106
 107         if ((cval & apll_mask) == apll_mask)
 108                 return 0;   /* apll already enabled */
 109
 110         cval &= ~apll_mask;
 111         cval |= apll_mask;
 112         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 113
 114         if (clk == &apll96_ck)
 115                 cval = OMAP24XX_ST_96M_APLL;
 116         else if (clk == &apll54_ck)
 117                 cval = OMAP24XX_ST_54M_CLK;
 118
 119         omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
 120                             clk->name);
 121
 122         /*
 123          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
 124          * fails?
 125          */
 126         return 0;
 127 }
 128
 129 /* Stop APLL */
 130 static void omap2_clk_fixed_disable(struct clk *clk)
 131 {
 132         u32 cval;
 133
 134         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 135         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 136         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 137 }
 138
 139 /*
 140  * Uses the current prcm set to tell if a rate is valid.
 141  * You can go slower, but not faster within a given rate set.
 142  */
 143 static u32 omap2_dpll_round_rate(unsigned long target_rate)
 144 {
 145         u32 high, low, core_clk_src;
 146
 147         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 148         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 149
 150         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
 151                 high = curr_prcm_set->dpll_speed * 2;
 152                 low = curr_prcm_set->dpll_speed;
 153         } else {                                /* DPLL clockout x 2 */
 154                 high = curr_prcm_set->dpll_speed;
 155                 low = curr_prcm_set->dpll_speed / 2;
 156         }
 157
 158 #ifdef DOWN_VARIABLE_DPLL
 159         if (target_rate > high)
 160                 return high;
 161         else
 162                 return target_rate;
 163 #else
 164         if (target_rate > low)
 165                 return high;
 166         else
 167                 return low;
 168 #endif
 169
 170 }
 171
 172 static void omap2_dpll_recalc(struct clk *clk)
 173 {
 174         clk->rate = omap2_get_dpll_rate_24xx(clk);
 175
 176         propagate_rate(clk);
 177 }
 178
 179 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
 180 {
 181         u32 cur_rate, low, mult, div, valid_rate, done_rate;
 182         u32 bypass = 0;
 183         struct prcm_config tmpset;
 184         const struct dpll_data *dd;
 185         unsigned long flags;
 186         int ret = -EINVAL;
 187
 188         local_irq_save(flags);
 189         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 190         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 191         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 192
 193         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 194                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 195         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 196                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 197         } else if (rate != cur_rate) {
 198                 valid_rate = omap2_dpll_round_rate(rate);
 199                 if (valid_rate != rate)
 200                         goto dpll_exit;
 201
 202                 if (mult == 1)
 203                         low = curr_prcm_set->dpll_speed;
 204                 else
 205                         low = curr_prcm_set->dpll_speed / 2;
 206
 207                 dd = clk->dpll_data;
 208                 if (!dd)
 209                         goto dpll_exit;
 210
 211                 tmpset.cm_clksel1_pll = cm_read_reg(dd->mult_div1_reg);
 212                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
 213                                            dd->div1_mask);
 214                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 215                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 216                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 217                 if (rate > low) {
 218                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
 219                         mult = ((rate / 2) / 1000000);
 220                         done_rate = CORE_CLK_SRC_DPLL_X2;
 221                 } else {
 222                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
 223                         mult = (rate / 1000000);
 224                         done_rate = CORE_CLK_SRC_DPLL;
 225                 }
 226                 tmpset.cm_clksel1_pll |= (div << mask_to_shift(dd->mult_mask));
 227                 tmpset.cm_clksel1_pll |= (mult << mask_to_shift(dd->div1_mask));
 228
 229                 /* Worst case */
 230                 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
 231
 232                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 233                         bypass = 1;
 234
 235                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
 236
 237                 /* Force dll lock mode */
 238                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 239                                bypass);
 240
 241                 /* Errata: ret dll entry state */
 242                 omap2_init_memory_params(omap2_dll_force_needed());
 243                 omap2_reprogram_sdrc(done_rate, 0);
 244         }
 245         omap2_dpll_recalc(&dpll_ck);
 246         ret = 0;
 247
 248 dpll_exit:
 249         local_irq_restore(flags);
 250         return(ret);
 251 }
 252
 253 /**
 254  * omap2_table_mpu_recalc - just return the MPU speed
 255  * @clk: virt_prcm_set struct clk
 256  *
 257  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 258  */
 259 static void omap2_table_mpu_recalc(struct clk *clk)
 260 {
 261         clk->rate = curr_prcm_set->mpu_speed;
 262 }
 263
 264 /*
 265  * Look for a rate equal or less than the target rate given a configuration set.
 266  *
 267  * What's not entirely clear is "which" field represents the key field.
 268  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 269  * just uses the ARM rates.
 270  */
 271 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 272 {
 273         struct prcm_config *ptr;
 274         long highest_rate;
 275
 276         if (clk != &virt_prcm_set)
 277                 return -EINVAL;
 278
 279         highest_rate = -EINVAL;
 280
 281         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 282                 if (!(ptr->flags & cpu_mask))
 283                         continue;
 284                 if (ptr->xtal_speed != sys_ck.rate)
 285                         continue;
 286
 287                 highest_rate = ptr->mpu_speed;
 288
 289                 /* Can check only after xtal frequency check */
 290                 if (ptr->mpu_speed <= rate)
 291                         break;
 292         }
 293         return highest_rate;
 294 }
 295
 296 /* Sets basic clocks based on the specified rate */
 297 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 298 {
 299         u32 cur_rate, done_rate, bypass = 0, tmp;
 300         struct prcm_config *prcm;
 301         unsigned long found_speed = 0;
 302         unsigned long flags;
 303
 304         if (clk != &virt_prcm_set)
 305                 return -EINVAL;
 306
 307         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 308                 if (!(prcm->flags & cpu_mask))
 309                         continue;
 310
 311                 if (prcm->xtal_speed != sys_ck.rate)
 312                         continue;
 313
 314                 if (prcm->mpu_speed <= rate) {
 315                         found_speed = prcm->mpu_speed;
 316                         break;
 317                 }
 318         }
 319
 320         if (!found_speed) {
 321                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 322                        rate / 1000000);
 323                 return -EINVAL;
 324         }
 325
 326         curr_prcm_set = prcm;
 327         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 328
 329         if (prcm->dpll_speed == cur_rate / 2) {
 330                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 331         } else if (prcm->dpll_speed == cur_rate * 2) {
 332                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 333         } else if (prcm->dpll_speed != cur_rate) {
 334                 local_irq_save(flags);
 335
 336                 if (prcm->dpll_speed == prcm->xtal_speed)
 337                         bypass = 1;
 338
 339                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
 340                     CORE_CLK_SRC_DPLL_X2)
 341                         done_rate = CORE_CLK_SRC_DPLL_X2;
 342                 else
 343                         done_rate = CORE_CLK_SRC_DPLL;
 344
 345                 /* MPU divider */
 346                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 347
 348                 /* dsp + iva1 div(2420), iva2.1(2430) */
 349                 cm_write_mod_reg(prcm->cm_clksel_dsp,
 350                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 351
 352                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 353
 354                 /* Major subsystem dividers */
 355                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
 356                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
 357                 if (cpu_is_omap2430())
 358                         cm_write_mod_reg(prcm->cm_clksel_mdm,
 359                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 360
 361                 /* x2 to enter init_mem */
 362                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 363
 364                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 365                                bypass);
 366
 367                 omap2_init_memory_params(omap2_dll_force_needed());
 368                 omap2_reprogram_sdrc(done_rate, 0);
 369
 370                 local_irq_restore(flags);
 371         }
 372         omap2_dpll_recalc(&dpll_ck);
 373
 374         return 0;
 375 }
 376
 377 static struct clk_functions omap2_clk_functions = {
 378         .clk_enable             = omap2_clk_enable,
 379         .clk_disable            = omap2_clk_disable,
 380         .clk_round_rate         = omap2_clk_round_rate,
 381         .clk_set_rate           = omap2_clk_set_rate,
 382         .clk_set_parent         = omap2_clk_set_parent,
 383         .clk_disable_unused     = omap2_clk_disable_unused,
 384 };
 385
 386 static u32 omap2_get_apll_clkin(void)
 387 {
 388         u32 aplls, sclk = 0;
 389
 390         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 391         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 392         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 393
 394         if (aplls == APLLS_CLKIN_19_2MHZ)
 395                 sclk = 19200000;
 396         else if (aplls == APLLS_CLKIN_13MHZ)
 397                 sclk = 13000000;
 398         else if (aplls == APLLS_CLKIN_12MHZ)
 399                 sclk = 12000000;
 400
 401         return sclk;
 402 }
 403
 404 static u32 omap2_get_sysclkdiv(void)
 405 {
 406         u32 div;
 407
 408         div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
 409         div &= OMAP_SYSCLKDIV_MASK;
 410         div >>= OMAP_SYSCLKDIV_SHIFT;
 411
 412         return div;
 413 }
 414
 415 static void omap2_osc_clk_recalc(struct clk *clk)
 416 {
 417         clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
 418         propagate_rate(clk);
 419 }
 420
 421 static void omap2_sys_clk_recalc(struct clk *clk)
 422 {
 423         clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
 424         propagate_rate(clk);
 425 }
 426
 427 /*
 428  * Set clocks for bypass mode for reboot to work.
 429  */
 430 void omap2_clk_prepare_for_reboot(void)
 431 {
 432         u32 rate;
 433
 434         if (vclk == NULL || sclk == NULL)
 435                 return;
 436
 437         rate = clk_get_rate(sclk);
 438         clk_set_rate(vclk, rate);
 439 }
 440
 441 /*
 442  * Switch the MPU rate if specified on cmdline.
 443  * We cannot do this early until cmdline is parsed.
 444  */
 445 static int __init omap2_clk_arch_init(void)
 446 {
 447         if (!mpurate)
 448                 return -EINVAL;
 449
 450         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
 451                 printk(KERN_ERR "Could not find matching MPU rate\n");
 452
 453         recalculate_root_clocks();
 454
 455         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
 456                "%ld.%01ld/%ld/%ld MHz\n",
 457                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 458                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 459
 460         return 0;
 461 }
 462 arch_initcall(omap2_clk_arch_init);
 463
 464 int __init omap2_clk_init(void)
 465 {
 466         struct prcm_config *prcm;
 467         struct clk **clkp;
 468         u32 clkrate;
 469
 470         if (cpu_is_omap242x())
 471                 cpu_mask = RATE_IN_242X;
 472         else if (cpu_is_omap2430())
 473                 cpu_mask = RATE_IN_243X;
 474
 475         clk_init(&omap2_clk_functions);
 476
 477         omap2_osc_clk_recalc(&osc_ck);
 478
 479         for (clkp = onchip_24xx_clks;
 480              clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
 481              clkp++) {
 482
 483                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
 484                         clk_register(*clkp);
 485                         continue;
 486                 }
 487
 488                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && (cpu_is_omap2430() || cpu_is_omap34xx())) {
 489                         clk_register(*clkp);
 490                         continue;
 491                 }
 492         }
 493
 494         /* Check the MPU rate set by bootloader */
 495         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
 496         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 497                 if (!(prcm->flags & cpu_mask))
 498                         continue;
 499                 if (prcm->xtal_speed != sys_ck.rate)
 500                         continue;
 501                 if (prcm->dpll_speed <= clkrate)
 502                          break;
 503         }
 504         curr_prcm_set = prcm;
 505
 506         recalculate_root_clocks();
 507
 508         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
 509                "%ld.%01ld/%ld/%ld MHz\n",
 510                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 511                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 512
 513         /*
 514          * Only enable those clocks we will need, let the drivers
 515          * enable other clocks as necessary
 516          */
 517         clk_enable_init_clocks();
 518
 519         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
 520         vclk = clk_get(NULL, "virt_prcm_set");
 521         sclk = clk_get(NULL, "sys_ck");
 522
 523         return 0;
 524 }