arch/arm/mach-omap2/clock24xx.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
  12  *  Gordon McNutt and RidgeRun, Inc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #undef DEBUG
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/list.h>
  24 #include <linux/errno.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/bitops.h>
  28 #include <linux/io.h>
  29 #include <linux/cpufreq.h>
  30
  31 #include <asm/arch/clock.h>
  32 #include <asm/arch/sram.h>
  33 #include <asm/div64.h>
  34
  35 #include "memory.h"
  36 #include "clock.h"
  37 #include "clock24xx.h"
  38 #include "prm.h"
  39 #include "prm-regbits-24xx.h"
  40 #include "cm.h"
  41 #include "cm-regbits-24xx.h"
  42
  43 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
  44 #define EN_APLL_STOPPED                 0
  45 #define EN_APLL_LOCKED                  3
  46
  47 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
  48 #define APLLS_CLKIN_19_2MHZ             0
  49 #define APLLS_CLKIN_13MHZ               2
  50 #define APLLS_CLKIN_12MHZ               3
  51
  52 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
  53
  54 static struct prcm_config *curr_prcm_set;
  55 static struct clk *vclk;
  56 static struct clk *sclk;
  57
  58 /*-------------------------------------------------------------------------
  59  * Omap24xx specific clock functions
  60  *-------------------------------------------------------------------------*/
  61
  62 /* This actually returns the rate of core_ck, not dpll_ck. */
  63 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
  64 {
  65         long long dpll_clk;
  66         u8 amult;
  67
  68         dpll_clk = omap2_get_dpll_rate(tclk);
  69
  70         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  71         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  72         dpll_clk *= amult;
  73
  74         return dpll_clk;
  75 }
  76
  77 static int omap2_enable_osc_ck(struct clk *clk)
  78 {
  79
  80         prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0,
  81                          OMAP24XX_PRCM_CLKSRC_CTRL);
  82
  83         return 0;
  84 }
  85
  86 static void omap2_disable_osc_ck(struct clk *clk)
  87 {
  88         prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
  89                          OMAP24XX_PRCM_CLKSRC_CTRL);
  90 }
  91
  92 /* Enable an APLL if off */
  93 static int omap2_clk_fixed_enable(struct clk *clk)
  94 {
  95         u32 cval, apll_mask;
  96
  97         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
  98
  99         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 100
 101         if ((cval & apll_mask) == apll_mask)
 102                 return 0;   /* apll already enabled */
 103
 104         cval &= ~apll_mask;
 105         cval |= apll_mask;
 106         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 107
 108         if (clk == &apll96_ck)
 109                 cval = OMAP24XX_ST_96M_APLL;
 110         else if (clk == &apll54_ck)
 111                 cval = OMAP24XX_ST_54M_APLL;
 112
 113         omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
 114                             clk->name);
 115
 116         /*
 117          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
 118          * fails?
 119          */
 120         return 0;
 121 }
 122
 123 /* Stop APLL */
 124 static void omap2_clk_fixed_disable(struct clk *clk)
 125 {
 126         u32 cval;
 127
 128         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 129         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 130         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 131 }
 132
 133 /*
 134  * Uses the current prcm set to tell if a rate is valid.
 135  * You can go slower, but not faster within a given rate set.
 136  */
 137 static long omap2_dpllcore_round_rate(unsigned long target_rate)
 138 {
 139         u32 high, low, core_clk_src;
 140
 141         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 142         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 143
 144         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
 145                 high = curr_prcm_set->dpll_speed * 2;
 146                 low = curr_prcm_set->dpll_speed;
 147         } else {                                /* DPLL clockout x 2 */
 148                 high = curr_prcm_set->dpll_speed;
 149                 low = curr_prcm_set->dpll_speed / 2;
 150         }
 151
 152 #ifdef DOWN_VARIABLE_DPLL
 153         if (target_rate > high)
 154                 return high;
 155         else
 156                 return target_rate;
 157 #else
 158         if (target_rate > low)
 159                 return high;
 160         else
 161                 return low;
 162 #endif
 163
 164 }
 165
 166 static void omap2_dpllcore_recalc(struct clk *clk)
 167 {
 168         clk->rate = omap2_get_dpll_rate_24xx(clk);
 169
 170         propagate_rate(clk);
 171 }
 172
 173 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 174 {
 175         u32 cur_rate, low, mult, div, valid_rate, done_rate;
 176         u32 bypass = 0;
 177         struct prcm_config tmpset;
 178         const struct dpll_data *dd;
 179         unsigned long flags;
 180         int ret = -EINVAL;
 181
 182         local_irq_save(flags);
 183         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 184         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 185         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 186
 187         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 188                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 189         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 190                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 191         } else if (rate != cur_rate) {
 192                 valid_rate = omap2_dpllcore_round_rate(rate);
 193                 if (valid_rate != rate)
 194                         goto dpll_exit;
 195
 196                 if (mult == 1)
 197                         low = curr_prcm_set->dpll_speed;
 198                 else
 199                         low = curr_prcm_set->dpll_speed / 2;
 200
 201                 dd = clk->dpll_data;
 202                 if (!dd)
 203                         goto dpll_exit;
 204
 205                 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
 206                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
 207                                            dd->div1_mask);
 208                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 209                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 210                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 211                 if (rate > low) {
 212                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
 213                         mult = ((rate / 2) / 1000000);
 214                         done_rate = CORE_CLK_SRC_DPLL_X2;
 215                 } else {
 216                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
 217                         mult = (rate / 1000000);
 218                         done_rate = CORE_CLK_SRC_DPLL;
 219                 }
 220                 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
 221                 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
 222
 223                 /* Worst case */
 224                 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
 225
 226                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 227                         bypass = 1;
 228
 229                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
 230
 231                 /* Force dll lock mode */
 232                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 233                                bypass);
 234
 235                 /* Errata: ret dll entry state */
 236                 omap2_init_memory_params(omap2_dll_force_needed());
 237                 omap2_reprogram_sdrc(done_rate, 0);
 238         }
 239         omap2_dpllcore_recalc(&dpll_ck);
 240         ret = 0;
 241
 242 dpll_exit:
 243         local_irq_restore(flags);
 244         return(ret);
 245 }
 246
 247 /**
 248  * omap2_table_mpu_recalc - just return the MPU speed
 249  * @clk: virt_prcm_set struct clk
 250  *
 251  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 252  */
 253 static void omap2_table_mpu_recalc(struct clk *clk)
 254 {
 255         clk->rate = curr_prcm_set->mpu_speed;
 256 }
 257
 258 /*
 259  * Look for a rate equal or less than the target rate given a configuration set.
 260  *
 261  * What's not entirely clear is "which" field represents the key field.
 262  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 263  * just uses the ARM rates.
 264  */
 265 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 266 {
 267         struct prcm_config *ptr;
 268         long highest_rate;
 269
 270         if (clk != &virt_prcm_set)
 271                 return -EINVAL;
 272
 273         highest_rate = -EINVAL;
 274
 275         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 276                 if (!(ptr->flags & cpu_mask))
 277                         continue;
 278                 if (ptr->xtal_speed != sys_ck.rate)
 279                         continue;
 280
 281                 highest_rate = ptr->mpu_speed;
 282
 283                 /* Can check only after xtal frequency check */
 284                 if (ptr->mpu_speed <= rate)
 285                         break;
 286         }
 287         return highest_rate;
 288 }
 289
 290 /* Sets basic clocks based on the specified rate */
 291 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 292 {
 293         u32 cur_rate, done_rate, bypass = 0, tmp;
 294         struct prcm_config *prcm;
 295         unsigned long found_speed = 0;
 296         unsigned long flags;
 297
 298         if (clk != &virt_prcm_set)
 299                 return -EINVAL;
 300
 301         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 302                 if (!(prcm->flags & cpu_mask))
 303                         continue;
 304
 305                 if (prcm->xtal_speed != sys_ck.rate)
 306                         continue;
 307
 308                 if (prcm->mpu_speed <= rate) {
 309                         found_speed = prcm->mpu_speed;
 310                         break;
 311                 }
 312         }
 313
 314         if (!found_speed) {
 315                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 316                        rate / 1000000);
 317                 return -EINVAL;
 318         }
 319
 320         curr_prcm_set = prcm;
 321         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 322
 323         if (prcm->dpll_speed == cur_rate / 2) {
 324                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 325         } else if (prcm->dpll_speed == cur_rate * 2) {
 326                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 327         } else if (prcm->dpll_speed != cur_rate) {
 328                 local_irq_save(flags);
 329
 330                 if (prcm->dpll_speed == prcm->xtal_speed)
 331                         bypass = 1;
 332
 333                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
 334                     CORE_CLK_SRC_DPLL_X2)
 335                         done_rate = CORE_CLK_SRC_DPLL_X2;
 336                 else
 337                         done_rate = CORE_CLK_SRC_DPLL;
 338
 339                 /* MPU divider */
 340                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 341
 342                 /* dsp + iva1 div(2420), iva2.1(2430) */
 343                 cm_write_mod_reg(prcm->cm_clksel_dsp,
 344                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 345
 346                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 347
 348                 /* Major subsystem dividers */
 349                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
 350                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
 351                                  CM_CLKSEL1);
 352
 353                 if (cpu_is_omap2430())
 354                         cm_write_mod_reg(prcm->cm_clksel_mdm,
 355                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 356
 357                 /* x2 to enter init_mem */
 358                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 359
 360                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 361                                bypass);
 362
 363                 omap2_init_memory_params(omap2_dll_force_needed());
 364                 omap2_reprogram_sdrc(done_rate, 0);
 365
 366                 local_irq_restore(flags);
 367         }
 368         omap2_dpllcore_recalc(&dpll_ck);
 369
 370         return 0;
 371 }
 372
 373 #ifdef CONFIG_CPU_FREQ
 374 /*
 375  * Walk PRCM rate table and fillout cpufreq freq_table
 376  */
 377 static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
 378
 379 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 380 {
 381         struct prcm_config *prcm;
 382         int i = 0;
 383
 384         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 385                 if (!(prcm->flags & cpu_mask))
 386                         continue;
 387                 if (prcm->xtal_speed != sys_ck.rate)
 388                         continue;
 389
 390                 /* don't put bypass rates in table */
 391                 if (prcm->dpll_speed == prcm->xtal_speed)
 392                         continue;
 393
 394                 freq_table[i].index = i;
 395                 freq_table[i].frequency = prcm->mpu_speed / 1000;
 396                 i++;
 397         }
 398
 399         if (i == 0) {
 400                 printk(KERN_WARNING "%s: failed to initialize frequency "
 401                        "table\n", __func__);
 402                 return;
 403         }
 404
 405         freq_table[i].index = i;
 406         freq_table[i].frequency = CPUFREQ_TABLE_END;
 407
 408         *table = &freq_table[0];
 409 }
 410 #endif
 411
 412 static struct clk_functions omap2_clk_functions = {
 413         .clk_enable             = omap2_clk_enable,
 414         .clk_disable            = omap2_clk_disable,
 415         .clk_round_rate         = omap2_clk_round_rate,
 416         .clk_set_rate           = omap2_clk_set_rate,
 417         .clk_set_parent         = omap2_clk_set_parent,
 418         .clk_disable_unused     = omap2_clk_disable_unused,
 419 #ifdef  CONFIG_CPU_FREQ
 420         .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
 421 #endif
 422 };
 423
 424 static u32 omap2_get_apll_clkin(void)
 425 {
 426         u32 aplls, srate = 0;
 427
 428         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 429         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 430         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 431
 432         if (aplls == APLLS_CLKIN_19_2MHZ)
 433                 srate = 19200000;
 434         else if (aplls == APLLS_CLKIN_13MHZ)
 435                 srate = 13000000;
 436         else if (aplls == APLLS_CLKIN_12MHZ)
 437                 srate = 12000000;
 438
 439         return srate;
 440 }
 441
 442 static u32 omap2_get_sysclkdiv(void)
 443 {
 444         u32 div;
 445
 446         div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
 447         div &= OMAP_SYSCLKDIV_MASK;
 448         div >>= OMAP_SYSCLKDIV_SHIFT;
 449
 450         return div;
 451 }
 452
 453 static void omap2_osc_clk_recalc(struct clk *clk)
 454 {
 455         clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
 456         propagate_rate(clk);
 457 }
 458
 459 static void omap2_sys_clk_recalc(struct clk *clk)
 460 {
 461         clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
 462         propagate_rate(clk);
 463 }
 464
 465 /*
 466  * Set clocks for bypass mode for reboot to work.
 467  */
 468 void omap2_clk_prepare_for_reboot(void)
 469 {
 470         u32 rate;
 471
 472         if (vclk == NULL || sclk == NULL)
 473                 return;
 474
 475         rate = clk_get_rate(sclk);
 476         clk_set_rate(vclk, rate);
 477 }
 478
 479 /*
 480  * Switch the MPU rate if specified on cmdline.
 481  * We cannot do this early until cmdline is parsed.
 482  */
 483 static int __init omap2_clk_arch_init(void)
 484 {
 485         if (!mpurate)
 486                 return -EINVAL;
 487
 488         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
 489                 printk(KERN_ERR "Could not find matching MPU rate\n");
 490
 491         recalculate_root_clocks();
 492
 493         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
 494                "%ld.%01ld/%ld/%ld MHz\n",
 495                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 496                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 497
 498         return 0;
 499 }
 500 arch_initcall(omap2_clk_arch_init);
 501
 502 int __init omap2_clk_init(void)
 503 {
 504         struct prcm_config *prcm;
 505         struct clk **clkp;
 506         u32 clkrate;
 507
 508         if (cpu_is_omap242x())
 509                 cpu_mask = RATE_IN_242X;
 510         else if (cpu_is_omap2430())
 511                 cpu_mask = RATE_IN_243X;
 512
 513         clk_init(&omap2_clk_functions);
 514
 515         omap2_osc_clk_recalc(&osc_ck);
 516         omap2_sys_clk_recalc(&sys_ck);
 517
 518         for (clkp = onchip_24xx_clks;
 519              clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
 520              clkp++) {
 521
 522                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
 523                         clk_register(*clkp);
 524                         continue;
 525                 }
 526
 527                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
 528                         clk_register(*clkp);
 529                         continue;
 530                 }
 531         }
 532
 533         /* Check the MPU rate set by bootloader */
 534         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
 535         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 536                 if (!(prcm->flags & cpu_mask))
 537                         continue;
 538                 if (prcm->xtal_speed != sys_ck.rate)
 539                         continue;
 540                 if (prcm->dpll_speed <= clkrate)
 541                          break;
 542         }
 543         curr_prcm_set = prcm;
 544
 545         recalculate_root_clocks();
 546
 547         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
 548                "%ld.%01ld/%ld/%ld MHz\n",
 549                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 550                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 551
 552         /*
 553          * Only enable those clocks we will need, let the drivers
 554          * enable other clocks as necessary
 555          */
 556         clk_enable_init_clocks();
 557
 558         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
 559         vclk = clk_get(NULL, "virt_prcm_set");
 560         sclk = clk_get(NULL, "sys_ck");
 561
 562         return 0;
 563 }