2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
27 #include <linux/bitops.h>
29 #include <linux/cpufreq.h>
31 #include <asm/arch/common.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/sram.h>
34 #include <asm/div64.h>
38 #include "clock24xx.h"
40 #include "prm-regbits-24xx.h"
42 #include "cm-regbits-24xx.h"
44 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
45 #define EN_APLL_STOPPED 0
46 #define EN_APLL_LOCKED 3
48 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
49 #define APLLS_CLKIN_19_2MHZ 0
50 #define APLLS_CLKIN_13MHZ 2
51 #define APLLS_CLKIN_12MHZ 3
53 /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
55 static struct prcm_config *curr_prcm_set;
56 static struct clk *vclk;
57 static struct clk *sclk;
59 /*-------------------------------------------------------------------------
60 * Omap24xx specific clock functions
61 *-------------------------------------------------------------------------*/
63 /* This actually returns the rate of core_ck, not dpll_ck. */
64 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
69 dpll_clk = omap2_get_dpll_rate(tclk);
71 amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
72 amult &= OMAP24XX_CORE_CLK_SRC_MASK;
78 static int omap2_enable_osc_ck(struct clk *clk)
81 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0,
82 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
87 static void omap2_disable_osc_ck(struct clk *clk)
89 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
90 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
93 /* Enable an APLL if off */
94 static int omap2_clk_fixed_enable(struct clk *clk)
99 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
101 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
103 if ((cval & apll_mask) == apll_mask)
104 return 0; /* apll already enabled */
108 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
110 if (clk == &apll96_ck)
111 cval = OMAP24XX_ST_96M_APLL;
112 else if (clk == &apll54_ck)
113 cval = OMAP24XX_ST_54M_APLL;
115 if (cpu_is_omap242x())
116 idlest = (__force void __iomem *)OMAP2420_CM_REGADDR(PLL_MOD,
119 idlest = (__force void __iomem *)OMAP2430_CM_REGADDR(PLL_MOD,
122 omap2_wait_clock_ready(idlest, cval, clk->name);
125 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
132 static void omap2_clk_fixed_disable(struct clk *clk)
136 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
137 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
138 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
142 * Uses the current prcm set to tell if a rate is valid.
143 * You can go slower, but not faster within a given rate set.
145 static long omap2_dpllcore_round_rate(unsigned long target_rate)
147 u32 high, low, core_clk_src;
149 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
150 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
152 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
153 high = curr_prcm_set->dpll_speed * 2;
154 low = curr_prcm_set->dpll_speed;
155 } else { /* DPLL clockout x 2 */
156 high = curr_prcm_set->dpll_speed;
157 low = curr_prcm_set->dpll_speed / 2;
160 #ifdef DOWN_VARIABLE_DPLL
161 if (target_rate > high)
166 if (target_rate > low)
174 static void omap2_dpllcore_recalc(struct clk *clk)
176 clk->rate = omap2_get_dpll_rate_24xx(clk);
181 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
183 u32 cur_rate, low, mult, div, valid_rate, done_rate;
185 struct prcm_config tmpset;
186 const struct dpll_data *dd;
190 local_irq_save(flags);
191 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
192 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
193 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
195 if ((rate == (cur_rate / 2)) && (mult == 2)) {
196 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
197 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
198 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
199 } else if (rate != cur_rate) {
200 valid_rate = omap2_dpllcore_round_rate(rate);
201 if (valid_rate != rate)
205 low = curr_prcm_set->dpll_speed;
207 low = curr_prcm_set->dpll_speed / 2;
213 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
214 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
216 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
217 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
218 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
220 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
221 mult = ((rate / 2) / 1000000);
222 done_rate = CORE_CLK_SRC_DPLL_X2;
224 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
225 mult = (rate / 1000000);
226 done_rate = CORE_CLK_SRC_DPLL;
228 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
229 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
232 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
234 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
237 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
239 /* Force dll lock mode */
240 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
243 /* Errata: ret dll entry state */
244 omap2_init_memory_params(omap2_dll_force_needed());
245 omap2_reprogram_sdrc(done_rate, 0);
247 omap2_dpllcore_recalc(&dpll_ck);
251 local_irq_restore(flags);
256 * omap2_table_mpu_recalc - just return the MPU speed
257 * @clk: virt_prcm_set struct clk
259 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
261 static void omap2_table_mpu_recalc(struct clk *clk)
263 clk->rate = curr_prcm_set->mpu_speed;
267 * Look for a rate equal or less than the target rate given a configuration set.
269 * What's not entirely clear is "which" field represents the key field.
270 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
271 * just uses the ARM rates.
273 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
275 struct prcm_config *ptr;
278 if (clk != &virt_prcm_set)
281 highest_rate = -EINVAL;
283 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
284 if (!(ptr->flags & cpu_mask))
286 if (ptr->xtal_speed != sys_ck.rate)
289 highest_rate = ptr->mpu_speed;
291 /* Can check only after xtal frequency check */
292 if (ptr->mpu_speed <= rate)
298 /* Sets basic clocks based on the specified rate */
299 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
301 u32 cur_rate, done_rate, bypass = 0, tmp;
302 struct prcm_config *prcm;
303 unsigned long found_speed = 0;
306 if (clk != &virt_prcm_set)
309 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
310 if (!(prcm->flags & cpu_mask))
313 if (prcm->xtal_speed != sys_ck.rate)
316 if (prcm->mpu_speed <= rate) {
317 found_speed = prcm->mpu_speed;
323 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
328 curr_prcm_set = prcm;
329 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
331 if (prcm->dpll_speed == cur_rate / 2) {
332 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
333 } else if (prcm->dpll_speed == cur_rate * 2) {
334 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
335 } else if (prcm->dpll_speed != cur_rate) {
336 local_irq_save(flags);
338 if (prcm->dpll_speed == prcm->xtal_speed)
341 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
342 CORE_CLK_SRC_DPLL_X2)
343 done_rate = CORE_CLK_SRC_DPLL_X2;
345 done_rate = CORE_CLK_SRC_DPLL;
348 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
350 /* dsp + iva1 div(2420), iva2.1(2430) */
351 cm_write_mod_reg(prcm->cm_clksel_dsp,
352 OMAP24XX_DSP_MOD, CM_CLKSEL);
354 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
356 /* Major subsystem dividers */
357 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
358 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
361 if (cpu_is_omap2430())
362 cm_write_mod_reg(prcm->cm_clksel_mdm,
363 OMAP2430_MDM_MOD, CM_CLKSEL);
365 /* x2 to enter init_mem */
366 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
368 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
371 omap2_init_memory_params(omap2_dll_force_needed());
372 omap2_reprogram_sdrc(done_rate, 0);
374 local_irq_restore(flags);
376 omap2_dpllcore_recalc(&dpll_ck);
381 #ifdef CONFIG_CPU_FREQ
383 * Walk PRCM rate table and fillout cpufreq freq_table
385 static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
387 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
389 struct prcm_config *prcm;
392 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
393 if (!(prcm->flags & cpu_mask))
395 if (prcm->xtal_speed != sys_ck.rate)
398 /* don't put bypass rates in table */
399 if (prcm->dpll_speed == prcm->xtal_speed)
402 freq_table[i].index = i;
403 freq_table[i].frequency = prcm->mpu_speed / 1000;
408 printk(KERN_WARNING "%s: failed to initialize frequency "
409 "table\n", __func__);
413 freq_table[i].index = i;
414 freq_table[i].frequency = CPUFREQ_TABLE_END;
416 *table = &freq_table[0];
420 static struct clk_functions omap2_clk_functions = {
421 .clk_enable = omap2_clk_enable,
422 .clk_disable = omap2_clk_disable,
423 .clk_round_rate = omap2_clk_round_rate,
424 .clk_set_rate = omap2_clk_set_rate,
425 .clk_set_parent = omap2_clk_set_parent,
426 .clk_disable_unused = omap2_clk_disable_unused,
427 #ifdef CONFIG_CPU_FREQ
428 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
432 static u32 omap2_get_apll_clkin(void)
434 u32 aplls, srate = 0;
436 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
437 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
438 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
440 if (aplls == APLLS_CLKIN_19_2MHZ)
442 else if (aplls == APLLS_CLKIN_13MHZ)
444 else if (aplls == APLLS_CLKIN_12MHZ)
450 static u32 omap2_get_sysclkdiv(void)
454 div = prm_read_mod_reg(OMAP24XX_GR_MOD,
455 OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
456 div &= OMAP_SYSCLKDIV_MASK;
457 div >>= OMAP_SYSCLKDIV_SHIFT;
462 static void omap2_osc_clk_recalc(struct clk *clk)
464 clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
468 static void omap2_sys_clk_recalc(struct clk *clk)
470 clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
475 * Set clocks for bypass mode for reboot to work.
477 void omap2_clk_prepare_for_reboot(void)
481 if (vclk == NULL || sclk == NULL)
484 rate = clk_get_rate(sclk);
485 clk_set_rate(vclk, rate);
489 * Switch the MPU rate if specified on cmdline.
490 * We cannot do this early until cmdline is parsed.
492 static int __init omap2_clk_arch_init(void)
497 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
498 printk(KERN_ERR "Could not find matching MPU rate\n");
500 recalculate_root_clocks();
502 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
503 "%ld.%01ld/%ld/%ld MHz\n",
504 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
505 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
509 arch_initcall(omap2_clk_arch_init);
515 * Since we share clock data for 242x and 243x, we need to rewrite some
516 * some register base offsets. Assume offset is at prm_base if flagged,
517 * else assume it's cm_base.
519 static inline void omap2_clk_check_reg(u32 flags, void __iomem **reg)
521 u32 tmp = (__force u32)*reg;
523 if ((tmp >> 24) != 0)
526 if (flags & OFFSET_GR_MOD)
531 *reg = (__force void __iomem *)tmp;
534 void __init omap2_clk_rewrite_base(struct clk *clk)
536 omap2_clk_check_reg(clk->flags, &clk->clksel_reg);
537 omap2_clk_check_reg(clk->flags, &clk->enable_reg);
539 omap2_clk_check_reg(0, &clk->dpll_data->mult_div1_reg);
542 int __init omap2_clk_init(void)
544 struct prcm_config *prcm;
548 if (cpu_is_omap242x())
549 cpu_mask = RATE_IN_242X;
550 else if (cpu_is_omap2430())
551 cpu_mask = RATE_IN_243X;
553 for (clkp = onchip_24xx_clks;
554 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
556 omap2_clk_rewrite_base(*clkp);
559 clk_init(&omap2_clk_functions);
561 omap2_osc_clk_recalc(&osc_ck);
562 omap2_sys_clk_recalc(&sys_ck);
564 for (clkp = onchip_24xx_clks;
565 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
568 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
573 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
579 /* Check the MPU rate set by bootloader */
580 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
581 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
582 if (!(prcm->flags & cpu_mask))
584 if (prcm->xtal_speed != sys_ck.rate)
586 if (prcm->dpll_speed <= clkrate)
589 curr_prcm_set = prcm;
591 recalculate_root_clocks();
593 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
594 "%ld.%01ld/%ld/%ld MHz\n",
595 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
596 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
599 * Only enable those clocks we will need, let the drivers
600 * enable other clocks as necessary
602 clk_enable_init_clocks();
604 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
605 vclk = clk_get(NULL, "virt_prcm_set");
606 sclk = clk_get(NULL, "sys_ck");
611 void __init omap2_set_globals_clock24xx(struct omap_globals *omap2_globals)
613 prm_base = (__force u32)omap2_globals->prm;
614 cm_base = (__force u32)omap2_globals->cm;