2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
27 #include <linux/bitops.h>
29 #include <linux/cpufreq.h>
31 #include <mach/common.h>
32 #include <mach/clock.h>
33 #include <mach/sram.h>
34 #include <asm/div64.h>
36 #include <mach/sdrc.h>
38 #include "clock24xx.h"
40 #include "prm-regbits-24xx.h"
42 #include "cm-regbits-24xx.h"
44 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
45 #define EN_APLL_STOPPED 0
46 #define EN_APLL_LOCKED 3
48 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
49 #define APLLS_CLKIN_19_2MHZ 0
50 #define APLLS_CLKIN_13MHZ 2
51 #define APLLS_CLKIN_12MHZ 3
53 /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
55 static struct prcm_config *curr_prcm_set;
56 static struct clk *vclk;
57 static struct clk *sclk;
59 /*-------------------------------------------------------------------------
60 * Omap24xx specific clock functions
61 *-------------------------------------------------------------------------*/
63 /* This actually returns the rate of core_ck, not dpll_ck. */
64 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
69 dpll_clk = omap2_get_dpll_rate(tclk);
71 amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
72 amult &= OMAP24XX_CORE_CLK_SRC_MASK;
78 static int omap2_enable_osc_ck(struct clk *clk)
80 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0,
81 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
86 static void omap2_disable_osc_ck(struct clk *clk)
88 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
89 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
92 /* Enable an APLL if off */
93 static int omap2_clk_fixed_enable(struct clk *clk)
97 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
99 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
101 if ((cval & apll_mask) == apll_mask)
102 return 0; /* apll already enabled */
106 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
108 if (clk == &apll96_ck)
109 cval = OMAP24XX_ST_96M_APLL;
110 else if (clk == &apll54_ck)
111 cval = OMAP24XX_ST_54M_APLL;
113 omap2_wait_clock_ready(PLL_MOD, CM_IDLEST, cval, clk->name);
116 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
123 static void omap2_clk_fixed_disable(struct clk *clk)
127 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
128 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
129 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
133 * Uses the current prcm set to tell if a rate is valid.
134 * You can go slower, but not faster within a given rate set.
136 static long omap2_dpllcore_round_rate(unsigned long target_rate)
138 u32 high, low, core_clk_src;
140 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
141 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
143 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
144 high = curr_prcm_set->dpll_speed * 2;
145 low = curr_prcm_set->dpll_speed;
146 } else { /* DPLL clockout x 2 */
147 high = curr_prcm_set->dpll_speed;
148 low = curr_prcm_set->dpll_speed / 2;
151 #ifdef DOWN_VARIABLE_DPLL
152 if (target_rate > high)
157 if (target_rate > low)
165 static void omap2_dpllcore_recalc(struct clk *clk)
167 clk->rate = omap2_get_dpll_rate_24xx(clk);
172 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
174 u32 cur_rate, low, mult, div, valid_rate, done_rate;
176 struct prcm_config tmpset;
177 const struct dpll_data *dd;
181 local_irq_save(flags);
182 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
183 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
184 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
186 if ((rate == (cur_rate / 2)) && (mult == 2)) {
187 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
188 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
189 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
190 } else if (rate != cur_rate) {
191 valid_rate = omap2_dpllcore_round_rate(rate);
192 if (valid_rate != rate)
196 low = curr_prcm_set->dpll_speed;
198 low = curr_prcm_set->dpll_speed / 2;
204 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
205 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
207 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
208 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
209 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
211 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
212 mult = ((rate / 2) / 1000000);
213 done_rate = CORE_CLK_SRC_DPLL_X2;
215 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
216 mult = (rate / 1000000);
217 done_rate = CORE_CLK_SRC_DPLL;
219 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
220 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
223 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
225 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
228 /* For omap2xxx_sdrc_init_params() */
229 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
231 /* Force dll lock mode */
232 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
235 /* Errata: ret dll entry state */
236 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
237 omap2xxx_sdrc_reprogram(done_rate, 0);
239 omap2_dpllcore_recalc(&dpll_ck);
243 local_irq_restore(flags);
248 * omap2_table_mpu_recalc - just return the MPU speed
249 * @clk: virt_prcm_set struct clk
251 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
253 static void omap2_table_mpu_recalc(struct clk *clk)
255 clk->rate = curr_prcm_set->mpu_speed;
259 * Look for a rate equal or less than the target rate given a configuration set.
261 * What's not entirely clear is "which" field represents the key field.
262 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
263 * just uses the ARM rates.
265 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
267 struct prcm_config *ptr;
270 if (clk != &virt_prcm_set)
273 highest_rate = -EINVAL;
275 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
276 if (!(ptr->flags & cpu_mask))
278 if (ptr->xtal_speed != sys_ck.rate)
281 highest_rate = ptr->mpu_speed;
283 /* Can check only after xtal frequency check */
284 if (ptr->mpu_speed <= rate)
290 /* Sets basic clocks based on the specified rate */
291 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
293 u32 cur_rate, done_rate, bypass = 0, tmp;
294 struct prcm_config *prcm;
295 unsigned long found_speed = 0;
298 if (clk != &virt_prcm_set)
301 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
302 if (!(prcm->flags & cpu_mask))
305 if (prcm->xtal_speed != sys_ck.rate)
308 if (prcm->mpu_speed <= rate) {
309 found_speed = prcm->mpu_speed;
315 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
320 curr_prcm_set = prcm;
321 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
323 if (prcm->dpll_speed == cur_rate / 2) {
324 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
325 } else if (prcm->dpll_speed == cur_rate * 2) {
326 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
327 } else if (prcm->dpll_speed != cur_rate) {
328 local_irq_save(flags);
330 if (prcm->dpll_speed == prcm->xtal_speed)
333 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
334 CORE_CLK_SRC_DPLL_X2)
335 done_rate = CORE_CLK_SRC_DPLL_X2;
337 done_rate = CORE_CLK_SRC_DPLL;
340 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
342 /* dsp + iva1 div(2420), iva2.1(2430) */
343 cm_write_mod_reg(prcm->cm_clksel_dsp,
344 OMAP24XX_DSP_MOD, CM_CLKSEL);
346 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
348 /* Major subsystem dividers */
349 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
350 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
353 if (cpu_is_omap2430())
354 cm_write_mod_reg(prcm->cm_clksel_mdm,
355 OMAP2430_MDM_MOD, CM_CLKSEL);
357 /* x2 to enter omap2xxx_sdrc_init_params() */
358 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
360 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
363 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
364 omap2xxx_sdrc_reprogram(done_rate, 0);
366 local_irq_restore(flags);
368 omap2_dpllcore_recalc(&dpll_ck);
373 #ifdef CONFIG_CPU_FREQ
375 * Walk PRCM rate table and fillout cpufreq freq_table
377 static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
379 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
381 struct prcm_config *prcm;
384 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
385 if (!(prcm->flags & cpu_mask))
387 if (prcm->xtal_speed != sys_ck.rate)
390 /* don't put bypass rates in table */
391 if (prcm->dpll_speed == prcm->xtal_speed)
394 freq_table[i].index = i;
395 freq_table[i].frequency = prcm->mpu_speed / 1000;
400 printk(KERN_WARNING "%s: failed to initialize frequency "
401 "table\n", __func__);
405 freq_table[i].index = i;
406 freq_table[i].frequency = CPUFREQ_TABLE_END;
408 *table = &freq_table[0];
412 static struct clk_functions omap2_clk_functions = {
413 .clk_enable = omap2_clk_enable,
414 .clk_disable = omap2_clk_disable,
415 .clk_round_rate = omap2_clk_round_rate,
416 .clk_set_rate = omap2_clk_set_rate,
417 .clk_set_parent = omap2_clk_set_parent,
418 .clk_disable_unused = omap2_clk_disable_unused,
419 #ifdef CONFIG_CPU_FREQ
420 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
424 static u32 omap2_get_apll_clkin(void)
426 u32 aplls, srate = 0;
428 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
429 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
430 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
432 if (aplls == APLLS_CLKIN_19_2MHZ)
434 else if (aplls == APLLS_CLKIN_13MHZ)
436 else if (aplls == APLLS_CLKIN_12MHZ)
442 static u32 omap2_get_sysclkdiv(void)
446 div = prm_read_mod_reg(OMAP24XX_GR_MOD,
447 OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
448 div &= OMAP_SYSCLKDIV_MASK;
449 div >>= OMAP_SYSCLKDIV_SHIFT;
454 static void omap2_osc_clk_recalc(struct clk *clk)
456 clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
460 static void omap2_sys_clk_recalc(struct clk *clk)
462 clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
467 * Set clocks for bypass mode for reboot to work.
469 void omap2_clk_prepare_for_reboot(void)
473 if (vclk == NULL || sclk == NULL)
476 rate = clk_get_rate(sclk);
477 clk_set_rate(vclk, rate);
481 * Switch the MPU rate if specified on cmdline.
482 * We cannot do this early until cmdline is parsed.
484 static int __init omap2_clk_arch_init(void)
489 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
490 printk(KERN_ERR "Could not find matching MPU rate\n");
492 recalculate_root_clocks();
494 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
495 "%ld.%01ld/%ld/%ld MHz\n",
496 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
497 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
501 arch_initcall(omap2_clk_arch_init);
507 * Since we share clock data for 242x and 243x, we need to rewrite some
508 * some register base offsets. Assume offset is at prm_base if flagged,
509 * else assume it's cm_base.
511 static inline void omap2_clk_check_reg(u32 flags, void __iomem **reg)
513 u32 tmp = (__force u32)*reg;
515 if ((tmp >> 24) != 0)
518 if (flags & OFFSET_GR_MOD)
523 *reg = (__force void __iomem *)tmp;
526 static void __init omap2_clk_rewrite_base(struct clk *clk)
528 omap2_clk_check_reg(clk->flags, &clk->clksel_reg);
529 omap2_clk_check_reg(clk->flags, &clk->enable_reg);
530 if (clk->dpll_data) {
531 omap2_clk_check_reg(0, &clk->dpll_data->mult_div1_reg);
532 omap2_clk_check_reg(0, &clk->dpll_data->idlest_reg);
536 int __init omap2_clk_init(void)
538 struct prcm_config *prcm;
542 if (cpu_is_omap242x())
543 cpu_mask = RATE_IN_242X;
544 else if (cpu_is_omap2430())
545 cpu_mask = RATE_IN_243X;
547 for (clkp = onchip_24xx_clks;
548 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
550 omap2_clk_rewrite_base(*clkp);
553 clk_init(&omap2_clk_functions);
555 omap2_osc_clk_recalc(&osc_ck);
556 omap2_sys_clk_recalc(&sys_ck);
558 for (clkp = onchip_24xx_clks;
559 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
562 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
564 omap2_init_clk_clkdm(*clkp);
568 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
570 omap2_init_clk_clkdm(*clkp);
575 /* Check the MPU rate set by bootloader */
576 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
577 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
578 if (!(prcm->flags & cpu_mask))
580 if (prcm->xtal_speed != sys_ck.rate)
582 if (prcm->dpll_speed <= clkrate)
585 curr_prcm_set = prcm;
587 recalculate_root_clocks();
589 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
590 "%ld.%01ld/%ld/%ld MHz\n",
591 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
592 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
595 * Only enable those clocks we will need, let the drivers
596 * enable other clocks as necessary
598 clk_enable_init_clocks();
600 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
601 vclk = clk_get(NULL, "virt_prcm_set");
602 sclk = clk_get(NULL, "sys_ck");
607 void __init omap2_set_globals_clock24xx(struct omap_globals *omap2_globals)
609 prm_base = (__force u32)omap2_globals->prm;
610 cm_base = (__force u32)omap2_globals->cm;