2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Cleaned up and modified to use omap shared clock framework by
9 * Tony Lindgren <tony@atomide.com>
11 * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
12 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/sram.h>
33 #include <asm/div64.h>
37 #include "clock24xx.h"
39 #include "prm_regbits_24xx.h"
41 #include "cm_regbits_24xx.h"
43 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
44 #define EN_APLL_STOPPED 0
45 #define EN_APLL_LOCKED 3
47 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
48 #define APLLS_CLKIN_19_2MHZ 0
49 #define APLLS_CLKIN_13MHZ 2
50 #define APLLS_CLKIN_12MHZ 3
52 /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
54 static struct prcm_config *curr_prcm_set;
55 static struct clk *vclk;
56 static struct clk *sclk;
58 /*-------------------------------------------------------------------------
59 * Omap24xx specific clock functions
60 *-------------------------------------------------------------------------*/
62 /* This actually returns the rate of core_ck, not dpll_ck. */
63 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
68 dpll_clk = omap2_get_dpll_rate(tclk);
70 amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
71 amult &= OMAP24XX_CORE_CLK_SRC_MASK;
77 static int omap2_enable_osc_ck(struct clk *clk)
81 pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
83 prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
84 OMAP24XX_PRCM_CLKSRC_CTRL);
89 static void omap2_disable_osc_ck(struct clk *clk)
93 pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
95 prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
96 OMAP24XX_PRCM_CLKSRC_CTRL);
99 /* Enable an APLL if off */
100 static int omap2_clk_fixed_enable(struct clk *clk)
104 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
106 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
108 if ((cval & apll_mask) == apll_mask)
109 return 0; /* apll already enabled */
113 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
115 if (clk == &apll96_ck)
116 cval = OMAP24XX_ST_96M_APLL;
117 else if (clk == &apll54_ck)
118 cval = OMAP24XX_ST_54M_APLL;
120 omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
124 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
131 static void omap2_clk_fixed_disable(struct clk *clk)
135 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
136 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
137 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
141 * Uses the current prcm set to tell if a rate is valid.
142 * You can go slower, but not faster within a given rate set.
144 static u32 omap2_dpll_round_rate(unsigned long target_rate)
146 u32 high, low, core_clk_src;
148 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
149 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
151 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
152 high = curr_prcm_set->dpll_speed * 2;
153 low = curr_prcm_set->dpll_speed;
154 } else { /* DPLL clockout x 2 */
155 high = curr_prcm_set->dpll_speed;
156 low = curr_prcm_set->dpll_speed / 2;
159 #ifdef DOWN_VARIABLE_DPLL
160 if (target_rate > high)
165 if (target_rate > low)
173 static void omap2_dpll_recalc(struct clk *clk)
175 clk->rate = omap2_get_dpll_rate_24xx(clk);
180 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
182 u32 cur_rate, low, mult, div, valid_rate, done_rate;
184 struct prcm_config tmpset;
185 const struct dpll_data *dd;
189 local_irq_save(flags);
190 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
191 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
192 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
194 if ((rate == (cur_rate / 2)) && (mult == 2)) {
195 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
196 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
197 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
198 } else if (rate != cur_rate) {
199 valid_rate = omap2_dpll_round_rate(rate);
200 if (valid_rate != rate)
204 low = curr_prcm_set->dpll_speed;
206 low = curr_prcm_set->dpll_speed / 2;
212 tmpset.cm_clksel1_pll = cm_read_reg(dd->mult_div1_reg);
213 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
215 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
216 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
217 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
219 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
220 mult = ((rate / 2) / 1000000);
221 done_rate = CORE_CLK_SRC_DPLL_X2;
223 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
224 mult = (rate / 1000000);
225 done_rate = CORE_CLK_SRC_DPLL;
227 tmpset.cm_clksel1_pll |= (div << mask_to_shift(dd->mult_mask));
228 tmpset.cm_clksel1_pll |= (mult << mask_to_shift(dd->div1_mask));
231 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
233 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
236 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
238 /* Force dll lock mode */
239 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
242 /* Errata: ret dll entry state */
243 omap2_init_memory_params(omap2_dll_force_needed());
244 omap2_reprogram_sdrc(done_rate, 0);
246 omap2_dpll_recalc(&dpll_ck);
250 local_irq_restore(flags);
255 * omap2_table_mpu_recalc - just return the MPU speed
256 * @clk: virt_prcm_set struct clk
258 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
260 static void omap2_table_mpu_recalc(struct clk *clk)
262 clk->rate = curr_prcm_set->mpu_speed;
266 * Look for a rate equal or less than the target rate given a configuration set.
268 * What's not entirely clear is "which" field represents the key field.
269 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
270 * just uses the ARM rates.
272 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
274 struct prcm_config *ptr;
277 if (clk != &virt_prcm_set)
280 highest_rate = -EINVAL;
282 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
283 if (!(ptr->flags & cpu_mask))
285 if (ptr->xtal_speed != sys_ck.rate)
288 highest_rate = ptr->mpu_speed;
290 /* Can check only after xtal frequency check */
291 if (ptr->mpu_speed <= rate)
297 /* Sets basic clocks based on the specified rate */
298 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
300 u32 cur_rate, done_rate, bypass = 0, tmp;
301 struct prcm_config *prcm;
302 unsigned long found_speed = 0;
305 if (clk != &virt_prcm_set)
308 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
309 if (!(prcm->flags & cpu_mask))
312 if (prcm->xtal_speed != sys_ck.rate)
315 if (prcm->mpu_speed <= rate) {
316 found_speed = prcm->mpu_speed;
322 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
327 curr_prcm_set = prcm;
328 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
330 if (prcm->dpll_speed == cur_rate / 2) {
331 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
332 } else if (prcm->dpll_speed == cur_rate * 2) {
333 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
334 } else if (prcm->dpll_speed != cur_rate) {
335 local_irq_save(flags);
337 if (prcm->dpll_speed == prcm->xtal_speed)
340 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
341 CORE_CLK_SRC_DPLL_X2)
342 done_rate = CORE_CLK_SRC_DPLL_X2;
344 done_rate = CORE_CLK_SRC_DPLL;
347 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
349 /* dsp + iva1 div(2420), iva2.1(2430) */
350 cm_write_mod_reg(prcm->cm_clksel_dsp,
351 OMAP24XX_DSP_MOD, CM_CLKSEL);
353 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
355 /* Major subsystem dividers */
356 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
357 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
358 if (cpu_is_omap2430())
359 cm_write_mod_reg(prcm->cm_clksel_mdm,
360 OMAP2430_MDM_MOD, CM_CLKSEL);
362 /* x2 to enter init_mem */
363 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
365 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
368 omap2_init_memory_params(omap2_dll_force_needed());
369 omap2_reprogram_sdrc(done_rate, 0);
371 local_irq_restore(flags);
373 omap2_dpll_recalc(&dpll_ck);
378 #ifdef CONFIG_CPU_FREQ
380 * Walk PRCM rate table and fillout cpufreq freq_table
382 static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
384 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
386 struct prcm_config *prcm;
389 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
390 if (!(prcm->flags & cpu_mask))
392 if (prcm->xtal_speed != sys_ck.rate)
395 /* don't put bypass rates in table */
396 if (prcm->dpll_speed == prcm->xtal_speed)
399 freq_table[i].index = i;
400 freq_table[i].frequency = prcm->mpu_speed / 1000;
405 printk(KERN_WARNING "%s: failed to initialize frequency table\n",
410 freq_table[i].index = i;
411 freq_table[i].frequency = CPUFREQ_TABLE_END;
413 *table = &freq_table[0];
417 static struct clk_functions omap2_clk_functions = {
418 .clk_enable = omap2_clk_enable,
419 .clk_disable = omap2_clk_disable,
420 .clk_round_rate = omap2_clk_round_rate,
421 .clk_set_rate = omap2_clk_set_rate,
422 .clk_set_parent = omap2_clk_set_parent,
423 .clk_disable_unused = omap2_clk_disable_unused,
424 #ifdef CONFIG_CPU_FREQ
425 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
429 static u32 omap2_get_apll_clkin(void)
433 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
434 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
435 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
437 if (aplls == APLLS_CLKIN_19_2MHZ)
439 else if (aplls == APLLS_CLKIN_13MHZ)
441 else if (aplls == APLLS_CLKIN_12MHZ)
447 static u32 omap2_get_sysclkdiv(void)
451 div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
452 div &= OMAP_SYSCLKDIV_MASK;
453 div >>= OMAP_SYSCLKDIV_SHIFT;
458 static void omap2_osc_clk_recalc(struct clk *clk)
460 clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
464 static void omap2_sys_clk_recalc(struct clk *clk)
466 clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
471 * Set clocks for bypass mode for reboot to work.
473 void omap2_clk_prepare_for_reboot(void)
477 if (vclk == NULL || sclk == NULL)
480 rate = clk_get_rate(sclk);
481 clk_set_rate(vclk, rate);
485 * Switch the MPU rate if specified on cmdline.
486 * We cannot do this early until cmdline is parsed.
488 static int __init omap2_clk_arch_init(void)
493 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
494 printk(KERN_ERR "Could not find matching MPU rate\n");
496 recalculate_root_clocks();
498 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
499 "%ld.%01ld/%ld/%ld MHz\n",
500 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
501 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
505 arch_initcall(omap2_clk_arch_init);
507 int __init omap2_clk_init(void)
509 struct prcm_config *prcm;
513 if (cpu_is_omap242x())
514 cpu_mask = RATE_IN_242X;
515 else if (cpu_is_omap2430())
516 cpu_mask = RATE_IN_243X;
518 clk_init(&omap2_clk_functions);
520 omap2_osc_clk_recalc(&osc_ck);
521 omap2_sys_clk_recalc(&sys_ck);
523 for (clkp = onchip_24xx_clks;
524 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
527 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
532 if ((*clkp)->flags & CLOCK_IN_OMAP243X && (cpu_is_omap2430() || cpu_is_omap34xx())) {
538 /* Check the MPU rate set by bootloader */
539 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
540 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
541 if (!(prcm->flags & cpu_mask))
543 if (prcm->xtal_speed != sys_ck.rate)
545 if (prcm->dpll_speed <= clkrate)
548 curr_prcm_set = prcm;
550 recalculate_root_clocks();
552 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
553 "%ld.%01ld/%ld/%ld MHz\n",
554 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
555 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
558 * Only enable those clocks we will need, let the drivers
559 * enable other clocks as necessary
561 clk_enable_init_clocks();
563 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
564 vclk = clk_get(NULL, "virt_prcm_set");
565 sclk = clk_get(NULL, "sys_ck");